wdc.c revision 1.97
1 /* $NetBSD: wdc.c,v 1.97 2001/06/11 21:18:36 bjh21 Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "atapibus.h" 105 106 #define WDCDELAY 100 /* 100 microseconds */ 107 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 108 #if 0 109 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 110 #define WDCNDELAY_DEBUG 50 111 #endif 112 113 struct pool wdc_xfer_pool; 114 115 static void __wdcerror __P((struct channel_softc*, char *)); 116 static int __wdcwait_reset __P((struct channel_softc *, int)); 117 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 118 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 119 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 120 int wdprint __P((void *, const char *)); 121 122 123 #define DEBUG_INTR 0x01 124 #define DEBUG_XFERS 0x02 125 #define DEBUG_STATUS 0x04 126 #define DEBUG_FUNCS 0x08 127 #define DEBUG_PROBE 0x10 128 #define DEBUG_DETACH 0x20 129 #define DEBUG_DELAY 0x40 130 #ifdef WDCDEBUG 131 int wdcdebug_mask = 0; 132 int wdc_nxfer = 0; 133 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 134 #else 135 #define WDCDEBUG_PRINT(args, level) 136 #endif 137 138 int 139 wdprint(aux, pnp) 140 void *aux; 141 const char *pnp; 142 { 143 struct ata_atapi_attach *aa_link = aux; 144 if (pnp) 145 printf("drive at %s", pnp); 146 printf(" channel %d drive %d", aa_link->aa_channel, 147 aa_link->aa_drv_data->drive); 148 return (UNCONF); 149 } 150 151 int 152 atapiprint(aux, pnp) 153 void *aux; 154 const char *pnp; 155 { 156 struct ata_atapi_attach *aa_link = aux; 157 if (pnp) 158 printf("atapibus at %s", pnp); 159 printf(" channel %d", aa_link->aa_channel); 160 return (UNCONF); 161 } 162 163 /* Test to see controller with at last one attached drive is there. 164 * Returns a bit for each possible drive found (0x01 for drive 0, 165 * 0x02 for drive 1). 166 * Logic: 167 * - If a status register is at 0xff, assume there is no drive here 168 * (ISA has pull-up resistors). Similarly if the status register has 169 * the value we last wrote to the bus (for IDE interfaces without pullups). 170 * If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 int found; 185 186 /* 187 * Sanity check to see if the wdc channel responds at all. 188 */ 189 190 if (chp->wdc == NULL || 191 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM); 194 delay(10); 195 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 197 WDSD_IBM | 0x10); 198 delay(10); 199 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 200 201 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 202 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 203 chp->channel, st0, st1), DEBUG_PROBE); 204 205 if (st0 == 0xff || st0 == WDSD_IBM) 206 ret_value &= ~0x01; 207 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 208 ret_value &= ~0x02; 209 if (ret_value == 0) 210 return 0; 211 } 212 213 /* assert SRST, wait for reset to complete */ 214 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 215 WDSD_IBM); 216 delay(10); 217 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 218 WDCTL_RST | WDCTL_IDS); 219 DELAY(1000); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 221 WDCTL_IDS); 222 delay(1000); 223 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 224 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 225 delay(10); 226 227 ret_value = __wdcwait_reset(chp, ret_value); 228 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 229 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 230 ret_value), DEBUG_PROBE); 231 232 /* if reset failed, there's nothing here */ 233 if (ret_value == 0) 234 return 0; 235 236 /* 237 * Test presence of drives. First test register signatures looking for 238 * ATAPI devices. If it's not an ATAPI and reset said there may be 239 * something here assume it's ATA or OLD. Ghost will be killed later in 240 * attach routine. 241 */ 242 found = 0; 243 for (drive = 0; drive < 2; drive++) { 244 if ((ret_value & (0x01 << drive)) == 0) 245 continue; 246 if (1 < ++found && chp->wdc != NULL && 247 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 248 /* 249 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 250 * is set. 251 * 252 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 253 * doesn't seem to implement drive select command. In 254 * this case, you can't eliminate ghost drive properly. 255 */ 256 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 257 chp->wdc->sc_dev.dv_xname, 258 chp->channel, drive), DEBUG_PROBE); 259 break; 260 } 261 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 262 WDSD_IBM | (drive << 4)); 263 delay(10); 264 /* Save registers contents */ 265 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 266 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 267 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 268 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 269 270 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 271 "cl=0x%x ch=0x%x\n", 272 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 273 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 274 /* 275 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 276 * we get wrong values here, so ignore it. 277 */ 278 if (cl == 0x14 && ch == 0xeb) { 279 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 280 } else { 281 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 282 if (chp->wdc == NULL || 283 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 284 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 285 } 286 } 287 return (ret_value); 288 } 289 290 void 291 wdcattach(chp) 292 struct channel_softc *chp; 293 { 294 int channel_flags, ctrl_flags, i, error; 295 struct ata_atapi_attach aa_link; 296 struct ataparams params; 297 static int inited = 0; 298 299 callout_init(&chp->ch_callout); 300 301 if ((error = wdc_addref(chp)) != 0) { 302 printf("%s: unable to enable controller\n", 303 chp->wdc->sc_dev.dv_xname); 304 return; 305 } 306 307 if (wdcprobe(chp) == 0) 308 /* If no drives, abort attach here. */ 309 goto out; 310 311 /* initialise global data */ 312 if (inited == 0) { 313 /* Initialize the wdc_xfer pool. */ 314 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 315 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 316 inited++; 317 } 318 TAILQ_INIT(&chp->ch_queue->sc_xfer); 319 320 for (i = 0; i < 2; i++) { 321 chp->ch_drive[i].chnl_softc = chp; 322 chp->ch_drive[i].drive = i; 323 /* 324 * Init error counter so that an error withing the first xfers 325 * will trigger a downgrade 326 */ 327 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 328 329 /* If controller can't do 16bit flag the drives as 32bit */ 330 if ((chp->wdc->cap & 331 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 332 WDC_CAPABILITY_DATA32) 333 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 334 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 335 continue; 336 337 /* 338 * Wait a bit, some devices are weird just after a reset. 339 * Then issue a IDENTIFY command, to try to detect slave ghost 340 */ 341 delay(100); 342 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 343 if (error != CMD_OK) { 344 delay(1000000); 345 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 346 ¶ms); 347 } 348 if (error == CMD_OK) { 349 /* If IDENTIFY succeded, this is not an OLD ctrl */ 350 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 351 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 352 } else { 353 chp->ch_drive[i].drive_flags &= 354 ~(DRIVE_ATA | DRIVE_ATAPI); 355 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 356 chp->wdc->sc_dev.dv_xname, 357 chp->channel, i, error), DEBUG_PROBE); 358 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 359 continue; 360 /* 361 * Pre-ATA drive ? 362 * Test registers writability (Error register not 363 * writable, but cyllo is), then try an ATA command. 364 */ 365 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 366 WDSD_IBM | (i << 4)); 367 delay(10); 368 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 369 wd_error, 0x58); 370 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 371 wd_cyl_lo, 0xa5); 372 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 373 wd_error == 0x58) || 374 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 375 wd_cyl_lo) != 0xa5) { 376 WDCDEBUG_PRINT(("%s:%d:%d: register " 377 "writability failed\n", 378 chp->wdc->sc_dev.dv_xname, 379 chp->channel, i), DEBUG_PROBE); 380 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 381 } 382 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 383 WDSD_IBM | (i << 4)); 384 delay(100); 385 if (wait_for_ready(chp, 10000) != 0) { 386 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 387 chp->wdc->sc_dev.dv_xname, 388 chp->channel, i), DEBUG_PROBE); 389 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 390 continue; 391 } 392 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 393 wd_command, WDCC_RECAL); 394 if (wait_for_ready(chp, 10000) != 0) { 395 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 396 chp->wdc->sc_dev.dv_xname, 397 chp->channel, i), DEBUG_PROBE); 398 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 399 } 400 } 401 } 402 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 403 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 404 405 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 406 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 407 DEBUG_PROBE); 408 409 /* If no drives, abort here */ 410 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 411 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 412 goto out; 413 414 /* 415 * Attach an ATAPI bus, if needed. 416 */ 417 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 418 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 419 #if NATAPIBUS > 0 420 wdc_atapibus_attach(chp); 421 #else 422 /* 423 * Fills in a fake aa_link and call config_found, so that 424 * the config machinery will print 425 * "atapibus at xxx not configured" 426 */ 427 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 428 aa_link.aa_type = T_ATAPI; 429 aa_link.aa_channel = chp->channel; 430 aa_link.aa_openings = 1; 431 aa_link.aa_drv_data = 0; 432 aa_link.aa_bus_private = NULL; 433 chp->atapibus = config_found(&chp->wdc->sc_dev, 434 (void *)&aa_link, atapiprint); 435 #endif 436 } 437 438 for (i = 0; i < 2; i++) { 439 if ((chp->ch_drive[i].drive_flags & 440 (DRIVE_ATA | DRIVE_OLD)) == 0) { 441 continue; 442 } 443 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 444 aa_link.aa_type = T_ATA; 445 aa_link.aa_channel = chp->channel; 446 aa_link.aa_openings = 1; 447 aa_link.aa_drv_data = &chp->ch_drive[i]; 448 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 449 wdc_probe_caps(&chp->ch_drive[i]); 450 } 451 452 /* 453 * reset drive_flags for unnatached devices, reset state for attached 454 * ones 455 */ 456 for (i = 0; i < 2; i++) { 457 if (chp->ch_drive[i].drv_softc == NULL) 458 chp->ch_drive[i].drive_flags = 0; 459 else 460 chp->ch_drive[i].state = 0; 461 } 462 463 /* 464 * Reset channel. The probe, with some combinations of ATA/ATAPI 465 * devices keep it in a mostly working, but strange state (with busy 466 * led on) 467 */ 468 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 469 delay(50); 470 wdcreset(chp, VERBOSE); 471 /* 472 * Read status registers to avoid spurious interrupts. 473 */ 474 for (i = 1; i >= 0; i--) { 475 if (chp->ch_drive[i].drive_flags & DRIVE) { 476 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 477 wd_sdh, WDSD_IBM | (i << 4)); 478 if (wait_for_unbusy(chp, 10000) < 0) 479 printf("%s:%d:%d: device busy\n", 480 chp->wdc->sc_dev.dv_xname, 481 chp->channel, i); 482 } 483 } 484 } 485 486 out: 487 wdc_delref(chp); 488 } 489 490 /* 491 * Call activate routine of underlying devices. 492 */ 493 int 494 wdcactivate(self, act) 495 struct device *self; 496 enum devact act; 497 { 498 struct wdc_softc *wdc = (struct wdc_softc *)self; 499 struct channel_softc *chp; 500 struct device *sc = 0; 501 int s, i, j, error = 0; 502 503 s = splbio(); 504 switch (act) { 505 case DVACT_ACTIVATE: 506 error = EOPNOTSUPP; 507 break; 508 509 case DVACT_DEACTIVATE: 510 for (i = 0; i < wdc->nchannels; i++) { 511 chp = wdc->channels[i]; 512 513 /* 514 * We might call deactivate routine for 515 * the children of atapibus twice (once via 516 * atapibus, once directly), but since 517 * config_deactivate maintains DVF_ACTIVE flag, 518 * it's safe. 519 */ 520 sc = chp->atapibus; 521 if (sc != NULL) { 522 error = config_deactivate(sc); 523 if (error != 0) 524 goto out; 525 } 526 527 for (j = 0; j < 2; j++) { 528 sc = chp->ch_drive[j].drv_softc; 529 WDCDEBUG_PRINT(("wdcactivate: %s:" 530 " deactivating %s\n", wdc->sc_dev.dv_xname, 531 sc == NULL ? "nodrv" : sc->dv_xname), 532 DEBUG_DETACH); 533 if (sc != NULL) { 534 error = config_deactivate(sc); 535 if (error != 0) 536 goto out; 537 } 538 } 539 } 540 break; 541 } 542 543 out: 544 splx(s); 545 546 #ifdef WDCDEBUG 547 if (sc && error != 0) 548 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 549 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 550 #endif 551 return (error); 552 } 553 554 int 555 wdcdetach(self, flags) 556 struct device *self; 557 int flags; 558 { 559 struct wdc_softc *wdc = (struct wdc_softc *)self; 560 struct channel_softc *chp; 561 struct device *sc = 0; 562 int i, j, error = 0; 563 564 for (i = 0; i < wdc->nchannels; i++) { 565 chp = wdc->channels[i]; 566 567 /* 568 * Detach atapibus and its children. 569 */ 570 sc = chp->atapibus; 571 if (sc != NULL) { 572 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 573 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 574 error = config_detach(sc, flags); 575 if (error != 0) 576 goto out; 577 } 578 579 /* 580 * Detach our other children. 581 */ 582 for (j = 0; j < 2; j++) { 583 sc = chp->ch_drive[j].drv_softc; 584 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 585 wdc->sc_dev.dv_xname, 586 sc == NULL ? "nodrv" : sc->dv_xname), 587 DEBUG_DETACH); 588 if (sc != NULL) { 589 error = config_detach(sc, flags); 590 if (error != 0) 591 goto out; 592 } 593 } 594 595 wdc_kill_pending(chp); 596 } 597 598 out: 599 #ifdef WDCDEBUG 600 if (sc && error != 0) 601 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 602 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 603 #endif 604 return (error); 605 } 606 607 /* 608 * Start I/O on a controller, for the given channel. 609 * The first xfer may be not for our channel if the channel queues 610 * are shared. 611 */ 612 void 613 wdcstart(chp) 614 struct channel_softc *chp; 615 { 616 struct wdc_xfer *xfer; 617 618 #ifdef WDC_DIAGNOSTIC 619 int spl1, spl2; 620 621 spl1 = splbio(); 622 spl2 = splbio(); 623 if (spl2 != spl1) { 624 printf("wdcstart: not at splbio()\n"); 625 panic("wdcstart"); 626 } 627 splx(spl2); 628 splx(spl1); 629 #endif /* WDC_DIAGNOSTIC */ 630 631 /* is there a xfer ? */ 632 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 633 return; 634 635 /* adjust chp, in case we have a shared queue */ 636 chp = xfer->chp; 637 638 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 639 return; /* channel aleady active */ 640 } 641 #ifdef DIAGNOSTIC 642 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 643 panic("wdcstart: channel waiting for irq\n"); 644 #endif 645 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 646 if (!(*chp->wdc->claim_hw)(chp, 0)) 647 return; 648 649 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 650 chp->channel, xfer->drive), DEBUG_XFERS); 651 chp->ch_flags |= WDCF_ACTIVE; 652 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 653 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 654 chp->ch_drive[xfer->drive].state = 0; 655 } 656 xfer->c_start(chp, xfer); 657 } 658 659 /* restart an interrupted I/O */ 660 void 661 wdcrestart(v) 662 void *v; 663 { 664 struct channel_softc *chp = v; 665 int s; 666 667 s = splbio(); 668 wdcstart(chp); 669 splx(s); 670 } 671 672 673 /* 674 * Interrupt routine for the controller. Acknowledge the interrupt, check for 675 * errors on the current operation, mark it done if necessary, and start the 676 * next request. Also check for a partially done transfer, and continue with 677 * the next chunk if so. 678 */ 679 int 680 wdcintr(arg) 681 void *arg; 682 { 683 struct channel_softc *chp = arg; 684 struct wdc_xfer *xfer; 685 int ret; 686 687 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 688 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 689 DEBUG_INTR); 690 return (0); 691 } 692 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 693 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 694 return (0); 695 } 696 697 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 698 xfer = chp->ch_queue->sc_xfer.tqh_first; 699 if (chp->ch_flags & WDCF_DMA_WAIT) { 700 chp->wdc->dma_status = 701 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 702 xfer->drive, 0); 703 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 704 /* IRQ not for us, not detected by DMA engine */ 705 return 0; 706 } 707 chp->ch_flags &= ~WDCF_DMA_WAIT; 708 } 709 chp->ch_flags &= ~WDCF_IRQ_WAIT; 710 ret = xfer->c_intr(chp, xfer, 1); 711 if (ret == 0) /* irq was not for us, still waiting for irq */ 712 chp->ch_flags |= WDCF_IRQ_WAIT; 713 return (ret); 714 } 715 716 /* Put all disk in RESET state */ 717 void wdc_reset_channel(drvp) 718 struct ata_drive_datas *drvp; 719 { 720 struct channel_softc *chp = drvp->chnl_softc; 721 int drive; 722 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 723 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 724 DEBUG_FUNCS); 725 (void) wdcreset(chp, VERBOSE); 726 for (drive = 0; drive < 2; drive++) { 727 chp->ch_drive[drive].state = 0; 728 } 729 } 730 731 int 732 wdcreset(chp, verb) 733 struct channel_softc *chp; 734 int verb; 735 { 736 int drv_mask1, drv_mask2; 737 738 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 739 WDSD_IBM); /* master */ 740 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 741 WDCTL_RST | WDCTL_IDS); 742 delay(1000); 743 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 744 WDCTL_IDS); 745 delay(1000); 746 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 747 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 748 WDCTL_4BIT); 749 750 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 751 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 752 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 753 if (verb && drv_mask2 != drv_mask1) { 754 printf("%s channel %d: reset failed for", 755 chp->wdc->sc_dev.dv_xname, chp->channel); 756 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 757 printf(" drive 0"); 758 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 759 printf(" drive 1"); 760 printf("\n"); 761 } 762 return (drv_mask1 != drv_mask2) ? 1 : 0; 763 } 764 765 static int 766 __wdcwait_reset(chp, drv_mask) 767 struct channel_softc *chp; 768 int drv_mask; 769 { 770 int timeout; 771 u_int8_t st0, st1; 772 #ifdef WDCDEBUG 773 u_int8_t sc0, sn0, cl0, ch0; 774 u_int8_t sc1, sn1, cl1, ch1; 775 #endif 776 /* wait for BSY to deassert */ 777 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 778 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 779 WDSD_IBM); /* master */ 780 delay(10); 781 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 782 #ifdef WDCDEBUG 783 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 784 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 785 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 786 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 787 #endif 788 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 789 WDSD_IBM | 0x10); /* slave */ 790 delay(10); 791 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 792 #ifdef WDCDEBUG 793 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 794 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 795 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 796 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 797 #endif 798 799 if ((drv_mask & 0x01) == 0) { 800 /* no master */ 801 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 802 /* No master, slave is ready, it's done */ 803 goto end; 804 } 805 } else if ((drv_mask & 0x02) == 0) { 806 /* no slave */ 807 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 808 /* No slave, master is ready, it's done */ 809 goto end; 810 } 811 } else { 812 /* Wait for both master and slave to be ready */ 813 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 814 goto end; 815 } 816 } 817 delay(WDCDELAY); 818 } 819 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 820 if (st0 & WDCS_BSY) 821 drv_mask &= ~0x01; 822 if (st1 & WDCS_BSY) 823 drv_mask &= ~0x02; 824 end: 825 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 826 "cl=0x%x ch=0x%x\n", 827 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 828 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 829 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 830 "cl=0x%x ch=0x%x\n", 831 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 832 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 833 834 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 835 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 836 st0, st1), DEBUG_PROBE); 837 838 return drv_mask; 839 } 840 841 /* 842 * Wait for a drive to be !BSY, and have mask in its status register. 843 * return -1 for a timeout after "timeout" ms. 844 */ 845 int 846 wdcwait(chp, mask, bits, timeout) 847 struct channel_softc *chp; 848 int mask, bits, timeout; 849 { 850 u_char status; 851 int time = 0; 852 #ifdef WDCNDELAY_DEBUG 853 extern int cold; 854 #endif 855 856 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 857 :"none", chp->channel), DEBUG_STATUS); 858 chp->ch_error = 0; 859 860 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 861 862 for (;;) { 863 chp->ch_status = status = 864 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 865 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 866 break; 867 if (++time > timeout) { 868 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 869 "status %x error %x (mask 0x%x bits 0x%x)\n", 870 time, status, 871 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 872 wd_error), mask, bits), 873 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 874 return -1; 875 } 876 delay(WDCDELAY); 877 } 878 #ifdef WDCDEBUG 879 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 880 printf("wdcwait: did busy-wait, time=%d\n", time); 881 #endif 882 if (status & WDCS_ERR) 883 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 884 wd_error); 885 #ifdef WDCNDELAY_DEBUG 886 /* After autoconfig, there should be no long delays. */ 887 if (!cold && time > WDCNDELAY_DEBUG) { 888 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 889 if (xfer == NULL) 890 printf("%s channel %d: warning: busy-wait took %dus\n", 891 chp->wdc->sc_dev.dv_xname, chp->channel, 892 WDCDELAY * time); 893 else 894 printf("%s:%d:%d: warning: busy-wait took %dus\n", 895 chp->wdc->sc_dev.dv_xname, chp->channel, 896 xfer->drive, 897 WDCDELAY * time); 898 } 899 #endif 900 return 0; 901 } 902 903 /* 904 * Busy-wait for DMA to complete 905 */ 906 int 907 wdc_dmawait(chp, xfer, timeout) 908 struct channel_softc *chp; 909 struct wdc_xfer *xfer; 910 int timeout; 911 { 912 int time; 913 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 914 chp->wdc->dma_status = 915 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 916 chp->channel, xfer->drive, 0); 917 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 918 return 0; 919 delay(WDCDELAY); 920 } 921 /* timeout, force a DMA halt */ 922 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 923 chp->channel, xfer->drive, 1); 924 return 1; 925 } 926 927 void 928 wdctimeout(arg) 929 void *arg; 930 { 931 struct channel_softc *chp = (struct channel_softc *)arg; 932 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 933 int s; 934 935 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 936 937 s = splbio(); 938 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 939 __wdcerror(chp, "lost interrupt"); 940 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 941 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 942 xfer->c_bcount, 943 xfer->c_skip); 944 if (chp->ch_flags & WDCF_DMA_WAIT) { 945 chp->wdc->dma_status = 946 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 947 chp->channel, xfer->drive, 1); 948 chp->ch_flags &= ~WDCF_DMA_WAIT; 949 } 950 /* 951 * Call the interrupt routine. If we just missed and interrupt, 952 * it will do what's needed. Else, it will take the needed 953 * action (reset the device). 954 * Before that we need to reinstall the timeout callback, 955 * in case it will miss another irq while in this transfer 956 * We arbitray chose it to be 1s 957 */ 958 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 959 xfer->c_flags |= C_TIMEOU; 960 chp->ch_flags &= ~WDCF_IRQ_WAIT; 961 xfer->c_intr(chp, xfer, 1); 962 } else 963 __wdcerror(chp, "missing untimeout"); 964 splx(s); 965 } 966 967 /* 968 * Probe drive's capabilites, for use by the controller later 969 * Assumes drvp points to an existing drive. 970 * XXX this should be a controller-indep function 971 */ 972 void 973 wdc_probe_caps(drvp) 974 struct ata_drive_datas *drvp; 975 { 976 struct ataparams params, params2; 977 struct channel_softc *chp = drvp->chnl_softc; 978 struct device *drv_dev = drvp->drv_softc; 979 struct wdc_softc *wdc = chp->wdc; 980 int i, printed; 981 char *sep = ""; 982 int cf_flags; 983 984 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 985 /* IDENTIFY failed. Can't tell more about the device */ 986 return; 987 } 988 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 989 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 990 /* 991 * Controller claims 16 and 32 bit transfers. 992 * Re-do an IDENTIFY with 32-bit transfers, 993 * and compare results. 994 */ 995 drvp->drive_flags |= DRIVE_CAP32; 996 ata_get_params(drvp, AT_POLL, ¶ms2); 997 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 998 /* Not good. fall back to 16bits */ 999 drvp->drive_flags &= ~DRIVE_CAP32; 1000 } else { 1001 printf("%s: 32-bit data port", drv_dev->dv_xname); 1002 } 1003 } 1004 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1005 if (params.atap_ata_major > 0x01 && 1006 params.atap_ata_major != 0xffff) { 1007 for (i = 14; i > 0; i--) { 1008 if (params.atap_ata_major & (1 << i)) { 1009 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1010 printf("%s: ", drv_dev->dv_xname); 1011 else 1012 printf(", "); 1013 printf("ATA version %d\n", i); 1014 drvp->ata_vers = i; 1015 break; 1016 } 1017 } 1018 } else 1019 #endif 1020 if (drvp->drive_flags & DRIVE_CAP32) 1021 printf("\n"); 1022 1023 /* An ATAPI device is at last PIO mode 3 */ 1024 if (drvp->drive_flags & DRIVE_ATAPI) 1025 drvp->PIO_mode = 3; 1026 1027 /* 1028 * It's not in the specs, but it seems that some drive 1029 * returns 0xffff in atap_extensions when this field is invalid 1030 */ 1031 if (params.atap_extensions != 0xffff && 1032 (params.atap_extensions & WDC_EXT_MODES)) { 1033 printed = 0; 1034 /* 1035 * XXX some drives report something wrong here (they claim to 1036 * support PIO mode 8 !). As mode is coded on 3 bits in 1037 * SET FEATURE, limit it to 7 (so limit i to 4). 1038 * If higther mode than 7 is found, abort. 1039 */ 1040 for (i = 7; i >= 0; i--) { 1041 if ((params.atap_piomode_supp & (1 << i)) == 0) 1042 continue; 1043 if (i > 4) 1044 return; 1045 /* 1046 * See if mode is accepted. 1047 * If the controller can't set its PIO mode, 1048 * assume the defaults are good, so don't try 1049 * to set it 1050 */ 1051 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1052 if (ata_set_mode(drvp, 0x08 | (i + 3), 1053 AT_POLL) != CMD_OK) 1054 continue; 1055 if (!printed) { 1056 printf("%s: drive supports PIO mode %d", 1057 drv_dev->dv_xname, i + 3); 1058 sep = ","; 1059 printed = 1; 1060 } 1061 /* 1062 * If controller's driver can't set its PIO mode, 1063 * get the highter one for the drive. 1064 */ 1065 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1066 wdc->PIO_cap >= i + 3) { 1067 drvp->PIO_mode = i + 3; 1068 drvp->PIO_cap = i + 3; 1069 break; 1070 } 1071 } 1072 if (!printed) { 1073 /* 1074 * We didn't find a valid PIO mode. 1075 * Assume the values returned for DMA are buggy too 1076 */ 1077 return; 1078 } 1079 drvp->drive_flags |= DRIVE_MODE; 1080 printed = 0; 1081 for (i = 7; i >= 0; i--) { 1082 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1083 continue; 1084 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1085 (wdc->cap & WDC_CAPABILITY_MODE)) 1086 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1087 != CMD_OK) 1088 continue; 1089 if (!printed) { 1090 printf("%s DMA mode %d", sep, i); 1091 sep = ","; 1092 printed = 1; 1093 } 1094 if (wdc->cap & WDC_CAPABILITY_DMA) { 1095 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1096 wdc->DMA_cap < i) 1097 continue; 1098 drvp->DMA_mode = i; 1099 drvp->DMA_cap = i; 1100 drvp->drive_flags |= DRIVE_DMA; 1101 } 1102 break; 1103 } 1104 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1105 printed = 0; 1106 for (i = 7; i >= 0; i--) { 1107 if ((params.atap_udmamode_supp & (1 << i)) 1108 == 0) 1109 continue; 1110 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1111 (wdc->cap & WDC_CAPABILITY_UDMA)) 1112 if (ata_set_mode(drvp, 0x40 | i, 1113 AT_POLL) != CMD_OK) 1114 continue; 1115 if (!printed) { 1116 printf("%s Ultra-DMA mode %d", sep, i); 1117 if (i == 2) 1118 printf(" (Ultra/33)"); 1119 else if (i == 4) 1120 printf(" (Ultra/66)"); 1121 else if (i == 5) 1122 printf(" (Ultra/100)"); 1123 sep = ","; 1124 printed = 1; 1125 } 1126 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1127 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1128 wdc->UDMA_cap < i) 1129 continue; 1130 drvp->UDMA_mode = i; 1131 drvp->UDMA_cap = i; 1132 drvp->drive_flags |= DRIVE_UDMA; 1133 } 1134 break; 1135 } 1136 } 1137 printf("\n"); 1138 } 1139 1140 /* Try to guess ATA version here, if it didn't get reported */ 1141 if (drvp->ata_vers == 0) { 1142 if (drvp->drive_flags & DRIVE_UDMA) 1143 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1144 else if (drvp->PIO_cap > 2) 1145 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1146 } 1147 cf_flags = drv_dev->dv_cfdata->cf_flags; 1148 if (cf_flags & ATA_CONFIG_PIO_SET) { 1149 drvp->PIO_mode = 1150 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1151 drvp->drive_flags |= DRIVE_MODE; 1152 } 1153 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1154 /* don't care about DMA modes */ 1155 return; 1156 } 1157 if (cf_flags & ATA_CONFIG_DMA_SET) { 1158 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1159 ATA_CONFIG_DMA_DISABLE) { 1160 drvp->drive_flags &= ~DRIVE_DMA; 1161 } else { 1162 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1163 ATA_CONFIG_DMA_OFF; 1164 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1165 } 1166 } 1167 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1168 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1169 ATA_CONFIG_UDMA_DISABLE) { 1170 drvp->drive_flags &= ~DRIVE_UDMA; 1171 } else { 1172 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1173 ATA_CONFIG_UDMA_OFF; 1174 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1175 } 1176 } 1177 } 1178 1179 /* 1180 * downgrade the transfer mode of a drive after an error. return 1 if 1181 * downgrade was possible, 0 otherwise. 1182 */ 1183 int 1184 wdc_downgrade_mode(drvp) 1185 struct ata_drive_datas *drvp; 1186 { 1187 struct channel_softc *chp = drvp->chnl_softc; 1188 struct device *drv_dev = drvp->drv_softc; 1189 struct wdc_softc *wdc = chp->wdc; 1190 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1191 1192 /* if drive or controller don't know its mode, we can't do much */ 1193 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1194 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1195 return 0; 1196 /* current drive mode was set by a config flag, let it this way */ 1197 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1198 (cf_flags & ATA_CONFIG_DMA_SET) || 1199 (cf_flags & ATA_CONFIG_UDMA_SET)) 1200 return 0; 1201 1202 /* 1203 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1204 * Maybe we didn't properly notice the cable type 1205 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1206 * It helps in some cases. 1207 */ 1208 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1209 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1210 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1211 drv_dev->dv_xname, drvp->UDMA_mode); 1212 } 1213 1214 /* 1215 * If we were using ultra-DMA, don't downgrade to multiword DMA 1216 * if we noticed a CRC error. It has been noticed that CRC errors 1217 * in ultra-DMA lead to silent data corruption in multiword DMA. 1218 * Data corruption is less likely to occur in PIO mode. 1219 */ 1220 else if ((drvp->drive_flags & DRIVE_UDMA) && 1221 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1222 drvp->drive_flags &= ~DRIVE_UDMA; 1223 drvp->drive_flags |= DRIVE_DMA; 1224 drvp->DMA_mode = drvp->DMA_cap; 1225 printf("%s: transfer error, downgrading to DMA mode %d\n", 1226 drv_dev->dv_xname, drvp->DMA_mode); 1227 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1228 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1229 drvp->PIO_mode = drvp->PIO_cap; 1230 printf("%s: transfer error, downgrading to PIO mode %d\n", 1231 drv_dev->dv_xname, drvp->PIO_mode); 1232 } else /* already using PIO, can't downgrade */ 1233 return 0; 1234 1235 wdc->set_modes(chp); 1236 /* reset the channel, which will shedule all drives for setup */ 1237 wdc_reset_channel(drvp); 1238 return 1; 1239 } 1240 1241 int 1242 wdc_exec_command(drvp, wdc_c) 1243 struct ata_drive_datas *drvp; 1244 struct wdc_command *wdc_c; 1245 { 1246 struct channel_softc *chp = drvp->chnl_softc; 1247 struct wdc_xfer *xfer; 1248 int s, ret; 1249 1250 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1251 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1252 DEBUG_FUNCS); 1253 1254 /* set up an xfer and queue. Wait for completion */ 1255 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1256 WDC_NOSLEEP); 1257 if (xfer == NULL) { 1258 return WDC_TRY_AGAIN; 1259 } 1260 1261 if (wdc_c->flags & AT_POLL) 1262 xfer->c_flags |= C_POLL; 1263 xfer->drive = drvp->drive; 1264 xfer->databuf = wdc_c->data; 1265 xfer->c_bcount = wdc_c->bcount; 1266 xfer->cmd = wdc_c; 1267 xfer->c_start = __wdccommand_start; 1268 xfer->c_intr = __wdccommand_intr; 1269 xfer->c_kill_xfer = __wdccommand_done; 1270 1271 s = splbio(); 1272 wdc_exec_xfer(chp, xfer); 1273 #ifdef DIAGNOSTIC 1274 if ((wdc_c->flags & AT_POLL) != 0 && 1275 (wdc_c->flags & AT_DONE) == 0) 1276 panic("wdc_exec_command: polled command not done\n"); 1277 #endif 1278 if (wdc_c->flags & AT_DONE) { 1279 ret = WDC_COMPLETE; 1280 } else { 1281 if (wdc_c->flags & AT_WAIT) { 1282 while ((wdc_c->flags & AT_DONE) == 0) { 1283 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1284 } 1285 ret = WDC_COMPLETE; 1286 } else { 1287 ret = WDC_QUEUED; 1288 } 1289 } 1290 splx(s); 1291 return ret; 1292 } 1293 1294 void 1295 __wdccommand_start(chp, xfer) 1296 struct channel_softc *chp; 1297 struct wdc_xfer *xfer; 1298 { 1299 int drive = xfer->drive; 1300 struct wdc_command *wdc_c = xfer->cmd; 1301 1302 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1303 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1304 DEBUG_FUNCS); 1305 1306 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1307 WDSD_IBM | (drive << 4)); 1308 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1309 wdc_c->timeout) != 0) { 1310 wdc_c->flags |= AT_TIMEOU; 1311 __wdccommand_done(chp, xfer); 1312 return; 1313 } 1314 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1315 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1316 if ((wdc_c->flags & AT_POLL) == 0) { 1317 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1318 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1319 wdctimeout, chp); 1320 return; 1321 } 1322 /* 1323 * Polled command. Wait for drive ready or drq. Done in intr(). 1324 * Wait for at last 400ns for status bit to be valid. 1325 */ 1326 delay(10); 1327 __wdccommand_intr(chp, xfer, 0); 1328 } 1329 1330 int 1331 __wdccommand_intr(chp, xfer, irq) 1332 struct channel_softc *chp; 1333 struct wdc_xfer *xfer; 1334 int irq; 1335 { 1336 struct wdc_command *wdc_c = xfer->cmd; 1337 int bcount = wdc_c->bcount; 1338 char *data = wdc_c->data; 1339 1340 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1341 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1342 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1343 (irq == 0) ? wdc_c->timeout : 0)) { 1344 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1345 return 0; /* IRQ was not for us */ 1346 wdc_c->flags |= AT_TIMEOU; 1347 __wdccommand_done(chp, xfer); 1348 return 1; 1349 } 1350 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1351 chp->wdc->irqack(chp); 1352 if (wdc_c->flags & AT_READ) { 1353 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1354 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1355 0, (u_int32_t*)data, bcount >> 2); 1356 data += bcount & 0xfffffffc; 1357 bcount = bcount & 0x03; 1358 } 1359 if (bcount > 0) 1360 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1361 wd_data, (u_int16_t *)data, bcount >> 1); 1362 } else if (wdc_c->flags & AT_WRITE) { 1363 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1364 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1365 0, (u_int32_t*)data, bcount >> 2); 1366 data += bcount & 0xfffffffc; 1367 bcount = bcount & 0x03; 1368 } 1369 if (bcount > 0) 1370 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1371 wd_data, (u_int16_t *)data, bcount >> 1); 1372 } 1373 __wdccommand_done(chp, xfer); 1374 return 1; 1375 } 1376 1377 void 1378 __wdccommand_done(chp, xfer) 1379 struct channel_softc *chp; 1380 struct wdc_xfer *xfer; 1381 { 1382 struct wdc_command *wdc_c = xfer->cmd; 1383 1384 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1385 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1386 1387 callout_stop(&chp->ch_callout); 1388 1389 if (chp->ch_status & WDCS_DWF) 1390 wdc_c->flags |= AT_DF; 1391 if (chp->ch_status & WDCS_ERR) { 1392 wdc_c->flags |= AT_ERROR; 1393 wdc_c->r_error = chp->ch_error; 1394 } 1395 wdc_c->flags |= AT_DONE; 1396 if ((wdc_c->flags & AT_READREG) != 0 && 1397 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1398 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1399 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1400 wd_sdh); 1401 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1402 wd_cyl_hi) << 8; 1403 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1404 wd_cyl_lo); 1405 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1406 wd_sector); 1407 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1408 wd_seccnt); 1409 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1410 wd_error); 1411 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1412 wd_precomp); 1413 } 1414 wdc_free_xfer(chp, xfer); 1415 if (wdc_c->flags & AT_WAIT) 1416 wakeup(wdc_c); 1417 else if (wdc_c->callback) 1418 wdc_c->callback(wdc_c->callback_arg); 1419 wdcstart(chp); 1420 return; 1421 } 1422 1423 /* 1424 * Send a command. The drive should be ready. 1425 * Assumes interrupts are blocked. 1426 */ 1427 void 1428 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1429 struct channel_softc *chp; 1430 u_int8_t drive; 1431 u_int8_t command; 1432 u_int16_t cylin; 1433 u_int8_t head, sector, count, precomp; 1434 { 1435 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1436 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1437 chp->channel, drive, command, cylin, head, sector, count, precomp), 1438 DEBUG_FUNCS); 1439 1440 /* Select drive, head, and addressing mode. */ 1441 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1442 WDSD_IBM | (drive << 4) | head); 1443 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1444 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1445 precomp); 1446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1447 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1448 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1449 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1450 1451 /* Send command. */ 1452 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1453 return; 1454 } 1455 1456 /* 1457 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1458 * tested by the caller. 1459 */ 1460 void 1461 wdccommandshort(chp, drive, command) 1462 struct channel_softc *chp; 1463 int drive; 1464 int command; 1465 { 1466 1467 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1468 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1469 DEBUG_FUNCS); 1470 1471 /* Select drive. */ 1472 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1473 WDSD_IBM | (drive << 4)); 1474 1475 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1476 } 1477 1478 /* Add a command to the queue and start controller. Must be called at splbio */ 1479 1480 void 1481 wdc_exec_xfer(chp, xfer) 1482 struct channel_softc *chp; 1483 struct wdc_xfer *xfer; 1484 { 1485 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1486 chp->channel, xfer->drive), DEBUG_XFERS); 1487 1488 /* complete xfer setup */ 1489 xfer->chp = chp; 1490 1491 /* 1492 * If we are a polled command, and the list is not empty, 1493 * we are doing a dump. Drop the list to allow the polled command 1494 * to complete, we're going to reboot soon anyway. 1495 */ 1496 if ((xfer->c_flags & C_POLL) != 0 && 1497 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1498 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1499 } 1500 /* insert at the end of command list */ 1501 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1502 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1503 chp->ch_flags), DEBUG_XFERS); 1504 wdcstart(chp); 1505 } 1506 1507 struct wdc_xfer * 1508 wdc_get_xfer(flags) 1509 int flags; 1510 { 1511 struct wdc_xfer *xfer; 1512 int s; 1513 1514 s = splbio(); 1515 xfer = pool_get(&wdc_xfer_pool, 1516 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1517 splx(s); 1518 memset(xfer, 0, sizeof(struct wdc_xfer)); 1519 return xfer; 1520 } 1521 1522 void 1523 wdc_free_xfer(chp, xfer) 1524 struct channel_softc *chp; 1525 struct wdc_xfer *xfer; 1526 { 1527 struct wdc_softc *wdc = chp->wdc; 1528 int s; 1529 1530 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1531 (*wdc->free_hw)(chp); 1532 s = splbio(); 1533 chp->ch_flags &= ~WDCF_ACTIVE; 1534 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1535 pool_put(&wdc_xfer_pool, xfer); 1536 splx(s); 1537 } 1538 1539 /* 1540 * Kill off all pending xfers for a channel_softc. 1541 * 1542 * Must be called at splbio(). 1543 */ 1544 void 1545 wdc_kill_pending(chp) 1546 struct channel_softc *chp; 1547 { 1548 struct wdc_xfer *xfer; 1549 1550 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1551 chp = xfer->chp; 1552 (*xfer->c_kill_xfer)(chp, xfer); 1553 } 1554 } 1555 1556 static void 1557 __wdcerror(chp, msg) 1558 struct channel_softc *chp; 1559 char *msg; 1560 { 1561 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1562 1563 if (xfer == NULL) 1564 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1565 msg); 1566 else 1567 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1568 chp->channel, xfer->drive, msg); 1569 } 1570 1571 /* 1572 * the bit bucket 1573 */ 1574 void 1575 wdcbit_bucket(chp, size) 1576 struct channel_softc *chp; 1577 int size; 1578 { 1579 1580 for (; size >= 2; size -= 2) 1581 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1582 if (size) 1583 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1584 } 1585 1586 int 1587 wdc_addref(chp) 1588 struct channel_softc *chp; 1589 { 1590 struct wdc_softc *wdc = chp->wdc; 1591 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1592 int s, error = 0; 1593 1594 s = splbio(); 1595 if (adapt->adapt_refcnt++ == 0 && 1596 adapt->adapt_enable != NULL) { 1597 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1598 if (error) 1599 adapt->adapt_refcnt--; 1600 } 1601 splx(s); 1602 return (error); 1603 } 1604 1605 void 1606 wdc_delref(chp) 1607 struct channel_softc *chp; 1608 { 1609 struct wdc_softc *wdc = chp->wdc; 1610 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1611 int s; 1612 1613 s = splbio(); 1614 if (adapt->adapt_refcnt-- == 1 && 1615 adapt->adapt_enable != NULL) 1616 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1617 splx(s); 1618 } 1619 1620 void 1621 wdc_print_modes(struct channel_softc *chp) 1622 { 1623 int drive; 1624 struct ata_drive_datas *drvp; 1625 1626 for (drive = 0; drive < 2; drive++) { 1627 drvp = &chp->ch_drive[drive]; 1628 if ((drvp->drive_flags & DRIVE) == 0) 1629 continue; 1630 printf("%s(%s:%d:%d): using PIO mode %d", 1631 drvp->drv_softc->dv_xname, 1632 chp->wdc->sc_dev.dv_xname, 1633 chp->channel, drive, drvp->PIO_mode); 1634 if (drvp->drive_flags & DRIVE_DMA) 1635 printf(", DMA mode %d", drvp->DMA_mode); 1636 if (drvp->drive_flags & DRIVE_UDMA) { 1637 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1638 if (drvp->UDMA_mode == 2) 1639 printf(" (Ultra/33)"); 1640 else if (drvp->UDMA_mode == 4) 1641 printf(" (Ultra/66)"); 1642 else if (drvp->UDMA_mode == 5) 1643 printf(" (Ultra/100)"); 1644 } 1645 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1646 printf(" (using DMA data transfers)"); 1647 printf("\n"); 1648 } 1649 } 1650
Indexes created Thu Sep 25 02:09:54 GMT 2025