wdcreg.h revision 1.16
1 /* $NetBSD: wdcreg.h,v 1.16 1998/04/23 10:37:01 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 39 */ 40 41 /* 42 * Disk Controller register definitions. 43 */ 44 45 /* offsets of registers in the 'regular' register region */ 46 #define wd_data 0 /* data register (R/W - 16 bits) */ 47 #define wd_error 1 /* error register (R) */ 48 #define wd_precomp 1 /* write precompensation (W) */ 49 #define wd_features 1 /* features (W) */ 50 #define wd_seccnt 2 /* sector count (R/W) */ 51 #define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */ 52 #define wd_sector 3 /* first sector number (R/W) */ 53 #define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */ 54 #define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */ 55 #define wd_sdh 6 /* sector size/drive/head (R/W) */ 56 #define wd_command 7 /* command register (W) */ 57 #define wd_status 7 /* immediate status (R) */ 58 59 /* offsets of registers in the auxiliary register region */ 60 #define wd_aux_altsts 0 /* alternate fixed disk status (R) */ 61 #define wd_aux_ctlr 0 /* fixed disk controller control (W) */ 62 #define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ 63 #define WDCTL_RST 0x04 /* reset the controller */ 64 #define WDCTL_IDS 0x02 /* disable controller interrupts */ 65 #if 0 /* NOT MAPPED; fd uses this register on PCs */ 66 #define wd_digin 1 /* disk controller input (R) */ 67 #endif 68 69 /* 70 * Status bits. 71 */ 72 #define WDCS_BSY 0x80 /* busy */ 73 #define WDCS_DRDY 0x40 /* drive ready */ 74 #define WDCS_DWF 0x20 /* drive write fault */ 75 #define WDCS_DSC 0x10 /* drive seek complete */ 76 #define WDCS_DRQ 0x08 /* data request */ 77 #define WDCS_CORR 0x04 /* corrected data */ 78 #define WDCS_IDX 0x02 /* index */ 79 #define WDCS_ERR 0x01 /* error */ 80 #define WDCS_BITS "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 81 82 /* 83 * Error bits. 84 */ 85 #define WDCE_BBK 0x80 /* bad block detected */ 86 #define WDCE_UNC 0x40 /* uncorrectable data error */ 87 #define WDCE_MC 0x20 /* media changed */ 88 #define WDCE_IDNF 0x10 /* id not found */ 89 #define WDCE_MCR 0x08 /* media change requested */ 90 #define WDCE_ABRT 0x04 /* aborted command */ 91 #define WDCE_TK0NF 0x02 /* track 0 not found */ 92 #define WDCE_AMNF 0x01 /* address mark not found */ 93 #define WDERR_BITS "\020\010bbk\007unc\006mc\005idnf\004mcr\003abrt\002tk0nf\001amnf" 94 95 /* 96 * Commands for Disk Controller. 97 */ 98 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 99 100 #define WDCC_READ 0x20 /* disk read code */ 101 #define WDCC_WRITE 0x30 /* disk write code */ 102 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 103 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 104 105 #define WDCC_FORMAT 0x50 /* disk format code */ 106 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 107 #define WDCC_IDP 0x91 /* initialize drive parameters */ 108 109 #define WDCC_READMULTI 0xc4 /* read multiple */ 110 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 111 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 112 113 #define WDCC_READDMA 0xc8 /* read with DMA */ 114 #define WDCC_WRITEDMA 0xca /* write with DMA */ 115 116 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 117 #define WDCC_LOCK 0xde /* lock drawer */ 118 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 119 120 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 121 #define WDCC_CACHEC 0xef /* cache control */ 122 123 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 124 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 125 #define WDSD_LBA 0x40 /* logical block addressing */ 126 127 /* Commands for ATAPI devices */ 128 #define ATAPI_CHECK_POWER_MODE 0xe5 129 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 130 #define ATAPI_IDLE_IMMEDIATE 0xe1 131 #define ATAPI_NOP 0x00 132 #define ATAPI_PACKET_COMMAND 0xa0 133 #define ATAPI_IDENTIFY_DEVICE 0xa1 134 #define ATAPI_SOFT_RESET 0x08 135 #define ATAPI_SET_FEATURES 0xef 136 #define ATAPI_SLEEP 0xe6 137 #define ATAPI_STANDBY_IMMEDIATE 0xe0 138 139 /* ireason */ 140 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 141 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 142 #define WDCI_RELEASE 0x04 /* bus released until completion */ 143 144 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 145 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 146 #define PHASE_DATAOUT WDCS_DRQ 147 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 148 #define PHASE_ABORTED 0 149 150 151 #ifdef _KERNEL 152 /* 153 * read parameters command returns this: 154 */ 155 struct wdparams { 156 /* drive info */ 157 short wdp_config; /* general configuration */ 158 #define WD_CFG_REMOVABLE 0x0080 159 #define WD_CFG_FIXED 0x0040 160 short wdp_cylinders; /* number of non-removable cylinders */ 161 char __reserved1[2]; 162 short wdp_heads; /* number of heads */ 163 short wdp_unfbytespertrk; /* number of unformatted bytes/track */ 164 short wdp_unfbytespersec; /* number of unformatted bytes/sector */ 165 short wdp_sectors; /* number of sectors */ 166 char wdp_vendor1[6]; 167 /* controller info */ 168 char wdp_serial[20]; /* serial number */ 169 short wdp_buftype; /* buffer type */ 170 #define WD_BUF_SINGLEPORTSECTOR 1 /* single port, single sector buffer */ 171 #define WD_BUF_DUALPORTMULTI 2 /* dual port, multiple sector buffer */ 172 #define WD_BUF_DUALPORTMULTICACHE 3 /* above plus track cache */ 173 short wdp_bufsize; /* buffer size, in 512-byte units */ 174 short wdp_eccbytes; /* ecc bytes appended */ 175 char wdp_revision[8]; /* firmware revision */ 176 char wdp_model[40]; /* model name */ 177 u_char wdp_maxmulti; /* maximum sectors per interrupt */ 178 char wdp_vendor2[1]; 179 short wdp_usedmovsd; /* can use double word read/write? */ 180 char wdp_vendor3[1]; 181 char wdp_capabilities; /* capability flags */ 182 #define WD_CAP_LBA 0x02 183 #define WD_CAP_DMA 0x01 184 char __reserved2[2]; 185 char wdp_vendor4[1]; 186 char wdp_piotiming; /* PIO timing mode */ 187 char wdp_vendor5[1]; 188 char wdp_dmatiming; /* DMA timing mode */ 189 }; 190 #endif /* _KERNEL */ 191
Indexes created Tue Sep 30 11:09:46 GMT 2025