wdcvar.h revision 1.2 1 1.2 leo /* $NetBSD: wdcvar.h,v 1.2 1998/04/07 19:51:58 leo Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.1 cgd * Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved.
5 1.1 cgd *
6 1.1 cgd * DMA and multi-sector PIO handling are derived from code contributed by
7 1.1 cgd * Onno van der Linden.
8 1.1 cgd *
9 1.1 cgd * Atapi support added by Manuel Bouyer.
10 1.1 cgd *
11 1.1 cgd * bus_space-ified by Christopher G. Demetriou.
12 1.1 cgd *
13 1.1 cgd * Redistribution and use in source and binary forms, with or without
14 1.1 cgd * modification, are permitted provided that the following conditions
15 1.1 cgd * are met:
16 1.1 cgd * 1. Redistributions of source code must retain the above copyright
17 1.1 cgd * notice, this list of conditions and the following disclaimer.
18 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 cgd * notice, this list of conditions and the following disclaimer in the
20 1.1 cgd * documentation and/or other materials provided with the distribution.
21 1.1 cgd * 3. All advertising materials mentioning features or use of this software
22 1.1 cgd * must display the following acknowledgement:
23 1.1 cgd * This product includes software developed by Charles M. Hannum.
24 1.1 cgd * 4. The name of the author may not be used to endorse or promote products
25 1.1 cgd * derived from this software without specific prior written permission.
26 1.1 cgd *
27 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 1.1 cgd * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 1.1 cgd * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 1.1 cgd * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 1.1 cgd * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 1.1 cgd * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 1.1 cgd * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 1.1 cgd * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 1.1 cgd * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 1.1 cgd * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 1.1 cgd */
38 1.1 cgd
39 1.1 cgd struct wdc_attachment_data {
40 1.1 cgd /* manadatory fields */
41 1.1 cgd int cap;
42 1.1 cgd bus_space_tag_t iot;
43 1.1 cgd bus_space_handle_t ioh;
44 1.1 cgd bus_space_tag_t auxiot;
45 1.1 cgd bus_space_handle_t auxioh;
46 1.1 cgd /*
47 1.1 cgd * XXX data access (normal and 32-bit) may need to be
48 1.1 cgd * done via a separate iot/ioh on some systems. Let's
49 1.1 cgd * wait and see if that's the case before implementing
50 1.1 cgd * it.
51 1.1 cgd */
52 1.1 cgd
53 1.1 cgd /* if WDC_CAPABILITY_DMA set in 'cap' */
54 1.1 cgd void *dma_arg;
55 1.1 cgd void (*dma_setup) __P((void *));
56 1.1 cgd void (*dma_start) __P((void *, void *, size_t,
57 1.1 cgd int));
58 1.1 cgd void (*dma_finish) __P((void *));
59 1.2 leo
60 1.2 leo /* if WDC_CAPABILITY_HWLOCK set in 'cap' */
61 1.2 leo int (*claim_hw) __P((void *, int));
62 1.2 leo void (*free_hw) __P((void *));
63 1.1 cgd };
64 1.1 cgd
65 1.1 cgd /* Capabilities supported by the controller */
66 1.1 cgd #define WDC_CAPABILITY_DATA32 0x01 /* 32-bit data access */
67 1.1 cgd #define WDC_CAPABILITY_DMA 0x02 /* DMA */
68 1.2 leo #define WDC_CAPABILITY_HWLOCK 0x04 /* Needs to lock HW */
69 1.1 cgd
70 1.1 cgd struct wdc_softc {
71 1.1 cgd struct device sc_dev;
72 1.1 cgd const struct wdc_attachment_data *sc_adp;
73 1.1 cgd
74 1.1 cgd struct wd_link *d_link[2];
75 1.1 cgd struct scsipi_link *ab_link;
76 1.1 cgd
77 1.1 cgd TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
78 1.1 cgd int sc_flags;
79 1.1 cgd #define WDCF_ACTIVE 0x01 /* controller is active */
80 1.1 cgd #define WDCF_SINGLE 0x02 /* sector at a time mode */
81 1.1 cgd #define WDCF_ERROR 0x04 /* processing a disk error */
82 1.1 cgd #define WDCF_WANTED 0x08 /* XXX locking for wd_get_parms() */
83 1.1 cgd #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */
84 1.1 cgd #define WDCF_ONESLAVE 0x20 /* ctrl. has one ATAPI slave attached */
85 1.1 cgd int sc_errors; /* errors during current transfer */
86 1.1 cgd u_char sc_status; /* copy of status register */
87 1.1 cgd u_char sc_error; /* copy of error register */
88 1.1 cgd u_char sc_drives_mask; /* bitmask for drives present/absent */
89 1.1 cgd };
90 1.1 cgd
91 1.1 cgd #define sc_cap sc_adp->cap
92 1.1 cgd #define sc_iot sc_adp->iot
93 1.1 cgd #define sc_ioh sc_adp->ioh
94 1.1 cgd #define sc_auxiot sc_adp->auxiot
95 1.1 cgd #define sc_auxioh sc_adp->auxioh
96 1.1 cgd #define sc_dma_arg sc_adp->dma_arg
97 1.1 cgd #define sc_dma_setup sc_adp->dma_setup
98 1.1 cgd #define sc_dma_start sc_adp->dma_start
99 1.1 cgd #define sc_dma_finish sc_adp->dma_finish
100 1.2 leo #define sc_claim_hw sc_adp->claim_hw
101 1.2 leo #define sc_free_hw sc_adp->free_hw
102 1.1 cgd
103 1.1 cgd void wdcattach(struct wdc_softc *, const struct wdc_attachment_data *);
104 1.1 cgd int wdcintr(void *);
105 1.1 cgd int wdcprobe(const struct wdc_attachment_data *);
106