wdcvar.h revision 1.11
1 /* $NetBSD: wdcvar.h,v 1.11 1998/12/02 15:53:35 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* XXX for scsipi_adapter */ 40 #include <dev/scsipi/scsipi_all.h> 41 #include <dev/scsipi/scsipiconf.h> 42 43 #define WAITTIME (10 * hz) /* time to wait for a completion */ 44 /* this is a lot for hard drives, but not for cdroms */ 45 46 struct channel_queue { /* per channel queue (may be shared) */ 47 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 48 }; 49 50 struct channel_softc { /* Per channel data */ 51 /* Our location */ 52 int channel; 53 /* Our controller's softc */ 54 struct wdc_softc *wdc; 55 /* Our registers */ 56 bus_space_tag_t cmd_iot; 57 bus_space_handle_t cmd_ioh; 58 bus_space_tag_t ctl_iot; 59 bus_space_handle_t ctl_ioh; 60 /* data32{iot,ioh} are only used for 32 bit xfers */ 61 bus_space_tag_t data32iot; 62 bus_space_handle_t data32ioh; 63 /* Our state */ 64 int ch_flags; 65 #define WDCF_ACTIVE 0x01 /* channel is active */ 66 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 67 u_int8_t ch_status; /* copy of status register */ 68 u_int8_t ch_error; /* copy of error register */ 69 /* per-drive infos */ 70 struct ata_drive_datas ch_drive[2]; 71 72 /* 73 * channel queues. May be the same for all channels, if hw channels 74 * are not independants 75 */ 76 struct channel_queue *ch_queue; 77 }; 78 79 struct wdc_softc { /* Per controller state */ 80 struct device sc_dev; 81 /* mandatory fields */ 82 int cap; 83 /* Capabilities supported by the controller */ 84 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 85 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 86 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 87 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 88 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 89 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 90 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 91 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 92 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 93 u_int8_t pio_mode; /* highest PIO mode supported */ 94 u_int8_t dma_mode; /* highest DMA mode supported */ 95 int nchannels; /* Number of channels on this controller */ 96 struct channel_softc **channels; /* channels-specific datas (array) */ 97 98 /* 99 * The reference count here is used for both IDE and ATAPI devices. 100 */ 101 struct scsipi_adapter sc_atapi_adapter; 102 103 /* if WDC_CAPABILITY_DMA set in 'cap' */ 104 void *dma_arg; 105 int (*dma_init) __P((void *, int, int, void *, size_t, 106 int)); 107 void (*dma_start) __P((void *, int, int, int)); 108 int (*dma_finish) __P((void *, int, int, int)); 109 /* flags passed to DMA functions */ 110 #define WDC_DMA_READ 0x01 111 #define WDC_DMA_POLL 0x02 112 113 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 114 int (*claim_hw) __P((void *, int)); 115 void (*free_hw) __P((void *)); 116 }; 117 118 /* 119 * Description of a command to be handled by a controller. 120 * These commands are queued in a list. 121 */ 122 struct wdc_xfer { 123 volatile u_int c_flags; 124 #define C_INUSE 0x0001 /* xfer struct is in use */ 125 #define C_ATAPI 0x0002 /* xfer is ATAPI request */ 126 #define C_TIMEOU 0x0004 /* xfer processing timed out */ 127 #define C_NEEDDONE 0x0010 /* need to call upper-level done */ 128 #define C_POLL 0x0020 /* cmd is polled */ 129 #define C_DMA 0x0040 /* cmd uses DMA */ 130 #define C_SENSE 0x0080 /* cmd is a internal command */ 131 132 /* Informations about our location */ 133 struct channel_softc *chp; 134 u_int8_t drive; 135 136 /* Information about the current transfer */ 137 void *cmd; /* wdc, ata or scsipi command structure */ 138 void *databuf; 139 int c_bcount; /* byte count left */ 140 int c_skip; /* bytes already transferred */ 141 TAILQ_ENTRY(wdc_xfer) c_xferchain; 142 LIST_ENTRY(wdc_xfer) free_list; 143 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 144 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *)); 145 }; 146 147 /* 148 * Public functions which can be called by ATA or ATAPI specific parts, 149 * or bus-specific backends. 150 */ 151 152 int wdcprobe __P((struct channel_softc *)); 153 void wdcattach __P((struct channel_softc *)); 154 int wdcintr __P((void *)); 155 void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 156 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 157 #define WDC_CANSLEEP 0x00 158 #define WDC_NOSLEEP 0x01 159 void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 160 void wdcstart __P((struct channel_softc *)); 161 void wdcrestart __P((void*)); 162 int wdcreset __P((struct channel_softc *, int)); 163 #define VERBOSE 1 164 #define SILENT 0 /* wdcreset will not print errors */ 165 int wdcwait __P((struct channel_softc *, int, int, int)); 166 void wdcbit_bucket __P(( struct channel_softc *, int)); 167 void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 168 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 169 void wdccommandshort __P((struct channel_softc *, int, int)); 170 void wdctimeout __P((void *arg)); 171 172 int wdc_addref __P((struct channel_softc *)); 173 void wdc_delref __P((struct channel_softc *)); 174 175 /* 176 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 177 * command is aborted. 178 */ 179 #define wait_for_drq(chp, timeout) wdcwait((chp), \ 180 WDCS_DRDY | WDCS_DSC | WDCS_DRQ, \ 181 WDCS_DRDY | WDCS_DSC | WDCS_DRQ, (timeout)) 182 #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 183 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY | WDCS_DSC, \ 184 WDCS_DRDY | WDCS_DSC, (timeout)) 185 /* ATA/ATAPI specs says a device can take 31s to reset */ 186 #define WDC_RESET_WAIT 31000 187 188 void wdc_atapibus_attach __P((struct channel_softc *)); 189 int atapi_print __P((void *, const char *)); 190
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