wdcvar.h revision 1.13
1 /* $NetBSD: wdcvar.h,v 1.13 1998/12/03 18:24:31 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* XXX for scsipi_adapter */ 40 #include <dev/scsipi/scsipi_all.h> 41 #include <dev/scsipi/scsipiconf.h> 42 43 #define WAITTIME (10 * hz) /* time to wait for a completion */ 44 /* this is a lot for hard drives, but not for cdroms */ 45 46 struct channel_queue { /* per channel queue (may be shared) */ 47 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 48 }; 49 50 struct channel_softc { /* Per channel data */ 51 /* Our location */ 52 int channel; 53 /* Our controller's softc */ 54 struct wdc_softc *wdc; 55 /* Our registers */ 56 bus_space_tag_t cmd_iot; 57 bus_space_handle_t cmd_ioh; 58 bus_space_tag_t ctl_iot; 59 bus_space_handle_t ctl_ioh; 60 /* data32{iot,ioh} are only used for 32 bit xfers */ 61 bus_space_tag_t data32iot; 62 bus_space_handle_t data32ioh; 63 /* Our state */ 64 int ch_flags; 65 #define WDCF_ACTIVE 0x01 /* channel is active */ 66 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 67 u_int8_t ch_status; /* copy of status register */ 68 u_int8_t ch_error; /* copy of error register */ 69 /* per-drive infos */ 70 struct ata_drive_datas ch_drive[2]; 71 72 /* 73 * channel queues. May be the same for all channels, if hw channels 74 * are not independants 75 */ 76 struct channel_queue *ch_queue; 77 }; 78 79 struct wdc_softc { /* Per controller state */ 80 struct device sc_dev; 81 /* mandatory fields */ 82 int cap; 83 /* Capabilities supported by the controller */ 84 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 85 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 86 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 87 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 88 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 89 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 90 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 91 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 92 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 93 u_int8_t PIO_cap; /* highest PIO mode supported */ 94 u_int8_t DMA_cap; /* highest DMA mode supported */ 95 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 96 int nchannels; /* Number of channels on this controller */ 97 struct channel_softc **channels; /* channels-specific datas (array) */ 98 99 /* 100 * The reference count here is used for both IDE and ATAPI devices. 101 */ 102 struct scsipi_adapter sc_atapi_adapter; 103 104 /* if WDC_CAPABILITY_DMA set in 'cap' */ 105 void *dma_arg; 106 int (*dma_init) __P((void *, int, int, void *, size_t, 107 int)); 108 void (*dma_start) __P((void *, int, int, int)); 109 int (*dma_finish) __P((void *, int, int, int)); 110 /* flags passed to DMA functions */ 111 #define WDC_DMA_READ 0x01 112 #define WDC_DMA_POLL 0x02 113 114 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 115 int (*claim_hw) __P((void *, int)); 116 void (*free_hw) __P((void *)); 117 }; 118 119 /* 120 * Description of a command to be handled by a controller. 121 * These commands are queued in a list. 122 */ 123 struct wdc_xfer { 124 volatile u_int c_flags; 125 #define C_INUSE 0x0001 /* xfer struct is in use */ 126 #define C_ATAPI 0x0002 /* xfer is ATAPI request */ 127 #define C_TIMEOU 0x0004 /* xfer processing timed out */ 128 #define C_NEEDDONE 0x0010 /* need to call upper-level done */ 129 #define C_POLL 0x0020 /* cmd is polled */ 130 #define C_DMA 0x0040 /* cmd uses DMA */ 131 #define C_SENSE 0x0080 /* cmd is a internal command */ 132 133 /* Informations about our location */ 134 struct channel_softc *chp; 135 u_int8_t drive; 136 137 /* Information about the current transfer */ 138 void *cmd; /* wdc, ata or scsipi command structure */ 139 void *databuf; 140 int c_bcount; /* byte count left */ 141 int c_skip; /* bytes already transferred */ 142 TAILQ_ENTRY(wdc_xfer) c_xferchain; 143 LIST_ENTRY(wdc_xfer) free_list; 144 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 145 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *)); 146 }; 147 148 /* 149 * Public functions which can be called by ATA or ATAPI specific parts, 150 * or bus-specific backends. 151 */ 152 153 int wdcprobe __P((struct channel_softc *)); 154 void wdcattach __P((struct channel_softc *)); 155 int wdcintr __P((void *)); 156 void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 157 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 158 #define WDC_CANSLEEP 0x00 159 #define WDC_NOSLEEP 0x01 160 void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 161 void wdcstart __P((struct channel_softc *)); 162 void wdcrestart __P((void*)); 163 int wdcreset __P((struct channel_softc *, int)); 164 #define VERBOSE 1 165 #define SILENT 0 /* wdcreset will not print errors */ 166 int wdcwait __P((struct channel_softc *, int, int, int)); 167 void wdcbit_bucket __P(( struct channel_softc *, int)); 168 void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 169 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 170 void wdccommandshort __P((struct channel_softc *, int, int)); 171 void wdctimeout __P((void *arg)); 172 173 int wdc_addref __P((struct channel_softc *)); 174 void wdc_delref __P((struct channel_softc *)); 175 176 /* 177 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 178 * command is aborted. 179 */ 180 #define wait_for_drq(chp, timeout) wdcwait((chp), \ 181 WDCS_DRDY | WDCS_DSC | WDCS_DRQ, \ 182 WDCS_DRDY | WDCS_DSC | WDCS_DRQ, (timeout)) 183 #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 184 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY | WDCS_DSC, \ 185 WDCS_DRDY | WDCS_DSC, (timeout)) 186 /* ATA/ATAPI specs says a device can take 31s to reset */ 187 #define WDC_RESET_WAIT 31000 188 189 void wdc_atapibus_attach __P((struct channel_softc *)); 190 int atapi_print __P((void *, const char *)); 191
Indexes created Wed Oct 22 06:10:02 GMT 2025