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wdcvar.h revision 1.19.6.1
      1 /*	$NetBSD: wdcvar.h,v 1.19.6.1 1999/12/27 18:34:53 wrstuden Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *	notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *	notice, this list of conditions and the following disclaimer in the
     17  *	documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /* XXX for scsipi_adapter */
     40 #include <dev/scsipi/scsipi_all.h>
     41 #include <dev/scsipi/scsipiconf.h>
     42 
     43 #define	WAITTIME    (10 * hz)    /* time to wait for a completion */
     44 	/* this is a lot for hard drives, but not for cdroms */
     45 
     46 struct channel_queue {  /* per channel queue (may be shared) */
     47 	TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
     48 };
     49 
     50 struct channel_softc { /* Per channel data */
     51 	/* Our location */
     52 	int channel;
     53 	/* Our controller's softc */
     54 	struct wdc_softc *wdc;
     55 	/* Our registers */
     56 	bus_space_tag_t       cmd_iot;
     57 	bus_space_handle_t    cmd_ioh;
     58 	bus_space_tag_t       ctl_iot;
     59 	bus_space_handle_t    ctl_ioh;
     60 	/* data32{iot,ioh} are only used for 32 bit xfers */
     61 	bus_space_tag_t         data32iot;
     62 	bus_space_handle_t      data32ioh;
     63 	/* Our state */
     64 	int ch_flags;
     65 #define WDCF_ACTIVE   0x01	/* channel is active */
     66 #define WDCF_IRQ_WAIT 0x10	/* controller is waiting for irq */
     67 	u_int8_t ch_status;         /* copy of status register */
     68 	u_int8_t ch_error;          /* copy of error register */
     69 	/* per-drive infos */
     70 	struct ata_drive_datas ch_drive[2];
     71 
     72 	struct device *atapibus;
     73 
     74 	/*
     75 	 * channel queues. May be the same for all channels, if hw channels
     76 	 * are not independants
     77 	 */
     78 	struct channel_queue *ch_queue;
     79 };
     80 
     81 struct wdc_softc { /* Per controller state */
     82 	struct device sc_dev;
     83 	/* mandatory fields */
     84 	int           cap;
     85 /* Capabilities supported by the controller */
     86 #define	WDC_CAPABILITY_DATA16 0x0001    /* can do  16-bit data access */
     87 #define	WDC_CAPABILITY_DATA32 0x0002    /* can do 32-bit data access */
     88 #define WDC_CAPABILITY_MODE   0x0004	/* controller knows its PIO/DMA modes */
     89 #define	WDC_CAPABILITY_DMA    0x0008	/* DMA */
     90 #define	WDC_CAPABILITY_UDMA   0x0010	/* Ultra-DMA/33 */
     91 #define	WDC_CAPABILITY_HWLOCK 0x0020	/* Needs to lock HW */
     92 #define	WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
     93 #define	WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
     94 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
     95 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
     96 	u_int8_t      PIO_cap; /* highest PIO mode supported */
     97 	u_int8_t      DMA_cap; /* highest DMA mode supported */
     98 	u_int8_t      UDMA_cap; /* highest UDMA mode supported */
     99 	int nchannels;	/* Number of channels on this controller */
    100 	struct channel_softc **channels;  /* channels-specific datas (array) */
    101 
    102 	/*
    103 	 * The reference count here is used for both IDE and ATAPI devices.
    104 	 */
    105 	struct scsipi_adapter sc_atapi_adapter;
    106 	int		sc_dying;
    107 
    108 	/* if WDC_CAPABILITY_DMA set in 'cap' */
    109 	void            *dma_arg;
    110 	int            (*dma_init) __P((void *, int, int, void *, size_t,
    111 	                int));
    112 	void           (*dma_start) __P((void *, int, int, int));
    113 	int            (*dma_finish) __P((void *, int, int, int));
    114 /* flags passed to DMA functions */
    115 #define WDC_DMA_READ 0x01
    116 #define WDC_DMA_POLL 0x02
    117 
    118 	/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
    119 	int            (*claim_hw) __P((void *, int));
    120 	void            (*free_hw) __P((void *));
    121 
    122 	/* if WDC_CAPABILITY_MODE set in 'cap' */
    123 	void 		(*set_modes) __P((struct channel_softc *));
    124 };
    125 
    126  /*
    127   * Description of a command to be handled by a controller.
    128   * These commands are queued in a list.
    129   */
    130 struct wdc_xfer {
    131 	volatile u_int c_flags;
    132 #define C_ATAPI  	0x0001 /* xfer is ATAPI request */
    133 #define C_TIMEOU  	0x0002 /* xfer processing timed out */
    134 #define C_POLL		0x0004 /* cmd is polled */
    135 #define C_DMA		0x0008 /* cmd uses DMA */
    136 #define C_SENSE		0x0010 /* cmd is a internal command */
    137 
    138 	/* Informations about our location */
    139 	struct channel_softc *chp;
    140 	u_int8_t drive;
    141 
    142 	/* Information about the current transfer  */
    143 	void *cmd; /* wdc, ata or scsipi command structure */
    144 	void *databuf;
    145 	int c_bcount;      /* byte count left */
    146 	int c_skip;        /* bytes already transferred */
    147 	TAILQ_ENTRY(wdc_xfer) c_xferchain;
    148 	void (*c_start) __P((struct channel_softc *, struct wdc_xfer *));
    149 	int  (*c_intr)  __P((struct channel_softc *, struct wdc_xfer *, int));
    150 	void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *));
    151 };
    152 
    153 /*
    154  * Public functions which can be called by ATA or ATAPI specific parts,
    155  * or bus-specific backends.
    156  */
    157 
    158 int   wdcprobe __P((struct channel_softc *));
    159 void  wdcattach __P((struct channel_softc *));
    160 int   wdcdetach __P((struct device *, int));
    161 int   wdcactivate __P((struct device *, enum devact));
    162 int   wdcintr __P((void *));
    163 void  wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *));
    164 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */
    165 #define WDC_CANSLEEP 0x00
    166 #define WDC_NOSLEEP 0x01
    167 void   wdc_free_xfer  __P((struct channel_softc *, struct wdc_xfer *));
    168 void  wdcstart __P((struct channel_softc *));
    169 void  wdcrestart __P((void*));
    170 int   wdcreset	__P((struct channel_softc *, int));
    171 #define VERBOSE 1
    172 #define SILENT 0 /* wdcreset will not print errors */
    173 int   wdcwait __P((struct channel_softc *, int, int, int));
    174 void  wdcbit_bucket __P(( struct channel_softc *, int));
    175 void  wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
    176 	                  u_int8_t, u_int8_t, u_int8_t, u_int8_t));
    177 void   wdccommandshort __P((struct channel_softc *, int, int));
    178 void  wdctimeout	__P((void *arg));
    179 
    180 int	wdc_addref __P((struct channel_softc *));
    181 void	wdc_delref __P((struct channel_softc *));
    182 void	wdc_kill_pending __P((struct channel_softc *));
    183 
    184 /*
    185  * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
    186  * command is aborted.
    187  */
    188 #define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout))
    189 #define wait_for_unbusy(chp, timeout)	wdcwait((chp), 0, 0, (timeout))
    190 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \
    191 	WDCS_DRDY, (timeout))
    192 /* ATA/ATAPI specs says a device can take 31s to reset */
    193 #define WDC_RESET_WAIT 31000
    194 
    195 void wdc_atapibus_attach __P((struct channel_softc *));
    196 int   atapi_print       __P((void *, const char *));
    197