wdcvar.h revision 1.2.2.10
1 /* $NetBSD: wdcvar.h,v 1.2.2.10 1998/09/20 19:00:15 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define WAITTIME (10 * hz) /* time to wait for a completion */ 40 /* this is a lot for hard drives, but not for cdroms */ 41 42 struct channel_queue { /* per channel queue (may be shared) */ 43 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 44 }; 45 46 struct channel_softc { /* Per channel data */ 47 /* Our location */ 48 int channel; 49 /* Our controller's softc */ 50 struct wdc_softc *wdc; 51 /* Our registers */ 52 bus_space_tag_t cmd_iot; 53 bus_space_handle_t cmd_ioh; 54 bus_space_tag_t ctl_iot; 55 bus_space_handle_t ctl_ioh; 56 /* 57 * XXX data access (normal and 32-bit) may need to be 58 * done via a separate iot/ioh on some systems. Let's 59 * wait and see if that's the case before implementing 60 * it. 61 */ 62 /* Our state */ 63 int ch_flags; 64 #define WDCF_ACTIVE 0x01 /* channel is active */ 65 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 66 u_int8_t ch_status; /* copy of status register */ 67 u_int8_t ch_error; /* copy of error register */ 68 /* per-drive infos */ 69 struct ata_drive_datas ch_drive[2]; 70 71 /* 72 * channel queues. May be the same for all channels, if hw channels 73 * are not independants 74 */ 75 struct channel_queue *ch_queue; 76 }; 77 78 struct wdc_softc { /* Per controller state */ 79 struct device sc_dev; 80 /* mandatory fields */ 81 int cap; 82 /* Capabilities supported by the controller */ 83 #define WDC_CAPABILITY_DATA32 0x0001 /* 32-bit data access */ 84 #define WDC_CAPABILITY_PIO 0x0002 /* controller knows its PIO modes */ 85 #define WDC_CAPABILITY_DMA 0x0004 /* DMA */ 86 #define WDC_CAPABILITY_UDMA 0x0008 /* Ultra-DMA/33 */ 87 #define WDC_CAPABILITY_HWLOCK 0x0010 /* Needs to lock HW */ 88 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0020 /* Don't use stream funcs on ATA */ 89 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0040 /* Don't use stream funcs on ATAPI */ 90 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0080 /* only reset once */ 91 u_int8_t pio_mode; /* highest PIO mode supported */ 92 u_int8_t dma_mode; /* highest DMA mode supported */ 93 int nchannels; /* Number of channels on this controller */ 94 struct channel_softc *channels; /* channels-specific datas (array) */ 95 96 /* if WDC_CAPABILITY_DMA set in 'cap' */ 97 void *dma_arg; 98 int (*dma_init) __P((void *, int, int, void *, size_t, 99 int)); 100 void (*dma_start) __P((void *, int, int, int)); 101 int (*dma_finish) __P((void *, int, int, int)); 102 /* flags passed to DMA functions */ 103 #define WDC_DMA_READ 0x01 104 #define WDC_DMA_POLL 0x02 105 106 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 107 int (*claim_hw) __P((void *, int)); 108 void (*free_hw) __P((void *)); 109 }; 110 111 /* 112 * Description of a command to be handled by a controller. 113 * These commands are queued in a list. 114 */ 115 struct wdc_xfer { 116 volatile u_int c_flags; 117 #define C_INUSE 0x0001 /* xfer struct is in use */ 118 #define C_ATAPI 0x0002 /* xfer is ATAPI request */ 119 #define C_TIMEOU 0x0004 /* xfer processing timed out */ 120 #define C_NEEDDONE 0x0010 /* need to call upper-level done */ 121 #define C_POLL 0x0020 /* cmd is polled */ 122 123 /* Information about our location */ 124 u_int8_t drive; 125 u_int8_t channel; 126 127 /* Information about the current transfer */ 128 void *cmd; /* wdc, ata or scsipi command structure */ 129 void *databuf; 130 int c_bcount; /* byte count left */ 131 int c_skip; /* bytes already transferred */ 132 TAILQ_ENTRY(wdc_xfer) c_xferchain; 133 LIST_ENTRY(wdc_xfer) free_list; 134 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 135 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *)); 136 }; 137 138 /* 139 * Public functions which can be called by ATA or ATAPI specific parts, 140 * or bus-specific backends. 141 */ 142 143 int wdcprobe __P((struct channel_softc *)); 144 void wdcattach __P((struct channel_softc *)); 145 int wdcintr __P((void *)); 146 void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 147 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 148 #define WDC_CANSLEEP 0x00 149 #define WDC_NOSLEEP 0x01 150 void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 151 void wdcstart __P((struct wdc_softc *, int)); 152 void wdcrestart __P((void*)); 153 int wdcreset __P((struct channel_softc *, int)); 154 #define VERBOSE 1 155 #define SILENT 0 /* wdcreset will not print errors */ 156 int wdcwait __P((struct channel_softc *, int, int, int)); 157 void wdcbit_bucket __P(( struct channel_softc *, int)); 158 void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 159 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 160 void wdccommandshort __P((struct channel_softc *, int, int)); 161 void wdctimeout __P((void *arg)); 162 163 /* 164 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 165 * command is aborted. 166 */ 167 #define wait_for_drq(chp, timeout) wdcwait((chp), \ 168 WDCS_DRDY | WDCS_DSC | WDCS_DRQ, \ 169 WDCS_DRDY | WDCS_DSC | WDCS_DRQ, (timeout)) 170 #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 171 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY | WDCS_DSC, \ 172 WDCS_DRDY | WDCS_DSC, (timeout)) 173 /* ATA/ATAPI specs says a device can take 31s to reset */ 174 #define WDC_RESET_WAIT 31000 175 176 void wdc_atapibus_attach __P((struct channel_softc *)); 177 int atapi_print __P((void *, const char *)); 178
Indexes created Sun Oct 19 02:09:48 GMT 2025