Home | History | Annotate | Line # | Download | only in ic
wdcvar.h revision 1.2.2.2 
      1 /*	$NetBSD: wdcvar.h,v 1.2.2.2 1998/06/05 08:38:57 bouyer Exp $    */
      2 
      3 /*
      4  * Copyright (c) 1994, 1995 Charles M. Hannum.  All rights reserved.
      5  *
      6  * DMA and multi-sector PIO handling are derived from code contributed by
      7  * Onno van der Linden.
      8  *
      9  * Atapi support added by Manuel Bouyer.
     10  *
     11  * bus_space-ified by Christopher G. Demetriou.
     12  *
     13  * Redistribution and use in source and binary forms, with or without
     14  * modification, are permitted provided that the following conditions
     15  * are met:
     16  * 1. Redistributions of source code must retain the above copyright
     17  *	notice, this list of conditions and the following disclaimer.
     18  * 2. Redistributions in binary form must reproduce the above copyright
     19  *	notice, this list of conditions and the following disclaimer in the
     20  *	documentation and/or other materials provided with the distribution.
     21  * 3. All advertising materials mentioning features or use of this software
     22  *	must display the following acknowledgement:
     23  *  This product includes software developed by Charles M. Hannum.
     24  * 4. The name of the author may not be used to endorse or promote products
     25  *	derived from this software without specific prior written permission.
     26  *
     27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     29  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     30  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     31  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     32  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     36  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #define	WAITTIME    (10 * hz)    /* time to wait for a completion */
     40 	/* this is a lot for hard drives, but not for cdroms */
     41 
     42 struct channel_queue {  /* per channel queue (may be shared) */
     43 	TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
     44 };
     45 
     46 struct channel_softc { /* Per channel data */
     47 	/* Our location */
     48 	int channel;
     49 	/* Our controller's softc */
     50 	struct wdc_softc *wdc;
     51 	/* Our registers */
     52 	bus_space_tag_t       cmd_iot;
     53 	bus_space_handle_t    cmd_ioh;
     54 	bus_space_tag_t       ctl_iot;
     55 	bus_space_handle_t    ctl_ioh;
     56 	/*
     57 	 * XXX data access (normal and 32-bit) may need to be
     58 	 * done via a separate iot/ioh on some systems.  Let's
     59 	 * wait and see if that's the case before implementing
     60 	 * it.
     61 	 */
     62 	/* Our state */
     63 	int ch_flags;
     64 #define WDCF_ACTIVE   0x01	/* channel is active */
     65 #define WDCF_IRQ_WAIT 0x10	/* controller is waiting for irq */
     66 	u_int8_t ch_status;         /* copy of status register */
     67 	u_int8_t ch_error;          /* copy of error register */
     68 	/* per-drive infos */
     69 	struct ata_drive_datas ch_drive[2];
     70 
     71 	/*
     72 	 * channel queues. May be the same for all channels, if hw channels
     73 	 * are not independants
     74 	 */
     75 	struct channel_queue *ch_queue;
     76 };
     77 
     78 struct wdc_softc { /* Per controller state */
     79 	struct device sc_dev;
     80 	/* manadatory fields */
     81 	int           cap;
     82 /* Capabilities supported by the controller */
     83 #define	WDC_CAPABILITY_DATA32 0x01     /* 32-bit data access */
     84 #define	WDC_CAPABILITY_DMA    0x02     /* DMA */
     85 #define	   WDC_CAPABILITY_UDMA   0x04	 /* Ultra-DMA/33 */
     86 #define	WDC_CAPABILITY_HWLOCK 0x08     /* Needs to lock HW */
     87 	u_int8_t      pio_mode; /* hightest PIO mode supported */
     88 	u_int8_t      dma_mode; /* hightest DMA mode supported */
     89 	int nchannels;	/* Number of channels on this controller */
     90 	struct channel_softc *channels;  /* channels-specific datas (array) */
     91 
     92 	/* if WDC_CAPABILITY_DMA set in 'cap' */
     93 	void            *dma_arg;
     94 	int            (*dma_init) __P((void *, int, int, void *, size_t,
     95 	                int));
     96 	void           (*dma_start) __P((void *, int, int, int));
     97 	int            (*dma_finish) __P((void *, int, int, int));
     98 
     99 	/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
    100 	int            (*claim_hw) __P((void *, int));
    101 	void            (*free_hw) __P((void *));
    102 
    103 };
    104 
    105  /*
    106   * Description of a command to be handled by a controller.
    107   * These commands are queued in a list.
    108   */
    109 struct wdc_xfer {
    110 	volatile u_int c_flags;
    111 #define C_INUSE  	0x0001 /* xfer struct is in use */
    112 #define C_ATAPI  	0x0002 /* xfer is ATAPI request */
    113 #define C_TIMEOU  	0x0004 /* xfer processing timed out */
    114 #define C_NEEDDONE  	0x0010 /* need to call upper-level done */
    115 
    116 	/* Information about our location */
    117 	u_int8_t drive;
    118 	u_int8_t channel;
    119 
    120 	/* Information about the current transfer  */
    121 	void *cmd; /* wdc, ata or scsipi command structure */
    122 	void *databuf;
    123 	int c_bcount;      /* byte count left */
    124 	int c_skip;        /* bytes already transferred */
    125 	TAILQ_ENTRY(wdc_xfer) c_xferchain;
    126 	LIST_ENTRY(wdc_xfer) free_list;
    127 	void (*c_start) __P((struct channel_softc *, struct wdc_xfer *));
    128 	int  (*c_intr)  __P((struct channel_softc *, struct wdc_xfer *));
    129 };
    130 
    131 /*
    132  * Public functions which can be called by ATA or ATAPI specific parts,
    133  * or bus-specific backends.
    134  */
    135 
    136 int   wdcprobe __P((const struct channel_softc *));
    137 void  wdcattach __P((struct channel_softc *));
    138 int   wdcintr __P((void *));
    139 void  wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *));
    140 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */
    141 #define WDC_CANSLEEP 0x00
    142 #define WDC_NOSLEEP 0x01
    143 void   wdc_free_xfer  __P((struct channel_softc *, struct wdc_xfer *));
    144 void  wdcstart __P((struct wdc_softc *, int));
    145 void  wdcrestart __P((void*));
    146 int   wdcreset	__P((struct channel_softc *, int));
    147 #define VERBOSE 1
    148 #define SILENT 0 /* wdcreset will not print errors */
    149 int   wdcwait __P((struct channel_softc *, int));
    150 void  wdcbit_bucket __P(( struct channel_softc *, int));
    151 void  wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
    152 	                  u_int8_t, u_int8_t, u_int8_t, u_int8_t));
    153 void   wdccommandshort __P((struct channel_softc *, int, int));
    154 void  wdctimeout	__P((void *arg));
    155 
    156 /*
    157  * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
    158  * command is aborted.
    159  */
    160 #define wait_for_drq(chp)	wdcwait(chp, WDCS_DRDY | WDCS_DSC | WDCS_DRQ)
    161 #define wait_for_unbusy(chp)	wdcwait(chp, 0)
    162 #define wait_for_ready(chp) 	wdcwait(chp, WDCS_DRDY | WDCS_DSC)
    163 
    164 void wdc_atapibus_attach __P((struct channel_softc *));
    165 void wdc_ata_attach __P((struct channel_softc *));
    166