wdcvar.h revision 1.25.2.2
1 /* $NetBSD: wdcvar.h,v 1.25.2.2 2002/01/16 10:14:50 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* XXX for atapi_adapter */ 40 #include <dev/scsipi/scsipi_all.h> 41 #include <dev/scsipi/atapiconf.h> 42 43 #include <sys/callout.h> 44 45 #define WAITTIME (10 * hz) /* time to wait for a completion */ 46 /* this is a lot for hard drives, but not for cdroms */ 47 48 struct channel_queue { /* per channel queue (may be shared) */ 49 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 50 }; 51 52 struct channel_softc { /* Per channel data */ 53 /* Our timeout callout */ 54 struct callout ch_callout; 55 /* Our location */ 56 int channel; 57 /* Our controller's softc */ 58 struct wdc_softc *wdc; 59 /* Our registers */ 60 bus_space_tag_t cmd_iot; 61 bus_space_handle_t cmd_ioh; 62 bus_space_tag_t ctl_iot; 63 bus_space_handle_t ctl_ioh; 64 /* data32{iot,ioh} are only used for 32 bit xfers */ 65 bus_space_tag_t data32iot; 66 bus_space_handle_t data32ioh; 67 /* Our state */ 68 int ch_flags; 69 #define WDCF_ACTIVE 0x01 /* channel is active */ 70 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 71 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 72 u_int8_t ch_status; /* copy of status register */ 73 u_int8_t ch_error; /* copy of error register */ 74 /* per-drive infos */ 75 struct ata_drive_datas ch_drive[2]; 76 77 struct device *atapibus; 78 79 /* 80 * channel queues. May be the same for all channels, if hw channels 81 * are not independants 82 */ 83 struct channel_queue *ch_queue; 84 }; 85 86 struct wdc_softc { /* Per controller state */ 87 struct device sc_dev; 88 /* mandatory fields */ 89 int cap; 90 /* Capabilities supported by the controller */ 91 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 92 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 93 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 94 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 95 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 96 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 97 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 98 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 99 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 100 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 101 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 102 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 103 u_int8_t PIO_cap; /* highest PIO mode supported */ 104 u_int8_t DMA_cap; /* highest DMA mode supported */ 105 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 106 int nchannels; /* Number of channels on this controller */ 107 struct channel_softc **channels; /* channels-specific datas (array) */ 108 109 /* 110 * The reference count here is used for both IDE and ATAPI devices. 111 */ 112 struct atapi_adapter sc_atapi_adapter; 113 114 /* if WDC_CAPABILITY_DMA set in 'cap' */ 115 void *dma_arg; 116 int (*dma_init) __P((void *, int, int, void *, size_t, 117 int)); 118 void (*dma_start) __P((void *, int, int)); 119 int (*dma_finish) __P((void *, int, int, int)); 120 /* flags passed to dma_init */ 121 #define WDC_DMA_READ 0x01 122 #define WDC_DMA_IRQW 0x02 123 int dma_status; /* status returned from dma_finish() */ 124 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 125 #define WDC_DMAST_ERR 0x02 /* DMA error */ 126 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 127 128 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 129 int (*claim_hw) __P((void *, int)); 130 void (*free_hw) __P((void *)); 131 132 /* if WDC_CAPABILITY_MODE set in 'cap' */ 133 void (*set_modes) __P((struct channel_softc *)); 134 135 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 136 void (*select) __P((struct channel_softc *,int)); 137 138 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 139 void (*irqack) __P((struct channel_softc *)); 140 }; 141 142 /* 143 * Description of a command to be handled by a controller. 144 * These commands are queued in a list. 145 */ 146 struct wdc_xfer { 147 volatile u_int c_flags; 148 #define C_ATAPI 0x0001 /* xfer is ATAPI request */ 149 #define C_TIMEOU 0x0002 /* xfer processing timed out */ 150 #define C_POLL 0x0004 /* cmd is polled */ 151 #define C_DMA 0x0008 /* cmd uses DMA */ 152 #define C_SENSE 0x0010 /* cmd is a internal command */ 153 #define C_FORCEPIO 0x0020 /* cmd must use PIO */ 154 155 /* Informations about our location */ 156 struct channel_softc *chp; 157 u_int8_t drive; 158 159 /* Information about the current transfer */ 160 void *cmd; /* wdc, ata or scsipi command structure */ 161 void *databuf; 162 int c_bcount; /* byte count left */ 163 int c_skip; /* bytes already transferred */ 164 TAILQ_ENTRY(wdc_xfer) c_xferchain; 165 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 166 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *, int)); 167 void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *)); 168 }; 169 170 /* 171 * Public functions which can be called by ATA or ATAPI specific parts, 172 * or bus-specific backends. 173 */ 174 175 int wdcprobe __P((struct channel_softc *)); 176 void wdcattach __P((struct channel_softc *)); 177 int wdcdetach __P((struct device *, int)); 178 int wdcactivate __P((struct device *, enum devact)); 179 int wdcintr __P((void *)); 180 void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 181 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 182 #define WDC_CANSLEEP 0x00 183 #define WDC_NOSLEEP 0x01 184 void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 185 void wdcstart __P((struct channel_softc *)); 186 void wdcrestart __P((void*)); 187 int wdcreset __P((struct channel_softc *, int)); 188 #define VERBOSE 1 189 #define SILENT 0 /* wdcreset will not print errors */ 190 int wdcwait __P((struct channel_softc *, int, int, int)); 191 int wdc_dmawait __P((struct channel_softc *, struct wdc_xfer *, int)); 192 void wdcbit_bucket __P(( struct channel_softc *, int)); 193 void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 194 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 195 void wdccommandshort __P((struct channel_softc *, int, int)); 196 void wdctimeout __P((void *arg)); 197 198 int wdc_addref __P((struct channel_softc *)); 199 void wdc_delref __P((struct channel_softc *)); 200 void wdc_kill_pending __P((struct channel_softc *)); 201 202 /* 203 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 204 * command is aborted. 205 */ 206 #define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 207 #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 208 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 209 WDCS_DRDY, (timeout)) 210 /* ATA/ATAPI specs says a device can take 31s to reset */ 211 #define WDC_RESET_WAIT 31000 212 213 void wdc_atapibus_attach __P((struct channel_softc *)); 214 int atapi_print __P((void *, const char *)); 215
Indexes created Sat Oct 18 21:09:54 GMT 2025