wdcvar.h revision 1.28.2.3
1 /* $NetBSD: wdcvar.h,v 1.28.2.3 2002/01/11 23:39:01 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* XXX For scsipi_adapter and scsipi_channel. */ 40 #include <dev/scsipi/scsipi_all.h> 41 #include <dev/scsipi/atapiconf.h> 42 43 #include <sys/callout.h> 44 45 #define WAITTIME (10 * hz) /* time to wait for a completion */ 46 /* this is a lot for hard drives, but not for cdroms */ 47 48 struct channel_queue { /* per channel queue (may be shared) */ 49 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 50 }; 51 52 struct channel_softc { /* Per channel data */ 53 /* Our timeout callout */ 54 struct callout ch_callout; 55 /* Our location */ 56 int channel; 57 /* Our controller's softc */ 58 struct wdc_softc *wdc; 59 /* Our registers */ 60 bus_space_tag_t cmd_iot; 61 bus_space_handle_t cmd_ioh; 62 bus_space_tag_t ctl_iot; 63 bus_space_handle_t ctl_ioh; 64 /* data32{iot,ioh} are only used for 32 bit xfers */ 65 bus_space_tag_t data32iot; 66 bus_space_handle_t data32ioh; 67 /* Our state */ 68 int ch_flags; 69 #define WDCF_ACTIVE 0x01 /* channel is active */ 70 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 71 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 72 u_int8_t ch_status; /* copy of status register */ 73 u_int8_t ch_error; /* copy of error register */ 74 /* per-drive infos */ 75 struct ata_drive_datas ch_drive[2]; 76 77 struct device *atapibus; 78 struct scsipi_channel ch_atapi_channel; 79 80 /* 81 * channel queues. May be the same for all channels, if hw channels 82 * are not independants 83 */ 84 struct channel_queue *ch_queue; 85 }; 86 87 struct wdc_softc { /* Per controller state */ 88 struct device sc_dev; 89 /* mandatory fields */ 90 int cap; 91 /* Capabilities supported by the controller */ 92 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 93 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 94 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 95 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 96 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 97 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 98 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 99 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 100 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 101 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 102 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 103 #define WDC_CAPABILITY_SINGLE_DRIVE 0x0800 /* Don't probe second drive */ 104 #define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */ 105 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 106 u_int8_t PIO_cap; /* highest PIO mode supported */ 107 u_int8_t DMA_cap; /* highest DMA mode supported */ 108 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 109 int nchannels; /* Number of channels on this controller */ 110 struct channel_softc **channels; /* channels-specific datas (array) */ 111 112 /* 113 * The reference count here is used for both IDE and ATAPI devices. 114 */ 115 struct atapi_adapter sc_atapi_adapter; 116 117 /* if WDC_CAPABILITY_DMA set in 'cap' */ 118 void *dma_arg; 119 int (*dma_init) __P((void *, int, int, void *, size_t, 120 int)); 121 void (*dma_start) __P((void *, int, int)); 122 int (*dma_finish) __P((void *, int, int, int)); 123 /* flags passed to dma_init */ 124 #define WDC_DMA_READ 0x01 125 #define WDC_DMA_IRQW 0x02 126 int dma_status; /* status returned from dma_finish() */ 127 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 128 #define WDC_DMAST_ERR 0x02 /* DMA error */ 129 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 130 131 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 132 int (*claim_hw) __P((void *, int)); 133 void (*free_hw) __P((void *)); 134 135 /* if WDC_CAPABILITY_MODE set in 'cap' */ 136 void (*set_modes) __P((struct channel_softc *)); 137 138 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 139 void (*select) __P((struct channel_softc *,int)); 140 141 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 142 void (*irqack) __P((struct channel_softc *)); 143 }; 144 145 /* 146 * Description of a command to be handled by a controller. 147 * These commands are queued in a list. 148 */ 149 struct wdc_xfer { 150 volatile u_int c_flags; 151 #define C_ATAPI 0x0001 /* xfer is ATAPI request */ 152 #define C_TIMEOU 0x0002 /* xfer processing timed out */ 153 #define C_POLL 0x0004 /* cmd is polled */ 154 #define C_DMA 0x0008 /* cmd uses DMA */ 155 #define C_SENSE 0x0010 /* cmd is a internal command */ 156 #define C_FORCEPIO 0x0020 /* cmd must use PIO */ 157 158 /* Informations about our location */ 159 struct channel_softc *chp; 160 u_int8_t drive; 161 162 /* Information about the current transfer */ 163 void *cmd; /* wdc, ata or scsipi command structure */ 164 void *databuf; 165 int c_bcount; /* byte count left */ 166 int c_skip; /* bytes already transferred */ 167 int c_dscpoll; /* counter for dsc polling (ATAPI) */ 168 TAILQ_ENTRY(wdc_xfer) c_xferchain; 169 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 170 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *, int)); 171 void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *)); 172 }; 173 174 /* 175 * Public functions which can be called by ATA or ATAPI specific parts, 176 * or bus-specific backends. 177 */ 178 179 int wdcprobe __P((struct channel_softc *)); 180 void wdcattach __P((struct channel_softc *)); 181 int wdcdetach __P((struct device *, int)); 182 int wdcactivate __P((struct device *, enum devact)); 183 int wdcintr __P((void *)); 184 void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 185 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 186 #define WDC_CANSLEEP 0x00 187 #define WDC_NOSLEEP 0x01 188 void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 189 void wdcstart __P((struct channel_softc *)); 190 void wdcrestart __P((void*)); 191 int wdcreset __P((struct channel_softc *, int)); 192 #define VERBOSE 1 193 #define SILENT 0 /* wdcreset will not print errors */ 194 int wdcwait __P((struct channel_softc *, int, int, int)); 195 int wdc_dmawait __P((struct channel_softc *, struct wdc_xfer *, int)); 196 void wdcbit_bucket __P(( struct channel_softc *, int)); 197 void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 198 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 199 void wdccommandshort __P((struct channel_softc *, int, int)); 200 void wdctimeout __P((void *arg)); 201 void wdc_reset_channel __P((struct ata_drive_datas *)); 202 int wdc_exec_command __P((struct ata_drive_datas *, struct wdc_command*)); 203 #define WDC_COMPLETE 0x01 204 #define WDC_QUEUED 0x02 205 #define WDC_TRY_AGAIN 0x03 206 207 int wdc_addref __P((struct channel_softc *)); 208 void wdc_delref __P((struct channel_softc *)); 209 void wdc_kill_pending __P((struct channel_softc *)); 210 211 void wdc_print_modes (struct channel_softc *); 212 void wdc_probe_caps __P((struct ata_drive_datas*)); 213 214 /* 215 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 216 * command is aborted. 217 */ 218 #define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 219 #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 220 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 221 WDCS_DRDY, (timeout)) 222 /* ATA/ATAPI specs says a device can take 31s to reset */ 223 #define WDC_RESET_WAIT 31000 224 225 void wdc_atapibus_attach __P((struct channel_softc *)); 226
Indexes created Sun Oct 19 02:09:48 GMT 2025