wdcvar.h revision 1.47
1 /* $NetBSD: wdcvar.h,v 1.47 2003/12/30 16:28:37 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* XXX For scsipi_adapter and scsipi_channel. */ 40 #include <dev/scsipi/scsipi_all.h> 41 #include <dev/scsipi/atapiconf.h> 42 43 #include <sys/callout.h> 44 45 #define WAITTIME (10 * hz) /* time to wait for a completion */ 46 /* this is a lot for hard drives, but not for cdroms */ 47 48 struct channel_queue { /* per channel queue (may be shared) */ 49 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 50 int queue_freeze; 51 }; 52 53 #define WDC_NREG 8 /* number of command registers */ 54 55 struct channel_softc { /* Per channel data */ 56 /* Our timeout callout */ 57 struct callout ch_callout; 58 /* Our location */ 59 int channel; 60 /* Our controller's softc */ 61 struct wdc_softc *wdc; 62 /* Our registers */ 63 bus_space_tag_t cmd_iot; 64 bus_space_handle_t cmd_baseioh; 65 bus_space_handle_t cmd_iohs[WDC_NREG]; 66 bus_space_tag_t ctl_iot; 67 bus_space_handle_t ctl_ioh; 68 /* data32{iot,ioh} are only used for 32 bit data xfers */ 69 bus_space_tag_t data32iot; 70 bus_space_handle_t data32ioh; 71 /* Our state */ 72 int ch_flags; 73 #define WDCF_ACTIVE 0x01 /* channel is active */ 74 #define WDCF_SHUTDOWN 0x02 /* channel is shutting down */ 75 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 76 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 77 #define WDCF_DISABLED 0x80 /* channel is disabled */ 78 #define WDCF_TH_RUN 0x100 /* the kenrel thread is working */ 79 #define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */ 80 u_int8_t ch_status; /* copy of status register */ 81 u_int8_t ch_error; /* copy of error register */ 82 /* per-drive infos */ 83 struct ata_drive_datas ch_drive[2]; 84 85 struct device *atabus; /* self */ 86 struct device *atapibus; /* children */ 87 struct scsipi_channel ch_atapi_channel; 88 89 struct device *ata_drives[2]; /* children */ 90 91 /* 92 * channel queues. May be the same for all channels, if hw channels 93 * are not independent. 94 */ 95 struct channel_queue *ch_queue; 96 /* the channel kenrel thread */ 97 struct proc *thread; 98 }; 99 100 struct wdc_softc { /* Per controller state */ 101 struct device sc_dev; 102 /* mandatory fields */ 103 int cap; 104 /* Capabilities supported by the controller */ 105 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 106 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 107 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 108 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 109 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 110 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 111 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 112 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 113 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 114 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 115 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 116 #define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */ 117 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 118 #define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */ 119 #define WDC_CAPABILITY_DRVPROBE 0x8000 /* Controller has smart drive probe */ 120 u_int8_t PIO_cap; /* highest PIO mode supported */ 121 u_int8_t DMA_cap; /* highest DMA mode supported */ 122 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 123 int nchannels; /* Number of channels on this controller */ 124 struct channel_softc **channels; /* channels-specific datas (array) */ 125 126 /* 127 * The reference count here is used for both IDE and ATAPI devices. 128 */ 129 struct atapi_adapter sc_atapi_adapter; 130 131 /* if WDC_CAPABILITY_DMA set in 'cap' */ 132 void *dma_arg; 133 int (*dma_init) __P((void *, int, int, void *, size_t, 134 int)); 135 void (*dma_start) __P((void *, int, int)); 136 int (*dma_finish) __P((void *, int, int, int)); 137 /* flags passed to dma_init */ 138 #define WDC_DMA_READ 0x01 139 #define WDC_DMA_IRQW 0x02 140 #define WDC_DMA_LBA48 0x04 141 int dma_status; /* status returned from dma_finish() */ 142 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 143 #define WDC_DMAST_ERR 0x02 /* DMA error */ 144 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 145 146 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 147 int (*claim_hw) __P((void *, int)); 148 void (*free_hw) __P((void *)); 149 150 /* if WDC_CAPABILITY_MODE set in 'cap' */ 151 void (*set_modes) __P((struct channel_softc *)); 152 153 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 154 void (*select) __P((struct channel_softc *,int)); 155 156 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 157 void (*irqack) __P((struct channel_softc *)); 158 159 /* if WDC_CAPABILITY_DRVPROBE is set in 'cap' */ 160 int (*drv_probe) __P((struct channel_softc *)); 161 }; 162 163 /* 164 * Description of a command to be handled by a controller. 165 * These commands are queued in a list. 166 */ 167 struct wdc_xfer { 168 volatile u_int c_flags; 169 #define C_ATAPI 0x0001 /* xfer is ATAPI request */ 170 #define C_TIMEOU 0x0002 /* xfer processing timed out */ 171 #define C_POLL 0x0004 /* cmd is polled */ 172 #define C_DMA 0x0008 /* cmd uses DMA */ 173 174 /* Informations about our location */ 175 struct channel_softc *chp; 176 u_int8_t drive; 177 178 /* Information about the current transfer */ 179 void *cmd; /* wdc, ata or scsipi command structure */ 180 void *databuf; 181 int c_bcount; /* byte count left */ 182 int c_skip; /* bytes already transferred */ 183 int c_dscpoll; /* counter for dsc polling (ATAPI) */ 184 TAILQ_ENTRY(wdc_xfer) c_xferchain; 185 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 186 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *, int)); 187 void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *)); 188 }; 189 190 /* 191 * Public functions which can be called by ATA or ATAPI specific parts, 192 * or bus-specific backends. 193 */ 194 195 int wdcprobe __P((struct channel_softc *)); 196 void wdcattach __P((struct channel_softc *)); 197 int wdcdetach __P((struct device *, int)); 198 int wdcactivate __P((struct device *, enum devact)); 199 int wdcintr __P((void *)); 200 void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 201 struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 202 #define WDC_CANSLEEP 0x00 203 #define WDC_NOSLEEP 0x01 204 void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 205 void wdcstart __P((struct channel_softc *)); 206 void wdcrestart __P((void*)); 207 int wdcreset __P((struct channel_softc *, int)); 208 #define RESET_POLL 1 209 #define RESET_SLEEP 0 /* wdcreset will use tsleep() */ 210 int wdcwait __P((struct channel_softc *, int, int, int, int)); 211 #define WDCWAIT_OK 0 /* we have what we asked */ 212 #define WDCWAIT_TOUT -1 /* timed out */ 213 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */ 214 int wdc_dmawait __P((struct channel_softc *, struct wdc_xfer *, int)); 215 void wdcbit_bucket __P(( struct channel_softc *, int)); 216 void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 217 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 218 void wdccommandext __P((struct channel_softc *, u_int8_t, u_int8_t, u_int64_t, 219 u_int16_t)); 220 void wdccommandshort __P((struct channel_softc *, int, int)); 221 void wdctimeout __P((void *arg)); 222 void wdc_reset_channel __P((struct ata_drive_datas *, int)); 223 int wdc_exec_command __P((struct ata_drive_datas *, struct wdc_command*)); 224 #define WDC_COMPLETE 0x01 225 #define WDC_QUEUED 0x02 226 #define WDC_TRY_AGAIN 0x03 227 228 int wdc_addref __P((struct channel_softc *)); 229 void wdc_delref __P((struct channel_softc *)); 230 void wdc_kill_pending __P((struct channel_softc *)); 231 232 void wdc_print_modes (struct channel_softc *); 233 void wdc_probe_caps __P((struct ata_drive_datas*)); 234 235 /* 236 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 237 * command is aborted. 238 */ 239 #define wait_for_drq(chp, timeout, flags) \ 240 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags)) 241 #define wait_for_unbusy(chp, timeout, flags) \ 242 wdcwait((chp), 0, 0, (timeout), (flags)) 243 #define wait_for_ready(chp, timeout, flags) \ 244 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags)) 245 /* ATA/ATAPI specs says a device can take 31s to reset */ 246 #define WDC_RESET_WAIT 31000 247 248 void wdc_atapibus_attach __P((struct atabus_softc *)); 249 250 /* XXX */ 251 struct atabus_softc; 252 void atabusconfig(struct atabus_softc *); 253
Indexes created Sun Oct 19 02:09:48 GMT 2025