wdcvar.h revision 1.52
1 /* $NetBSD: wdcvar.h,v 1.52 2004/01/03 01:50:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_WDCVAR_H_ 40 #define _DEV_IC_WDCVAR_H_ 41 42 /* XXX For scsipi_adapter and scsipi_channel. */ 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/atapiconf.h> 45 46 #include <sys/callout.h> 47 48 #define WAITTIME (10 * hz) /* time to wait for a completion */ 49 /* this is a lot for hard drives, but not for cdroms */ 50 51 #define WDC_NREG 8 /* number of command registers */ 52 53 struct wdc_channel { /* Per channel data */ 54 /* Our timeout callout */ 55 struct callout ch_callout; 56 /* Our location */ 57 int channel; 58 /* Our controller's softc */ 59 struct wdc_softc *wdc; 60 /* Our registers */ 61 bus_space_tag_t cmd_iot; 62 bus_space_handle_t cmd_baseioh; 63 bus_space_handle_t cmd_iohs[WDC_NREG]; 64 bus_space_tag_t ctl_iot; 65 bus_space_handle_t ctl_ioh; 66 /* data32{iot,ioh} are only used for 32 bit data xfers */ 67 bus_space_tag_t data32iot; 68 bus_space_handle_t data32ioh; 69 /* Our state */ 70 int ch_flags; 71 #define WDCF_ACTIVE 0x01 /* channel is active */ 72 #define WDCF_SHUTDOWN 0x02 /* channel is shutting down */ 73 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 74 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 75 #define WDCF_DISABLED 0x80 /* channel is disabled */ 76 #define WDCF_TH_RUN 0x100 /* the kenrel thread is working */ 77 #define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */ 78 u_int8_t ch_status; /* copy of status register */ 79 u_int8_t ch_error; /* copy of error register */ 80 /* per-drive infos */ 81 struct ata_drive_datas ch_drive[2]; 82 83 struct device *atabus; /* self */ 84 struct device *atapibus; /* children */ 85 struct scsipi_channel ch_atapi_channel; 86 87 struct device *ata_drives[2]; /* children */ 88 89 /* 90 * channel queues. May be the same for all channels, if hw channels 91 * are not independent. 92 */ 93 struct ata_queue *ch_queue; 94 95 /* the channel kernel thread */ 96 struct proc *thread; 97 }; 98 99 struct wdc_softc { /* Per controller state */ 100 struct device sc_dev; 101 /* mandatory fields */ 102 int cap; 103 /* Capabilities supported by the controller */ 104 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 105 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 106 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 107 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 108 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 109 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 110 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 111 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 112 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 113 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 114 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 115 #define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */ 116 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 117 #define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */ 118 u_int8_t PIO_cap; /* highest PIO mode supported */ 119 u_int8_t DMA_cap; /* highest DMA mode supported */ 120 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 121 int nchannels; /* Number of channels on this controller */ 122 struct wdc_channel **channels; /* channels-specific datas (array) */ 123 124 /* 125 * The reference count here is used for both IDE and ATAPI devices. 126 */ 127 struct atapi_adapter sc_atapi_adapter; 128 129 /* Function used to probe for drives. */ 130 void (*drv_probe)(struct wdc_channel *); 131 132 /* if WDC_CAPABILITY_DMA set in 'cap' */ 133 void *dma_arg; 134 int (*dma_init)(void *, int, int, void *, size_t, int); 135 void (*dma_start)(void *, int, int); 136 int (*dma_finish)(void *, int, int, int); 137 /* flags passed to dma_init */ 138 #define WDC_DMA_READ 0x01 139 #define WDC_DMA_IRQW 0x02 140 #define WDC_DMA_LBA48 0x04 141 142 int dma_status; /* status returned from dma_finish() */ 143 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 144 #define WDC_DMAST_ERR 0x02 /* DMA error */ 145 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 146 147 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 148 int (*claim_hw)(void *, int); 149 void (*free_hw)(void *); 150 151 /* if WDC_CAPABILITY_MODE set in 'cap' */ 152 void (*set_modes)(struct wdc_channel *); 153 154 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 155 void (*select)(struct wdc_channel *,int); 156 157 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 158 void (*irqack)(struct wdc_channel *); 159 }; 160 161 /* 162 * Public functions which can be called by ATA or ATAPI specific parts, 163 * or bus-specific backends. 164 */ 165 166 int wdcprobe(struct wdc_channel *); 167 void wdcattach(struct wdc_channel *); 168 int wdcdetach(struct device *, int); 169 int wdcactivate(struct device *, enum devact); 170 int wdcintr(void *); 171 void wdc_exec_xfer(struct wdc_channel *, struct ata_xfer *); 172 173 struct ata_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 174 #define WDC_CANSLEEP 0x00 175 #define WDC_NOSLEEP 0x01 176 177 void wdc_free_xfer (struct wdc_channel *, struct ata_xfer *); 178 void wdcstart(struct wdc_channel *); 179 void wdcrestart(void*); 180 181 int wdcreset(struct wdc_channel *, int); 182 #define RESET_POLL 1 183 #define RESET_SLEEP 0 /* wdcreset will use tsleep() */ 184 185 int wdcwait(struct wdc_channel *, int, int, int, int); 186 #define WDCWAIT_OK 0 /* we have what we asked */ 187 #define WDCWAIT_TOUT -1 /* timed out */ 188 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */ 189 190 int wdc_dmawait(struct wdc_channel *, struct ata_xfer *, int); 191 void wdcbit_bucket( struct wdc_channel *, int); 192 void wdccommand(struct wdc_channel *, u_int8_t, u_int8_t, u_int16_t, 193 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 194 void wdccommandext(struct wdc_channel *, u_int8_t, u_int8_t, u_int64_t, 195 u_int16_t); 196 void wdccommandshort(struct wdc_channel *, int, int); 197 void wdctimeout(void *arg); 198 void wdc_reset_channel(struct ata_drive_datas *, int); 199 200 int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*); 201 #define WDC_COMPLETE 0x01 202 #define WDC_QUEUED 0x02 203 #define WDC_TRY_AGAIN 0x03 204 205 int wdc_addref(struct wdc_channel *); 206 void wdc_delref(struct wdc_channel *); 207 void wdc_kill_pending(struct wdc_channel *); 208 209 void wdc_print_modes (struct wdc_channel *); 210 void wdc_probe_caps(struct ata_drive_datas*); 211 212 /* 213 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 214 * command is aborted. 215 */ 216 #define wdc_wait_for_drq(chp, timeout, flags) \ 217 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags)) 218 #define wdc_wait_for_unbusy(chp, timeout, flags) \ 219 wdcwait((chp), 0, 0, (timeout), (flags)) 220 #define wdc_wait_for_ready(chp, timeout, flags) \ 221 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags)) 222 223 /* ATA/ATAPI specs says a device can take 31s to reset */ 224 #define WDC_RESET_WAIT 31000 225 226 void wdc_atapibus_attach(struct atabus_softc *); 227 228 /* XXX */ 229 struct atabus_softc; 230 void atabusconfig(struct atabus_softc *); 231 232 #endif /* _DEV_IC_WDCVAR_H_ */ 233
Indexes created Sun Oct 19 02:09:48 GMT 2025