wdcvar.h revision 1.55
1 /* $NetBSD: wdcvar.h,v 1.55 2004/01/03 23:59:58 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_WDCVAR_H_ 40 #define _DEV_IC_WDCVAR_H_ 41 42 /* XXX For scsipi_adapter and scsipi_channel. */ 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/atapiconf.h> 45 46 #include <sys/callout.h> 47 48 #define WAITTIME (10 * hz) /* time to wait for a completion */ 49 /* this is a lot for hard drives, but not for cdroms */ 50 51 #define WDC_NREG 8 /* number of command registers */ 52 53 /* 54 * Per-channel data 55 */ 56 struct wdc_channel { 57 struct callout ch_callout; /* callout handle */ 58 int ch_channel; /* location */ 59 struct wdc_softc *ch_wdc; /* controller's softc */ 60 61 /* Our registers */ 62 bus_space_tag_t cmd_iot; 63 bus_space_handle_t cmd_baseioh; 64 bus_space_handle_t cmd_iohs[WDC_NREG]; 65 bus_space_tag_t ctl_iot; 66 bus_space_handle_t ctl_ioh; 67 68 /* data32{iot,ioh} are only used for 32 bit data xfers */ 69 bus_space_tag_t data32iot; 70 bus_space_handle_t data32ioh; 71 72 /* Our state */ 73 int ch_flags; 74 #define WDCF_ACTIVE 0x01 /* channel is active */ 75 #define WDCF_SHUTDOWN 0x02 /* channel is shutting down */ 76 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 77 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 78 #define WDCF_DISABLED 0x80 /* channel is disabled */ 79 #define WDCF_TH_RUN 0x100 /* the kenrel thread is working */ 80 #define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */ 81 u_int8_t ch_status; /* copy of status register */ 82 u_int8_t ch_error; /* copy of error register */ 83 84 /* per-drive info */ 85 struct ata_drive_datas ch_drive[2]; 86 87 struct device *atabus; /* self */ 88 89 /* ATAPI children */ 90 struct device *atapibus; 91 struct scsipi_channel ch_atapi_channel; 92 93 /* ATA children */ 94 struct device *ata_drives[2]; 95 96 /* 97 * Channel queues. May be the same for all channels, if hw 98 * channels are not independent. 99 */ 100 struct ata_queue *ch_queue; 101 102 /* The channel kernel thread */ 103 struct proc *ch_thread; 104 }; 105 106 /* 107 * Per-controller data 108 */ 109 struct wdc_softc { 110 struct device sc_dev; /* generic device info */ 111 112 int cap; /* controller capabilities */ 113 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 114 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 115 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 116 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 117 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 118 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 119 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 120 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 121 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 122 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 123 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 124 #define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */ 125 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 126 #define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */ 127 u_int8_t PIO_cap; /* highest PIO mode supported */ 128 u_int8_t DMA_cap; /* highest DMA mode supported */ 129 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 130 int nchannels; /* # channels on this controller */ 131 struct wdc_channel **channels; /* channel-specific data (array) */ 132 133 /* 134 * The reference count here is used for both IDE and ATAPI devices. 135 */ 136 struct atapi_adapter sc_atapi_adapter; 137 138 /* Function used to probe for drives. */ 139 void (*drv_probe)(struct wdc_channel *); 140 141 /* if WDC_CAPABILITY_DMA set in 'cap' */ 142 void *dma_arg; 143 int (*dma_init)(void *, int, int, void *, size_t, int); 144 void (*dma_start)(void *, int, int); 145 int (*dma_finish)(void *, int, int, int); 146 /* flags passed to dma_init */ 147 #define WDC_DMA_READ 0x01 148 #define WDC_DMA_IRQW 0x02 149 #define WDC_DMA_LBA48 0x04 150 151 int dma_status; /* status returned from dma_finish() */ 152 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 153 #define WDC_DMAST_ERR 0x02 /* DMA error */ 154 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 155 156 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 157 int (*claim_hw)(void *, int); 158 void (*free_hw)(void *); 159 160 /* if WDC_CAPABILITY_MODE set in 'cap' */ 161 void (*set_modes)(struct wdc_channel *); 162 163 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 164 void (*select)(struct wdc_channel *,int); 165 166 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 167 void (*irqack)(struct wdc_channel *); 168 }; 169 170 /* 171 * Public functions which can be called by ATA or ATAPI specific parts, 172 * or bus-specific backends. 173 */ 174 175 int wdcprobe(struct wdc_channel *); 176 void wdcattach(struct wdc_channel *); 177 int wdcdetach(struct device *, int); 178 int wdcactivate(struct device *, enum devact); 179 int wdcintr(void *); 180 void wdc_exec_xfer(struct wdc_channel *, struct ata_xfer *); 181 182 struct ata_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 183 #define WDC_CANSLEEP 0x00 184 #define WDC_NOSLEEP 0x01 185 186 void wdc_free_xfer (struct wdc_channel *, struct ata_xfer *); 187 void wdcstart(struct wdc_channel *); 188 void wdcrestart(void*); 189 190 int wdcreset(struct wdc_channel *, int); 191 #define RESET_POLL 1 192 #define RESET_SLEEP 0 /* wdcreset will use tsleep() */ 193 194 int wdcwait(struct wdc_channel *, int, int, int, int); 195 #define WDCWAIT_OK 0 /* we have what we asked */ 196 #define WDCWAIT_TOUT -1 /* timed out */ 197 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */ 198 199 int wdc_dmawait(struct wdc_channel *, struct ata_xfer *, int); 200 void wdcbit_bucket( struct wdc_channel *, int); 201 void wdccommand(struct wdc_channel *, u_int8_t, u_int8_t, u_int16_t, 202 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 203 void wdccommandext(struct wdc_channel *, u_int8_t, u_int8_t, u_int64_t, 204 u_int16_t); 205 void wdccommandshort(struct wdc_channel *, int, int); 206 void wdctimeout(void *arg); 207 void wdc_reset_channel(struct ata_drive_datas *, int); 208 209 int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*); 210 #define WDC_COMPLETE 0x01 211 #define WDC_QUEUED 0x02 212 #define WDC_TRY_AGAIN 0x03 213 214 int wdc_addref(struct wdc_channel *); 215 void wdc_delref(struct wdc_channel *); 216 void wdc_kill_pending(struct wdc_channel *); 217 218 void wdc_print_modes (struct wdc_channel *); 219 void wdc_probe_caps(struct ata_drive_datas*); 220 221 /* 222 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 223 * command is aborted. 224 */ 225 #define wdc_wait_for_drq(chp, timeout, flags) \ 226 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags)) 227 #define wdc_wait_for_unbusy(chp, timeout, flags) \ 228 wdcwait((chp), 0, 0, (timeout), (flags)) 229 #define wdc_wait_for_ready(chp, timeout, flags) \ 230 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags)) 231 232 /* ATA/ATAPI specs says a device can take 31s to reset */ 233 #define WDC_RESET_WAIT 31000 234 235 void wdc_atapibus_attach(struct atabus_softc *); 236 237 /* XXX */ 238 struct atabus_softc; 239 void atabusconfig(struct atabus_softc *); 240 241 #endif /* _DEV_IC_WDCVAR_H_ */ 242
Indexes created Sat Oct 18 17:09:52 GMT 2025