wdcvar.h revision 1.59
1 /* $NetBSD: wdcvar.h,v 1.59 2004/08/02 22:02:35 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_WDCVAR_H_ 40 #define _DEV_IC_WDCVAR_H_ 41 42 #include <sys/callout.h> 43 44 /* XXX For scsipi_adapter and scsipi_channel. */ 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/atapiconf.h> 47 48 #include <dev/ic/wdcreg.h> 49 50 #define WAITTIME (10 * hz) /* time to wait for a completion */ 51 /* this is a lot for hard drives, but not for cdroms */ 52 53 #define WDC_NREG 8 /* number of command registers */ 54 #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */ 55 56 /* 57 * Per-channel data 58 */ 59 struct wdc_channel { 60 struct callout ch_callout; /* callout handle */ 61 int ch_channel; /* location */ 62 struct wdc_softc *ch_wdc; /* controller's softc */ 63 64 /* Our registers */ 65 bus_space_tag_t cmd_iot; 66 bus_space_handle_t cmd_baseioh; 67 bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG]; 68 bus_space_tag_t ctl_iot; 69 bus_space_handle_t ctl_ioh; 70 71 /* data32{iot,ioh} are only used for 32 bit data xfers */ 72 bus_space_tag_t data32iot; 73 bus_space_handle_t data32ioh; 74 75 /* Our state */ 76 volatile int ch_flags; 77 #define WDCF_ACTIVE 0x01 /* channel is active */ 78 #define WDCF_SHUTDOWN 0x02 /* channel is shutting down */ 79 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 80 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 81 #define WDCF_DISABLED 0x80 /* channel is disabled */ 82 #define WDCF_TH_RUN 0x100 /* the kenrel thread is working */ 83 #define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */ 84 u_int8_t ch_status; /* copy of status register */ 85 u_int8_t ch_error; /* copy of error register */ 86 87 /* for the reset callback */ 88 int ch_reset_flags; 89 90 /* per-drive info */ 91 struct ata_drive_datas ch_drive[2]; 92 93 struct device *atabus; /* self */ 94 95 /* ATAPI children */ 96 struct device *atapibus; 97 struct scsipi_channel ch_atapi_channel; 98 99 /* ATA children */ 100 struct device *ata_drives[2]; 101 102 /* 103 * Channel queues. May be the same for all channels, if hw 104 * channels are not independent. 105 */ 106 struct ata_queue *ch_queue; 107 108 /* The channel kernel thread */ 109 struct proc *ch_thread; 110 }; 111 112 /* 113 * Per-controller data 114 */ 115 struct wdc_softc { 116 struct device sc_dev; /* generic device info */ 117 118 int cap; /* controller capabilities */ 119 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 120 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 121 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 122 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 123 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 124 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 125 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 126 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 127 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 128 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 129 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 130 #define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */ 131 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 132 #define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */ 133 u_int8_t PIO_cap; /* highest PIO mode supported */ 134 u_int8_t DMA_cap; /* highest DMA mode supported */ 135 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 136 int nchannels; /* # channels on this controller */ 137 struct wdc_channel **channels; /* channel-specific data (array) */ 138 139 /* 140 * The reference count here is used for both IDE and ATAPI devices. 141 */ 142 struct atapi_adapter sc_atapi_adapter; 143 144 /* Function used to probe for drives. */ 145 void (*drv_probe)(struct wdc_channel *); 146 147 /* if WDC_CAPABILITY_DMA set in 'cap' */ 148 void *dma_arg; 149 int (*dma_init)(void *, int, int, void *, size_t, int); 150 void (*dma_start)(void *, int, int); 151 int (*dma_finish)(void *, int, int, int); 152 /* flags passed to dma_init */ 153 #define WDC_DMA_READ 0x01 154 #define WDC_DMA_IRQW 0x02 155 #define WDC_DMA_LBA48 0x04 156 157 int dma_status; /* status returned from dma_finish() */ 158 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 159 #define WDC_DMAST_ERR 0x02 /* DMA error */ 160 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 161 162 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 163 int (*claim_hw)(void *, int); 164 void (*free_hw)(void *); 165 166 /* if WDC_CAPABILITY_MODE set in 'cap' */ 167 void (*set_modes)(struct wdc_channel *); 168 169 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 170 void (*select)(struct wdc_channel *,int); 171 172 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 173 void (*irqack)(struct wdc_channel *); 174 }; 175 176 /* 177 * Public functions which can be called by ATA or ATAPI specific parts, 178 * or bus-specific backends. 179 */ 180 181 void wdc_init_shadow_regs(struct wdc_channel *); 182 183 int wdcprobe(struct wdc_channel *); 184 void wdcattach(struct wdc_channel *); 185 int wdcdetach(struct device *, int); 186 int wdcactivate(struct device *, enum devact); 187 int wdcintr(void *); 188 void wdc_exec_xfer(struct wdc_channel *, struct ata_xfer *); 189 190 struct ata_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 191 #define WDC_CANSLEEP 0x00 192 #define WDC_NOSLEEP 0x01 193 194 void wdc_free_xfer (struct wdc_channel *, struct ata_xfer *); 195 void wdcstart(struct wdc_channel *); 196 void wdcrestart(void*); 197 198 int wdcreset(struct wdc_channel *, int); 199 #define RESET_POLL 1 200 #define RESET_SLEEP 0 /* wdcreset will use tsleep() */ 201 202 int wdcwait(struct wdc_channel *, int, int, int, int); 203 #define WDCWAIT_OK 0 /* we have what we asked */ 204 #define WDCWAIT_TOUT -1 /* timed out */ 205 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */ 206 207 int wdc_dmawait(struct wdc_channel *, struct ata_xfer *, int); 208 void wdcbit_bucket( struct wdc_channel *, int); 209 void wdccommand(struct wdc_channel *, u_int8_t, u_int8_t, u_int16_t, 210 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 211 void wdccommandext(struct wdc_channel *, u_int8_t, u_int8_t, u_int64_t, 212 u_int16_t); 213 void wdccommandshort(struct wdc_channel *, int, int); 214 void wdctimeout(void *arg); 215 void wdc_reset_drive(struct ata_drive_datas *, int); 216 void wdc_reset_channel(struct wdc_channel *, int); 217 218 int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*); 219 #define WDC_COMPLETE 0x01 220 #define WDC_QUEUED 0x02 221 #define WDC_TRY_AGAIN 0x03 222 223 int wdc_addref(struct wdc_channel *); 224 void wdc_delref(struct wdc_channel *); 225 void wdc_kill_pending(struct wdc_channel *); 226 227 void wdc_print_modes (struct wdc_channel *); 228 void wdc_probe_caps(struct ata_drive_datas*); 229 230 /* 231 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 232 * command is aborted. 233 */ 234 #define wdc_wait_for_drq(chp, timeout, flags) \ 235 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags)) 236 #define wdc_wait_for_unbusy(chp, timeout, flags) \ 237 wdcwait((chp), 0, 0, (timeout), (flags)) 238 #define wdc_wait_for_ready(chp, timeout, flags) \ 239 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags)) 240 241 /* ATA/ATAPI specs says a device can take 31s to reset */ 242 #define WDC_RESET_WAIT 31000 243 244 void wdc_atapibus_attach(struct atabus_softc *); 245 246 /* XXX */ 247 struct atabus_softc; 248 void atabusconfig(struct atabus_softc *); 249 250 #endif /* _DEV_IC_WDCVAR_H_ */ 251
Indexes created Tue Oct 21 08:09:48 GMT 2025