wdcvar.h revision 1.63
1 /* $NetBSD: wdcvar.h,v 1.63 2004/08/11 17:49:27 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_WDCVAR_H_ 40 #define _DEV_IC_WDCVAR_H_ 41 42 #include <sys/callout.h> 43 44 /* XXX For scsipi_adapter and scsipi_channel. */ 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/atapiconf.h> 47 48 #include <dev/ic/wdcreg.h> 49 50 #define WAITTIME (10 * hz) /* time to wait for a completion */ 51 /* this is a lot for hard drives, but not for cdroms */ 52 53 #define WDC_NREG 8 /* number of command registers */ 54 #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */ 55 56 /* 57 * Per-channel data 58 */ 59 struct wdc_channel { 60 struct callout ch_callout; /* callout handle */ 61 int ch_channel; /* location */ 62 struct wdc_softc *ch_wdc; /* controller's softc */ 63 64 /* Our registers */ 65 bus_space_tag_t cmd_iot; 66 bus_space_handle_t cmd_baseioh; 67 bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG]; 68 bus_space_tag_t ctl_iot; 69 bus_space_handle_t ctl_ioh; 70 bus_space_tag_t data32iot; 71 bus_space_handle_t data32ioh; 72 73 /* Our state */ 74 volatile int ch_flags; 75 #define WDCF_SHUTDOWN 0x02 /* channel is shutting down */ 76 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 77 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 78 #define WDCF_DISABLED 0x80 /* channel is disabled */ 79 #define WDCF_TH_RUN 0x100 /* the kenrel thread is working */ 80 #define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */ 81 u_int8_t ch_status; /* copy of status register */ 82 u_int8_t ch_error; /* copy of error register */ 83 84 /* for the reset callback */ 85 int ch_reset_flags; 86 87 /* per-drive info */ 88 struct ata_drive_datas ch_drive[2]; 89 90 struct device *atabus; /* self */ 91 92 /* ATAPI children */ 93 struct device *atapibus; 94 struct scsipi_channel ch_atapi_channel; 95 96 /* ATA children */ 97 struct device *ata_drives[2]; 98 99 /* 100 * Channel queues. May be the same for all channels, if hw 101 * channels are not independent. 102 */ 103 struct ata_queue *ch_queue; 104 105 /* The channel kernel thread */ 106 struct proc *ch_thread; 107 }; 108 109 /* 110 * Per-controller data 111 */ 112 struct wdc_softc { 113 struct device sc_dev; /* generic device info */ 114 115 int cap; /* controller capabilities */ 116 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 117 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 118 #define WDC_CAPABILITY_DATA1K 0x8000 /* CF-style data port */ 119 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 120 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 121 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 122 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 123 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 124 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 125 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 126 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 127 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 128 #define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */ 129 #define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */ 130 #define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */ 131 u_int8_t PIO_cap; /* highest PIO mode supported */ 132 u_int8_t DMA_cap; /* highest DMA mode supported */ 133 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 134 int nchannels; /* # channels on this controller */ 135 struct wdc_channel **channels; /* channel-specific data (array) */ 136 137 /* 138 * The reference count here is used for both IDE and ATAPI devices. 139 */ 140 struct atapi_adapter sc_atapi_adapter; 141 142 /* Function used to probe for drives. */ 143 void (*drv_probe)(struct wdc_channel *); 144 145 /* if WDC_CAPABILITY_DMA set in 'cap' */ 146 void *dma_arg; 147 int (*dma_init)(void *, int, int, void *, size_t, int); 148 void (*dma_start)(void *, int, int); 149 int (*dma_finish)(void *, int, int, int); 150 /* flags passed to dma_init */ 151 #define WDC_DMA_READ 0x01 152 #define WDC_DMA_IRQW 0x02 153 #define WDC_DMA_LBA48 0x04 154 155 /* values passed to dma_finish */ 156 #define WDC_DMAEND_END 0 /* check for proper end of a DMA xfer */ 157 #define WDC_DMAEND_ABRT 1 /* abort a DMA xfer, verbose */ 158 #define WDC_DMAEND_ABRT_QUIET 2 /* abort a DMA xfer, quiet */ 159 160 int dma_status; /* status returned from dma_finish() */ 161 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 162 #define WDC_DMAST_ERR 0x02 /* DMA error */ 163 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 164 165 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 166 int (*claim_hw)(void *, int); 167 void (*free_hw)(void *); 168 169 /* if WDC_CAPABILITY_MODE set in 'cap' */ 170 void (*set_modes)(struct wdc_channel *); 171 172 /* if WDC_CAPABILITY_SELECT set in 'cap' */ 173 void (*select)(struct wdc_channel *,int); 174 175 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 176 void (*irqack)(struct wdc_channel *); 177 }; 178 179 /* 180 * Public functions which can be called by ATA or ATAPI specific parts, 181 * or bus-specific backends. 182 */ 183 184 void wdc_init_shadow_regs(struct wdc_channel *); 185 186 int wdcprobe(struct wdc_channel *); 187 void wdcattach(struct wdc_channel *); 188 int wdcdetach(struct device *, int); 189 int wdcactivate(struct device *, enum devact); 190 int wdcintr(void *); 191 void wdc_exec_xfer(struct wdc_channel *, struct ata_xfer *); 192 193 struct ata_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 194 #define WDC_CANSLEEP 0x00 195 #define WDC_NOSLEEP 0x01 196 197 void wdc_free_xfer (struct wdc_channel *, struct ata_xfer *); 198 void wdcstart(struct wdc_channel *); 199 void wdcrestart(void*); 200 201 int wdcreset(struct wdc_channel *, int); 202 #define RESET_POLL 1 203 #define RESET_SLEEP 0 /* wdcreset will use tsleep() */ 204 205 int wdcwait(struct wdc_channel *, int, int, int, int); 206 #define WDCWAIT_OK 0 /* we have what we asked */ 207 #define WDCWAIT_TOUT -1 /* timed out */ 208 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */ 209 210 void wdc_datain_pio(struct wdc_channel *, int, void *, size_t); 211 void wdc_dataout_pio(struct wdc_channel *, int, void *, size_t); 212 void wdcbit_bucket(struct wdc_channel *, int); 213 214 int wdc_dmawait(struct wdc_channel *, struct ata_xfer *, int); 215 void wdccommand(struct wdc_channel *, u_int8_t, u_int8_t, u_int16_t, 216 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 217 void wdccommandext(struct wdc_channel *, u_int8_t, u_int8_t, u_int64_t, 218 u_int16_t); 219 void wdccommandshort(struct wdc_channel *, int, int); 220 void wdctimeout(void *arg); 221 void wdc_reset_drive(struct ata_drive_datas *, int); 222 void wdc_reset_channel(struct wdc_channel *, int); 223 224 int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*); 225 #define WDC_COMPLETE 0x01 226 #define WDC_QUEUED 0x02 227 #define WDC_TRY_AGAIN 0x03 228 229 int wdc_addref(struct wdc_channel *); 230 void wdc_delref(struct wdc_channel *); 231 void wdc_kill_pending(struct ata_drive_datas *); 232 233 void wdc_print_modes (struct wdc_channel *); 234 void wdc_probe_caps(struct ata_drive_datas*); 235 236 /* 237 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 238 * command is aborted. 239 */ 240 #define wdc_wait_for_drq(chp, timeout, flags) \ 241 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags)) 242 #define wdc_wait_for_unbusy(chp, timeout, flags) \ 243 wdcwait((chp), 0, 0, (timeout), (flags)) 244 #define wdc_wait_for_ready(chp, timeout, flags) \ 245 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags)) 246 247 /* ATA/ATAPI specs says a device can take 31s to reset */ 248 #define WDC_RESET_WAIT 31000 249 250 void wdc_atapibus_attach(struct atabus_softc *); 251 252 /* XXX */ 253 struct atabus_softc; 254 void atabusconfig(struct atabus_softc *); 255 256 #endif /* _DEV_IC_WDCVAR_H_ */ 257
Indexes created Sun Oct 19 02:09:48 GMT 2025