wdcvar.h revision 1.90.2.1
1 /* $NetBSD: wdcvar.h,v 1.90.2.1 2010/11/06 08:08:29 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_IC_WDCVAR_H_ 33 #define _DEV_IC_WDCVAR_H_ 34 35 #include <sys/callout.h> 36 37 #include <dev/ata/ataconf.h> 38 #include <dev/ic/wdcreg.h> 39 40 #define WAITTIME (10 * hz) /* time to wait for a completion */ 41 /* this is a lot for hard drives, but not for cdroms */ 42 43 #define WDC_NREG 8 /* number of command registers */ 44 #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */ 45 46 struct wdc_regs { 47 /* Our registers */ 48 bus_space_tag_t cmd_iot; 49 bus_space_handle_t cmd_baseioh; 50 bus_size_t cmd_ios; 51 bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG]; 52 bus_space_tag_t ctl_iot; 53 bus_space_handle_t ctl_ioh; 54 bus_size_t ctl_ios; 55 56 /* data32{iot,ioh} are only used for 32-bit data xfers */ 57 bus_space_tag_t data32iot; 58 bus_space_handle_t data32ioh; 59 60 /* SATA native registers */ 61 bus_space_tag_t sata_iot; 62 bus_space_handle_t sata_baseioh; 63 bus_space_handle_t sata_control; 64 bus_space_handle_t sata_status; 65 bus_space_handle_t sata_error; 66 67 }; 68 69 /* 70 * Per-controller data 71 */ 72 struct wdc_softc { 73 struct atac_softc sc_atac; /* generic ATA controller info */ 74 75 struct wdc_regs *regs; /* register array (per-channel) */ 76 77 int cap; /* controller capabilities */ 78 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 79 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 80 #define WDC_CAPABILITY_WIDEREGS 0x0400 /* Ctrl has wide (16bit) registers */ 81 82 #if NATA_DMA || NATA_PIOBM 83 /* if WDC_CAPABILITY_DMA set in 'cap' */ 84 void *dma_arg; 85 int (*dma_init)(void *, int, int, void *, size_t, int); 86 void (*dma_start)(void *, int, int); 87 int (*dma_finish)(void *, int, int, int); 88 #if NATA_PIOBM 89 void (*piobm_start)(void *, int, int, int, int, int); 90 void (*piobm_done)(void *, int, int); 91 #endif 92 /* flags passed to dma_init */ 93 #define WDC_DMA_READ 0x01 94 #define WDC_DMA_IRQW 0x02 95 #define WDC_DMA_LBA48 0x04 96 #define WDC_DMA_PIOBM_ATA 0x08 97 #define WDC_DMA_PIOBM_ATAPI 0x10 98 #if NATA_PIOBM 99 /* flags passed to piobm_start */ 100 #define WDC_PIOBM_XFER_IRQ 0x01 101 #endif 102 103 /* values passed to dma_finish */ 104 #define WDC_DMAEND_END 0 /* check for proper end of a DMA xfer */ 105 #define WDC_DMAEND_ABRT 1 /* abort a DMA xfer, verbose */ 106 #define WDC_DMAEND_ABRT_QUIET 2 /* abort a DMA xfer, quiet */ 107 108 int dma_status; /* status returned from dma_finish() */ 109 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 110 #define WDC_DMAST_ERR 0x02 /* DMA error */ 111 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 112 #endif /* NATA_DMA || NATA_PIOBM */ 113 114 /* Optional callback to select drive. */ 115 void (*select)(struct ata_channel *,int); 116 117 /* Optional callback to ack IRQ. */ 118 void (*irqack)(struct ata_channel *); 119 120 /* Optional callback to perform a bus reset */ 121 void (*reset)(struct ata_channel *, int); 122 123 /* overridden if the backend has a different data transfer method */ 124 void (*datain_pio)(struct ata_channel *, int, void *, size_t); 125 void (*dataout_pio)(struct ata_channel *, int, void *, size_t); 126 }; 127 128 /* Given an ata_channel, get the wdc_softc. */ 129 #define CHAN_TO_WDC(chp) ((struct wdc_softc *)(chp)->ch_atac) 130 131 /* Given an ata_channel, get the wdc_regs. */ 132 #define CHAN_TO_WDC_REGS(chp) (&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel]) 133 134 /* 135 * Public functions which can be called by ATA or ATAPI specific parts, 136 * or bus-specific backends. 137 */ 138 139 void wdc_allocate_regs(struct wdc_softc *); 140 void wdc_init_shadow_regs(struct ata_channel *); 141 142 int wdcprobe(struct ata_channel *); 143 void wdcattach(struct ata_channel *); 144 int wdcdetach(device_t, int); 145 void wdc_childdetached(device_t, device_t); 146 int wdcintr(void *); 147 148 void wdc_sataprobe(struct ata_channel *); 149 void wdc_drvprobe(struct ata_channel *); 150 151 void wdcrestart(void*); 152 153 int wdcwait(struct ata_channel *, int, int, int, int); 154 #define WDCWAIT_OK 0 /* we have what we asked */ 155 #define WDCWAIT_TOUT -1 /* timed out */ 156 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */ 157 158 void wdcbit_bucket(struct ata_channel *, int); 159 160 int wdc_dmawait(struct ata_channel *, struct ata_xfer *, int); 161 void wdccommand(struct ata_channel *, u_int8_t, u_int8_t, u_int16_t, 162 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 163 void wdccommandext(struct ata_channel *, u_int8_t, u_int8_t, u_int64_t, 164 u_int16_t); 165 void wdccommandshort(struct ata_channel *, int, int); 166 void wdctimeout(void *arg); 167 void wdc_reset_drive(struct ata_drive_datas *, int); 168 void wdc_reset_channel(struct ata_channel *, int); 169 void wdc_do_reset(struct ata_channel *, int); 170 171 int wdc_exec_command(struct ata_drive_datas *, struct ata_command*); 172 173 /* 174 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 175 * command is aborted. 176 */ 177 #define wdc_wait_for_drq(chp, timeout, flags) \ 178 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags)) 179 #define wdc_wait_for_unbusy(chp, timeout, flags) \ 180 wdcwait((chp), 0, 0, (timeout), (flags)) 181 #define wdc_wait_for_ready(chp, timeout, flags) \ 182 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags)) 183 184 /* ATA/ATAPI specs says a device can take 31s to reset */ 185 #define WDC_RESET_WAIT 31000 186 187 void wdc_atapibus_attach(struct atabus_softc *); 188 189 #endif /* _DEV_IC_WDCVAR_H_ */ 190
Indexes created Sun Oct 19 02:09:48 GMT 2025