wireg.h revision 1.10 1 1.10 explorer /* $NetBSD: wireg.h,v 1.10 2001/09/22 17:22:25 explorer Exp $ */
2 1.1 ichiro
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 1997, 1998, 1999
5 1.1 ichiro * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
16 1.1 ichiro * must display the following acknowledgement:
17 1.1 ichiro * This product includes software developed by Bill Paul.
18 1.1 ichiro * 4. Neither the name of the author nor the names of any co-contributors
19 1.1 ichiro * may be used to endorse or promote products derived from this software
20 1.1 ichiro * without specific prior written permission.
21 1.1 ichiro *
22 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 1.1 ichiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 1.1 ichiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 1.1 ichiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 1.1 ichiro * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 1.1 ichiro * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 1.1 ichiro * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 1.1 ichiro * THE POSSIBILITY OF SUCH DAMAGE.
33 1.1 ichiro */
34 1.1 ichiro
35 1.1 ichiro /*
36 1.1 ichiro * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the
37 1.1 ichiro * Oslo IETF plenary meeting.
38 1.1 ichiro */
39 1.1 ichiro
40 1.1 ichiro #define WI_TIMEOUT 65536
41 1.1 ichiro
42 1.1 ichiro #define WI_PORT0 0
43 1.1 ichiro #define WI_PORT1 1
44 1.1 ichiro #define WI_PORT2 2
45 1.1 ichiro #define WI_PORT3 3
46 1.1 ichiro #define WI_PORT4 4
47 1.1 ichiro #define WI_PORT5 5
48 1.1 ichiro
49 1.1 ichiro /* Default port: 0 (only 0 exists on stations) */
50 1.1 ichiro #define WI_DEFAULT_PORT (WI_PORT0 << 8)
51 1.1 ichiro
52 1.1 ichiro /* Default TX rate: 2Mbps, auto fallback */
53 1.1 ichiro #define WI_DEFAULT_TX_RATE 3
54 1.1 ichiro
55 1.1 ichiro /* Default network name: ANY */
56 1.1 ichiro /*
57 1.1 ichiro * [sommerfeld 1999/07/15] Changed from "ANY" to ""; according to Bill Fenner,
58 1.1 ichiro * ANY is used in MS driver user interfaces, while "" is used over the
59 1.1 ichiro * wire..
60 1.1 ichiro */
61 1.1 ichiro #define WI_DEFAULT_NETNAME ""
62 1.1 ichiro
63 1.1 ichiro #define WI_DEFAULT_AP_DENSITY 1
64 1.1 ichiro
65 1.1 ichiro #define WI_DEFAULT_RTS_THRESH 2347
66 1.5 tsubai
67 1.1 ichiro #define WI_DEFAULT_DATALEN 2304
68 1.1 ichiro
69 1.1 ichiro #define WI_DEFAULT_CREATE_IBSS 0
70 1.1 ichiro
71 1.1 ichiro #define WI_DEFAULT_PM_ENABLED 0
72 1.1 ichiro
73 1.1 ichiro #define WI_DEFAULT_MAX_SLEEP 100
74 1.1 ichiro
75 1.2 ichiro #define WI_DEFAULT_ROAMING 1
76 1.2 ichiro
77 1.2 ichiro #define WI_DEFAULT_AUTHTYPE 1
78 1.2 ichiro
79 1.1 ichiro #ifdef __NetBSD__
80 1.1 ichiro #define OS_STRING_NAME "NetBSD"
81 1.1 ichiro #endif
82 1.1 ichiro #ifdef __FreeBSD__
83 1.1 ichiro #define OS_STRING_NAME "FreeBSD"
84 1.1 ichiro #endif
85 1.1 ichiro #ifdef __OpenBSD__
86 1.1 ichiro #define OS_STRING_NAME "OpenBSD"
87 1.1 ichiro #endif
88 1.1 ichiro
89 1.1 ichiro #define WI_DEFAULT_NODENAME OS_STRING_NAME " WaveLAN/IEEE node"
90 1.1 ichiro
91 1.1 ichiro #define WI_DEFAULT_IBSS OS_STRING_NAME " IBSS"
92 1.1 ichiro
93 1.1 ichiro #define WI_DEFAULT_CHAN 3
94 1.1 ichiro
95 1.1 ichiro /*
96 1.1 ichiro * register space access macros
97 1.1 ichiro */
98 1.1 ichiro #define CSR_WRITE_4(sc, reg, val) \
99 1.1 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val)
100 1.1 ichiro #define CSR_WRITE_2(sc, reg, val) \
101 1.1 ichiro bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
102 1.1 ichiro #define CSR_WRITE_1(sc, reg, val) \
103 1.1 ichiro bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)
104 1.1 ichiro
105 1.1 ichiro #define CSR_READ_4(sc, reg) \
106 1.1 ichiro bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg)
107 1.1 ichiro #define CSR_READ_2(sc, reg) \
108 1.1 ichiro bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
109 1.1 ichiro #define CSR_READ_1(sc, reg) \
110 1.1 ichiro bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg)
111 1.1 ichiro
112 1.5 tsubai #ifndef __BUS_SPACE_HAS_STREAM_METHODS
113 1.5 tsubai #define bus_space_write_stream_2 bus_space_write_2
114 1.7 toshii #define bus_space_write_multi_stream_2 bus_space_write_multi_2
115 1.5 tsubai #define bus_space_read_stream_2 bus_space_read_2
116 1.7 toshii #define bus_space_read_multi_stream_2 bus_space_read_multi_2
117 1.5 tsubai #endif
118 1.5 tsubai
119 1.5 tsubai #define CSR_WRITE_STREAM_2(sc, reg, val) \
120 1.5 tsubai bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, reg, val)
121 1.7 toshii #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
122 1.7 toshii bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)
123 1.5 tsubai #define CSR_READ_STREAM_2(sc, reg) \
124 1.5 tsubai bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, reg)
125 1.7 toshii #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \
126 1.7 toshii bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, buf, count)
127 1.5 tsubai
128 1.1 ichiro /*
129 1.1 ichiro * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
130 1.1 ichiro * calls 'Hermes.' In typical fashion, getting documentation about this
131 1.1 ichiro * controller is about as easy as squeezing blood from a stone. Here
132 1.1 ichiro * is more or less what I know:
133 1.1 ichiro *
134 1.1 ichiro * - The Hermes controller is firmware driven, and the host interacts
135 1.1 ichiro * with the Hermes via a firmware interface, which can change.
136 1.1 ichiro *
137 1.1 ichiro * - The Hermes is described in a document called: "Hermes Firmware
138 1.1 ichiro * WaveLAN/IEEE Station Functions," document #010245, which of course
139 1.1 ichiro * Lucent will not release without an NDA.
140 1.1 ichiro *
141 1.1 ichiro * - Lucent has created a library called HCF (Hardware Control Functions)
142 1.1 ichiro * though which it wants developers to interact with the card. The HCF
143 1.1 ichiro * is needlessly complex, ill conceived and badly documented. Actually,
144 1.1 ichiro * the comments in the HCP code itself aren't bad, but the publically
145 1.1 ichiro * available manual that comes with it is awful, probably due largely to
146 1.1 ichiro * the fact that it has been emasculated in order to hide information
147 1.1 ichiro * that Lucent wants to keep proprietary. The purpose of the HCF seems
148 1.1 ichiro * to be to insulate the driver programmer from the Hermes itself so that
149 1.1 ichiro * Lucent has an excuse not to release programming in for it.
150 1.1 ichiro *
151 1.1 ichiro * - Lucent only makes available documentation and code for 'HCF Light'
152 1.1 ichiro * which is a stripped down version of HCF with certain features not
153 1.1 ichiro * implemented, most notably support for 802.11 frames.
154 1.1 ichiro *
155 1.1 ichiro * - The HCF code which I have seen blows goats. Whoever decided to
156 1.1 ichiro * use a 132 column format should be shot.
157 1.1 ichiro *
158 1.1 ichiro * Rather than actually use the Lucent HCF library, I have stripped all
159 1.1 ichiro * the useful information from it and used it to create a driver in the
160 1.1 ichiro * usual BSD form. Note: I don't want to hear anybody whining about the
161 1.1 ichiro * fact that the Lucent code is GPLed and mine isn't. I did not actually
162 1.1 ichiro * put any of Lucent's code in this driver: I only used it as a reference
163 1.1 ichiro * to obtain information about the underlying hardware. The Hermes
164 1.1 ichiro * programming interface is not GPLed, so bite me.
165 1.1 ichiro */
166 1.1 ichiro
167 1.1 ichiro /*
168 1.1 ichiro * Size of Hermes I/O space.
169 1.1 ichiro */
170 1.1 ichiro #define WI_IOSIZE 0x40
171 1.1 ichiro
172 1.1 ichiro /*
173 1.1 ichiro * Hermes register definitions and what little I know about them.
174 1.1 ichiro */
175 1.1 ichiro
176 1.1 ichiro /* Hermes command/status registers. */
177 1.1 ichiro #define WI_COMMAND 0x00
178 1.1 ichiro #define WI_PARAM0 0x02
179 1.1 ichiro #define WI_PARAM1 0x04
180 1.1 ichiro #define WI_PARAM2 0x06
181 1.1 ichiro #define WI_STATUS 0x08
182 1.1 ichiro #define WI_RESP0 0x0A
183 1.1 ichiro #define WI_RESP1 0x0C
184 1.1 ichiro #define WI_RESP2 0x0E
185 1.1 ichiro
186 1.1 ichiro /* Command register values. */
187 1.1 ichiro #define WI_CMD_BUSY 0x8000 /* busy bit */
188 1.1 ichiro #define WI_CMD_INI 0x0000 /* initialize */
189 1.1 ichiro #define WI_CMD_ENABLE 0x0001 /* enable */
190 1.1 ichiro #define WI_CMD_DISABLE 0x0002 /* disable */
191 1.1 ichiro #define WI_CMD_DIAG 0x0003
192 1.1 ichiro #define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
193 1.1 ichiro #define WI_CMD_TX 0x000B /* transmit */
194 1.1 ichiro #define WI_CMD_NOTIFY 0x0010
195 1.1 ichiro #define WI_CMD_INQUIRE 0x0011
196 1.1 ichiro #define WI_CMD_ACCESS 0x0021
197 1.1 ichiro #define WI_CMD_PROGRAM 0x0022
198 1.10 explorer #define WI_CMD_READMIF 0x0030 /* prism2 only? */
199 1.10 explorer #define WI_CMD_WRITEMIF 0x0031 /* prism2 only? */
200 1.10 explorer #define WI_CMD_TEST 0x0038 /* prism2 only? */
201 1.1 ichiro
202 1.1 ichiro #define WI_CMD_CODE_MASK 0x003F
203 1.1 ichiro
204 1.1 ichiro /*
205 1.10 explorer * prism2 test mode commands
206 1.10 explorer */
207 1.10 explorer #define WI_TEST_MONITOR 0x000b
208 1.10 explorer #define WI_TEST_STOP 0x000f
209 1.10 explorer
210 1.10 explorer /*
211 1.1 ichiro * Reclaim qualifier bit, applicable to the
212 1.1 ichiro * TX and INQUIRE commands.
213 1.1 ichiro */
214 1.1 ichiro #define WI_RECLAIM 0x0100 /* reclaim NIC memory */
215 1.1 ichiro
216 1.1 ichiro /*
217 1.1 ichiro * ACCESS command qualifier bits.
218 1.1 ichiro */
219 1.1 ichiro #define WI_ACCESS_READ 0x0000
220 1.1 ichiro #define WI_ACCESS_WRITE 0x0100
221 1.1 ichiro
222 1.1 ichiro /*
223 1.1 ichiro * PROGRAM command qualifier bits.
224 1.1 ichiro */
225 1.1 ichiro #define WI_PROGRAM_DISABLE 0x0000
226 1.1 ichiro #define WI_PROGRAM_ENABLE_RAM 0x0100
227 1.1 ichiro #define WI_PROGRAM_ENABLE_NVRAM 0x0200
228 1.1 ichiro #define WI_PROGRAM_NVRAM 0x0300
229 1.1 ichiro
230 1.1 ichiro /* Status register values */
231 1.1 ichiro #define WI_STAT_CMD_CODE 0x003F
232 1.1 ichiro #define WI_STAT_DIAG_ERR 0x0100
233 1.1 ichiro #define WI_STAT_INQ_ERR 0x0500
234 1.1 ichiro #define WI_STAT_CMD_RESULT 0x7F00
235 1.1 ichiro
236 1.1 ichiro /* memory handle management registers */
237 1.1 ichiro #define WI_INFO_FID 0x10
238 1.1 ichiro #define WI_RX_FID 0x20
239 1.1 ichiro #define WI_ALLOC_FID 0x22
240 1.1 ichiro #define WI_TX_CMP_FID 0x24
241 1.1 ichiro
242 1.1 ichiro /*
243 1.1 ichiro * Buffer Access Path (BAP) registers.
244 1.1 ichiro * These are I/O channels. I believe you can use each one for
245 1.1 ichiro * any desired purpose independently of the other. In general
246 1.1 ichiro * though, we use BAP1 for reading and writing LTV records and
247 1.1 ichiro * reading received data frames, and BAP0 for writing transmit
248 1.1 ichiro * frames. This is a convention though, not a rule.
249 1.1 ichiro */
250 1.1 ichiro #define WI_SEL0 0x18
251 1.1 ichiro #define WI_SEL1 0x1A
252 1.1 ichiro #define WI_OFF0 0x1C
253 1.1 ichiro #define WI_OFF1 0x1E
254 1.1 ichiro #define WI_DATA0 0x36
255 1.1 ichiro #define WI_DATA1 0x38
256 1.1 ichiro #define WI_BAP0 WI_DATA0
257 1.1 ichiro #define WI_BAP1 WI_DATA1
258 1.1 ichiro
259 1.1 ichiro #define WI_OFF_BUSY 0x8000
260 1.1 ichiro #define WI_OFF_ERR 0x4000
261 1.1 ichiro #define WI_OFF_DATAOFF 0x0FFF
262 1.1 ichiro
263 1.1 ichiro /* Event registers */
264 1.1 ichiro #define WI_EVENT_STAT 0x30 /* Event status */
265 1.1 ichiro #define WI_INT_EN 0x32 /* Interrupt enable/disable */
266 1.1 ichiro #define WI_EVENT_ACK 0x34 /* Ack event */
267 1.1 ichiro
268 1.1 ichiro /* Events */
269 1.1 ichiro #define WI_EV_TICK 0x8000 /* aux timer tick */
270 1.1 ichiro #define WI_EV_RES 0x4000 /* controller h/w error (time out) */
271 1.1 ichiro #define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */
272 1.1 ichiro #define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */
273 1.10 explorer #define WI_EV_AWAKE 0x0100
274 1.1 ichiro #define WI_EV_INFO 0x0080 /* async info frame */
275 1.1 ichiro #define WI_EV_CMD 0x0010 /* command completed */
276 1.1 ichiro #define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
277 1.1 ichiro #define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */
278 1.1 ichiro #define WI_EV_TX 0x0002 /* async xmit completed succesfully */
279 1.1 ichiro #define WI_EV_RX 0x0001 /* async rx completed */
280 1.1 ichiro
281 1.1 ichiro #define WI_INTRS \
282 1.1 ichiro (WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP)
283 1.1 ichiro
284 1.1 ichiro /* Host software registers */
285 1.1 ichiro #define WI_SW0 0x28
286 1.1 ichiro #define WI_SW1 0x2A
287 1.1 ichiro #define WI_SW2 0x2C
288 1.1 ichiro #define WI_SW3 0x2E
289 1.1 ichiro
290 1.1 ichiro #define WI_CNTL 0x14
291 1.1 ichiro
292 1.1 ichiro #define WI_CNTL_AUX_ENA 0xC000
293 1.1 ichiro #define WI_CNTL_AUX_ENA_STAT 0xC000
294 1.1 ichiro #define WI_CNTL_AUX_DIS_STAT 0x0000
295 1.1 ichiro #define WI_CNTL_AUX_ENA_CNTL 0x8000
296 1.1 ichiro #define WI_CNTL_AUX_DIS_CNTL 0x4000
297 1.1 ichiro
298 1.1 ichiro #define WI_AUX_PAGE 0x3A
299 1.1 ichiro #define WI_AUX_OFFSET 0x3C
300 1.1 ichiro #define WI_AUX_DATA 0x3E
301 1.1 ichiro
302 1.1 ichiro /*
303 1.1 ichiro * One form of communication with the Hermes is with what Lucent calls
304 1.1 ichiro * LTV records, where LTV stands for Length, Type and Value. The length
305 1.1 ichiro * and type are 16 bits and are in native byte order. The value is in
306 1.1 ichiro * multiples of 16 bits and is in little endian byte order.
307 1.1 ichiro */
308 1.1 ichiro struct wi_ltv_gen {
309 1.1 ichiro u_int16_t wi_len;
310 1.1 ichiro u_int16_t wi_type;
311 1.1 ichiro u_int16_t wi_val;
312 1.1 ichiro };
313 1.1 ichiro
314 1.1 ichiro struct wi_ltv_str {
315 1.1 ichiro u_int16_t wi_len;
316 1.1 ichiro u_int16_t wi_type;
317 1.1 ichiro u_int16_t wi_str[17];
318 1.1 ichiro };
319 1.1 ichiro
320 1.1 ichiro #define WI_SETVAL(recno, val) \
321 1.1 ichiro do { \
322 1.1 ichiro struct wi_ltv_gen g; \
323 1.1 ichiro \
324 1.1 ichiro g.wi_len = 2; \
325 1.1 ichiro g.wi_type = recno; \
326 1.5 tsubai g.wi_val = htole16(val); \
327 1.1 ichiro wi_write_record(sc, &g); \
328 1.1 ichiro } while (0)
329 1.1 ichiro
330 1.1 ichiro #define WI_SETSTR(recno, str) \
331 1.1 ichiro do { \
332 1.1 ichiro struct wi_ltv_str s; \
333 1.1 ichiro int l; \
334 1.1 ichiro \
335 1.1 ichiro l = (strlen(str) + 1) & ~0x1; \
336 1.9 thorpej memset((char *)&s, 0, sizeof(s)); \
337 1.1 ichiro s.wi_len = (l / 2) + 2; \
338 1.1 ichiro s.wi_type = recno; \
339 1.5 tsubai s.wi_str[0] = htole16(strlen(str)); \
340 1.8 thorpej memcpy((char *)&s.wi_str[1], str, strlen(str)); \
341 1.1 ichiro wi_write_record(sc, (struct wi_ltv_gen *)&s); \
342 1.1 ichiro } while (0)
343 1.1 ichiro
344 1.1 ichiro /*
345 1.1 ichiro * Download buffer location and length (0xFD01).
346 1.1 ichiro */
347 1.1 ichiro #define WI_RID_DNLD_BUF 0xFD01
348 1.1 ichiro struct wi_ltv_dnld_buf {
349 1.1 ichiro u_int16_t wi_len;
350 1.1 ichiro u_int16_t wi_type;
351 1.1 ichiro u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/
352 1.1 ichiro u_int16_t wi_buf_off; /* offset of idb */
353 1.1 ichiro u_int16_t wi_buf_len; /* len of idb */
354 1.1 ichiro };
355 1.1 ichiro
356 1.1 ichiro /*
357 1.1 ichiro * Mem sizes (0xFD02).
358 1.1 ichiro */
359 1.1 ichiro #define WI_RID_MEMSZ 0xFD02
360 1.1 ichiro struct wi_ltv_memsz {
361 1.1 ichiro u_int16_t wi_len;
362 1.1 ichiro u_int16_t wi_type;
363 1.1 ichiro u_int16_t wi_mem_ram;
364 1.1 ichiro u_int16_t wi_mem_nvram;
365 1.2 ichiro };
366 1.2 ichiro
367 1.2 ichiro /*
368 1.2 ichiro * NIC Identification (0xFD0B)
369 1.2 ichiro */
370 1.2 ichiro #define WI_RID_CARDID 0xFD0B
371 1.3 ichiro #define WI_RID_IDENT 0xFD20
372 1.2 ichiro struct wi_ltv_ver {
373 1.2 ichiro u_int16_t wi_len;
374 1.2 ichiro u_int16_t wi_type;
375 1.2 ichiro u_int16_t wi_ver[4];
376 1.2 ichiro #define WI_NIC_EVB2 0x8000
377 1.2 ichiro #define WI_NIC_HWB3763 0x8001
378 1.2 ichiro #define WI_NIC_HWB3163 0x8002
379 1.2 ichiro #define WI_NIC_HWB3163B 0x8003
380 1.2 ichiro #define WI_NIC_EVB3 0x8004
381 1.2 ichiro #define WI_NIC_HWB1153 0x8007
382 1.4 ichiro #define WI_NIC_P2_SST 0x8008 /* Prism2 with SST flush */
383 1.6 ichiro #define WI_NIC_PRISM2_5 0x800C
384 1.1 ichiro };
385 1.1 ichiro
386 1.1 ichiro /*
387 1.1 ichiro * List of intended regulatory domains (0xFD11).
388 1.1 ichiro */
389 1.1 ichiro #define WI_RID_DOMAINS 0xFD11
390 1.1 ichiro struct wi_ltv_domains {
391 1.1 ichiro u_int16_t wi_len;
392 1.1 ichiro u_int16_t wi_type;
393 1.1 ichiro u_int16_t wi_domains[6];
394 1.1 ichiro };
395 1.1 ichiro
396 1.1 ichiro /*
397 1.1 ichiro * CIS struct (0xFD13).
398 1.1 ichiro */
399 1.1 ichiro #define WI_RID_CIS 0xFD13
400 1.1 ichiro struct wi_ltv_cis {
401 1.1 ichiro u_int16_t wi_len;
402 1.1 ichiro u_int16_t wi_type;
403 1.1 ichiro u_int16_t wi_cis[240];
404 1.1 ichiro };
405 1.1 ichiro
406 1.1 ichiro /*
407 1.1 ichiro * Communications quality (0xFD43).
408 1.1 ichiro */
409 1.1 ichiro #define WI_RID_COMMQUAL 0xFD43
410 1.1 ichiro struct wi_ltv_commqual {
411 1.1 ichiro u_int16_t wi_len;
412 1.1 ichiro u_int16_t wi_type;
413 1.1 ichiro u_int16_t wi_coms_qual;
414 1.1 ichiro u_int16_t wi_sig_lvl;
415 1.1 ichiro u_int16_t wi_noise_lvl;
416 1.1 ichiro };
417 1.1 ichiro
418 1.1 ichiro /*
419 1.1 ichiro * Actual system scale thresholds (0xFD46).
420 1.1 ichiro */
421 1.1 ichiro #define WI_RID_SYSTEM_SCALE 0xFC06
422 1.1 ichiro #define WI_RID_SCALETHRESH 0xFD46
423 1.1 ichiro struct wi_ltv_scalethresh {
424 1.1 ichiro u_int16_t wi_len;
425 1.1 ichiro u_int16_t wi_type;
426 1.1 ichiro u_int16_t wi_energy_detect;
427 1.1 ichiro u_int16_t wi_carrier_detect;
428 1.1 ichiro u_int16_t wi_defer;
429 1.1 ichiro u_int16_t wi_cell_search;
430 1.1 ichiro u_int16_t wi_out_of_range;
431 1.1 ichiro u_int16_t wi_delta_snr;
432 1.1 ichiro };
433 1.1 ichiro
434 1.1 ichiro /*
435 1.1 ichiro * PCF info struct (0xFD87).
436 1.1 ichiro */
437 1.1 ichiro #define WI_RID_PCF 0xFD87
438 1.1 ichiro struct wi_ltv_pcf {
439 1.1 ichiro u_int16_t wi_len;
440 1.1 ichiro u_int16_t wi_type;
441 1.1 ichiro u_int16_t wi_medium_occupancy_limit;
442 1.1 ichiro u_int16_t wi_cfp_period;
443 1.1 ichiro u_int16_t wi_cfp_max_duration;
444 1.1 ichiro };
445 1.1 ichiro
446 1.1 ichiro /*
447 1.1 ichiro * Connection control characteristics.
448 1.1 ichiro * 1 == Basic Service Set (BSS)
449 1.1 ichiro * 2 == Wireless Distribudion System (WDS)
450 1.1 ichiro * 3 == Pseudo IBSS
451 1.1 ichiro */
452 1.1 ichiro #define WI_RID_PORTTYPE 0xFC00
453 1.1 ichiro #define WI_PORTTYPE_BSS 0x1
454 1.1 ichiro #define WI_PORTTYPE_WDS 0x2
455 1.1 ichiro #define WI_PORTTYPE_ADHOC 0x3
456 1.1 ichiro
457 1.1 ichiro /*
458 1.1 ichiro * Mac addresses.
459 1.1 ichiro */
460 1.1 ichiro #define WI_RID_MAC_NODE 0xFC01
461 1.1 ichiro #define WI_RID_MAC_WDS 0xFC08
462 1.1 ichiro struct wi_ltv_macaddr {
463 1.1 ichiro u_int16_t wi_len;
464 1.1 ichiro u_int16_t wi_type;
465 1.1 ichiro u_int8_t wi_mac_addr[6];
466 1.1 ichiro };
467 1.1 ichiro
468 1.1 ichiro /*
469 1.1 ichiro * Station set identification (SSID).
470 1.1 ichiro */
471 1.1 ichiro #define WI_RID_DESIRED_SSID 0xFC02
472 1.1 ichiro #define WI_RID_OWN_SSID 0xFC04
473 1.1 ichiro struct wi_ltv_ssid {
474 1.1 ichiro u_int16_t wi_len;
475 1.1 ichiro u_int16_t wi_type;
476 1.1 ichiro u_int16_t wi_id[17];
477 1.1 ichiro };
478 1.1 ichiro
479 1.1 ichiro /*
480 1.1 ichiro * Set communications channel (radio frequency).
481 1.1 ichiro */
482 1.1 ichiro #define WI_RID_OWN_CHNL 0xFC03
483 1.1 ichiro
484 1.1 ichiro /*
485 1.1 ichiro * Frame data size.
486 1.1 ichiro */
487 1.1 ichiro #define WI_RID_MAX_DATALEN 0xFC07
488 1.1 ichiro
489 1.1 ichiro /*
490 1.1 ichiro * ESS power management enable
491 1.1 ichiro */
492 1.1 ichiro #define WI_RID_PM_ENABLED 0xFC09
493 1.1 ichiro
494 1.1 ichiro /*
495 1.1 ichiro * ESS max PM sleep internal
496 1.1 ichiro */
497 1.1 ichiro #define WI_RID_MAX_SLEEP 0xFC0C
498 1.1 ichiro
499 1.1 ichiro /*
500 1.1 ichiro * Set our station name.
501 1.1 ichiro */
502 1.1 ichiro #define WI_RID_NODENAME 0xFC0E
503 1.1 ichiro struct wi_ltv_nodename {
504 1.1 ichiro u_int16_t wi_len;
505 1.1 ichiro u_int16_t wi_type;
506 1.1 ichiro u_int16_t wi_nodename[17];
507 1.1 ichiro };
508 1.1 ichiro
509 1.1 ichiro /*
510 1.1 ichiro * Multicast addresses to be put in filter. We're
511 1.1 ichiro * allowed up to 16 addresses in the filter.
512 1.1 ichiro */
513 1.1 ichiro #define WI_RID_MCAST 0xFC80
514 1.1 ichiro struct wi_ltv_mcast {
515 1.1 ichiro u_int16_t wi_len;
516 1.1 ichiro u_int16_t wi_type;
517 1.1 ichiro struct ether_addr wi_mcast[16];
518 1.1 ichiro };
519 1.1 ichiro
520 1.1 ichiro /*
521 1.1 ichiro * Create IBSS.
522 1.1 ichiro */
523 1.1 ichiro #define WI_RID_CREATE_IBSS 0xFC81
524 1.1 ichiro
525 1.1 ichiro #define WI_RID_FRAG_THRESH 0xFC82
526 1.1 ichiro #define WI_RID_RTS_THRESH 0xFC83
527 1.1 ichiro
528 1.1 ichiro /*
529 1.1 ichiro * TX rate control
530 1.1 ichiro * 0 == Fixed 1mbps
531 1.1 ichiro * 1 == Fixed 2mbps
532 1.1 ichiro * 2 == auto fallback
533 1.1 ichiro */
534 1.1 ichiro #define WI_RID_TX_RATE 0xFC84
535 1.1 ichiro
536 1.1 ichiro /*
537 1.1 ichiro * promiscuous mode.
538 1.1 ichiro */
539 1.1 ichiro #define WI_RID_PROMISC 0xFC85
540 1.1 ichiro
541 1.1 ichiro /*
542 1.1 ichiro * Auxiliary Timer tick interval
543 1.1 ichiro */
544 1.1 ichiro #define WI_RID_TICK_TIME 0xFCE0
545 1.1 ichiro
546 1.1 ichiro /*
547 1.1 ichiro * Information frame types.
548 1.1 ichiro */
549 1.1 ichiro #define WI_INFO_NOTIFY 0xF000 /* Handover address */
550 1.1 ichiro #define WI_INFO_COUNTERS 0xF100 /* Statistics counters */
551 1.1 ichiro #define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */
552 1.1 ichiro #define WI_INFO_LINK_STAT 0xF200 /* Link status */
553 1.1 ichiro #define WI_INFO_ASSOC_STAT 0xF201 /* Association status */
554 1.1 ichiro
555 1.1 ichiro /*
556 1.1 ichiro * Hermes transmit/receive frame structure
557 1.1 ichiro */
558 1.1 ichiro struct wi_frame {
559 1.1 ichiro u_int16_t wi_status; /* 0x00 */
560 1.1 ichiro u_int16_t wi_rsvd0; /* 0x02 */
561 1.1 ichiro u_int16_t wi_rsvd1; /* 0x04 */
562 1.1 ichiro u_int16_t wi_q_info; /* 0x06 */
563 1.1 ichiro u_int16_t wi_rsvd2; /* 0x08 */
564 1.1 ichiro u_int16_t wi_rsvd3; /* 0x0A */
565 1.1 ichiro u_int16_t wi_tx_ctl; /* 0x0C */
566 1.10 explorer /* 802.11 */
567 1.1 ichiro u_int16_t wi_frame_ctl; /* 0x0E */
568 1.1 ichiro u_int16_t wi_id; /* 0x10 */
569 1.1 ichiro u_int8_t wi_addr1[6]; /* 0x12 */
570 1.1 ichiro u_int8_t wi_addr2[6]; /* 0x18 */
571 1.1 ichiro u_int8_t wi_addr3[6]; /* 0x1E */
572 1.1 ichiro u_int16_t wi_seq_ctl; /* 0x24 */
573 1.1 ichiro u_int8_t wi_addr4[6]; /* 0x26 */
574 1.1 ichiro u_int16_t wi_dat_len; /* 0x2C */
575 1.10 explorer /* 802.3 */
576 1.1 ichiro u_int8_t wi_dst_addr[6]; /* 0x2E */
577 1.1 ichiro u_int8_t wi_src_addr[6]; /* 0x34 */
578 1.1 ichiro u_int16_t wi_len; /* 0x3A */
579 1.10 explorer /* SNAP header */
580 1.10 explorer u_int16_t wi_dat[3]; /* 0x3C */
581 1.1 ichiro u_int16_t wi_type; /* 0x42 */
582 1.1 ichiro };
583 1.1 ichiro
584 1.1 ichiro #define WI_802_3_OFFSET 0x2E
585 1.1 ichiro #define WI_802_11_OFFSET 0x44
586 1.1 ichiro #define WI_802_11_OFFSET_RAW 0x3C
587 1.1 ichiro
588 1.1 ichiro #define WI_STAT_BADCRC 0x0001
589 1.1 ichiro #define WI_STAT_UNDECRYPTABLE 0x0002
590 1.1 ichiro #define WI_STAT_ERRSTAT 0x0003
591 1.1 ichiro #define WI_STAT_MAC_PORT 0x0700
592 1.1 ichiro #define WI_STAT_1042 0x2000 /* RFC1042 encoded */
593 1.1 ichiro #define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
594 1.1 ichiro #define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
595 1.1 ichiro #define WI_RXSTAT_MSG_TYPE 0xE000
596 1.10 explorer
597 1.10 explorer #define BIT(x) (1 << (x))
598 1.10 explorer
599 1.10 explorer #define WLAN_FC_GET_TYPE(fc) (((fc) & (BIT(3) | BIT(2))) >> 2)
600 1.10 explorer #define WLAN_FC_GET_STYPE(fc) \
601 1.10 explorer (((fc) & (BIT(7) | BIT(6) | BIT(5) | BIT(4))) >> 4)
602 1.10 explorer
603 1.10 explorer #define WLAN_FC_TYPE_MGMT 0
604 1.10 explorer #define WLAN_FC_TYPE_CTRL 1
605 1.10 explorer #define WLAN_FC_TYPE_DATA 2
606 1.1 ichiro
607 1.1 ichiro #define WI_ENC_TX_802_3 0x00
608 1.1 ichiro #define WI_ENC_TX_802_11 0x11
609 1.1 ichiro #define WI_ENC_TX_E_II 0x0E
610 1.1 ichiro
611 1.1 ichiro #define WI_ENC_TX_1042 0x00
612 1.1 ichiro #define WI_ENC_TX_TUNNEL 0xF8
613 1.1 ichiro
614 1.1 ichiro #define WI_TXCNTL_MACPORT 0x00FF
615 1.1 ichiro #define WI_TXCNTL_STRUCTTYPE 0xFF00
616 1.1 ichiro
617 1.1 ichiro /*
618 1.1 ichiro * SNAP (sub-network access protocol) constants for transmission
619 1.1 ichiro * of IP datagrams over IEEE 802 networks, taken from RFC1042.
620 1.1 ichiro * We need these for the LLC/SNAP header fields in the TX/RX frame
621 1.1 ichiro * structure.
622 1.1 ichiro */
623 1.1 ichiro #define WI_SNAP_K1 0xaa /* assigned global SAP for SNAP */
624 1.1 ichiro #define WI_SNAP_K2 0x00
625 1.1 ichiro #define WI_SNAP_CONTROL 0x03 /* unnumbered information format */
626 1.1 ichiro #define WI_SNAP_WORD0 (WI_SNAP_K1 | (WI_SNAP_K1 << 8))
627 1.1 ichiro #define WI_SNAP_WORD1 (WI_SNAP_K2 | (WI_SNAP_CONTROL << 8))
628 1.1 ichiro #define WI_SNAPHDR_LEN 0x6
629