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wireg.h revision 1.14
      1  1.14  explorer /*	$NetBSD: wireg.h,v 1.14 2002/01/05 20:10:53 explorer Exp $	*/
      2   1.1    ichiro 
      3   1.1    ichiro /*
      4   1.1    ichiro  * Copyright (c) 1997, 1998, 1999
      5   1.1    ichiro  *	Bill Paul <wpaul (at) ctr.columbia.edu>.  All rights reserved.
      6   1.1    ichiro  *
      7   1.1    ichiro  * Redistribution and use in source and binary forms, with or without
      8   1.1    ichiro  * modification, are permitted provided that the following conditions
      9   1.1    ichiro  * are met:
     10   1.1    ichiro  * 1. Redistributions of source code must retain the above copyright
     11   1.1    ichiro  *    notice, this list of conditions and the following disclaimer.
     12   1.1    ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1    ichiro  *    notice, this list of conditions and the following disclaimer in the
     14   1.1    ichiro  *    documentation and/or other materials provided with the distribution.
     15   1.1    ichiro  * 3. All advertising materials mentioning features or use of this software
     16   1.1    ichiro  *    must display the following acknowledgement:
     17   1.1    ichiro  *	This product includes software developed by Bill Paul.
     18   1.1    ichiro  * 4. Neither the name of the author nor the names of any co-contributors
     19   1.1    ichiro  *    may be used to endorse or promote products derived from this software
     20   1.1    ichiro  *    without specific prior written permission.
     21   1.1    ichiro  *
     22   1.1    ichiro  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
     23   1.1    ichiro  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24   1.1    ichiro  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25   1.1    ichiro  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
     26   1.1    ichiro  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     27   1.1    ichiro  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     28   1.1    ichiro  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     29   1.1    ichiro  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     30   1.1    ichiro  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     31   1.1    ichiro  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     32   1.1    ichiro  * THE POSSIBILITY OF SUCH DAMAGE.
     33   1.1    ichiro  */
     34   1.1    ichiro 
     35   1.1    ichiro /*
     36   1.1    ichiro  * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the
     37   1.1    ichiro  * Oslo IETF plenary meeting.
     38   1.1    ichiro  */
     39   1.1    ichiro 
     40   1.1    ichiro #define WI_TIMEOUT	65536
     41   1.1    ichiro 
     42   1.1    ichiro #define WI_PORT0	0
     43   1.1    ichiro #define WI_PORT1	1
     44   1.1    ichiro #define WI_PORT2	2
     45   1.1    ichiro #define WI_PORT3	3
     46   1.1    ichiro #define WI_PORT4	4
     47   1.1    ichiro #define WI_PORT5	5
     48   1.1    ichiro 
     49   1.1    ichiro /* Default port: 0 (only 0 exists on stations) */
     50   1.1    ichiro #define WI_DEFAULT_PORT	(WI_PORT0 << 8)
     51   1.1    ichiro 
     52   1.1    ichiro /* Default TX rate: 2Mbps, auto fallback */
     53   1.1    ichiro #define WI_DEFAULT_TX_RATE	3
     54   1.1    ichiro 
     55   1.1    ichiro /* Default network name: ANY */
     56   1.1    ichiro /*
     57   1.1    ichiro  * [sommerfeld 1999/07/15] Changed from "ANY" to ""; according to Bill Fenner,
     58   1.1    ichiro  * ANY is used in MS driver user interfaces, while "" is used over the
     59   1.1    ichiro  * wire..
     60   1.1    ichiro  */
     61   1.1    ichiro #define WI_DEFAULT_NETNAME	""
     62   1.1    ichiro 
     63   1.1    ichiro #define WI_DEFAULT_AP_DENSITY	1
     64   1.1    ichiro 
     65   1.1    ichiro #define WI_DEFAULT_RTS_THRESH	2347
     66   1.5    tsubai 
     67   1.1    ichiro #define WI_DEFAULT_DATALEN	2304
     68   1.1    ichiro 
     69   1.1    ichiro #define WI_DEFAULT_CREATE_IBSS	0
     70   1.1    ichiro 
     71   1.1    ichiro #define WI_DEFAULT_PM_ENABLED	0
     72   1.1    ichiro 
     73   1.1    ichiro #define WI_DEFAULT_MAX_SLEEP	100
     74   1.1    ichiro 
     75   1.2    ichiro #define WI_DEFAULT_ROAMING	1
     76   1.2    ichiro 
     77   1.2    ichiro #define WI_DEFAULT_AUTHTYPE	1
     78   1.2    ichiro 
     79   1.1    ichiro #ifdef __NetBSD__
     80   1.1    ichiro #define OS_STRING_NAME	"NetBSD"
     81   1.1    ichiro #endif
     82   1.1    ichiro #ifdef __FreeBSD__
     83   1.1    ichiro #define OS_STRING_NAME	"FreeBSD"
     84   1.1    ichiro #endif
     85   1.1    ichiro #ifdef __OpenBSD__
     86   1.1    ichiro #define OS_STRING_NAME	"OpenBSD"
     87   1.1    ichiro #endif
     88   1.1    ichiro 
     89   1.1    ichiro #define WI_DEFAULT_NODENAME	OS_STRING_NAME " WaveLAN/IEEE node"
     90   1.1    ichiro 
     91   1.1    ichiro #define WI_DEFAULT_IBSS		OS_STRING_NAME " IBSS"
     92   1.1    ichiro 
     93   1.1    ichiro #define WI_DEFAULT_CHAN		3
     94   1.1    ichiro 
     95   1.1    ichiro /*
     96   1.1    ichiro  * register space access macros
     97   1.1    ichiro  */
     98   1.1    ichiro #define CSR_WRITE_4(sc, reg, val)	\
     99  1.11    ichiro 	bus_space_write_4(sc->sc_iot, sc->sc_ioh,	\
    100  1.11    ichiro 			(sc->sc_pci? reg * 2: reg) , val)
    101   1.1    ichiro #define CSR_WRITE_2(sc, reg, val)	\
    102  1.11    ichiro 	bus_space_write_2(sc->sc_iot, sc->sc_ioh,	\
    103  1.11    ichiro 			(sc->sc_pci? reg * 2: reg), val)
    104   1.1    ichiro #define CSR_WRITE_1(sc, reg, val)	\
    105  1.11    ichiro 	bus_space_write_1(sc->sc_iot, sc->sc_ioh,	\
    106  1.11    ichiro 			(sc->sc_pci? reg * 2: reg), val)
    107   1.1    ichiro 
    108   1.1    ichiro #define CSR_READ_4(sc, reg)		\
    109  1.11    ichiro 	bus_space_read_4(sc->sc_iot, sc->sc_ioh,	\
    110  1.11    ichiro 			(sc->sc_pci? reg * 2: reg))
    111   1.1    ichiro #define CSR_READ_2(sc, reg)		\
    112  1.11    ichiro 	bus_space_read_2(sc->sc_iot, sc->sc_ioh,	\
    113  1.11    ichiro 			(sc->sc_pci? reg * 2: reg))
    114   1.1    ichiro #define CSR_READ_1(sc, reg)		\
    115  1.11    ichiro 	bus_space_read_1(sc->sc_iot, sc->sc_ioh,	\
    116  1.11    ichiro 			(sc->sc_pci? reg * 2: reg))
    117   1.1    ichiro 
    118   1.5    tsubai #ifndef __BUS_SPACE_HAS_STREAM_METHODS
    119   1.5    tsubai #define bus_space_write_stream_2	bus_space_write_2
    120   1.7    toshii #define bus_space_write_multi_stream_2	bus_space_write_multi_2
    121   1.5    tsubai #define bus_space_read_stream_2		bus_space_read_2
    122   1.7    toshii #define bus_space_read_multi_stream_2		bus_space_read_multi_2
    123   1.5    tsubai #endif
    124   1.5    tsubai 
    125   1.5    tsubai #define CSR_WRITE_STREAM_2(sc, reg, val)	\
    126  1.11    ichiro 	bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh,	\
    127  1.11    ichiro 			(sc->sc_pci? reg * 2: reg), val)
    128   1.7    toshii #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count)	\
    129  1.11    ichiro 	bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh,	\
    130  1.11    ichiro 			(sc->sc_pci? reg * 2: reg), val, count)
    131   1.5    tsubai #define CSR_READ_STREAM_2(sc, reg)		\
    132  1.11    ichiro 	bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh,	\
    133  1.11    ichiro 			(sc->sc_pci? reg * 2: reg))
    134   1.7    toshii #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count)		\
    135  1.11    ichiro 	bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh,	\
    136  1.11    ichiro 			(sc->sc_pci? reg * 2: reg), buf, count)
    137   1.5    tsubai 
    138   1.1    ichiro /*
    139   1.1    ichiro  * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
    140   1.1    ichiro  * calls 'Hermes.' In typical fashion, getting documentation about this
    141   1.1    ichiro  * controller is about as easy as squeezing blood from a stone. Here
    142   1.1    ichiro  * is more or less what I know:
    143   1.1    ichiro  *
    144   1.1    ichiro  * - The Hermes controller is firmware driven, and the host interacts
    145   1.1    ichiro  *   with the Hermes via a firmware interface, which can change.
    146   1.1    ichiro  *
    147   1.1    ichiro  * - The Hermes is described in a document called: "Hermes Firmware
    148   1.1    ichiro  *   WaveLAN/IEEE Station Functions," document #010245, which of course
    149   1.1    ichiro  *   Lucent will not release without an NDA.
    150   1.1    ichiro  *
    151   1.1    ichiro  * - Lucent has created a library called HCF (Hardware Control Functions)
    152   1.1    ichiro  *   though which it wants developers to interact with the card. The HCF
    153   1.1    ichiro  *   is needlessly complex, ill conceived and badly documented. Actually,
    154   1.1    ichiro  *   the comments in the HCP code itself aren't bad, but the publically
    155   1.1    ichiro  *   available manual that comes with it is awful, probably due largely to
    156   1.1    ichiro  *   the fact that it has been emasculated in order to hide information
    157   1.1    ichiro  *   that Lucent wants to keep proprietary. The purpose of the HCF seems
    158   1.1    ichiro  *   to be to insulate the driver programmer from the Hermes itself so that
    159   1.1    ichiro  *   Lucent has an excuse not to release programming in for it.
    160   1.1    ichiro  *
    161   1.1    ichiro  * - Lucent only makes available documentation and code for 'HCF Light'
    162   1.1    ichiro  *   which is a stripped down version of HCF with certain features not
    163   1.1    ichiro  *   implemented, most notably support for 802.11 frames.
    164   1.1    ichiro  *
    165   1.1    ichiro  * - The HCF code which I have seen blows goats. Whoever decided to
    166   1.1    ichiro  *   use a 132 column format should be shot.
    167   1.1    ichiro  *
    168   1.1    ichiro  * Rather than actually use the Lucent HCF library, I have stripped all
    169   1.1    ichiro  * the useful information from it and used it to create a driver in the
    170   1.1    ichiro  * usual BSD form. Note: I don't want to hear anybody whining about the
    171   1.1    ichiro  * fact that the Lucent code is GPLed and mine isn't. I did not actually
    172   1.1    ichiro  * put any of Lucent's code in this driver: I only used it as a reference
    173   1.1    ichiro  * to obtain information about the underlying hardware. The Hermes
    174   1.1    ichiro  * programming interface is not GPLed, so bite me.
    175   1.1    ichiro  */
    176   1.1    ichiro 
    177   1.1    ichiro /*
    178  1.11    ichiro  * Size of Hermes & Prism2 I/O space.
    179   1.1    ichiro  */
    180   1.1    ichiro #define WI_IOSIZE		0x40
    181  1.11    ichiro #define WI_PCI_CBMA		0x10	/* Configuration Base Memory Address */
    182   1.1    ichiro 
    183   1.1    ichiro /*
    184  1.11    ichiro  * Hermes & Prism2 register definitions
    185   1.1    ichiro  */
    186   1.1    ichiro 
    187   1.1    ichiro /* Hermes command/status registers. */
    188   1.1    ichiro #define WI_COMMAND		0x00
    189   1.1    ichiro #define WI_PARAM0		0x02
    190   1.1    ichiro #define WI_PARAM1		0x04
    191   1.1    ichiro #define WI_PARAM2		0x06
    192   1.1    ichiro #define WI_STATUS		0x08
    193   1.1    ichiro #define WI_RESP0		0x0A
    194   1.1    ichiro #define WI_RESP1		0x0C
    195   1.1    ichiro #define WI_RESP2		0x0E
    196   1.1    ichiro 
    197   1.1    ichiro /* Command register values. */
    198   1.1    ichiro #define WI_CMD_BUSY		0x8000 /* busy bit */
    199   1.1    ichiro #define WI_CMD_INI		0x0000 /* initialize */
    200   1.1    ichiro #define WI_CMD_ENABLE		0x0001 /* enable */
    201   1.1    ichiro #define WI_CMD_DISABLE		0x0002 /* disable */
    202   1.1    ichiro #define WI_CMD_DIAG		0x0003
    203   1.1    ichiro #define WI_CMD_ALLOC_MEM	0x000A /* allocate NIC memory */
    204   1.1    ichiro #define WI_CMD_TX		0x000B /* transmit */
    205   1.1    ichiro #define WI_CMD_NOTIFY		0x0010
    206   1.1    ichiro #define WI_CMD_INQUIRE		0x0011
    207   1.1    ichiro #define WI_CMD_ACCESS		0x0021
    208   1.1    ichiro #define WI_CMD_PROGRAM		0x0022
    209   1.1    ichiro 
    210   1.1    ichiro #define WI_CMD_CODE_MASK	0x003F
    211   1.1    ichiro 
    212   1.1    ichiro /*
    213   1.1    ichiro  * Reclaim qualifier bit, applicable to the
    214   1.1    ichiro  * TX and INQUIRE commands.
    215   1.1    ichiro  */
    216   1.1    ichiro #define WI_RECLAIM		0x0100 /* reclaim NIC memory */
    217   1.1    ichiro 
    218   1.1    ichiro /*
    219   1.1    ichiro  * ACCESS command qualifier bits.
    220   1.1    ichiro  */
    221   1.1    ichiro #define WI_ACCESS_READ		0x0000
    222   1.1    ichiro #define WI_ACCESS_WRITE		0x0100
    223   1.1    ichiro 
    224   1.1    ichiro /*
    225   1.1    ichiro  * PROGRAM command qualifier bits.
    226   1.1    ichiro  */
    227   1.1    ichiro #define WI_PROGRAM_DISABLE	0x0000
    228   1.1    ichiro #define WI_PROGRAM_ENABLE_RAM	0x0100
    229   1.1    ichiro #define WI_PROGRAM_ENABLE_NVRAM	0x0200
    230   1.1    ichiro #define WI_PROGRAM_NVRAM	0x0300
    231   1.1    ichiro 
    232   1.1    ichiro /* Status register values */
    233   1.1    ichiro #define WI_STAT_CMD_CODE	0x003F
    234   1.1    ichiro #define WI_STAT_DIAG_ERR	0x0100
    235   1.1    ichiro #define WI_STAT_INQ_ERR		0x0500
    236   1.1    ichiro #define WI_STAT_CMD_RESULT	0x7F00
    237   1.1    ichiro 
    238   1.1    ichiro /* memory handle management registers */
    239   1.1    ichiro #define WI_INFO_FID		0x10
    240   1.1    ichiro #define WI_RX_FID		0x20
    241   1.1    ichiro #define WI_ALLOC_FID		0x22
    242   1.1    ichiro #define WI_TX_CMP_FID		0x24
    243   1.1    ichiro 
    244   1.1    ichiro /*
    245   1.1    ichiro  * Buffer Access Path (BAP) registers.
    246   1.1    ichiro  * These are I/O channels. I believe you can use each one for
    247   1.1    ichiro  * any desired purpose independently of the other. In general
    248   1.1    ichiro  * though, we use BAP1 for reading and writing LTV records and
    249   1.1    ichiro  * reading received data frames, and BAP0 for writing transmit
    250   1.1    ichiro  * frames. This is a convention though, not a rule.
    251   1.1    ichiro  */
    252   1.1    ichiro #define WI_SEL0			0x18
    253   1.1    ichiro #define WI_SEL1			0x1A
    254   1.1    ichiro #define WI_OFF0			0x1C
    255   1.1    ichiro #define WI_OFF1			0x1E
    256   1.1    ichiro #define WI_DATA0		0x36
    257   1.1    ichiro #define WI_DATA1		0x38
    258   1.1    ichiro #define WI_BAP0			WI_DATA0
    259   1.1    ichiro #define WI_BAP1			WI_DATA1
    260   1.1    ichiro 
    261   1.1    ichiro #define WI_OFF_BUSY		0x8000
    262   1.1    ichiro #define WI_OFF_ERR		0x4000
    263   1.1    ichiro #define WI_OFF_DATAOFF		0x0FFF
    264   1.1    ichiro 
    265   1.1    ichiro /* Event registers */
    266   1.1    ichiro #define WI_EVENT_STAT		0x30	/* Event status */
    267   1.1    ichiro #define WI_INT_EN		0x32	/* Interrupt enable/disable */
    268   1.1    ichiro #define WI_EVENT_ACK		0x34	/* Ack event */
    269   1.1    ichiro 
    270   1.1    ichiro /* Events */
    271   1.1    ichiro #define WI_EV_TICK		0x8000	/* aux timer tick */
    272   1.1    ichiro #define WI_EV_RES		0x4000	/* controller h/w error (time out) */
    273   1.1    ichiro #define WI_EV_INFO_DROP		0x2000	/* no RAM to build unsolicited frame */
    274   1.1    ichiro #define WI_EV_NO_CARD		0x0800	/* card removed (hunh?) */
    275  1.14  explorer #define WI_EV_DUIF_RX		0x0400	/* wavelan management packet received */
    276   1.1    ichiro #define WI_EV_INFO		0x0080	/* async info frame */
    277   1.1    ichiro #define WI_EV_CMD		0x0010	/* command completed */
    278   1.1    ichiro #define WI_EV_ALLOC		0x0008	/* async alloc/reclaim completed */
    279   1.1    ichiro #define WI_EV_TX_EXC		0x0004	/* async xmit completed with failure */
    280   1.1    ichiro #define WI_EV_TX		0x0002	/* async xmit completed succesfully */
    281   1.1    ichiro #define WI_EV_RX		0x0001	/* async rx completed */
    282   1.1    ichiro 
    283   1.1    ichiro #define WI_INTRS	\
    284   1.1    ichiro 	(WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP)
    285   1.1    ichiro 
    286   1.1    ichiro /* Host software registers */
    287   1.1    ichiro #define WI_SW0			0x28
    288   1.1    ichiro #define WI_SW1			0x2A
    289   1.1    ichiro #define WI_SW2			0x2C
    290  1.11    ichiro #define WI_SW3			0x2E 	/* does not appear in Prism2 */
    291   1.1    ichiro 
    292   1.1    ichiro #define WI_CNTL			0x14
    293   1.1    ichiro 
    294   1.1    ichiro #define WI_CNTL_AUX_ENA		0xC000
    295   1.1    ichiro #define WI_CNTL_AUX_ENA_STAT	0xC000
    296   1.1    ichiro #define WI_CNTL_AUX_DIS_STAT	0x0000
    297   1.1    ichiro #define WI_CNTL_AUX_ENA_CNTL	0x8000
    298   1.1    ichiro #define WI_CNTL_AUX_DIS_CNTL	0x4000
    299   1.1    ichiro 
    300   1.1    ichiro #define WI_AUX_PAGE		0x3A
    301   1.1    ichiro #define WI_AUX_OFFSET		0x3C
    302   1.1    ichiro #define WI_AUX_DATA		0x3E
    303   1.1    ichiro 
    304   1.1    ichiro /*
    305  1.11    ichiro  * PCI Host Interface Registers (HFA3842 Specific)
    306  1.11    ichiro  * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0,
    307  1.11    ichiro  * has doubled.
    308  1.12    ichiro  * About WI_PCI_COR: In this Register, only soft-reset bit implement; Bit(7).
    309  1.11    ichiro  */
    310  1.11    ichiro #define WI_PCI_COR		0x4C
    311  1.11    ichiro #define WI_PCI_HCR		0x5C
    312  1.11    ichiro #define WI_PCI_MASTER0_ADDRH	0x80
    313  1.11    ichiro #define WI_PCI_MASTER0_ADDRL	0x84
    314  1.11    ichiro #define WI_PCI_MASTER0_LEN	0x88
    315  1.11    ichiro #define WI_PCI_MASTER0_CON	0x8C
    316  1.11    ichiro 
    317  1.11    ichiro #define WI_PCI_STATUS		0x98
    318  1.11    ichiro 
    319  1.11    ichiro #define WI_PCI_MASTER1_ADDRH	0xA0
    320  1.11    ichiro #define WI_PCI_MASTER1_ADDRL	0xA4
    321  1.11    ichiro #define WI_PCI_MASTER1_LEN	0xA8
    322  1.12    ichiro #define WI_PCI_MASTER1_CON	0xAC
    323  1.12    ichiro 
    324  1.12    ichiro #define WI_PCI_SOFT_RESET	(1 << 7)
    325  1.11    ichiro 
    326  1.11    ichiro /*
    327   1.1    ichiro  * One form of communication with the Hermes is with what Lucent calls
    328   1.1    ichiro  * LTV records, where LTV stands for Length, Type and Value. The length
    329   1.1    ichiro  * and type are 16 bits and are in native byte order. The value is in
    330   1.1    ichiro  * multiples of 16 bits and is in little endian byte order.
    331   1.1    ichiro  */
    332   1.1    ichiro struct wi_ltv_gen {
    333   1.1    ichiro 	u_int16_t		wi_len;
    334   1.1    ichiro 	u_int16_t		wi_type;
    335   1.1    ichiro 	u_int16_t		wi_val;
    336   1.1    ichiro };
    337   1.1    ichiro 
    338   1.1    ichiro struct wi_ltv_str {
    339   1.1    ichiro 	u_int16_t		wi_len;
    340   1.1    ichiro 	u_int16_t		wi_type;
    341   1.1    ichiro 	u_int16_t		wi_str[17];
    342   1.1    ichiro };
    343   1.1    ichiro 
    344   1.1    ichiro #define WI_SETVAL(recno, val)			\
    345   1.1    ichiro 	do {					\
    346   1.1    ichiro 		struct wi_ltv_gen	g;	\
    347   1.1    ichiro 						\
    348   1.1    ichiro 		g.wi_len = 2;			\
    349   1.1    ichiro 		g.wi_type = recno;		\
    350   1.5    tsubai 		g.wi_val = htole16(val);	\
    351   1.1    ichiro 		wi_write_record(sc, &g);	\
    352   1.1    ichiro 	} while (0)
    353   1.1    ichiro 
    354   1.1    ichiro #define WI_SETSTR(recno, str)					\
    355   1.1    ichiro 	do {							\
    356   1.1    ichiro 		struct wi_ltv_str	s;			\
    357   1.1    ichiro 		int			l;			\
    358   1.1    ichiro 								\
    359   1.1    ichiro 		l = (strlen(str) + 1) & ~0x1;			\
    360   1.9   thorpej 		memset((char *)&s, 0, sizeof(s));		\
    361   1.1    ichiro 		s.wi_len = (l / 2) + 2;				\
    362   1.1    ichiro 		s.wi_type = recno;				\
    363   1.5    tsubai 		s.wi_str[0] = htole16(strlen(str));		\
    364   1.8   thorpej 		memcpy((char *)&s.wi_str[1], str, strlen(str));	\
    365   1.1    ichiro 		wi_write_record(sc, (struct wi_ltv_gen *)&s);	\
    366   1.1    ichiro 	} while (0)
    367   1.1    ichiro 
    368   1.1    ichiro /*
    369   1.1    ichiro  * Download buffer location and length (0xFD01).
    370   1.1    ichiro  */
    371   1.1    ichiro struct wi_ltv_dnld_buf {
    372   1.1    ichiro 	u_int16_t		wi_len;
    373   1.1    ichiro 	u_int16_t		wi_type;
    374   1.1    ichiro 	u_int16_t		wi_buf_pg; /* page addr of intermediate dl buf*/
    375   1.1    ichiro 	u_int16_t		wi_buf_off; /* offset of idb */
    376   1.1    ichiro 	u_int16_t		wi_buf_len; /* len of idb */
    377   1.1    ichiro };
    378   1.1    ichiro 
    379   1.1    ichiro /*
    380   1.1    ichiro  * Mem sizes (0xFD02).
    381   1.1    ichiro  */
    382   1.1    ichiro struct wi_ltv_memsz {
    383   1.1    ichiro 	u_int16_t		wi_len;
    384   1.1    ichiro 	u_int16_t		wi_type;
    385   1.1    ichiro 	u_int16_t		wi_mem_ram;
    386   1.1    ichiro 	u_int16_t		wi_mem_nvram;
    387   1.2    ichiro };
    388   1.2    ichiro 
    389   1.2    ichiro /*
    390  1.13  christos  * NIC Identification (0xFD0B, 0xFD20)
    391   1.2    ichiro  */
    392   1.2    ichiro struct wi_ltv_ver {
    393   1.2    ichiro 	u_int16_t		wi_len;
    394   1.2    ichiro 	u_int16_t		wi_type;
    395   1.2    ichiro 	u_int16_t		wi_ver[4];
    396   1.2    ichiro #define WI_NIC_EVB2	0x8000
    397   1.2    ichiro #define WI_NIC_HWB3763	0x8001
    398   1.2    ichiro #define WI_NIC_HWB3163	0x8002
    399   1.2    ichiro #define WI_NIC_HWB3163B	0x8003
    400   1.2    ichiro #define WI_NIC_EVB3	0x8004
    401   1.2    ichiro #define WI_NIC_HWB1153	0x8007
    402   1.4    ichiro #define WI_NIC_P2_SST	0x8008	/* Prism2 with SST flush */
    403   1.6    ichiro #define WI_NIC_PRISM2_5	0x800C
    404  1.11    ichiro #define WI_NIC_3874A	0x8013	/* Prism2.5 Mini-PCI */
    405   1.1    ichiro };
    406   1.1    ichiro 
    407   1.1    ichiro /*
    408   1.1    ichiro  * List of intended regulatory domains (0xFD11).
    409   1.1    ichiro  */
    410   1.1    ichiro struct wi_ltv_domains {
    411   1.1    ichiro 	u_int16_t		wi_len;
    412   1.1    ichiro 	u_int16_t		wi_type;
    413   1.1    ichiro 	u_int16_t		wi_domains[6];
    414   1.1    ichiro };
    415   1.1    ichiro 
    416   1.1    ichiro /*
    417   1.1    ichiro  * CIS struct (0xFD13).
    418   1.1    ichiro  */
    419   1.1    ichiro struct wi_ltv_cis {
    420   1.1    ichiro 	u_int16_t		wi_len;
    421   1.1    ichiro 	u_int16_t		wi_type;
    422   1.1    ichiro 	u_int16_t		wi_cis[240];
    423   1.1    ichiro };
    424   1.1    ichiro 
    425   1.1    ichiro /*
    426   1.1    ichiro  * Communications quality (0xFD43).
    427   1.1    ichiro  */
    428   1.1    ichiro struct wi_ltv_commqual {
    429   1.1    ichiro 	u_int16_t		wi_len;
    430   1.1    ichiro 	u_int16_t		wi_type;
    431   1.1    ichiro 	u_int16_t		wi_coms_qual;
    432   1.1    ichiro 	u_int16_t		wi_sig_lvl;
    433   1.1    ichiro 	u_int16_t		wi_noise_lvl;
    434   1.1    ichiro };
    435   1.1    ichiro 
    436   1.1    ichiro /*
    437  1.13  christos  * Actual system scale thresholds (0xFC06, 0xFD46).
    438   1.1    ichiro  */
    439   1.1    ichiro struct wi_ltv_scalethresh {
    440   1.1    ichiro 	u_int16_t		wi_len;
    441   1.1    ichiro 	u_int16_t		wi_type;
    442   1.1    ichiro 	u_int16_t		wi_energy_detect;
    443   1.1    ichiro 	u_int16_t		wi_carrier_detect;
    444   1.1    ichiro 	u_int16_t		wi_defer;
    445   1.1    ichiro 	u_int16_t		wi_cell_search;
    446   1.1    ichiro 	u_int16_t		wi_out_of_range;
    447   1.1    ichiro 	u_int16_t		wi_delta_snr;
    448   1.1    ichiro };
    449   1.1    ichiro 
    450   1.1    ichiro /*
    451   1.1    ichiro  * PCF info struct (0xFD87).
    452   1.1    ichiro  */
    453   1.1    ichiro struct wi_ltv_pcf {
    454   1.1    ichiro 	u_int16_t		wi_len;
    455   1.1    ichiro 	u_int16_t		wi_type;
    456   1.1    ichiro 	u_int16_t		wi_medium_occupancy_limit;
    457   1.1    ichiro 	u_int16_t		wi_cfp_period;
    458   1.1    ichiro 	u_int16_t		wi_cfp_max_duration;
    459   1.1    ichiro };
    460   1.1    ichiro 
    461   1.1    ichiro /*
    462  1.13  christos  * Connection control characteristics. (0xFC00)
    463   1.1    ichiro  * 1 == Basic Service Set (BSS)
    464   1.1    ichiro  * 2 == Wireless Distribudion System (WDS)
    465   1.1    ichiro  * 3 == Pseudo IBSS
    466   1.1    ichiro  */
    467   1.1    ichiro #define WI_PORTTYPE_BSS		0x1
    468   1.1    ichiro #define WI_PORTTYPE_WDS		0x2
    469   1.1    ichiro #define WI_PORTTYPE_ADHOC	0x3
    470   1.1    ichiro 
    471   1.1    ichiro /*
    472  1.13  christos  * Mac addresses. (0xFC01, 0xFC08)
    473   1.1    ichiro  */
    474   1.1    ichiro struct wi_ltv_macaddr {
    475   1.1    ichiro 	u_int16_t		wi_len;
    476   1.1    ichiro 	u_int16_t		wi_type;
    477   1.1    ichiro 	u_int8_t		wi_mac_addr[6];
    478   1.1    ichiro };
    479   1.1    ichiro 
    480   1.1    ichiro /*
    481  1.13  christos  * Station set identification (SSID). (0xFC02, 0xFC04)
    482   1.1    ichiro  */
    483   1.1    ichiro struct wi_ltv_ssid {
    484   1.1    ichiro 	u_int16_t		wi_len;
    485   1.1    ichiro 	u_int16_t		wi_type;
    486   1.1    ichiro 	u_int16_t		wi_id[17];
    487   1.1    ichiro };
    488   1.1    ichiro 
    489   1.1    ichiro /*
    490  1.13  christos  * Set our station name. (0xFC0E)
    491   1.1    ichiro  */
    492   1.1    ichiro struct wi_ltv_nodename {
    493   1.1    ichiro 	u_int16_t		wi_len;
    494   1.1    ichiro 	u_int16_t		wi_type;
    495   1.1    ichiro 	u_int16_t		wi_nodename[17];
    496   1.1    ichiro };
    497   1.1    ichiro 
    498   1.1    ichiro /*
    499   1.1    ichiro  * Multicast addresses to be put in filter. We're
    500  1.13  christos  * allowed up to 16 addresses in the filter. (0xFC80)
    501   1.1    ichiro  */
    502   1.1    ichiro struct wi_ltv_mcast {
    503   1.1    ichiro 	u_int16_t		wi_len;
    504   1.1    ichiro 	u_int16_t		wi_type;
    505   1.1    ichiro 	struct ether_addr	wi_mcast[16];
    506   1.1    ichiro };
    507   1.1    ichiro 
    508   1.1    ichiro /*
    509   1.1    ichiro  * Information frame types.
    510   1.1    ichiro  */
    511   1.1    ichiro #define WI_INFO_NOTIFY		0xF000	/* Handover address */
    512   1.1    ichiro #define WI_INFO_COUNTERS	0xF100	/* Statistics counters */
    513   1.1    ichiro #define WI_INFO_SCAN_RESULTS	0xF101	/* Scan results */
    514   1.1    ichiro #define WI_INFO_LINK_STAT	0xF200	/* Link status */
    515   1.1    ichiro #define WI_INFO_ASSOC_STAT	0xF201	/* Association status */
    516   1.1    ichiro 
    517   1.1    ichiro /*
    518   1.1    ichiro  * Hermes transmit/receive frame structure
    519   1.1    ichiro  */
    520   1.1    ichiro struct wi_frame {
    521   1.1    ichiro 	u_int16_t		wi_status;	/* 0x00 */
    522   1.1    ichiro 	u_int16_t		wi_rsvd0;	/* 0x02 */
    523   1.1    ichiro 	u_int16_t		wi_rsvd1;	/* 0x04 */
    524   1.1    ichiro 	u_int16_t		wi_q_info;	/* 0x06 */
    525   1.1    ichiro 	u_int16_t		wi_rsvd2;	/* 0x08 */
    526   1.1    ichiro 	u_int16_t		wi_rsvd3;	/* 0x0A */
    527   1.1    ichiro 	u_int16_t		wi_tx_ctl;	/* 0x0C */
    528   1.1    ichiro 	u_int16_t		wi_frame_ctl;	/* 0x0E */
    529   1.1    ichiro 	u_int16_t		wi_id;		/* 0x10 */
    530   1.1    ichiro 	u_int8_t		wi_addr1[6];	/* 0x12 */
    531   1.1    ichiro 	u_int8_t		wi_addr2[6];	/* 0x18 */
    532   1.1    ichiro 	u_int8_t		wi_addr3[6];	/* 0x1E */
    533   1.1    ichiro 	u_int16_t		wi_seq_ctl;	/* 0x24 */
    534   1.1    ichiro 	u_int8_t		wi_addr4[6];	/* 0x26 */
    535   1.1    ichiro 	u_int16_t		wi_dat_len;	/* 0x2C */
    536   1.1    ichiro 	u_int8_t		wi_dst_addr[6];	/* 0x2E */
    537   1.1    ichiro 	u_int8_t		wi_src_addr[6];	/* 0x34 */
    538   1.1    ichiro 	u_int16_t		wi_len;		/* 0x3A */
    539  1.14  explorer 	u_int16_t		wi_dat[3];	/* 0x3C */ /* SNAP header */
    540   1.1    ichiro 	u_int16_t		wi_type;	/* 0x42 */
    541   1.1    ichiro };
    542   1.1    ichiro 
    543   1.1    ichiro #define WI_802_3_OFFSET		0x2E
    544   1.1    ichiro #define WI_802_11_OFFSET	0x44
    545   1.1    ichiro #define WI_802_11_OFFSET_RAW	0x3C
    546   1.1    ichiro 
    547   1.1    ichiro #define WI_STAT_BADCRC		0x0001
    548   1.1    ichiro #define WI_STAT_UNDECRYPTABLE	0x0002
    549   1.1    ichiro #define WI_STAT_ERRSTAT		0x0003
    550   1.1    ichiro #define WI_STAT_MAC_PORT	0x0700
    551   1.1    ichiro #define WI_STAT_1042		0x2000	/* RFC1042 encoded */
    552   1.1    ichiro #define WI_STAT_TUNNEL		0x4000	/* Bridge-tunnel encoded */
    553   1.1    ichiro #define WI_STAT_WMP_MSG		0x6000	/* WaveLAN-II management protocol */
    554   1.1    ichiro #define WI_RXSTAT_MSG_TYPE	0xE000
    555   1.1    ichiro 
    556   1.1    ichiro #define WI_ENC_TX_802_3		0x00
    557   1.1    ichiro #define WI_ENC_TX_802_11	0x11
    558   1.1    ichiro #define WI_ENC_TX_E_II		0x0E
    559   1.1    ichiro 
    560   1.1    ichiro #define WI_ENC_TX_1042		0x00
    561   1.1    ichiro #define WI_ENC_TX_TUNNEL	0xF8
    562   1.1    ichiro 
    563   1.1    ichiro #define WI_TXCNTL_MACPORT	0x00FF
    564   1.1    ichiro #define WI_TXCNTL_STRUCTTYPE	0xFF00
    565   1.1    ichiro 
    566   1.1    ichiro /*
    567   1.1    ichiro  * SNAP (sub-network access protocol) constants for transmission
    568   1.1    ichiro  * of IP datagrams over IEEE 802 networks, taken from RFC1042.
    569   1.1    ichiro  * We need these for the LLC/SNAP header fields in the TX/RX frame
    570   1.1    ichiro  * structure.
    571   1.1    ichiro  */
    572   1.1    ichiro #define WI_SNAP_K1		0xaa	/* assigned global SAP for SNAP */
    573   1.1    ichiro #define WI_SNAP_K2		0x00
    574   1.1    ichiro #define WI_SNAP_CONTROL		0x03	/* unnumbered information format */
    575   1.1    ichiro #define WI_SNAP_WORD0		(WI_SNAP_K1 | (WI_SNAP_K1 << 8))
    576   1.1    ichiro #define WI_SNAP_WORD1		(WI_SNAP_K2 | (WI_SNAP_CONTROL << 8))
    577   1.1    ichiro #define WI_SNAPHDR_LEN		0x6
    578