wireg.h revision 1.39 1 1.39 thorpej /* $NetBSD: wireg.h,v 1.39 2002/09/23 14:31:28 thorpej Exp $ */
2 1.1 ichiro
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 1997, 1998, 1999
5 1.1 ichiro * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
16 1.1 ichiro * must display the following acknowledgement:
17 1.1 ichiro * This product includes software developed by Bill Paul.
18 1.1 ichiro * 4. Neither the name of the author nor the names of any co-contributors
19 1.1 ichiro * may be used to endorse or promote products derived from this software
20 1.1 ichiro * without specific prior written permission.
21 1.1 ichiro *
22 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 1.1 ichiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 1.1 ichiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 1.1 ichiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 1.1 ichiro * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 1.1 ichiro * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 1.1 ichiro * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 1.1 ichiro * THE POSSIBILITY OF SUCH DAMAGE.
33 1.1 ichiro */
34 1.1 ichiro
35 1.1 ichiro /*
36 1.1 ichiro * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the
37 1.1 ichiro * Oslo IETF plenary meeting.
38 1.1 ichiro */
39 1.1 ichiro
40 1.1 ichiro #define WI_TIMEOUT 65536
41 1.1 ichiro
42 1.1 ichiro #define WI_PORT0 0
43 1.1 ichiro #define WI_PORT1 1
44 1.1 ichiro #define WI_PORT2 2
45 1.1 ichiro #define WI_PORT3 3
46 1.1 ichiro #define WI_PORT4 4
47 1.1 ichiro #define WI_PORT5 5
48 1.1 ichiro
49 1.1 ichiro /* Default port: 0 (only 0 exists on stations) */
50 1.1 ichiro #define WI_DEFAULT_PORT (WI_PORT0 << 8)
51 1.1 ichiro
52 1.1 ichiro /* Default TX rate: 2Mbps, auto fallback */
53 1.1 ichiro #define WI_DEFAULT_TX_RATE 3
54 1.1 ichiro
55 1.1 ichiro /* Default network name: ANY */
56 1.1 ichiro /*
57 1.1 ichiro * [sommerfeld 1999/07/15] Changed from "ANY" to ""; according to Bill Fenner,
58 1.1 ichiro * ANY is used in MS driver user interfaces, while "" is used over the
59 1.1 ichiro * wire..
60 1.1 ichiro */
61 1.1 ichiro #define WI_DEFAULT_NETNAME ""
62 1.1 ichiro
63 1.1 ichiro #define WI_DEFAULT_AP_DENSITY 1
64 1.1 ichiro
65 1.1 ichiro #define WI_DEFAULT_RTS_THRESH 2347
66 1.5 tsubai
67 1.1 ichiro #define WI_DEFAULT_DATALEN 2304
68 1.1 ichiro
69 1.1 ichiro #define WI_DEFAULT_CREATE_IBSS 0
70 1.1 ichiro
71 1.1 ichiro #define WI_DEFAULT_PM_ENABLED 0
72 1.1 ichiro
73 1.1 ichiro #define WI_DEFAULT_MAX_SLEEP 100
74 1.1 ichiro
75 1.2 ichiro #define WI_DEFAULT_ROAMING 1
76 1.2 ichiro
77 1.2 ichiro #define WI_DEFAULT_AUTHTYPE 1
78 1.2 ichiro
79 1.1 ichiro #ifdef __NetBSD__
80 1.1 ichiro #define OS_STRING_NAME "NetBSD"
81 1.1 ichiro #endif
82 1.1 ichiro #ifdef __FreeBSD__
83 1.1 ichiro #define OS_STRING_NAME "FreeBSD"
84 1.1 ichiro #endif
85 1.1 ichiro #ifdef __OpenBSD__
86 1.1 ichiro #define OS_STRING_NAME "OpenBSD"
87 1.1 ichiro #endif
88 1.1 ichiro
89 1.1 ichiro #define WI_DEFAULT_NODENAME OS_STRING_NAME " WaveLAN/IEEE node"
90 1.1 ichiro
91 1.1 ichiro #define WI_DEFAULT_IBSS OS_STRING_NAME " IBSS"
92 1.1 ichiro
93 1.1 ichiro #define WI_DEFAULT_CHAN 3
94 1.1 ichiro
95 1.1 ichiro /*
96 1.1 ichiro * register space access macros
97 1.1 ichiro */
98 1.20 martin #ifdef WI_AT_BIGENDIAN_BUS_HACK
99 1.20 martin /*
100 1.20 martin * XXX - ugly hack for sparc bus_space_* macro deficiencies:
101 1.20 martin * assume the bus we are accessing is big endian.
102 1.20 martin */
103 1.20 martin
104 1.20 martin #define CSR_WRITE_4(sc, reg, val) \
105 1.20 martin bus_space_write_4(sc->sc_iot, sc->sc_ioh, \
106 1.20 martin (sc->sc_pci? reg * 2: reg) , htole32(val))
107 1.20 martin #define CSR_WRITE_2(sc, reg, val) \
108 1.20 martin bus_space_write_2(sc->sc_iot, sc->sc_ioh, \
109 1.20 martin (sc->sc_pci? reg * 2: reg), htole16(val))
110 1.20 martin #define CSR_WRITE_1(sc, reg, val) \
111 1.20 martin bus_space_write_1(sc->sc_iot, sc->sc_ioh, \
112 1.20 martin (sc->sc_pci? reg * 2: reg), val)
113 1.20 martin
114 1.20 martin #define CSR_READ_4(sc, reg) \
115 1.20 martin le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \
116 1.20 martin (sc->sc_pci? reg * 2: reg)))
117 1.20 martin #define CSR_READ_2(sc, reg) \
118 1.20 martin le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \
119 1.20 martin (sc->sc_pci? reg * 2: reg)))
120 1.20 martin #define CSR_READ_1(sc, reg) \
121 1.20 martin bus_space_read_1(sc->sc_iot, sc->sc_ioh, \
122 1.20 martin (sc->sc_pci? reg * 2: reg))
123 1.20 martin
124 1.20 martin #else
125 1.20 martin
126 1.1 ichiro #define CSR_WRITE_4(sc, reg, val) \
127 1.11 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, \
128 1.11 ichiro (sc->sc_pci? reg * 2: reg) , val)
129 1.1 ichiro #define CSR_WRITE_2(sc, reg, val) \
130 1.11 ichiro bus_space_write_2(sc->sc_iot, sc->sc_ioh, \
131 1.11 ichiro (sc->sc_pci? reg * 2: reg), val)
132 1.1 ichiro #define CSR_WRITE_1(sc, reg, val) \
133 1.11 ichiro bus_space_write_1(sc->sc_iot, sc->sc_ioh, \
134 1.11 ichiro (sc->sc_pci? reg * 2: reg), val)
135 1.1 ichiro
136 1.1 ichiro #define CSR_READ_4(sc, reg) \
137 1.11 ichiro bus_space_read_4(sc->sc_iot, sc->sc_ioh, \
138 1.11 ichiro (sc->sc_pci? reg * 2: reg))
139 1.1 ichiro #define CSR_READ_2(sc, reg) \
140 1.11 ichiro bus_space_read_2(sc->sc_iot, sc->sc_ioh, \
141 1.11 ichiro (sc->sc_pci? reg * 2: reg))
142 1.1 ichiro #define CSR_READ_1(sc, reg) \
143 1.11 ichiro bus_space_read_1(sc->sc_iot, sc->sc_ioh, \
144 1.11 ichiro (sc->sc_pci? reg * 2: reg))
145 1.20 martin #endif
146 1.1 ichiro
147 1.5 tsubai #ifndef __BUS_SPACE_HAS_STREAM_METHODS
148 1.5 tsubai #define bus_space_write_stream_2 bus_space_write_2
149 1.7 toshii #define bus_space_write_multi_stream_2 bus_space_write_multi_2
150 1.5 tsubai #define bus_space_read_stream_2 bus_space_read_2
151 1.7 toshii #define bus_space_read_multi_stream_2 bus_space_read_multi_2
152 1.5 tsubai #endif
153 1.5 tsubai
154 1.5 tsubai #define CSR_WRITE_STREAM_2(sc, reg, val) \
155 1.11 ichiro bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \
156 1.11 ichiro (sc->sc_pci? reg * 2: reg), val)
157 1.7 toshii #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
158 1.11 ichiro bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \
159 1.11 ichiro (sc->sc_pci? reg * 2: reg), val, count)
160 1.5 tsubai #define CSR_READ_STREAM_2(sc, reg) \
161 1.11 ichiro bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \
162 1.11 ichiro (sc->sc_pci? reg * 2: reg))
163 1.7 toshii #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \
164 1.11 ichiro bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \
165 1.11 ichiro (sc->sc_pci? reg * 2: reg), buf, count)
166 1.5 tsubai
167 1.1 ichiro /*
168 1.1 ichiro * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
169 1.1 ichiro * calls 'Hermes.' In typical fashion, getting documentation about this
170 1.1 ichiro * controller is about as easy as squeezing blood from a stone. Here
171 1.1 ichiro * is more or less what I know:
172 1.1 ichiro *
173 1.1 ichiro * - The Hermes controller is firmware driven, and the host interacts
174 1.1 ichiro * with the Hermes via a firmware interface, which can change.
175 1.1 ichiro *
176 1.1 ichiro * - The Hermes is described in a document called: "Hermes Firmware
177 1.1 ichiro * WaveLAN/IEEE Station Functions," document #010245, which of course
178 1.1 ichiro * Lucent will not release without an NDA.
179 1.1 ichiro *
180 1.1 ichiro * - Lucent has created a library called HCF (Hardware Control Functions)
181 1.1 ichiro * though which it wants developers to interact with the card. The HCF
182 1.1 ichiro * is needlessly complex, ill conceived and badly documented. Actually,
183 1.1 ichiro * the comments in the HCP code itself aren't bad, but the publically
184 1.1 ichiro * available manual that comes with it is awful, probably due largely to
185 1.1 ichiro * the fact that it has been emasculated in order to hide information
186 1.1 ichiro * that Lucent wants to keep proprietary. The purpose of the HCF seems
187 1.1 ichiro * to be to insulate the driver programmer from the Hermes itself so that
188 1.1 ichiro * Lucent has an excuse not to release programming in for it.
189 1.1 ichiro *
190 1.1 ichiro * - Lucent only makes available documentation and code for 'HCF Light'
191 1.1 ichiro * which is a stripped down version of HCF with certain features not
192 1.1 ichiro * implemented, most notably support for 802.11 frames.
193 1.1 ichiro *
194 1.1 ichiro * - The HCF code which I have seen blows goats. Whoever decided to
195 1.1 ichiro * use a 132 column format should be shot.
196 1.1 ichiro *
197 1.1 ichiro * Rather than actually use the Lucent HCF library, I have stripped all
198 1.1 ichiro * the useful information from it and used it to create a driver in the
199 1.1 ichiro * usual BSD form. Note: I don't want to hear anybody whining about the
200 1.1 ichiro * fact that the Lucent code is GPLed and mine isn't. I did not actually
201 1.1 ichiro * put any of Lucent's code in this driver: I only used it as a reference
202 1.1 ichiro * to obtain information about the underlying hardware. The Hermes
203 1.1 ichiro * programming interface is not GPLed, so bite me.
204 1.1 ichiro */
205 1.1 ichiro
206 1.1 ichiro /*
207 1.11 ichiro * Size of Hermes & Prism2 I/O space.
208 1.1 ichiro */
209 1.1 ichiro #define WI_IOSIZE 0x40
210 1.11 ichiro #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */
211 1.1 ichiro
212 1.39 thorpej #define WI_PCI_COR_OFFSET 0x4C
213 1.39 thorpej
214 1.1 ichiro /*
215 1.11 ichiro * Hermes & Prism2 register definitions
216 1.1 ichiro */
217 1.1 ichiro
218 1.1 ichiro /* Hermes command/status registers. */
219 1.1 ichiro #define WI_COMMAND 0x00
220 1.1 ichiro #define WI_PARAM0 0x02
221 1.1 ichiro #define WI_PARAM1 0x04
222 1.1 ichiro #define WI_PARAM2 0x06
223 1.1 ichiro #define WI_STATUS 0x08
224 1.1 ichiro #define WI_RESP0 0x0A
225 1.1 ichiro #define WI_RESP1 0x0C
226 1.1 ichiro #define WI_RESP2 0x0E
227 1.1 ichiro
228 1.1 ichiro /* Command register values. */
229 1.1 ichiro #define WI_CMD_BUSY 0x8000 /* busy bit */
230 1.1 ichiro #define WI_CMD_INI 0x0000 /* initialize */
231 1.1 ichiro #define WI_CMD_ENABLE 0x0001 /* enable */
232 1.1 ichiro #define WI_CMD_DISABLE 0x0002 /* disable */
233 1.1 ichiro #define WI_CMD_DIAG 0x0003
234 1.1 ichiro #define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
235 1.1 ichiro #define WI_CMD_TX 0x000B /* transmit */
236 1.1 ichiro #define WI_CMD_NOTIFY 0x0010
237 1.1 ichiro #define WI_CMD_INQUIRE 0x0011
238 1.1 ichiro #define WI_CMD_ACCESS 0x0021
239 1.1 ichiro #define WI_CMD_PROGRAM 0x0022
240 1.32 onoe #define WI_CMD_READEE 0x0030
241 1.1 ichiro
242 1.1 ichiro #define WI_CMD_CODE_MASK 0x003F
243 1.1 ichiro
244 1.1 ichiro /*
245 1.1 ichiro * Reclaim qualifier bit, applicable to the
246 1.1 ichiro * TX and INQUIRE commands.
247 1.1 ichiro */
248 1.1 ichiro #define WI_RECLAIM 0x0100 /* reclaim NIC memory */
249 1.1 ichiro
250 1.1 ichiro /*
251 1.1 ichiro * ACCESS command qualifier bits.
252 1.1 ichiro */
253 1.1 ichiro #define WI_ACCESS_READ 0x0000
254 1.1 ichiro #define WI_ACCESS_WRITE 0x0100
255 1.1 ichiro
256 1.1 ichiro /*
257 1.1 ichiro * PROGRAM command qualifier bits.
258 1.1 ichiro */
259 1.1 ichiro #define WI_PROGRAM_DISABLE 0x0000
260 1.1 ichiro #define WI_PROGRAM_ENABLE_RAM 0x0100
261 1.1 ichiro #define WI_PROGRAM_ENABLE_NVRAM 0x0200
262 1.1 ichiro #define WI_PROGRAM_NVRAM 0x0300
263 1.1 ichiro
264 1.1 ichiro /* Status register values */
265 1.1 ichiro #define WI_STAT_CMD_CODE 0x003F
266 1.1 ichiro #define WI_STAT_DIAG_ERR 0x0100
267 1.1 ichiro #define WI_STAT_INQ_ERR 0x0500
268 1.1 ichiro #define WI_STAT_CMD_RESULT 0x7F00
269 1.1 ichiro
270 1.1 ichiro /* memory handle management registers */
271 1.1 ichiro #define WI_INFO_FID 0x10
272 1.1 ichiro #define WI_RX_FID 0x20
273 1.1 ichiro #define WI_ALLOC_FID 0x22
274 1.1 ichiro #define WI_TX_CMP_FID 0x24
275 1.1 ichiro
276 1.1 ichiro /*
277 1.1 ichiro * Buffer Access Path (BAP) registers.
278 1.1 ichiro * These are I/O channels. I believe you can use each one for
279 1.1 ichiro * any desired purpose independently of the other. In general
280 1.1 ichiro * though, we use BAP1 for reading and writing LTV records and
281 1.1 ichiro * reading received data frames, and BAP0 for writing transmit
282 1.1 ichiro * frames. This is a convention though, not a rule.
283 1.1 ichiro */
284 1.1 ichiro #define WI_SEL0 0x18
285 1.1 ichiro #define WI_SEL1 0x1A
286 1.1 ichiro #define WI_OFF0 0x1C
287 1.1 ichiro #define WI_OFF1 0x1E
288 1.1 ichiro #define WI_DATA0 0x36
289 1.1 ichiro #define WI_DATA1 0x38
290 1.1 ichiro #define WI_BAP0 WI_DATA0
291 1.1 ichiro #define WI_BAP1 WI_DATA1
292 1.1 ichiro
293 1.1 ichiro #define WI_OFF_BUSY 0x8000
294 1.1 ichiro #define WI_OFF_ERR 0x4000
295 1.1 ichiro #define WI_OFF_DATAOFF 0x0FFF
296 1.1 ichiro
297 1.1 ichiro /* Event registers */
298 1.1 ichiro #define WI_EVENT_STAT 0x30 /* Event status */
299 1.1 ichiro #define WI_INT_EN 0x32 /* Interrupt enable/disable */
300 1.1 ichiro #define WI_EVENT_ACK 0x34 /* Ack event */
301 1.1 ichiro
302 1.1 ichiro /* Events */
303 1.1 ichiro #define WI_EV_TICK 0x8000 /* aux timer tick */
304 1.1 ichiro #define WI_EV_RES 0x4000 /* controller h/w error (time out) */
305 1.1 ichiro #define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */
306 1.1 ichiro #define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */
307 1.14 explorer #define WI_EV_DUIF_RX 0x0400 /* wavelan management packet received */
308 1.1 ichiro #define WI_EV_INFO 0x0080 /* async info frame */
309 1.1 ichiro #define WI_EV_CMD 0x0010 /* command completed */
310 1.1 ichiro #define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
311 1.1 ichiro #define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */
312 1.1 ichiro #define WI_EV_TX 0x0002 /* async xmit completed succesfully */
313 1.1 ichiro #define WI_EV_RX 0x0001 /* async rx completed */
314 1.1 ichiro
315 1.1 ichiro #define WI_INTRS \
316 1.1 ichiro (WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP)
317 1.1 ichiro
318 1.1 ichiro /* Host software registers */
319 1.1 ichiro #define WI_SW0 0x28
320 1.1 ichiro #define WI_SW1 0x2A
321 1.1 ichiro #define WI_SW2 0x2C
322 1.11 ichiro #define WI_SW3 0x2E /* does not appear in Prism2 */
323 1.1 ichiro
324 1.1 ichiro #define WI_CNTL 0x14
325 1.1 ichiro
326 1.1 ichiro #define WI_CNTL_AUX_ENA 0xC000
327 1.1 ichiro #define WI_CNTL_AUX_ENA_STAT 0xC000
328 1.1 ichiro #define WI_CNTL_AUX_DIS_STAT 0x0000
329 1.1 ichiro #define WI_CNTL_AUX_ENA_CNTL 0x8000
330 1.1 ichiro #define WI_CNTL_AUX_DIS_CNTL 0x4000
331 1.1 ichiro
332 1.1 ichiro #define WI_AUX_PAGE 0x3A
333 1.1 ichiro #define WI_AUX_OFFSET 0x3C
334 1.1 ichiro #define WI_AUX_DATA 0x3E
335 1.32 onoe
336 1.32 onoe #define WI_AUX_PGSZ 128
337 1.32 onoe #define WI_AUX_KEY0 0xfe01
338 1.32 onoe #define WI_AUX_KEY1 0xdc23
339 1.32 onoe #define WI_AUX_KEY2 0xba45
340 1.32 onoe
341 1.32 onoe #define WI_COR 0x40 /* only for Symbol */
342 1.32 onoe #define WI_COR_RESET 0x0080
343 1.32 onoe #define WI_COR_IOMODE 0x0041
344 1.32 onoe
345 1.32 onoe #define WI_HCR 0x42 /* only for Symbol */
346 1.32 onoe #define WI_HCR_4WIRE 0x0010
347 1.32 onoe #define WI_HCR_RUN 0x0007
348 1.32 onoe #define WI_HCR_HOLD 0x000f
349 1.32 onoe #define WI_HCR_EEHOLD 0x00ce
350 1.1 ichiro
351 1.1 ichiro /*
352 1.11 ichiro * PCI Host Interface Registers (HFA3842 Specific)
353 1.11 ichiro * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0,
354 1.11 ichiro * has doubled.
355 1.12 ichiro * About WI_PCI_COR: In this Register, only soft-reset bit implement; Bit(7).
356 1.11 ichiro */
357 1.11 ichiro #define WI_PCI_COR 0x4C
358 1.11 ichiro #define WI_PCI_HCR 0x5C
359 1.11 ichiro #define WI_PCI_MASTER0_ADDRH 0x80
360 1.11 ichiro #define WI_PCI_MASTER0_ADDRL 0x84
361 1.11 ichiro #define WI_PCI_MASTER0_LEN 0x88
362 1.11 ichiro #define WI_PCI_MASTER0_CON 0x8C
363 1.11 ichiro
364 1.39 thorpej #define WI_COR_SOFT_RESET (1 << 7)
365 1.39 thorpej #define WI_COR_CLEAR 0x00
366 1.39 thorpej
367 1.11 ichiro #define WI_PCI_STATUS 0x98
368 1.11 ichiro
369 1.11 ichiro #define WI_PCI_MASTER1_ADDRH 0xA0
370 1.11 ichiro #define WI_PCI_MASTER1_ADDRL 0xA4
371 1.11 ichiro #define WI_PCI_MASTER1_LEN 0xA8
372 1.12 ichiro #define WI_PCI_MASTER1_CON 0xAC
373 1.12 ichiro
374 1.12 ichiro #define WI_PCI_SOFT_RESET (1 << 7)
375 1.11 ichiro
376 1.11 ichiro /*
377 1.1 ichiro * One form of communication with the Hermes is with what Lucent calls
378 1.1 ichiro * LTV records, where LTV stands for Length, Type and Value. The length
379 1.1 ichiro * and type are 16 bits and are in native byte order. The value is in
380 1.1 ichiro * multiples of 16 bits and is in little endian byte order.
381 1.1 ichiro */
382 1.1 ichiro struct wi_ltv_gen {
383 1.1 ichiro u_int16_t wi_len;
384 1.1 ichiro u_int16_t wi_type;
385 1.1 ichiro u_int16_t wi_val;
386 1.1 ichiro };
387 1.1 ichiro
388 1.1 ichiro struct wi_ltv_str {
389 1.1 ichiro u_int16_t wi_len;
390 1.1 ichiro u_int16_t wi_type;
391 1.1 ichiro u_int16_t wi_str[17];
392 1.1 ichiro };
393 1.1 ichiro
394 1.1 ichiro #define WI_SETVAL(recno, val) \
395 1.1 ichiro do { \
396 1.1 ichiro struct wi_ltv_gen g; \
397 1.1 ichiro \
398 1.1 ichiro g.wi_len = 2; \
399 1.1 ichiro g.wi_type = recno; \
400 1.5 tsubai g.wi_val = htole16(val); \
401 1.1 ichiro wi_write_record(sc, &g); \
402 1.1 ichiro } while (0)
403 1.1 ichiro
404 1.1 ichiro #define WI_SETSTR(recno, str) \
405 1.1 ichiro do { \
406 1.1 ichiro struct wi_ltv_str s; \
407 1.1 ichiro int l; \
408 1.1 ichiro \
409 1.1 ichiro l = (strlen(str) + 1) & ~0x1; \
410 1.9 thorpej memset((char *)&s, 0, sizeof(s)); \
411 1.1 ichiro s.wi_len = (l / 2) + 2; \
412 1.1 ichiro s.wi_type = recno; \
413 1.5 tsubai s.wi_str[0] = htole16(strlen(str)); \
414 1.8 thorpej memcpy((char *)&s.wi_str[1], str, strlen(str)); \
415 1.1 ichiro wi_write_record(sc, (struct wi_ltv_gen *)&s); \
416 1.1 ichiro } while (0)
417 1.1 ichiro
418 1.1 ichiro /*
419 1.1 ichiro * Download buffer location and length (0xFD01).
420 1.1 ichiro */
421 1.1 ichiro struct wi_ltv_dnld_buf {
422 1.1 ichiro u_int16_t wi_len;
423 1.1 ichiro u_int16_t wi_type;
424 1.1 ichiro u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/
425 1.1 ichiro u_int16_t wi_buf_off; /* offset of idb */
426 1.1 ichiro u_int16_t wi_buf_len; /* len of idb */
427 1.1 ichiro };
428 1.1 ichiro
429 1.1 ichiro /*
430 1.1 ichiro * Mem sizes (0xFD02).
431 1.1 ichiro */
432 1.1 ichiro struct wi_ltv_memsz {
433 1.1 ichiro u_int16_t wi_len;
434 1.1 ichiro u_int16_t wi_type;
435 1.1 ichiro u_int16_t wi_mem_ram;
436 1.1 ichiro u_int16_t wi_mem_nvram;
437 1.2 ichiro };
438 1.2 ichiro
439 1.2 ichiro /*
440 1.13 christos * NIC Identification (0xFD0B, 0xFD20)
441 1.2 ichiro */
442 1.2 ichiro struct wi_ltv_ver {
443 1.2 ichiro u_int16_t wi_len;
444 1.2 ichiro u_int16_t wi_type;
445 1.2 ichiro u_int16_t wi_ver[4];
446 1.1 ichiro };
447 1.28 ichiro
448 1.28 ichiro /* define card ident */
449 1.30 ichiro /* Lucent */
450 1.30 ichiro #define WI_NIC_LUCENT_ID 0x0001
451 1.29 ichiro #define WI_NIC_LUCENT_STR "Lucent Technologies, WaveLAN/IEEE"
452 1.28 ichiro
453 1.30 ichiro #define WI_NIC_SONY_ID 0x0002
454 1.30 ichiro #define WI_NIC_SONY_STR "Sony WaveLAN/IEEE"
455 1.30 ichiro
456 1.30 ichiro #define WI_NIC_LUCENT_EMB_ID 0x0005
457 1.30 ichiro #define WI_NIC_LUCENT_EMB_STR "Lucent Embedded WaveLAN/IEEE"
458 1.30 ichiro
459 1.30 ichiro /* Intersil */
460 1.29 ichiro #define WI_NIC_EVB2_ID 0x8000
461 1.29 ichiro #define WI_NIC_EVB2_STR "RF:PRISM2 MAC:HFA3841"
462 1.28 ichiro
463 1.29 ichiro #define WI_NIC_HWB3763_ID 0x8001
464 1.29 ichiro #define WI_NIC_HWB3763_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3763 rev.B"
465 1.28 ichiro
466 1.29 ichiro #define WI_NIC_HWB3163_ID 0x8002
467 1.29 ichiro #define WI_NIC_HWB3163_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.A"
468 1.28 ichiro
469 1.29 ichiro #define WI_NIC_HWB3163B_ID 0x8003
470 1.29 ichiro #define WI_NIC_HWB3163B_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.B"
471 1.28 ichiro
472 1.29 ichiro #define WI_NIC_EVB3_ID 0x8004
473 1.29 ichiro #define WI_NIC_EVB3_STR "RF:PRISM2 MAC:HFA3842 CARD:HFA3842 EVAL"
474 1.28 ichiro
475 1.29 ichiro #define WI_NIC_HWB1153_ID 0x8007
476 1.29 ichiro #define WI_NIC_HWB1153_STR "RF:PRISM1 MAC:HFA3841 CARD:HWB1153"
477 1.28 ichiro
478 1.29 ichiro #define WI_NIC_P2_SST_ID 0x8008 /* Prism2 with SST flush */
479 1.29 ichiro #define WI_NIC_P2_SST_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash"
480 1.28 ichiro
481 1.28 ichiro #define WI_NIC_EVB2_SST_ID 0x8009
482 1.28 ichiro #define WI_NIC_EVB2_SST_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash"
483 1.28 ichiro
484 1.31 ichiro #define WI_NIC_3842_EVA_ID 0x800A /* Prism2 3842 Evaluation Board */
485 1.28 ichiro #define WI_NIC_3842_EVA_STR "RF:PRISM2 MAC:HFA3842 CARD:HFA3842 EVAL"
486 1.28 ichiro
487 1.28 ichiro #define WI_NIC_3842_PCMCIA_AMD_ID 0x800B /* Prism2.5 PCMCIA */
488 1.28 ichiro #define WI_NIC_3842_PCMCIA_SST_ID 0x800C
489 1.28 ichiro #define WI_NIC_3842_PCMCIA_ATM_ID 0x800D
490 1.31 ichiro #define WI_NIC_3842_PCMCIA_STR "RF:PRISM2.5 MAC:ISL3873B(PCMCIA)"
491 1.28 ichiro
492 1.28 ichiro #define WI_NIC_3842_MINI_AMD_ID 0x8012 /* Prism2.5 Mini-PCI */
493 1.28 ichiro #define WI_NIC_3842_MINI_SST_ID 0x8013
494 1.28 ichiro #define WI_NIC_3842_MINI_ATM_ID 0x8014
495 1.28 ichiro #define WI_NIC_3842_MINI_STR "RF:PRISM2.5 MAC:ISL3874A(Mini-PCI)"
496 1.28 ichiro
497 1.28 ichiro #define WI_NIC_3842_PCI_AMD_ID 0x8016 /* Prism2.5 PCI-bridge */
498 1.28 ichiro #define WI_NIC_3842_PCI_SST_ID 0x8017
499 1.28 ichiro #define WI_NIC_3842_PCI_ATM_ID 0x8018
500 1.28 ichiro #define WI_NIC_3842_PCI_STR "RF:PRISM2.5 MAC:ISL3874A(PCI-bridge)"
501 1.28 ichiro
502 1.28 ichiro #define WI_NIC_P3_PCMCIA_AMD_ID 0x801A /* Prism3 PCMCIA */
503 1.28 ichiro #define WI_NIC_P3_PCMCIA_SST_ID 0x801B
504 1.31 ichiro #define WI_NIC_P3_PCMCIA_STR "RF:PRISM3 MAC:ISL3871(PCMCIA)"
505 1.28 ichiro
506 1.28 ichiro #define WI_NIC_P3_MINI_AMD_ID 0x8021 /* Prism3 Mini-PCI */
507 1.28 ichiro #define WI_NIC_P3_MINI_SST_ID 0x8022
508 1.31 ichiro #define WI_NIC_P3_MINI_STR "RF:PRISM3 MAC:ISL3871(Mini-PCI)"
509 1.1 ichiro
510 1.1 ichiro /*
511 1.1 ichiro * List of intended regulatory domains (0xFD11).
512 1.1 ichiro */
513 1.1 ichiro struct wi_ltv_domains {
514 1.1 ichiro u_int16_t wi_len;
515 1.1 ichiro u_int16_t wi_type;
516 1.1 ichiro u_int16_t wi_domains[6];
517 1.1 ichiro };
518 1.1 ichiro
519 1.1 ichiro /*
520 1.1 ichiro * CIS struct (0xFD13).
521 1.1 ichiro */
522 1.1 ichiro struct wi_ltv_cis {
523 1.1 ichiro u_int16_t wi_len;
524 1.1 ichiro u_int16_t wi_type;
525 1.1 ichiro u_int16_t wi_cis[240];
526 1.1 ichiro };
527 1.1 ichiro
528 1.1 ichiro /*
529 1.1 ichiro * Communications quality (0xFD43).
530 1.1 ichiro */
531 1.1 ichiro struct wi_ltv_commqual {
532 1.1 ichiro u_int16_t wi_len;
533 1.1 ichiro u_int16_t wi_type;
534 1.1 ichiro u_int16_t wi_coms_qual;
535 1.1 ichiro u_int16_t wi_sig_lvl;
536 1.1 ichiro u_int16_t wi_noise_lvl;
537 1.1 ichiro };
538 1.1 ichiro
539 1.1 ichiro /*
540 1.13 christos * Actual system scale thresholds (0xFC06, 0xFD46).
541 1.1 ichiro */
542 1.1 ichiro struct wi_ltv_scalethresh {
543 1.1 ichiro u_int16_t wi_len;
544 1.1 ichiro u_int16_t wi_type;
545 1.1 ichiro u_int16_t wi_energy_detect;
546 1.1 ichiro u_int16_t wi_carrier_detect;
547 1.1 ichiro u_int16_t wi_defer;
548 1.1 ichiro u_int16_t wi_cell_search;
549 1.1 ichiro u_int16_t wi_out_of_range;
550 1.1 ichiro u_int16_t wi_delta_snr;
551 1.1 ichiro };
552 1.1 ichiro
553 1.1 ichiro /*
554 1.1 ichiro * PCF info struct (0xFD87).
555 1.1 ichiro */
556 1.1 ichiro struct wi_ltv_pcf {
557 1.1 ichiro u_int16_t wi_len;
558 1.1 ichiro u_int16_t wi_type;
559 1.1 ichiro u_int16_t wi_medium_occupancy_limit;
560 1.1 ichiro u_int16_t wi_cfp_period;
561 1.1 ichiro u_int16_t wi_cfp_max_duration;
562 1.1 ichiro };
563 1.1 ichiro
564 1.15 ichiro /*
565 1.13 christos * Connection control characteristics. (0xFC00)
566 1.25 ichiro * 0 == IBSS (802.11 compliant mode) (Only PRISM2)
567 1.1 ichiro * 1 == Basic Service Set (BSS)
568 1.1 ichiro * 2 == Wireless Distribudion System (WDS)
569 1.25 ichiro * 3 == Pseudo IBSS
570 1.25 ichiro * (Only PRISM2; not 802.11 compliant mode, testing use only)
571 1.25 ichiro * 6 == HOST AP (Only PRISM2)
572 1.1 ichiro */
573 1.35 thorpej #define WI_PORTTYPE_IBSS 0x0
574 1.1 ichiro #define WI_PORTTYPE_BSS 0x1
575 1.1 ichiro #define WI_PORTTYPE_WDS 0x2
576 1.1 ichiro #define WI_PORTTYPE_ADHOC 0x3
577 1.35 thorpej #define WI_PORTTYPE_HOSTAP 0x6
578 1.1 ichiro
579 1.1 ichiro /*
580 1.13 christos * Mac addresses. (0xFC01, 0xFC08)
581 1.1 ichiro */
582 1.1 ichiro struct wi_ltv_macaddr {
583 1.1 ichiro u_int16_t wi_len;
584 1.1 ichiro u_int16_t wi_type;
585 1.1 ichiro u_int8_t wi_mac_addr[6];
586 1.1 ichiro };
587 1.1 ichiro
588 1.1 ichiro /*
589 1.13 christos * Station set identification (SSID). (0xFC02, 0xFC04)
590 1.1 ichiro */
591 1.1 ichiro struct wi_ltv_ssid {
592 1.1 ichiro u_int16_t wi_len;
593 1.1 ichiro u_int16_t wi_type;
594 1.1 ichiro u_int16_t wi_id[17];
595 1.1 ichiro };
596 1.1 ichiro
597 1.1 ichiro /*
598 1.13 christos * Set our station name. (0xFC0E)
599 1.1 ichiro */
600 1.1 ichiro struct wi_ltv_nodename {
601 1.1 ichiro u_int16_t wi_len;
602 1.1 ichiro u_int16_t wi_type;
603 1.1 ichiro u_int16_t wi_nodename[17];
604 1.1 ichiro };
605 1.1 ichiro
606 1.1 ichiro /*
607 1.1 ichiro * Multicast addresses to be put in filter. We're
608 1.13 christos * allowed up to 16 addresses in the filter. (0xFC80)
609 1.1 ichiro */
610 1.1 ichiro struct wi_ltv_mcast {
611 1.1 ichiro u_int16_t wi_len;
612 1.1 ichiro u_int16_t wi_type;
613 1.1 ichiro struct ether_addr wi_mcast[16];
614 1.1 ichiro };
615 1.1 ichiro
616 1.1 ichiro /*
617 1.36 thorpej * Supported rates.
618 1.36 thorpej */
619 1.36 thorpej #define WI_SUPPRATES_1M 0x0001
620 1.36 thorpej #define WI_SUPPRATES_2M 0x0002
621 1.36 thorpej #define WI_SUPPRATES_5M 0x0004
622 1.36 thorpej #define WI_SUPPRATES_11M 0x0008
623 1.36 thorpej
624 1.36 thorpej /*
625 1.1 ichiro * Information frame types.
626 1.1 ichiro */
627 1.1 ichiro #define WI_INFO_NOTIFY 0xF000 /* Handover address */
628 1.1 ichiro #define WI_INFO_COUNTERS 0xF100 /* Statistics counters */
629 1.18 ichiro #define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */
630 1.33 onoe #define WI_INFO_HOST_SCAN_RESULTS 0xF104 /* Scan results */
631 1.1 ichiro #define WI_INFO_LINK_STAT 0xF200 /* Link status */
632 1.1 ichiro #define WI_INFO_ASSOC_STAT 0xF201 /* Association status */
633 1.18 ichiro struct wi_assoc {
634 1.18 ichiro u_int16_t wi_assoc_stat; /* Association Status */
635 1.18 ichiro #define ASSOC 1
636 1.18 ichiro #define REASSOC 2
637 1.18 ichiro #define DISASSOC 3
638 1.18 ichiro #define ASSOCFAIL 4
639 1.18 ichiro #define AUTHFAIL 5
640 1.18 ichiro u_int8_t wi_assoc_sta[6]; /* Station Address */
641 1.18 ichiro u_int8_t wi_assoc_osta[6]; /* OLD Station Address */
642 1.18 ichiro u_int16_t wi_assoc_reason; /* Reason */
643 1.18 ichiro u_int16_t wi_assoc_reserve; /* Reserved */
644 1.18 ichiro };
645 1.18 ichiro
646 1.15 ichiro #define WI_INFO_AUTH_REQUEST 0xF202 /* Authentication Request (AP) */
647 1.15 ichiro #define WI_INFO_POWERSAVE_COUNT 0xF203 /* PowerSave User Count (AP) */
648 1.17 ichiro
649 1.17 ichiro /*
650 1.18 ichiro * Scan Results of Prism2 chip
651 1.17 ichiro */
652 1.17 ichiro
653 1.17 ichiro #define MAXAPINFO 30
654 1.17 ichiro struct wi_scan_header {
655 1.17 ichiro u_int16_t wi_reserve; /* future use */
656 1.17 ichiro u_int16_t wi_reason; /* The reason this scan was initiated
657 1.17 ichiro 1: Host initiated
658 1.17 ichiro 2: Firmware initiated
659 1.17 ichiro 3: Inquiry request from host */
660 1.17 ichiro };
661 1.18 ichiro
662 1.17 ichiro struct wi_scan_data_p2 {
663 1.17 ichiro u_int16_t wi_chid; /* BSS Channel ID from Probe Res.(PR)*/
664 1.17 ichiro u_int16_t wi_noise; /* Average Noise Level of the PR */
665 1.17 ichiro u_int16_t wi_signal; /* Signal Level on the PR */
666 1.17 ichiro u_int8_t wi_bssid[6]; /* MACaddress of BSS responder from PR */
667 1.17 ichiro u_int16_t wi_interval; /* BSS beacon interval */
668 1.17 ichiro u_int16_t wi_capinfo; /* BSS Capability Information
669 1.17 ichiro IEEE Std 802.11(1997) ,see 7.3.1.4 */
670 1.17 ichiro u_int16_t wi_namelen; /* Length of SSID strings */
671 1.17 ichiro u_int8_t wi_name[32]; /* SSID strings */
672 1.17 ichiro u_int16_t wi_suprate[5]; /* Supported Rates element from the PR
673 1.17 ichiro IEEE Std 802.11(1997) ,see 7.3.2.2 */
674 1.17 ichiro u_int16_t wi_rate; /* Data rate of the PR */
675 1.17 ichiro #define WI_APRATE_1 0x0A /* 1 Mbps */
676 1.17 ichiro #define WI_APRATE_2 0x14 /* 2 Mbps */
677 1.17 ichiro #define WI_APRATE_5 0x37 /* 5.5 Mbps */
678 1.17 ichiro #define WI_APRATE_11 0x6E /* 11 Mbps */
679 1.17 ichiro };
680 1.17 ichiro
681 1.17 ichiro /*
682 1.17 ichiro * Scan Results of Lucent chip
683 1.17 ichiro */
684 1.17 ichiro struct wi_scan_data {
685 1.17 ichiro u_int16_t wi_chid; /* BSS Channel ID from PR */
686 1.17 ichiro u_int16_t wi_noise; /* Average Noise Level of the PR */
687 1.17 ichiro u_int16_t wi_signal; /* Signal Level on the PR */
688 1.17 ichiro u_int8_t wi_bssid[6]; /* MACaddress of BSS responder from PR */
689 1.17 ichiro u_int16_t wi_interval; /* BSS beacon interval */
690 1.17 ichiro u_int16_t wi_capinfo; /* BSS Capability Information
691 1.17 ichiro IEEE Std 802.11(1997) ,see 7.3.1.4 */
692 1.17 ichiro u_int16_t wi_namelen; /* Length of SSID strings */
693 1.17 ichiro u_int8_t wi_name[32]; /* SSID strings */
694 1.17 ichiro };
695 1.1 ichiro
696 1.1 ichiro /*
697 1.22 ichiro * transmit/receive frame structure
698 1.1 ichiro */
699 1.1 ichiro struct wi_frame {
700 1.1 ichiro u_int16_t wi_status; /* 0x00 */
701 1.21 ichiro u_int16_t wi_rsvd0; /* 0x02 */ /* 0 */
702 1.21 ichiro u_int16_t wi_rsvd1; /* 0x04 */ /* 0 */
703 1.1 ichiro u_int16_t wi_q_info; /* 0x06 */
704 1.36 thorpej u_int16_t wi_rsvd2; /* 0x08 */
705 1.36 thorpej u_int8_t wi_tx_rtry; /* 0x0A */ /* (Prism2 Only) */
706 1.36 thorpej u_int8_t wi_tx_rate; /* 0x0B */ /* (Prism2 Only) */
707 1.1 ichiro u_int16_t wi_tx_ctl; /* 0x0C */
708 1.1 ichiro u_int16_t wi_frame_ctl; /* 0x0E */
709 1.1 ichiro u_int16_t wi_id; /* 0x10 */
710 1.1 ichiro u_int8_t wi_addr1[6]; /* 0x12 */
711 1.1 ichiro u_int8_t wi_addr2[6]; /* 0x18 */
712 1.1 ichiro u_int8_t wi_addr3[6]; /* 0x1E */
713 1.1 ichiro u_int16_t wi_seq_ctl; /* 0x24 */
714 1.1 ichiro u_int8_t wi_addr4[6]; /* 0x26 */
715 1.1 ichiro u_int16_t wi_dat_len; /* 0x2C */
716 1.1 ichiro u_int8_t wi_dst_addr[6]; /* 0x2E */
717 1.1 ichiro u_int8_t wi_src_addr[6]; /* 0x34 */
718 1.1 ichiro u_int16_t wi_len; /* 0x3A */
719 1.39 thorpej #if 0
720 1.39 thorpej struct llc wi_llc; /* 0x3C */ /* SNAP header */
721 1.39 thorpej #endif
722 1.1 ichiro };
723 1.1 ichiro
724 1.39 thorpej #define WI_TX_BUFSIZE (ETHER_MAX_LEN + sizeof(struct wi_frame) + 8)
725 1.39 thorpej
726 1.1 ichiro #define WI_802_3_OFFSET 0x2E
727 1.1 ichiro #define WI_802_11_OFFSET 0x44
728 1.1 ichiro #define WI_802_11_OFFSET_RAW 0x3C
729 1.21 ichiro #define WI_802_11_OFFSET_HDR 0x0E
730 1.1 ichiro
731 1.39 thorpej #define WI_HWSPEC_END 0x0E
732 1.39 thorpej #define WI_802_11_BEGIN 0x0E
733 1.39 thorpej #define WI_SHORT_802_11_END 0x26
734 1.39 thorpej #define WI_LONG_802_11_END 0x2C
735 1.39 thorpej #define WI_802_3_BEGIN 0x2E
736 1.39 thorpej #define WI_802_3_END 0x3C
737 1.39 thorpej #define WI_DATA_BEGIN 0x3C
738 1.39 thorpej #define WI_LLC_BEGIN 0x3C
739 1.39 thorpej #define WI_LLC_END 0x44
740 1.39 thorpej
741 1.23 ichiro /* Tx Status Field */
742 1.23 ichiro #define WI_TXSTAT_RET_ERR 0x0001
743 1.23 ichiro #define WI_TXSTAT_AGED_ERR 0x0002
744 1.23 ichiro #define WI_TXSTAT_DISCONNECT 0x0004
745 1.23 ichiro #define WI_TXSTAT_FORM_ERR 0x0008
746 1.23 ichiro
747 1.23 ichiro /* Rx Status Field */
748 1.1 ichiro #define WI_STAT_BADCRC 0x0001
749 1.1 ichiro #define WI_STAT_UNDECRYPTABLE 0x0002
750 1.1 ichiro #define WI_STAT_ERRSTAT 0x0003
751 1.1 ichiro #define WI_STAT_MAC_PORT 0x0700
752 1.23 ichiro #define WI_STAT_PCF 0x1000
753 1.1 ichiro #define WI_RXSTAT_MSG_TYPE 0xE000
754 1.39 thorpej #define WI_STAT_NORMAL 0x0000
755 1.23 ichiro #define WI_STAT_1042 0x2000 /* RFC1042 encoded */
756 1.23 ichiro #define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
757 1.23 ichiro #define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
758 1.23 ichiro #define WI_STAT_MGMT 0x8000 /* 802.11b management frames */
759 1.1 ichiro
760 1.21 ichiro /* TxControl Field (enhanced) */
761 1.21 ichiro #define WI_TXCNTL_TX_OK 0x0002
762 1.21 ichiro #define WI_TXCNTL_TX_EX 0x0004
763 1.23 ichiro #define WI_TXCNTL_STRUCT_TYPE 0x0018
764 1.23 ichiro #define WI_ENC_TX_802_3 0x00
765 1.39 thorpej #define WI_ENC_TX_802_11 0x08
766 1.21 ichiro #define WI_TXCNTL_ALTRTRY 0x0020
767 1.21 ichiro #define WI_TXCNTL_NOCRYPT 0x0080
768 1.1 ichiro
769 1.1 ichiro /*
770 1.1 ichiro * SNAP (sub-network access protocol) constants for transmission
771 1.1 ichiro * of IP datagrams over IEEE 802 networks, taken from RFC1042.
772 1.1 ichiro * We need these for the LLC/SNAP header fields in the TX/RX frame
773 1.1 ichiro * structure.
774 1.1 ichiro */
775 1.39 thorpej #define WI_SNAP_LEN 8
776