wireg.h revision 1.41 1 1.41 onoe /* $NetBSD: wireg.h,v 1.41 2002/10/02 17:11:36 onoe Exp $ */
2 1.1 ichiro
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 1997, 1998, 1999
5 1.1 ichiro * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
16 1.1 ichiro * must display the following acknowledgement:
17 1.1 ichiro * This product includes software developed by Bill Paul.
18 1.1 ichiro * 4. Neither the name of the author nor the names of any co-contributors
19 1.1 ichiro * may be used to endorse or promote products derived from this software
20 1.1 ichiro * without specific prior written permission.
21 1.1 ichiro *
22 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 1.1 ichiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 1.1 ichiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 1.1 ichiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 1.1 ichiro * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 1.1 ichiro * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 1.1 ichiro * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 1.1 ichiro * THE POSSIBILITY OF SUCH DAMAGE.
33 1.1 ichiro */
34 1.1 ichiro
35 1.1 ichiro /*
36 1.1 ichiro * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the
37 1.1 ichiro * Oslo IETF plenary meeting.
38 1.1 ichiro */
39 1.1 ichiro
40 1.1 ichiro #define WI_TIMEOUT 65536
41 1.1 ichiro
42 1.40 onoe #define WI_PORT0 (0 << 8)
43 1.40 onoe #define WI_PORT1 (1 << 8)
44 1.40 onoe #define WI_PORT2 (2 << 8)
45 1.40 onoe #define WI_PORT3 (3 << 8)
46 1.40 onoe #define WI_PORT4 (4 << 8)
47 1.40 onoe #define WI_PORT5 (5 << 8)
48 1.5 tsubai
49 1.1 ichiro /*
50 1.1 ichiro * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
51 1.1 ichiro * calls 'Hermes.' In typical fashion, getting documentation about this
52 1.1 ichiro * controller is about as easy as squeezing blood from a stone. Here
53 1.1 ichiro * is more or less what I know:
54 1.1 ichiro *
55 1.1 ichiro * - The Hermes controller is firmware driven, and the host interacts
56 1.1 ichiro * with the Hermes via a firmware interface, which can change.
57 1.1 ichiro *
58 1.1 ichiro * - The Hermes is described in a document called: "Hermes Firmware
59 1.1 ichiro * WaveLAN/IEEE Station Functions," document #010245, which of course
60 1.1 ichiro * Lucent will not release without an NDA.
61 1.1 ichiro *
62 1.1 ichiro * - Lucent has created a library called HCF (Hardware Control Functions)
63 1.1 ichiro * though which it wants developers to interact with the card. The HCF
64 1.1 ichiro * is needlessly complex, ill conceived and badly documented. Actually,
65 1.1 ichiro * the comments in the HCP code itself aren't bad, but the publically
66 1.1 ichiro * available manual that comes with it is awful, probably due largely to
67 1.1 ichiro * the fact that it has been emasculated in order to hide information
68 1.1 ichiro * that Lucent wants to keep proprietary. The purpose of the HCF seems
69 1.1 ichiro * to be to insulate the driver programmer from the Hermes itself so that
70 1.1 ichiro * Lucent has an excuse not to release programming in for it.
71 1.1 ichiro *
72 1.1 ichiro * - Lucent only makes available documentation and code for 'HCF Light'
73 1.1 ichiro * which is a stripped down version of HCF with certain features not
74 1.1 ichiro * implemented, most notably support for 802.11 frames.
75 1.1 ichiro *
76 1.1 ichiro * - The HCF code which I have seen blows goats. Whoever decided to
77 1.1 ichiro * use a 132 column format should be shot.
78 1.1 ichiro *
79 1.1 ichiro * Rather than actually use the Lucent HCF library, I have stripped all
80 1.1 ichiro * the useful information from it and used it to create a driver in the
81 1.1 ichiro * usual BSD form. Note: I don't want to hear anybody whining about the
82 1.1 ichiro * fact that the Lucent code is GPLed and mine isn't. I did not actually
83 1.1 ichiro * put any of Lucent's code in this driver: I only used it as a reference
84 1.1 ichiro * to obtain information about the underlying hardware. The Hermes
85 1.1 ichiro * programming interface is not GPLed, so bite me.
86 1.1 ichiro */
87 1.1 ichiro
88 1.1 ichiro /*
89 1.11 ichiro * Size of Hermes & Prism2 I/O space.
90 1.1 ichiro */
91 1.1 ichiro #define WI_IOSIZE 0x40
92 1.11 ichiro #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */
93 1.1 ichiro
94 1.1 ichiro /*
95 1.11 ichiro * Hermes & Prism2 register definitions
96 1.1 ichiro */
97 1.1 ichiro
98 1.1 ichiro /* Hermes command/status registers. */
99 1.1 ichiro #define WI_COMMAND 0x00
100 1.1 ichiro #define WI_PARAM0 0x02
101 1.1 ichiro #define WI_PARAM1 0x04
102 1.1 ichiro #define WI_PARAM2 0x06
103 1.1 ichiro #define WI_STATUS 0x08
104 1.1 ichiro #define WI_RESP0 0x0A
105 1.1 ichiro #define WI_RESP1 0x0C
106 1.1 ichiro #define WI_RESP2 0x0E
107 1.1 ichiro
108 1.1 ichiro /* Command register values. */
109 1.1 ichiro #define WI_CMD_BUSY 0x8000 /* busy bit */
110 1.1 ichiro #define WI_CMD_INI 0x0000 /* initialize */
111 1.1 ichiro #define WI_CMD_ENABLE 0x0001 /* enable */
112 1.1 ichiro #define WI_CMD_DISABLE 0x0002 /* disable */
113 1.1 ichiro #define WI_CMD_DIAG 0x0003
114 1.1 ichiro #define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
115 1.1 ichiro #define WI_CMD_TX 0x000B /* transmit */
116 1.1 ichiro #define WI_CMD_NOTIFY 0x0010
117 1.1 ichiro #define WI_CMD_INQUIRE 0x0011
118 1.1 ichiro #define WI_CMD_ACCESS 0x0021
119 1.1 ichiro #define WI_CMD_PROGRAM 0x0022
120 1.32 onoe #define WI_CMD_READEE 0x0030
121 1.1 ichiro
122 1.1 ichiro #define WI_CMD_CODE_MASK 0x003F
123 1.1 ichiro
124 1.1 ichiro /*
125 1.1 ichiro * Reclaim qualifier bit, applicable to the
126 1.1 ichiro * TX and INQUIRE commands.
127 1.1 ichiro */
128 1.1 ichiro #define WI_RECLAIM 0x0100 /* reclaim NIC memory */
129 1.1 ichiro
130 1.1 ichiro /*
131 1.1 ichiro * ACCESS command qualifier bits.
132 1.1 ichiro */
133 1.1 ichiro #define WI_ACCESS_READ 0x0000
134 1.1 ichiro #define WI_ACCESS_WRITE 0x0100
135 1.1 ichiro
136 1.1 ichiro /*
137 1.1 ichiro * PROGRAM command qualifier bits.
138 1.1 ichiro */
139 1.1 ichiro #define WI_PROGRAM_DISABLE 0x0000
140 1.1 ichiro #define WI_PROGRAM_ENABLE_RAM 0x0100
141 1.1 ichiro #define WI_PROGRAM_ENABLE_NVRAM 0x0200
142 1.1 ichiro #define WI_PROGRAM_NVRAM 0x0300
143 1.1 ichiro
144 1.1 ichiro /* Status register values */
145 1.1 ichiro #define WI_STAT_CMD_CODE 0x003F
146 1.1 ichiro #define WI_STAT_DIAG_ERR 0x0100
147 1.1 ichiro #define WI_STAT_INQ_ERR 0x0500
148 1.1 ichiro #define WI_STAT_CMD_RESULT 0x7F00
149 1.1 ichiro
150 1.1 ichiro /* memory handle management registers */
151 1.1 ichiro #define WI_INFO_FID 0x10
152 1.1 ichiro #define WI_RX_FID 0x20
153 1.1 ichiro #define WI_ALLOC_FID 0x22
154 1.1 ichiro #define WI_TX_CMP_FID 0x24
155 1.1 ichiro
156 1.1 ichiro /*
157 1.1 ichiro * Buffer Access Path (BAP) registers.
158 1.1 ichiro * These are I/O channels. I believe you can use each one for
159 1.40 onoe * any desired purpose independently of the other.
160 1.40 onoe * Currently, we only use BAP0, and perhaps BAP1 can be used
161 1.40 onoe * within interrupt context.
162 1.1 ichiro */
163 1.1 ichiro #define WI_SEL0 0x18
164 1.1 ichiro #define WI_SEL1 0x1A
165 1.1 ichiro #define WI_OFF0 0x1C
166 1.1 ichiro #define WI_OFF1 0x1E
167 1.1 ichiro #define WI_DATA0 0x36
168 1.1 ichiro #define WI_DATA1 0x38
169 1.1 ichiro
170 1.1 ichiro #define WI_OFF_BUSY 0x8000
171 1.1 ichiro #define WI_OFF_ERR 0x4000
172 1.1 ichiro #define WI_OFF_DATAOFF 0x0FFF
173 1.1 ichiro
174 1.1 ichiro /* Event registers */
175 1.1 ichiro #define WI_EVENT_STAT 0x30 /* Event status */
176 1.1 ichiro #define WI_INT_EN 0x32 /* Interrupt enable/disable */
177 1.1 ichiro #define WI_EVENT_ACK 0x34 /* Ack event */
178 1.1 ichiro
179 1.1 ichiro /* Events */
180 1.1 ichiro #define WI_EV_TICK 0x8000 /* aux timer tick */
181 1.1 ichiro #define WI_EV_RES 0x4000 /* controller h/w error (time out) */
182 1.1 ichiro #define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */
183 1.1 ichiro #define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */
184 1.14 explorer #define WI_EV_DUIF_RX 0x0400 /* wavelan management packet received */
185 1.1 ichiro #define WI_EV_INFO 0x0080 /* async info frame */
186 1.1 ichiro #define WI_EV_CMD 0x0010 /* command completed */
187 1.1 ichiro #define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
188 1.1 ichiro #define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */
189 1.1 ichiro #define WI_EV_TX 0x0002 /* async xmit completed succesfully */
190 1.1 ichiro #define WI_EV_RX 0x0001 /* async rx completed */
191 1.1 ichiro
192 1.1 ichiro /* Host software registers */
193 1.1 ichiro #define WI_SW0 0x28
194 1.1 ichiro #define WI_SW1 0x2A
195 1.1 ichiro #define WI_SW2 0x2C
196 1.11 ichiro #define WI_SW3 0x2E /* does not appear in Prism2 */
197 1.1 ichiro
198 1.1 ichiro #define WI_CNTL 0x14
199 1.1 ichiro
200 1.1 ichiro #define WI_CNTL_AUX_ENA 0xC000
201 1.1 ichiro #define WI_CNTL_AUX_ENA_STAT 0xC000
202 1.1 ichiro #define WI_CNTL_AUX_DIS_STAT 0x0000
203 1.1 ichiro #define WI_CNTL_AUX_ENA_CNTL 0x8000
204 1.1 ichiro #define WI_CNTL_AUX_DIS_CNTL 0x4000
205 1.1 ichiro
206 1.1 ichiro #define WI_AUX_PAGE 0x3A
207 1.1 ichiro #define WI_AUX_OFFSET 0x3C
208 1.1 ichiro #define WI_AUX_DATA 0x3E
209 1.32 onoe
210 1.32 onoe #define WI_AUX_PGSZ 128
211 1.32 onoe #define WI_AUX_KEY0 0xfe01
212 1.32 onoe #define WI_AUX_KEY1 0xdc23
213 1.32 onoe #define WI_AUX_KEY2 0xba45
214 1.32 onoe
215 1.32 onoe #define WI_COR 0x40 /* only for Symbol */
216 1.32 onoe #define WI_COR_RESET 0x0080
217 1.32 onoe #define WI_COR_IOMODE 0x0041
218 1.32 onoe
219 1.32 onoe #define WI_HCR 0x42 /* only for Symbol */
220 1.32 onoe #define WI_HCR_4WIRE 0x0010
221 1.32 onoe #define WI_HCR_RUN 0x0007
222 1.32 onoe #define WI_HCR_HOLD 0x000f
223 1.32 onoe #define WI_HCR_EEHOLD 0x00ce
224 1.1 ichiro
225 1.1 ichiro /*
226 1.11 ichiro * PCI Host Interface Registers (HFA3842 Specific)
227 1.11 ichiro * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0,
228 1.11 ichiro * has doubled.
229 1.12 ichiro * About WI_PCI_COR: In this Register, only soft-reset bit implement; Bit(7).
230 1.11 ichiro */
231 1.11 ichiro #define WI_PCI_COR 0x4C
232 1.11 ichiro #define WI_PCI_HCR 0x5C
233 1.11 ichiro #define WI_PCI_MASTER0_ADDRH 0x80
234 1.11 ichiro #define WI_PCI_MASTER0_ADDRL 0x84
235 1.11 ichiro #define WI_PCI_MASTER0_LEN 0x88
236 1.11 ichiro #define WI_PCI_MASTER0_CON 0x8C
237 1.11 ichiro
238 1.11 ichiro #define WI_PCI_STATUS 0x98
239 1.11 ichiro
240 1.11 ichiro #define WI_PCI_MASTER1_ADDRH 0xA0
241 1.11 ichiro #define WI_PCI_MASTER1_ADDRL 0xA4
242 1.11 ichiro #define WI_PCI_MASTER1_LEN 0xA8
243 1.12 ichiro #define WI_PCI_MASTER1_CON 0xAC
244 1.12 ichiro
245 1.40 onoe #define WI_COR_SOFT_RESET (1 << 7)
246 1.40 onoe #define WI_COR_CLEAR 0x00
247 1.11 ichiro
248 1.11 ichiro /*
249 1.1 ichiro * One form of communication with the Hermes is with what Lucent calls
250 1.1 ichiro * LTV records, where LTV stands for Length, Type and Value. The length
251 1.1 ichiro * and type are 16 bits and are in native byte order. The value is in
252 1.1 ichiro * multiples of 16 bits and is in little endian byte order.
253 1.1 ichiro */
254 1.40 onoe struct wi_lt_hdr {
255 1.1 ichiro u_int16_t wi_len;
256 1.1 ichiro u_int16_t wi_type;
257 1.40 onoe /* value is vary depends on resource id */
258 1.1 ichiro };
259 1.1 ichiro
260 1.1 ichiro /*
261 1.1 ichiro * Download buffer location and length (0xFD01).
262 1.1 ichiro */
263 1.40 onoe struct wi_dnld_buf {
264 1.1 ichiro u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/
265 1.1 ichiro u_int16_t wi_buf_off; /* offset of idb */
266 1.1 ichiro u_int16_t wi_buf_len; /* len of idb */
267 1.1 ichiro };
268 1.1 ichiro
269 1.1 ichiro /*
270 1.1 ichiro * Mem sizes (0xFD02).
271 1.1 ichiro */
272 1.40 onoe struct wi_memsz {
273 1.1 ichiro u_int16_t wi_mem_ram;
274 1.1 ichiro u_int16_t wi_mem_nvram;
275 1.2 ichiro };
276 1.2 ichiro
277 1.2 ichiro /*
278 1.13 christos * NIC Identification (0xFD0B, 0xFD20)
279 1.2 ichiro */
280 1.40 onoe struct wi_ver {
281 1.2 ichiro u_int16_t wi_ver[4];
282 1.1 ichiro };
283 1.28 ichiro
284 1.28 ichiro /* define card ident */
285 1.30 ichiro /* Lucent */
286 1.30 ichiro #define WI_NIC_LUCENT_ID 0x0001
287 1.29 ichiro #define WI_NIC_LUCENT_STR "Lucent Technologies, WaveLAN/IEEE"
288 1.28 ichiro
289 1.30 ichiro #define WI_NIC_SONY_ID 0x0002
290 1.30 ichiro #define WI_NIC_SONY_STR "Sony WaveLAN/IEEE"
291 1.30 ichiro
292 1.30 ichiro #define WI_NIC_LUCENT_EMB_ID 0x0005
293 1.30 ichiro #define WI_NIC_LUCENT_EMB_STR "Lucent Embedded WaveLAN/IEEE"
294 1.30 ichiro
295 1.30 ichiro /* Intersil */
296 1.29 ichiro #define WI_NIC_EVB2_ID 0x8000
297 1.29 ichiro #define WI_NIC_EVB2_STR "RF:PRISM2 MAC:HFA3841"
298 1.28 ichiro
299 1.29 ichiro #define WI_NIC_HWB3763_ID 0x8001
300 1.29 ichiro #define WI_NIC_HWB3763_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3763 rev.B"
301 1.28 ichiro
302 1.29 ichiro #define WI_NIC_HWB3163_ID 0x8002
303 1.29 ichiro #define WI_NIC_HWB3163_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.A"
304 1.28 ichiro
305 1.29 ichiro #define WI_NIC_HWB3163B_ID 0x8003
306 1.29 ichiro #define WI_NIC_HWB3163B_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.B"
307 1.28 ichiro
308 1.29 ichiro #define WI_NIC_EVB3_ID 0x8004
309 1.29 ichiro #define WI_NIC_EVB3_STR "RF:PRISM2 MAC:HFA3842 CARD:HFA3842 EVAL"
310 1.28 ichiro
311 1.29 ichiro #define WI_NIC_HWB1153_ID 0x8007
312 1.29 ichiro #define WI_NIC_HWB1153_STR "RF:PRISM1 MAC:HFA3841 CARD:HWB1153"
313 1.28 ichiro
314 1.29 ichiro #define WI_NIC_P2_SST_ID 0x8008 /* Prism2 with SST flush */
315 1.29 ichiro #define WI_NIC_P2_SST_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash"
316 1.28 ichiro
317 1.28 ichiro #define WI_NIC_EVB2_SST_ID 0x8009
318 1.28 ichiro #define WI_NIC_EVB2_SST_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash"
319 1.28 ichiro
320 1.31 ichiro #define WI_NIC_3842_EVA_ID 0x800A /* Prism2 3842 Evaluation Board */
321 1.28 ichiro #define WI_NIC_3842_EVA_STR "RF:PRISM2 MAC:HFA3842 CARD:HFA3842 EVAL"
322 1.28 ichiro
323 1.28 ichiro #define WI_NIC_3842_PCMCIA_AMD_ID 0x800B /* Prism2.5 PCMCIA */
324 1.28 ichiro #define WI_NIC_3842_PCMCIA_SST_ID 0x800C
325 1.28 ichiro #define WI_NIC_3842_PCMCIA_ATM_ID 0x800D
326 1.31 ichiro #define WI_NIC_3842_PCMCIA_STR "RF:PRISM2.5 MAC:ISL3873B(PCMCIA)"
327 1.28 ichiro
328 1.28 ichiro #define WI_NIC_3842_MINI_AMD_ID 0x8012 /* Prism2.5 Mini-PCI */
329 1.28 ichiro #define WI_NIC_3842_MINI_SST_ID 0x8013
330 1.28 ichiro #define WI_NIC_3842_MINI_ATM_ID 0x8014
331 1.28 ichiro #define WI_NIC_3842_MINI_STR "RF:PRISM2.5 MAC:ISL3874A(Mini-PCI)"
332 1.28 ichiro
333 1.28 ichiro #define WI_NIC_3842_PCI_AMD_ID 0x8016 /* Prism2.5 PCI-bridge */
334 1.28 ichiro #define WI_NIC_3842_PCI_SST_ID 0x8017
335 1.28 ichiro #define WI_NIC_3842_PCI_ATM_ID 0x8018
336 1.28 ichiro #define WI_NIC_3842_PCI_STR "RF:PRISM2.5 MAC:ISL3874A(PCI-bridge)"
337 1.28 ichiro
338 1.28 ichiro #define WI_NIC_P3_PCMCIA_AMD_ID 0x801A /* Prism3 PCMCIA */
339 1.28 ichiro #define WI_NIC_P3_PCMCIA_SST_ID 0x801B
340 1.31 ichiro #define WI_NIC_P3_PCMCIA_STR "RF:PRISM3 MAC:ISL3871(PCMCIA)"
341 1.28 ichiro
342 1.28 ichiro #define WI_NIC_P3_MINI_AMD_ID 0x8021 /* Prism3 Mini-PCI */
343 1.28 ichiro #define WI_NIC_P3_MINI_SST_ID 0x8022
344 1.31 ichiro #define WI_NIC_P3_MINI_STR "RF:PRISM3 MAC:ISL3871(Mini-PCI)"
345 1.1 ichiro
346 1.1 ichiro /*
347 1.1 ichiro * List of intended regulatory domains (0xFD11).
348 1.1 ichiro */
349 1.40 onoe struct wi_domains {
350 1.1 ichiro u_int16_t wi_domains[6];
351 1.1 ichiro };
352 1.1 ichiro
353 1.1 ichiro /*
354 1.1 ichiro * CIS struct (0xFD13).
355 1.1 ichiro */
356 1.40 onoe struct wi_cis {
357 1.1 ichiro u_int16_t wi_cis[240];
358 1.1 ichiro };
359 1.1 ichiro
360 1.1 ichiro /*
361 1.1 ichiro * Communications quality (0xFD43).
362 1.1 ichiro */
363 1.40 onoe struct wi_commqual {
364 1.1 ichiro u_int16_t wi_coms_qual;
365 1.1 ichiro u_int16_t wi_sig_lvl;
366 1.1 ichiro u_int16_t wi_noise_lvl;
367 1.1 ichiro };
368 1.1 ichiro
369 1.1 ichiro /*
370 1.13 christos * Actual system scale thresholds (0xFC06, 0xFD46).
371 1.1 ichiro */
372 1.40 onoe struct wi_scalethresh {
373 1.1 ichiro u_int16_t wi_energy_detect;
374 1.1 ichiro u_int16_t wi_carrier_detect;
375 1.1 ichiro u_int16_t wi_defer;
376 1.1 ichiro u_int16_t wi_cell_search;
377 1.1 ichiro u_int16_t wi_out_of_range;
378 1.1 ichiro u_int16_t wi_delta_snr;
379 1.1 ichiro };
380 1.1 ichiro
381 1.1 ichiro /*
382 1.1 ichiro * PCF info struct (0xFD87).
383 1.1 ichiro */
384 1.40 onoe struct wi_pcf {
385 1.1 ichiro u_int16_t wi_medium_occupancy_limit;
386 1.1 ichiro u_int16_t wi_cfp_period;
387 1.1 ichiro u_int16_t wi_cfp_max_duration;
388 1.1 ichiro };
389 1.1 ichiro
390 1.15 ichiro /*
391 1.13 christos * Connection control characteristics. (0xFC00)
392 1.25 ichiro * 0 == IBSS (802.11 compliant mode) (Only PRISM2)
393 1.1 ichiro * 1 == Basic Service Set (BSS)
394 1.1 ichiro * 2 == Wireless Distribudion System (WDS)
395 1.25 ichiro * 3 == Pseudo IBSS
396 1.25 ichiro * (Only PRISM2; not 802.11 compliant mode, testing use only)
397 1.25 ichiro * 6 == HOST AP (Only PRISM2)
398 1.1 ichiro */
399 1.35 thorpej #define WI_PORTTYPE_IBSS 0x0
400 1.1 ichiro #define WI_PORTTYPE_BSS 0x1
401 1.1 ichiro #define WI_PORTTYPE_WDS 0x2
402 1.1 ichiro #define WI_PORTTYPE_ADHOC 0x3
403 1.35 thorpej #define WI_PORTTYPE_HOSTAP 0x6
404 1.1 ichiro
405 1.1 ichiro /*
406 1.13 christos * Mac addresses. (0xFC01, 0xFC08)
407 1.1 ichiro */
408 1.40 onoe struct wi_macaddr {
409 1.1 ichiro u_int8_t wi_mac_addr[6];
410 1.1 ichiro };
411 1.1 ichiro
412 1.1 ichiro /*
413 1.13 christos * Station set identification (SSID). (0xFC02, 0xFC04)
414 1.1 ichiro */
415 1.40 onoe struct wi_ssid {
416 1.1 ichiro u_int16_t wi_len;
417 1.40 onoe u_int8_t wi_ssid[32];
418 1.1 ichiro };
419 1.1 ichiro
420 1.1 ichiro /*
421 1.13 christos * Set our station name. (0xFC0E)
422 1.1 ichiro */
423 1.40 onoe struct wi_nodename {
424 1.40 onoe u_int16_t wi_nodelen;
425 1.40 onoe u_int8_t wi_nodename[32];
426 1.1 ichiro };
427 1.1 ichiro
428 1.1 ichiro /*
429 1.1 ichiro * Multicast addresses to be put in filter. We're
430 1.13 christos * allowed up to 16 addresses in the filter. (0xFC80)
431 1.1 ichiro */
432 1.40 onoe struct wi_mcast {
433 1.1 ichiro struct ether_addr wi_mcast[16];
434 1.1 ichiro };
435 1.1 ichiro
436 1.1 ichiro /*
437 1.40 onoe * Join request. (0xFCE2)
438 1.36 thorpej */
439 1.40 onoe struct wi_joinreq {
440 1.40 onoe struct ether_addr wi_bssid;
441 1.40 onoe u_int16_t wi_chan;
442 1.40 onoe };
443 1.36 thorpej
444 1.36 thorpej /*
445 1.1 ichiro * Information frame types.
446 1.1 ichiro */
447 1.1 ichiro #define WI_INFO_NOTIFY 0xF000 /* Handover address */
448 1.1 ichiro #define WI_INFO_COUNTERS 0xF100 /* Statistics counters */
449 1.18 ichiro #define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */
450 1.33 onoe #define WI_INFO_HOST_SCAN_RESULTS 0xF104 /* Scan results */
451 1.1 ichiro #define WI_INFO_LINK_STAT 0xF200 /* Link status */
452 1.40 onoe #define CONNECTED 1
453 1.40 onoe #define DISCONNECTED 2
454 1.40 onoe #define AP_CHANGE 3
455 1.40 onoe #define AP_OUT_OF_RANGE 4
456 1.40 onoe #define AP_IN_RANGE 5
457 1.40 onoe #define ASSOC_FAILED 6
458 1.1 ichiro #define WI_INFO_ASSOC_STAT 0xF201 /* Association status */
459 1.18 ichiro struct wi_assoc {
460 1.18 ichiro u_int16_t wi_assoc_stat; /* Association Status */
461 1.18 ichiro #define ASSOC 1
462 1.18 ichiro #define REASSOC 2
463 1.18 ichiro #define DISASSOC 3
464 1.18 ichiro #define ASSOCFAIL 4
465 1.18 ichiro #define AUTHFAIL 5
466 1.18 ichiro u_int8_t wi_assoc_sta[6]; /* Station Address */
467 1.18 ichiro u_int8_t wi_assoc_osta[6]; /* OLD Station Address */
468 1.18 ichiro u_int16_t wi_assoc_reason; /* Reason */
469 1.18 ichiro u_int16_t wi_assoc_reserve; /* Reserved */
470 1.18 ichiro };
471 1.18 ichiro
472 1.15 ichiro #define WI_INFO_AUTH_REQUEST 0xF202 /* Authentication Request (AP) */
473 1.15 ichiro #define WI_INFO_POWERSAVE_COUNT 0xF203 /* PowerSave User Count (AP) */
474 1.17 ichiro
475 1.17 ichiro /*
476 1.18 ichiro * Scan Results of Prism2 chip
477 1.17 ichiro */
478 1.17 ichiro
479 1.17 ichiro #define MAXAPINFO 30
480 1.17 ichiro struct wi_scan_header {
481 1.17 ichiro u_int16_t wi_reserve; /* future use */
482 1.17 ichiro u_int16_t wi_reason; /* The reason this scan was initiated
483 1.17 ichiro 1: Host initiated
484 1.17 ichiro 2: Firmware initiated
485 1.17 ichiro 3: Inquiry request from host */
486 1.17 ichiro };
487 1.18 ichiro
488 1.17 ichiro struct wi_scan_data_p2 {
489 1.17 ichiro u_int16_t wi_chid; /* BSS Channel ID from Probe Res.(PR)*/
490 1.17 ichiro u_int16_t wi_noise; /* Average Noise Level of the PR */
491 1.17 ichiro u_int16_t wi_signal; /* Signal Level on the PR */
492 1.17 ichiro u_int8_t wi_bssid[6]; /* MACaddress of BSS responder from PR */
493 1.17 ichiro u_int16_t wi_interval; /* BSS beacon interval */
494 1.17 ichiro u_int16_t wi_capinfo; /* BSS Capability Information
495 1.17 ichiro IEEE Std 802.11(1997) ,see 7.3.1.4 */
496 1.17 ichiro u_int16_t wi_namelen; /* Length of SSID strings */
497 1.17 ichiro u_int8_t wi_name[32]; /* SSID strings */
498 1.17 ichiro u_int16_t wi_suprate[5]; /* Supported Rates element from the PR
499 1.17 ichiro IEEE Std 802.11(1997) ,see 7.3.2.2 */
500 1.17 ichiro u_int16_t wi_rate; /* Data rate of the PR */
501 1.17 ichiro #define WI_APRATE_1 0x0A /* 1 Mbps */
502 1.17 ichiro #define WI_APRATE_2 0x14 /* 2 Mbps */
503 1.17 ichiro #define WI_APRATE_5 0x37 /* 5.5 Mbps */
504 1.17 ichiro #define WI_APRATE_11 0x6E /* 11 Mbps */
505 1.17 ichiro };
506 1.17 ichiro
507 1.17 ichiro /*
508 1.17 ichiro * Scan Results of Lucent chip
509 1.17 ichiro */
510 1.17 ichiro struct wi_scan_data {
511 1.17 ichiro u_int16_t wi_chid; /* BSS Channel ID from PR */
512 1.17 ichiro u_int16_t wi_noise; /* Average Noise Level of the PR */
513 1.17 ichiro u_int16_t wi_signal; /* Signal Level on the PR */
514 1.17 ichiro u_int8_t wi_bssid[6]; /* MACaddress of BSS responder from PR */
515 1.17 ichiro u_int16_t wi_interval; /* BSS beacon interval */
516 1.17 ichiro u_int16_t wi_capinfo; /* BSS Capability Information
517 1.17 ichiro IEEE Std 802.11(1997) ,see 7.3.1.4 */
518 1.17 ichiro u_int16_t wi_namelen; /* Length of SSID strings */
519 1.17 ichiro u_int8_t wi_name[32]; /* SSID strings */
520 1.17 ichiro };
521 1.1 ichiro
522 1.1 ichiro /*
523 1.22 ichiro * transmit/receive frame structure
524 1.1 ichiro */
525 1.1 ichiro struct wi_frame {
526 1.1 ichiro u_int16_t wi_status; /* 0x00 */
527 1.41 onoe u_int16_t wi_rx_tstamp1; /* 0x02 */
528 1.41 onoe u_int16_t wi_rx_tstamp0; /* 0x04 */
529 1.41 onoe u_int8_t wi_rx_silence; /* 0x06 */
530 1.41 onoe u_int8_t wi_rx_signal; /* 0x07 */
531 1.41 onoe u_int8_t wi_rx_rate; /* 0x08 */
532 1.41 onoe u_int8_t wi_rx_flow; /* 0x09 */
533 1.41 onoe u_int8_t wi_tx_rtry; /* 0x0a */ /* Prism2 AP Only */
534 1.41 onoe u_int8_t wi_tx_rate; /* 0x0b */ /* Prism2 AP Only */
535 1.40 onoe u_int16_t wi_tx_ctl; /* 0x0c */
536 1.40 onoe struct ieee80211_frame_addr4 wi_whdr; /* 0x0e */
537 1.40 onoe u_int16_t wi_dat_len; /* 0x2c */
538 1.40 onoe struct ether_header wi_ehdr; /* 0x2e */
539 1.40 onoe } __attribute__((__packed__));
540 1.39 thorpej
541 1.23 ichiro /* Tx Status Field */
542 1.23 ichiro #define WI_TXSTAT_RET_ERR 0x0001
543 1.23 ichiro #define WI_TXSTAT_AGED_ERR 0x0002
544 1.23 ichiro #define WI_TXSTAT_DISCONNECT 0x0004
545 1.23 ichiro #define WI_TXSTAT_FORM_ERR 0x0008
546 1.23 ichiro
547 1.23 ichiro /* Rx Status Field */
548 1.1 ichiro #define WI_STAT_BADCRC 0x0001
549 1.1 ichiro #define WI_STAT_UNDECRYPTABLE 0x0002
550 1.1 ichiro #define WI_STAT_ERRSTAT 0x0003
551 1.1 ichiro #define WI_STAT_MAC_PORT 0x0700
552 1.23 ichiro #define WI_STAT_PCF 0x1000
553 1.1 ichiro #define WI_RXSTAT_MSG_TYPE 0xE000
554 1.23 ichiro #define WI_STAT_1042 0x2000 /* RFC1042 encoded */
555 1.23 ichiro #define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
556 1.23 ichiro #define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
557 1.23 ichiro #define WI_STAT_MGMT 0x8000 /* 802.11b management frames */
558 1.1 ichiro
559 1.40 onoe #define WI_ENC_TX_E_II 0x0E
560 1.40 onoe
561 1.40 onoe #define WI_ENC_TX_1042 0x00
562 1.40 onoe #define WI_ENC_TX_TUNNEL 0xF8
563 1.40 onoe
564 1.21 ichiro /* TxControl Field (enhanced) */
565 1.21 ichiro #define WI_TXCNTL_TX_OK 0x0002
566 1.21 ichiro #define WI_TXCNTL_TX_EX 0x0004
567 1.23 ichiro #define WI_TXCNTL_STRUCT_TYPE 0x0018
568 1.23 ichiro #define WI_ENC_TX_802_3 0x00
569 1.39 thorpej #define WI_ENC_TX_802_11 0x08
570 1.21 ichiro #define WI_TXCNTL_ALTRTRY 0x0020
571 1.21 ichiro #define WI_TXCNTL_NOCRYPT 0x0080
572