wireg.h revision 1.31 1 /* $NetBSD: wireg.h,v 1.31 2002/04/10 04:01:27 ichiro Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the
37 * Oslo IETF plenary meeting.
38 */
39
40 #define WI_TIMEOUT 65536
41
42 #define WI_PORT0 0
43 #define WI_PORT1 1
44 #define WI_PORT2 2
45 #define WI_PORT3 3
46 #define WI_PORT4 4
47 #define WI_PORT5 5
48
49 /* Default port: 0 (only 0 exists on stations) */
50 #define WI_DEFAULT_PORT (WI_PORT0 << 8)
51
52 /* Default TX rate: 2Mbps, auto fallback */
53 #define WI_DEFAULT_TX_RATE 3
54
55 /* Default network name: ANY */
56 /*
57 * [sommerfeld 1999/07/15] Changed from "ANY" to ""; according to Bill Fenner,
58 * ANY is used in MS driver user interfaces, while "" is used over the
59 * wire..
60 */
61 #define WI_DEFAULT_NETNAME ""
62
63 #define WI_DEFAULT_AP_DENSITY 1
64
65 #define WI_DEFAULT_RTS_THRESH 2347
66
67 #define WI_DEFAULT_DATALEN 2304
68
69 #define WI_DEFAULT_CREATE_IBSS 0
70
71 #define WI_DEFAULT_PM_ENABLED 0
72
73 #define WI_DEFAULT_MAX_SLEEP 100
74
75 #define WI_DEFAULT_ROAMING 1
76
77 #define WI_DEFAULT_AUTHTYPE 1
78
79 #ifdef __NetBSD__
80 #define OS_STRING_NAME "NetBSD"
81 #endif
82 #ifdef __FreeBSD__
83 #define OS_STRING_NAME "FreeBSD"
84 #endif
85 #ifdef __OpenBSD__
86 #define OS_STRING_NAME "OpenBSD"
87 #endif
88
89 #define WI_DEFAULT_NODENAME OS_STRING_NAME " WaveLAN/IEEE node"
90
91 #define WI_DEFAULT_IBSS OS_STRING_NAME " IBSS"
92
93 #define WI_DEFAULT_CHAN 3
94
95 /*
96 * register space access macros
97 */
98 #ifdef WI_AT_BIGENDIAN_BUS_HACK
99 /*
100 * XXX - ugly hack for sparc bus_space_* macro deficiencies:
101 * assume the bus we are accessing is big endian.
102 */
103
104 #define CSR_WRITE_4(sc, reg, val) \
105 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \
106 (sc->sc_pci? reg * 2: reg) , htole32(val))
107 #define CSR_WRITE_2(sc, reg, val) \
108 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \
109 (sc->sc_pci? reg * 2: reg), htole16(val))
110 #define CSR_WRITE_1(sc, reg, val) \
111 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \
112 (sc->sc_pci? reg * 2: reg), val)
113
114 #define CSR_READ_4(sc, reg) \
115 le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \
116 (sc->sc_pci? reg * 2: reg)))
117 #define CSR_READ_2(sc, reg) \
118 le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \
119 (sc->sc_pci? reg * 2: reg)))
120 #define CSR_READ_1(sc, reg) \
121 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \
122 (sc->sc_pci? reg * 2: reg))
123
124 #else
125
126 #define CSR_WRITE_4(sc, reg, val) \
127 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \
128 (sc->sc_pci? reg * 2: reg) , val)
129 #define CSR_WRITE_2(sc, reg, val) \
130 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \
131 (sc->sc_pci? reg * 2: reg), val)
132 #define CSR_WRITE_1(sc, reg, val) \
133 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \
134 (sc->sc_pci? reg * 2: reg), val)
135
136 #define CSR_READ_4(sc, reg) \
137 bus_space_read_4(sc->sc_iot, sc->sc_ioh, \
138 (sc->sc_pci? reg * 2: reg))
139 #define CSR_READ_2(sc, reg) \
140 bus_space_read_2(sc->sc_iot, sc->sc_ioh, \
141 (sc->sc_pci? reg * 2: reg))
142 #define CSR_READ_1(sc, reg) \
143 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \
144 (sc->sc_pci? reg * 2: reg))
145 #endif
146
147 #ifndef __BUS_SPACE_HAS_STREAM_METHODS
148 #define bus_space_write_stream_2 bus_space_write_2
149 #define bus_space_write_multi_stream_2 bus_space_write_multi_2
150 #define bus_space_read_stream_2 bus_space_read_2
151 #define bus_space_read_multi_stream_2 bus_space_read_multi_2
152 #endif
153
154 #define CSR_WRITE_STREAM_2(sc, reg, val) \
155 bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \
156 (sc->sc_pci? reg * 2: reg), val)
157 #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
158 bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \
159 (sc->sc_pci? reg * 2: reg), val, count)
160 #define CSR_READ_STREAM_2(sc, reg) \
161 bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \
162 (sc->sc_pci? reg * 2: reg))
163 #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \
164 bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \
165 (sc->sc_pci? reg * 2: reg), buf, count)
166
167 /*
168 * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
169 * calls 'Hermes.' In typical fashion, getting documentation about this
170 * controller is about as easy as squeezing blood from a stone. Here
171 * is more or less what I know:
172 *
173 * - The Hermes controller is firmware driven, and the host interacts
174 * with the Hermes via a firmware interface, which can change.
175 *
176 * - The Hermes is described in a document called: "Hermes Firmware
177 * WaveLAN/IEEE Station Functions," document #010245, which of course
178 * Lucent will not release without an NDA.
179 *
180 * - Lucent has created a library called HCF (Hardware Control Functions)
181 * though which it wants developers to interact with the card. The HCF
182 * is needlessly complex, ill conceived and badly documented. Actually,
183 * the comments in the HCP code itself aren't bad, but the publically
184 * available manual that comes with it is awful, probably due largely to
185 * the fact that it has been emasculated in order to hide information
186 * that Lucent wants to keep proprietary. The purpose of the HCF seems
187 * to be to insulate the driver programmer from the Hermes itself so that
188 * Lucent has an excuse not to release programming in for it.
189 *
190 * - Lucent only makes available documentation and code for 'HCF Light'
191 * which is a stripped down version of HCF with certain features not
192 * implemented, most notably support for 802.11 frames.
193 *
194 * - The HCF code which I have seen blows goats. Whoever decided to
195 * use a 132 column format should be shot.
196 *
197 * Rather than actually use the Lucent HCF library, I have stripped all
198 * the useful information from it and used it to create a driver in the
199 * usual BSD form. Note: I don't want to hear anybody whining about the
200 * fact that the Lucent code is GPLed and mine isn't. I did not actually
201 * put any of Lucent's code in this driver: I only used it as a reference
202 * to obtain information about the underlying hardware. The Hermes
203 * programming interface is not GPLed, so bite me.
204 */
205
206 /*
207 * Size of Hermes & Prism2 I/O space.
208 */
209 #define WI_IOSIZE 0x40
210 #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */
211
212 /*
213 * Hermes & Prism2 register definitions
214 */
215
216 /* Hermes command/status registers. */
217 #define WI_COMMAND 0x00
218 #define WI_PARAM0 0x02
219 #define WI_PARAM1 0x04
220 #define WI_PARAM2 0x06
221 #define WI_STATUS 0x08
222 #define WI_RESP0 0x0A
223 #define WI_RESP1 0x0C
224 #define WI_RESP2 0x0E
225
226 /* Command register values. */
227 #define WI_CMD_BUSY 0x8000 /* busy bit */
228 #define WI_CMD_INI 0x0000 /* initialize */
229 #define WI_CMD_ENABLE 0x0001 /* enable */
230 #define WI_CMD_DISABLE 0x0002 /* disable */
231 #define WI_CMD_DIAG 0x0003
232 #define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
233 #define WI_CMD_TX 0x000B /* transmit */
234 #define WI_CMD_NOTIFY 0x0010
235 #define WI_CMD_INQUIRE 0x0011
236 #define WI_CMD_ACCESS 0x0021
237 #define WI_CMD_PROGRAM 0x0022
238
239 #define WI_CMD_CODE_MASK 0x003F
240
241 /*
242 * Reclaim qualifier bit, applicable to the
243 * TX and INQUIRE commands.
244 */
245 #define WI_RECLAIM 0x0100 /* reclaim NIC memory */
246
247 /*
248 * ACCESS command qualifier bits.
249 */
250 #define WI_ACCESS_READ 0x0000
251 #define WI_ACCESS_WRITE 0x0100
252
253 /*
254 * PROGRAM command qualifier bits.
255 */
256 #define WI_PROGRAM_DISABLE 0x0000
257 #define WI_PROGRAM_ENABLE_RAM 0x0100
258 #define WI_PROGRAM_ENABLE_NVRAM 0x0200
259 #define WI_PROGRAM_NVRAM 0x0300
260
261 /* Status register values */
262 #define WI_STAT_CMD_CODE 0x003F
263 #define WI_STAT_DIAG_ERR 0x0100
264 #define WI_STAT_INQ_ERR 0x0500
265 #define WI_STAT_CMD_RESULT 0x7F00
266
267 /* memory handle management registers */
268 #define WI_INFO_FID 0x10
269 #define WI_RX_FID 0x20
270 #define WI_ALLOC_FID 0x22
271 #define WI_TX_CMP_FID 0x24
272
273 /*
274 * Buffer Access Path (BAP) registers.
275 * These are I/O channels. I believe you can use each one for
276 * any desired purpose independently of the other. In general
277 * though, we use BAP1 for reading and writing LTV records and
278 * reading received data frames, and BAP0 for writing transmit
279 * frames. This is a convention though, not a rule.
280 */
281 #define WI_SEL0 0x18
282 #define WI_SEL1 0x1A
283 #define WI_OFF0 0x1C
284 #define WI_OFF1 0x1E
285 #define WI_DATA0 0x36
286 #define WI_DATA1 0x38
287 #define WI_BAP0 WI_DATA0
288 #define WI_BAP1 WI_DATA1
289
290 #define WI_OFF_BUSY 0x8000
291 #define WI_OFF_ERR 0x4000
292 #define WI_OFF_DATAOFF 0x0FFF
293
294 /* Event registers */
295 #define WI_EVENT_STAT 0x30 /* Event status */
296 #define WI_INT_EN 0x32 /* Interrupt enable/disable */
297 #define WI_EVENT_ACK 0x34 /* Ack event */
298
299 /* Events */
300 #define WI_EV_TICK 0x8000 /* aux timer tick */
301 #define WI_EV_RES 0x4000 /* controller h/w error (time out) */
302 #define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */
303 #define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */
304 #define WI_EV_DUIF_RX 0x0400 /* wavelan management packet received */
305 #define WI_EV_INFO 0x0080 /* async info frame */
306 #define WI_EV_CMD 0x0010 /* command completed */
307 #define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
308 #define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */
309 #define WI_EV_TX 0x0002 /* async xmit completed succesfully */
310 #define WI_EV_RX 0x0001 /* async rx completed */
311
312 #define WI_INTRS \
313 (WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP)
314
315 /* Host software registers */
316 #define WI_SW0 0x28
317 #define WI_SW1 0x2A
318 #define WI_SW2 0x2C
319 #define WI_SW3 0x2E /* does not appear in Prism2 */
320
321 #define WI_CNTL 0x14
322
323 #define WI_CNTL_AUX_ENA 0xC000
324 #define WI_CNTL_AUX_ENA_STAT 0xC000
325 #define WI_CNTL_AUX_DIS_STAT 0x0000
326 #define WI_CNTL_AUX_ENA_CNTL 0x8000
327 #define WI_CNTL_AUX_DIS_CNTL 0x4000
328
329 #define WI_AUX_PAGE 0x3A
330 #define WI_AUX_OFFSET 0x3C
331 #define WI_AUX_DATA 0x3E
332
333 /*
334 * PCI Host Interface Registers (HFA3842 Specific)
335 * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0,
336 * has doubled.
337 * About WI_PCI_COR: In this Register, only soft-reset bit implement; Bit(7).
338 */
339 #define WI_PCI_COR 0x4C
340 #define WI_PCI_HCR 0x5C
341 #define WI_PCI_MASTER0_ADDRH 0x80
342 #define WI_PCI_MASTER0_ADDRL 0x84
343 #define WI_PCI_MASTER0_LEN 0x88
344 #define WI_PCI_MASTER0_CON 0x8C
345
346 #define WI_PCI_STATUS 0x98
347
348 #define WI_PCI_MASTER1_ADDRH 0xA0
349 #define WI_PCI_MASTER1_ADDRL 0xA4
350 #define WI_PCI_MASTER1_LEN 0xA8
351 #define WI_PCI_MASTER1_CON 0xAC
352
353 #define WI_PCI_SOFT_RESET (1 << 7)
354
355 /*
356 * One form of communication with the Hermes is with what Lucent calls
357 * LTV records, where LTV stands for Length, Type and Value. The length
358 * and type are 16 bits and are in native byte order. The value is in
359 * multiples of 16 bits and is in little endian byte order.
360 */
361 struct wi_ltv_gen {
362 u_int16_t wi_len;
363 u_int16_t wi_type;
364 u_int16_t wi_val;
365 };
366
367 struct wi_ltv_str {
368 u_int16_t wi_len;
369 u_int16_t wi_type;
370 u_int16_t wi_str[17];
371 };
372
373 #define WI_SETVAL(recno, val) \
374 do { \
375 struct wi_ltv_gen g; \
376 \
377 g.wi_len = 2; \
378 g.wi_type = recno; \
379 g.wi_val = htole16(val); \
380 wi_write_record(sc, &g); \
381 } while (0)
382
383 #define WI_SETSTR(recno, str) \
384 do { \
385 struct wi_ltv_str s; \
386 int l; \
387 \
388 l = (strlen(str) + 1) & ~0x1; \
389 memset((char *)&s, 0, sizeof(s)); \
390 s.wi_len = (l / 2) + 2; \
391 s.wi_type = recno; \
392 s.wi_str[0] = htole16(strlen(str)); \
393 memcpy((char *)&s.wi_str[1], str, strlen(str)); \
394 wi_write_record(sc, (struct wi_ltv_gen *)&s); \
395 } while (0)
396
397 /*
398 * Download buffer location and length (0xFD01).
399 */
400 struct wi_ltv_dnld_buf {
401 u_int16_t wi_len;
402 u_int16_t wi_type;
403 u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/
404 u_int16_t wi_buf_off; /* offset of idb */
405 u_int16_t wi_buf_len; /* len of idb */
406 };
407
408 /*
409 * Mem sizes (0xFD02).
410 */
411 struct wi_ltv_memsz {
412 u_int16_t wi_len;
413 u_int16_t wi_type;
414 u_int16_t wi_mem_ram;
415 u_int16_t wi_mem_nvram;
416 };
417
418 /*
419 * NIC Identification (0xFD0B, 0xFD20)
420 */
421 struct wi_ltv_ver {
422 u_int16_t wi_len;
423 u_int16_t wi_type;
424 u_int16_t wi_ver[4];
425 };
426
427 /* define card ident */
428 /* Lucent */
429 #define WI_NIC_LUCENT_ID 0x0001
430 #define WI_NIC_LUCENT_STR "Lucent Technologies, WaveLAN/IEEE"
431
432 #define WI_NIC_SONY_ID 0x0002
433 #define WI_NIC_SONY_STR "Sony WaveLAN/IEEE"
434
435 #define WI_NIC_LUCENT_EMB_ID 0x0005
436 #define WI_NIC_LUCENT_EMB_STR "Lucent Embedded WaveLAN/IEEE"
437
438 /* Intersil */
439 #define WI_NIC_EVB2_ID 0x8000
440 #define WI_NIC_EVB2_STR "RF:PRISM2 MAC:HFA3841"
441
442 #define WI_NIC_HWB3763_ID 0x8001
443 #define WI_NIC_HWB3763_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3763 rev.B"
444
445 #define WI_NIC_HWB3163_ID 0x8002
446 #define WI_NIC_HWB3163_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.A"
447
448 #define WI_NIC_HWB3163B_ID 0x8003
449 #define WI_NIC_HWB3163B_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.B"
450
451 #define WI_NIC_EVB3_ID 0x8004
452 #define WI_NIC_EVB3_STR "RF:PRISM2 MAC:HFA3842 CARD:HFA3842 EVAL"
453
454 #define WI_NIC_HWB1153_ID 0x8007
455 #define WI_NIC_HWB1153_STR "RF:PRISM1 MAC:HFA3841 CARD:HWB1153"
456
457 #define WI_NIC_P2_SST_ID 0x8008 /* Prism2 with SST flush */
458 #define WI_NIC_P2_SST_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash"
459
460 #define WI_NIC_EVB2_SST_ID 0x8009
461 #define WI_NIC_EVB2_SST_STR "RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash"
462
463 #define WI_NIC_3842_EVA_ID 0x800A /* Prism2 3842 Evaluation Board */
464 #define WI_NIC_3842_EVA_STR "RF:PRISM2 MAC:HFA3842 CARD:HFA3842 EVAL"
465
466 #define WI_NIC_3842_PCMCIA_AMD_ID 0x800B /* Prism2.5 PCMCIA */
467 #define WI_NIC_3842_PCMCIA_SST_ID 0x800C
468 #define WI_NIC_3842_PCMCIA_ATM_ID 0x800D
469 #define WI_NIC_3842_PCMCIA_STR "RF:PRISM2.5 MAC:ISL3873B(PCMCIA)"
470
471 #define WI_NIC_3842_MINI_AMD_ID 0x8012 /* Prism2.5 Mini-PCI */
472 #define WI_NIC_3842_MINI_SST_ID 0x8013
473 #define WI_NIC_3842_MINI_ATM_ID 0x8014
474 #define WI_NIC_3842_MINI_STR "RF:PRISM2.5 MAC:ISL3874A(Mini-PCI)"
475
476 #define WI_NIC_3842_PCI_AMD_ID 0x8016 /* Prism2.5 PCI-bridge */
477 #define WI_NIC_3842_PCI_SST_ID 0x8017
478 #define WI_NIC_3842_PCI_ATM_ID 0x8018
479 #define WI_NIC_3842_PCI_STR "RF:PRISM2.5 MAC:ISL3874A(PCI-bridge)"
480
481 #define WI_NIC_P3_PCMCIA_AMD_ID 0x801A /* Prism3 PCMCIA */
482 #define WI_NIC_P3_PCMCIA_SST_ID 0x801B
483 #define WI_NIC_P3_PCMCIA_STR "RF:PRISM3 MAC:ISL3871(PCMCIA)"
484
485 #define WI_NIC_P3_MINI_AMD_ID 0x8021 /* Prism3 Mini-PCI */
486 #define WI_NIC_P3_MINI_SST_ID 0x8022
487 #define WI_NIC_P3_MINI_STR "RF:PRISM3 MAC:ISL3871(Mini-PCI)"
488
489 /*
490 * List of intended regulatory domains (0xFD11).
491 */
492 struct wi_ltv_domains {
493 u_int16_t wi_len;
494 u_int16_t wi_type;
495 u_int16_t wi_domains[6];
496 };
497
498 /*
499 * CIS struct (0xFD13).
500 */
501 struct wi_ltv_cis {
502 u_int16_t wi_len;
503 u_int16_t wi_type;
504 u_int16_t wi_cis[240];
505 };
506
507 /*
508 * Communications quality (0xFD43).
509 */
510 struct wi_ltv_commqual {
511 u_int16_t wi_len;
512 u_int16_t wi_type;
513 u_int16_t wi_coms_qual;
514 u_int16_t wi_sig_lvl;
515 u_int16_t wi_noise_lvl;
516 };
517
518 /*
519 * Actual system scale thresholds (0xFC06, 0xFD46).
520 */
521 struct wi_ltv_scalethresh {
522 u_int16_t wi_len;
523 u_int16_t wi_type;
524 u_int16_t wi_energy_detect;
525 u_int16_t wi_carrier_detect;
526 u_int16_t wi_defer;
527 u_int16_t wi_cell_search;
528 u_int16_t wi_out_of_range;
529 u_int16_t wi_delta_snr;
530 };
531
532 /*
533 * PCF info struct (0xFD87).
534 */
535 struct wi_ltv_pcf {
536 u_int16_t wi_len;
537 u_int16_t wi_type;
538 u_int16_t wi_medium_occupancy_limit;
539 u_int16_t wi_cfp_period;
540 u_int16_t wi_cfp_max_duration;
541 };
542
543 /*
544 * Connection control characteristics. (0xFC00)
545 * 0 == IBSS (802.11 compliant mode) (Only PRISM2)
546 * 1 == Basic Service Set (BSS)
547 * 2 == Wireless Distribudion System (WDS)
548 * 3 == Pseudo IBSS
549 * (Only PRISM2; not 802.11 compliant mode, testing use only)
550 * 6 == HOST AP (Only PRISM2)
551 */
552 #define WI_PORTTYPE_BSS 0x1
553 #define WI_PORTTYPE_WDS 0x2
554 #define WI_PORTTYPE_ADHOC 0x3
555
556 /*
557 * Mac addresses. (0xFC01, 0xFC08)
558 */
559 struct wi_ltv_macaddr {
560 u_int16_t wi_len;
561 u_int16_t wi_type;
562 u_int8_t wi_mac_addr[6];
563 };
564
565 /*
566 * Station set identification (SSID). (0xFC02, 0xFC04)
567 */
568 struct wi_ltv_ssid {
569 u_int16_t wi_len;
570 u_int16_t wi_type;
571 u_int16_t wi_id[17];
572 };
573
574 /*
575 * Set our station name. (0xFC0E)
576 */
577 struct wi_ltv_nodename {
578 u_int16_t wi_len;
579 u_int16_t wi_type;
580 u_int16_t wi_nodename[17];
581 };
582
583 /*
584 * Multicast addresses to be put in filter. We're
585 * allowed up to 16 addresses in the filter. (0xFC80)
586 */
587 struct wi_ltv_mcast {
588 u_int16_t wi_len;
589 u_int16_t wi_type;
590 struct ether_addr wi_mcast[16];
591 };
592
593 /*
594 * Information frame types.
595 */
596 #define WI_INFO_NOTIFY 0xF000 /* Handover address */
597 #define WI_INFO_COUNTERS 0xF100 /* Statistics counters */
598 #define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */
599 #define WI_INFO_LINK_STAT 0xF200 /* Link status */
600 #define WI_INFO_ASSOC_STAT 0xF201 /* Association status */
601 struct wi_assoc {
602 u_int16_t wi_assoc_stat; /* Association Status */
603 #define ASSOC 1
604 #define REASSOC 2
605 #define DISASSOC 3
606 #define ASSOCFAIL 4
607 #define AUTHFAIL 5
608 u_int8_t wi_assoc_sta[6]; /* Station Address */
609 u_int8_t wi_assoc_osta[6]; /* OLD Station Address */
610 u_int16_t wi_assoc_reason; /* Reason */
611 u_int16_t wi_assoc_reserve; /* Reserved */
612 };
613
614 #define WI_INFO_AUTH_REQUEST 0xF202 /* Authentication Request (AP) */
615 #define WI_INFO_POWERSAVE_COUNT 0xF203 /* PowerSave User Count (AP) */
616
617 /*
618 * Scan Results of Prism2 chip
619 */
620
621 #define MAXAPINFO 30
622 struct wi_scan_header {
623 u_int16_t wi_reserve; /* future use */
624 u_int16_t wi_reason; /* The reason this scan was initiated
625 1: Host initiated
626 2: Firmware initiated
627 3: Inquiry request from host */
628 };
629
630 struct wi_scan_data_p2 {
631 u_int16_t wi_chid; /* BSS Channel ID from Probe Res.(PR)*/
632 u_int16_t wi_noise; /* Average Noise Level of the PR */
633 u_int16_t wi_signal; /* Signal Level on the PR */
634 u_int8_t wi_bssid[6]; /* MACaddress of BSS responder from PR */
635 u_int16_t wi_interval; /* BSS beacon interval */
636 u_int16_t wi_capinfo; /* BSS Capability Information
637 IEEE Std 802.11(1997) ,see 7.3.1.4 */
638 u_int16_t wi_namelen; /* Length of SSID strings */
639 u_int8_t wi_name[32]; /* SSID strings */
640 u_int16_t wi_suprate[5]; /* Supported Rates element from the PR
641 IEEE Std 802.11(1997) ,see 7.3.2.2 */
642 u_int16_t wi_rate; /* Data rate of the PR */
643 #define WI_APRATE_1 0x0A /* 1 Mbps */
644 #define WI_APRATE_2 0x14 /* 2 Mbps */
645 #define WI_APRATE_5 0x37 /* 5.5 Mbps */
646 #define WI_APRATE_11 0x6E /* 11 Mbps */
647 };
648
649 /*
650 * Scan Results of Lucent chip
651 */
652 struct wi_scan_data {
653 u_int16_t wi_chid; /* BSS Channel ID from PR */
654 u_int16_t wi_noise; /* Average Noise Level of the PR */
655 u_int16_t wi_signal; /* Signal Level on the PR */
656 u_int8_t wi_bssid[6]; /* MACaddress of BSS responder from PR */
657 u_int16_t wi_interval; /* BSS beacon interval */
658 u_int16_t wi_capinfo; /* BSS Capability Information
659 IEEE Std 802.11(1997) ,see 7.3.1.4 */
660 u_int16_t wi_namelen; /* Length of SSID strings */
661 u_int8_t wi_name[32]; /* SSID strings */
662 };
663
664 /*
665 * transmit/receive frame structure
666 */
667 struct wi_frame {
668 u_int16_t wi_status; /* 0x00 */
669 u_int16_t wi_rsvd0; /* 0x02 */ /* 0 */
670 u_int16_t wi_rsvd1; /* 0x04 */ /* 0 */
671 u_int16_t wi_q_info; /* 0x06 */
672 u_int16_t wi_txrate; /* 0x08 */ /* (Prism2 Only) */
673 u_int16_t wi_retcount; /* 0x0A */ /* (Prism2 Only) */
674 u_int16_t wi_tx_ctl; /* 0x0C */
675 u_int16_t wi_frame_ctl; /* 0x0E */
676 u_int16_t wi_id; /* 0x10 */
677 u_int8_t wi_addr1[6]; /* 0x12 */
678 u_int8_t wi_addr2[6]; /* 0x18 */
679 u_int8_t wi_addr3[6]; /* 0x1E */
680 u_int16_t wi_seq_ctl; /* 0x24 */
681 u_int8_t wi_addr4[6]; /* 0x26 */
682 u_int16_t wi_dat_len; /* 0x2C */
683 u_int8_t wi_dst_addr[6]; /* 0x2E */
684 u_int8_t wi_src_addr[6]; /* 0x34 */
685 u_int16_t wi_len; /* 0x3A */
686 u_int16_t wi_dat[3]; /* 0x3C */ /* SNAP header */
687 u_int16_t wi_type; /* 0x42 */
688 };
689
690 #define WI_802_3_OFFSET 0x2E
691 #define WI_802_11_OFFSET 0x44
692 #define WI_802_11_OFFSET_RAW 0x3C
693 #define WI_802_11_OFFSET_HDR 0x0E
694
695 /* Tx Status Field */
696 #define WI_TXSTAT_RET_ERR 0x0001
697 #define WI_TXSTAT_AGED_ERR 0x0002
698 #define WI_TXSTAT_DISCONNECT 0x0004
699 #define WI_TXSTAT_FORM_ERR 0x0008
700
701 /* Rx Status Field */
702 #define WI_STAT_BADCRC 0x0001
703 #define WI_STAT_UNDECRYPTABLE 0x0002
704 #define WI_STAT_ERRSTAT 0x0003
705 #define WI_STAT_MAC_PORT 0x0700
706 #define WI_STAT_PCF 0x1000
707 #define WI_RXSTAT_MSG_TYPE 0xE000
708 #define WI_STAT_1042 0x2000 /* RFC1042 encoded */
709 #define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
710 #define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
711 #define WI_STAT_MGMT 0x8000 /* 802.11b management frames */
712
713 #define WI_ENC_TX_MGMT 0x08
714 #define WI_ENC_TX_E_II 0x0E
715
716 #define WI_ENC_TX_1042 0x00
717 #define WI_ENC_TX_TUNNEL 0xF8
718
719 /* TxControl Field (enhanced) */
720 #define WI_TXCNTL_TX_OK 0x0002
721 #define WI_TXCNTL_TX_EX 0x0004
722 #define WI_TXCNTL_STRUCT_TYPE 0x0018
723 #define WI_ENC_TX_802_3 0x00
724 #define WI_ENC_TX_802_11 0x11
725 #define WI_TXCNTL_ALTRTRY 0x0020
726 #define WI_TXCNTL_NOCRYPT 0x0080
727
728 /*
729 * SNAP (sub-network access protocol) constants for transmission
730 * of IP datagrams over IEEE 802 networks, taken from RFC1042.
731 * We need these for the LLC/SNAP header fields in the TX/RX frame
732 * structure.
733 */
734 #define WI_SNAP_K1 0xaa /* assigned global SAP for SNAP */
735 #define WI_SNAP_K2 0x00
736 #define WI_SNAP_CONTROL 0x03 /* unnumbered information format */
737 #define WI_SNAP_WORD0 (WI_SNAP_K1 | (WI_SNAP_K1 << 8))
738 #define WI_SNAP_WORD1 (WI_SNAP_K2 | (WI_SNAP_CONTROL << 8))
739 #define WI_SNAPHDR_LEN 0x6
740