wivar.h revision 1.23
1 /* $NetBSD: wivar.h,v 1.23 2002/10/04 04:23:23 onoe Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the 37 * Oslo IETF plenary meeting. 38 */ 39 struct wi_softc { 40 struct device sc_dev; 41 struct ieee80211com sc_ic; 42 void *sc_ih; /* interrupt handler */ 43 int (*sc_enable)(struct wi_softc *); 44 void (*sc_disable)(struct wi_softc *); 45 46 int sc_attached; 47 int sc_enabled; 48 int sc_firmware_type; 49 #define WI_NOTYPE 0 50 #define WI_LUCENT 1 51 #define WI_INTERSIL 2 52 #define WI_SYMBOL 3 53 int sc_pri_firmware_ver; /* Primary firm vers */ 54 int sc_sta_firmware_ver; /* Station firm vers */ 55 int sc_pci; /* attach to PCI-Bus */ 56 57 bus_space_tag_t sc_iot; /* bus cookie */ 58 bus_space_handle_t sc_ioh; /* bus i/o handle */ 59 60 struct ifmedia sc_media; 61 caddr_t sc_drvbpf; 62 int sc_flags; 63 int sc_bap_id; 64 int sc_bap_off; 65 66 u_int16_t sc_max_datalen; 67 u_int16_t sc_rts_thresh; 68 u_int16_t sc_system_scale; 69 u_int16_t sc_tx_rate; 70 u_int16_t sc_cnfauthmode; 71 u_int16_t sc_roaming_mode; 72 u_int16_t sc_microwave_oven; 73 74 int sc_nodelen; 75 char sc_nodename[IEEE80211_NWID_LEN]; 76 77 int sc_buflen; 78 #define WI_NTXBUF 3 79 struct sc_txdesc { 80 int d_fid; 81 int d_len; 82 } sc_txd[WI_NTXBUF]; 83 int sc_txnext; 84 int sc_txcur; 85 int sc_tx_timer; 86 int sc_scan_timer; 87 88 struct wi_counters sc_stats; 89 u_int16_t sc_ibss_port; 90 91 struct wi_apinfo sc_aps[MAXAPINFO]; 92 int sc_naps; 93 }; 94 95 #define sc_if sc_ic.ic_if 96 97 #define WI_SCAN_INQWAIT 3 /* wait sec before inquire */ 98 #define WI_SCAN_WAIT 5 /* maximum scan wait */ 99 100 /* Values for wi_flags. */ 101 #define WI_FLAGS_ATTACHED 0x0001 102 #define WI_FLAGS_INITIALIZED 0x0002 103 #define WI_FLAGS_OUTRANGE 0x0004 104 #define WI_FLAGS_HAS_MOR 0x0010 105 #define WI_FLAGS_HAS_ROAMING 0x0020 106 #define WI_FLAGS_HAS_DIVERSITY 0x0040 107 #define WI_FLAGS_HAS_SYSSCALE 0x0080 108 #define WI_FLAGS_BUG_AUTOINC 0x0100 109 110 struct wi_card_ident { 111 u_int16_t card_id; 112 char *card_name; 113 u_int8_t firm_type; 114 }; 115 116 /* 117 * register space access macros 118 */ 119 #ifdef WI_AT_BIGENDIAN_BUS_HACK 120 /* 121 * XXX - ugly hack for sparc bus_space_* macro deficiencies: 122 * assume the bus we are accessing is big endian. 123 */ 124 125 #define CSR_WRITE_4(sc, reg, val) \ 126 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 127 (sc->sc_pci? reg * 2: reg) , htole32(val)) 128 #define CSR_WRITE_2(sc, reg, val) \ 129 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 130 (sc->sc_pci? reg * 2: reg), htole16(val)) 131 #define CSR_WRITE_1(sc, reg, val) \ 132 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 133 (sc->sc_pci? reg * 2: reg), val) 134 135 #define CSR_READ_4(sc, reg) \ 136 le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 137 (sc->sc_pci? reg * 2: reg))) 138 #define CSR_READ_2(sc, reg) \ 139 le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 140 (sc->sc_pci? reg * 2: reg))) 141 #define CSR_READ_1(sc, reg) \ 142 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 143 (sc->sc_pci? reg * 2: reg)) 144 145 #else 146 147 #define CSR_WRITE_4(sc, reg, val) \ 148 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 149 (sc->sc_pci? reg * 2: reg) , val) 150 #define CSR_WRITE_2(sc, reg, val) \ 151 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 152 (sc->sc_pci? reg * 2: reg), val) 153 #define CSR_WRITE_1(sc, reg, val) \ 154 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 155 (sc->sc_pci? reg * 2: reg), val) 156 157 #define CSR_READ_4(sc, reg) \ 158 bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 159 (sc->sc_pci? reg * 2: reg)) 160 #define CSR_READ_2(sc, reg) \ 161 bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 162 (sc->sc_pci? reg * 2: reg)) 163 #define CSR_READ_1(sc, reg) \ 164 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 165 (sc->sc_pci? reg * 2: reg)) 166 #endif 167 168 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 169 #define bus_space_write_stream_2 bus_space_write_2 170 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 171 #define bus_space_read_stream_2 bus_space_read_2 172 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 173 #endif 174 175 #define CSR_WRITE_STREAM_2(sc, reg, val) \ 176 bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \ 177 (sc->sc_pci? reg * 2: reg), val) 178 #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \ 179 bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 180 (sc->sc_pci? reg * 2: reg), val, count) 181 #define CSR_READ_STREAM_2(sc, reg) \ 182 bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \ 183 (sc->sc_pci? reg * 2: reg)) 184 #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \ 185 bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 186 (sc->sc_pci? reg * 2: reg), buf, count) 187 188 189 int wi_attach(struct wi_softc *); 190 int wi_detach(struct wi_softc *); 191 int wi_activate(struct device *, enum devact); 192 int wi_intr(void *arg); 193 void wi_power(struct wi_softc *, int); 194 void wi_shutdown(struct wi_softc *); 195
Indexes created Sun Sep 28 07:09:56 GMT 2025