wivar.h revision 1.35
1 /* $NetBSD: wivar.h,v 1.35 2003/07/06 07:15:56 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the 37 * Oslo IETF plenary meeting. 38 */ 39 struct wi_softc { 40 struct device sc_dev; 41 struct ieee80211com sc_ic; 42 void *sc_ih; /* interrupt handler */ 43 int (*sc_enable)(struct wi_softc *); 44 void (*sc_disable)(struct wi_softc *); 45 void (*sc_reset)(struct wi_softc *); 46 47 int sc_attached; 48 int sc_enabled; 49 int sc_invalid; 50 int sc_firmware_type; 51 #define WI_NOTYPE 0 52 #define WI_LUCENT 1 53 #define WI_INTERSIL 2 54 #define WI_SYMBOL 3 55 int sc_pri_firmware_ver; /* Primary firm vers */ 56 int sc_sta_firmware_ver; /* Station firm vers */ 57 int sc_pci; /* attach to PCI-Bus */ 58 59 bus_space_tag_t sc_iot; /* bus cookie */ 60 bus_space_handle_t sc_ioh; /* bus i/o handle */ 61 62 struct ifmedia sc_media; 63 caddr_t sc_drvbpf; 64 int sc_flags; 65 int sc_bap_id; 66 int sc_bap_off; 67 68 u_int16_t sc_portnum; 69 70 /* RSSI interpretation */ 71 u_int16_t sc_min_rssi; /* clamp sc_min_rssi < RSSI */ 72 u_int16_t sc_max_rssi; /* clamp RSSI < sc_max_rssi */ 73 u_int16_t sc_dbm_offset; /* dBm ~ RSSI - sc_dbm_offset */ 74 u_int16_t sc_max_datalen; 75 u_int16_t sc_frag_thresh; 76 u_int16_t sc_rts_thresh; 77 u_int16_t sc_system_scale; 78 u_int16_t sc_tx_rate; 79 u_int16_t sc_cnfauthmode; 80 u_int16_t sc_roaming_mode; 81 u_int16_t sc_microwave_oven; 82 83 int sc_nodelen; 84 char sc_nodename[IEEE80211_NWID_LEN]; 85 86 int sc_buflen; 87 #define WI_NTXBUF 3 88 struct sc_txdesc { 89 int d_fid; 90 int d_len; 91 } sc_txd[WI_NTXBUF]; 92 int sc_txnext; 93 int sc_txcur; 94 int sc_tx_timer; 95 int sc_scan_timer; 96 int sc_syn_timer; 97 98 struct wi_counters sc_stats; 99 u_int16_t sc_ibss_port; 100 101 struct wi_apinfo sc_aps[MAXAPINFO]; 102 int sc_naps; 103 104 int sc_false_syns; 105 106 u_int16_t sc_txbuf[IEEE80211_MAX_LEN/2]; 107 }; 108 109 #define sc_if sc_ic.ic_if 110 111 /* maximum consecutive false change-of-BSSID indications */ 112 #define WI_MAX_FALSE_SYNS 10 113 114 #define WI_PRISM_MIN_RSSI 0x1b 115 #define WI_PRISM_MAX_RSSI 0x9a 116 #define WI_PRISM_DBM_OFFSET 100 /* XXX */ 117 118 #define WI_LUCENT_MIN_RSSI 47 119 #define WI_LUCENT_MAX_RSSI 138 120 #define WI_LUCENT_DBM_OFFSET 149 121 122 #define WI_RSSI_TO_DBM(sc, rssi) (MIN((sc)->sc_max_rssi, \ 123 MAX((sc)->sc_min_rssi, (rssi))) - (sc)->sc_dbm_offset) 124 125 #define WI_SCAN_INQWAIT 3 /* wait sec before inquire */ 126 #define WI_SCAN_WAIT 5 /* maximum scan wait */ 127 128 /* Values for wi_flags. */ 129 #define WI_FLAGS_ATTACHED 0x0001 130 #define WI_FLAGS_INITIALIZED 0x0002 131 #define WI_FLAGS_OUTRANGE 0x0004 132 #define WI_FLAGS_HAS_MOR 0x0010 133 #define WI_FLAGS_HAS_ROAMING 0x0020 134 #define WI_FLAGS_HAS_DIVERSITY 0x0040 135 #define WI_FLAGS_HAS_SYSSCALE 0x0080 136 #define WI_FLAGS_BUG_AUTOINC 0x0100 137 #define WI_FLAGS_HAS_FRAGTHR 0x0200 138 #define WI_FLAGS_HAS_DBMADJUST 0x0400 139 140 struct wi_card_ident { 141 u_int16_t card_id; 142 char *card_name; 143 u_int8_t firm_type; 144 }; 145 146 /* 147 * register space access macros 148 */ 149 #ifdef WI_AT_BIGENDIAN_BUS_HACK 150 /* 151 * XXX - ugly hack for sparc bus_space_* macro deficiencies: 152 * assume the bus we are accessing is big endian. 153 */ 154 155 #define CSR_WRITE_4(sc, reg, val) \ 156 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 157 (sc->sc_pci? reg * 2: reg) , htole32(val)) 158 #define CSR_WRITE_2(sc, reg, val) \ 159 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 160 (sc->sc_pci? reg * 2: reg), htole16(val)) 161 #define CSR_WRITE_1(sc, reg, val) \ 162 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 163 (sc->sc_pci? reg * 2: reg), val) 164 165 #define CSR_READ_4(sc, reg) \ 166 le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 167 (sc->sc_pci? reg * 2: reg))) 168 #define CSR_READ_2(sc, reg) \ 169 le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 170 (sc->sc_pci? reg * 2: reg))) 171 #define CSR_READ_1(sc, reg) \ 172 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 173 (sc->sc_pci? reg * 2: reg)) 174 175 #else 176 177 #define CSR_WRITE_4(sc, reg, val) \ 178 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 179 (sc->sc_pci? reg * 2: reg) , val) 180 #define CSR_WRITE_2(sc, reg, val) \ 181 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 182 (sc->sc_pci? reg * 2: reg), val) 183 #define CSR_WRITE_1(sc, reg, val) \ 184 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 185 (sc->sc_pci? reg * 2: reg), val) 186 187 #define CSR_READ_4(sc, reg) \ 188 bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 189 (sc->sc_pci? reg * 2: reg)) 190 #define CSR_READ_2(sc, reg) \ 191 bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 192 (sc->sc_pci? reg * 2: reg)) 193 #define CSR_READ_1(sc, reg) \ 194 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 195 (sc->sc_pci? reg * 2: reg)) 196 #endif 197 198 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 199 #define bus_space_write_stream_2 bus_space_write_2 200 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 201 #define bus_space_read_stream_2 bus_space_read_2 202 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 203 #endif 204 205 #define CSR_WRITE_STREAM_2(sc, reg, val) \ 206 bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \ 207 (sc->sc_pci? reg * 2: reg), val) 208 #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \ 209 bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 210 (sc->sc_pci? reg * 2: reg), val, count) 211 #define CSR_READ_STREAM_2(sc, reg) \ 212 bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \ 213 (sc->sc_pci? reg * 2: reg)) 214 #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \ 215 bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 216 (sc->sc_pci? reg * 2: reg), buf, count) 217 218 219 int wi_attach(struct wi_softc *); 220 int wi_detach(struct wi_softc *); 221 int wi_activate(struct device *, enum devact); 222 int wi_intr(void *arg); 223 void wi_power(struct wi_softc *, int); 224 void wi_shutdown(struct wi_softc *); 225
Indexes created Mon Sep 29 21:09:56 GMT 2025