wivar.h revision 1.37
1 /* $NetBSD: wivar.h,v 1.37 2003/10/13 08:07:21 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the 37 * Oslo IETF plenary meeting. 38 */ 39 struct wi_softc { 40 struct device sc_dev; 41 struct ieee80211com sc_ic; 42 void *sc_ih; /* interrupt handler */ 43 int (*sc_enable)(struct wi_softc *); 44 void (*sc_disable)(struct wi_softc *); 45 void (*sc_reset)(struct wi_softc *); 46 47 int (*sc_newstate)(struct ieee80211com *, 48 enum ieee80211_state, int); 49 50 int sc_attached; 51 int sc_enabled; 52 int sc_invalid; 53 int sc_firmware_type; 54 #define WI_NOTYPE 0 55 #define WI_LUCENT 1 56 #define WI_INTERSIL 2 57 #define WI_SYMBOL 3 58 int sc_pri_firmware_ver; /* Primary firm vers */ 59 int sc_sta_firmware_ver; /* Station firm vers */ 60 int sc_pci; /* attach to PCI-Bus */ 61 62 bus_space_tag_t sc_iot; /* bus cookie */ 63 bus_space_handle_t sc_ioh; /* bus i/o handle */ 64 65 caddr_t sc_drvbpf; 66 int sc_flags; 67 int sc_bap_id; 68 int sc_bap_off; 69 70 u_int16_t sc_portnum; 71 72 /* RSSI interpretation */ 73 u_int16_t sc_min_rssi; /* clamp sc_min_rssi < RSSI */ 74 u_int16_t sc_max_rssi; /* clamp RSSI < sc_max_rssi */ 75 u_int16_t sc_dbm_offset; /* dBm ~ RSSI - sc_dbm_offset */ 76 u_int16_t sc_max_datalen; 77 u_int16_t sc_frag_thresh; 78 u_int16_t sc_rts_thresh; 79 u_int16_t sc_system_scale; 80 u_int16_t sc_tx_rate; 81 u_int16_t sc_cnfauthmode; 82 u_int16_t sc_roaming_mode; 83 u_int16_t sc_microwave_oven; 84 85 int sc_nodelen; 86 char sc_nodename[IEEE80211_NWID_LEN]; 87 88 int sc_buflen; 89 #define WI_NTXBUF 3 90 struct sc_txdesc { 91 int d_fid; 92 int d_len; 93 } sc_txd[WI_NTXBUF]; 94 int sc_txnext; 95 int sc_txcur; 96 int sc_tx_timer; 97 int sc_scan_timer; 98 int sc_syn_timer; 99 100 struct wi_counters sc_stats; 101 u_int16_t sc_ibss_port; 102 103 struct wi_apinfo sc_aps[MAXAPINFO]; 104 int sc_naps; 105 106 int sc_false_syns; 107 108 u_int16_t sc_txbuf[IEEE80211_MAX_LEN/2]; 109 }; 110 111 #define sc_if sc_ic.ic_if 112 113 /* maximum consecutive false change-of-BSSID indications */ 114 #define WI_MAX_FALSE_SYNS 10 115 116 #define WI_PRISM_MIN_RSSI 0x1b 117 #define WI_PRISM_MAX_RSSI 0x9a 118 #define WI_PRISM_DBM_OFFSET 100 /* XXX */ 119 120 #define WI_LUCENT_MIN_RSSI 47 121 #define WI_LUCENT_MAX_RSSI 138 122 #define WI_LUCENT_DBM_OFFSET 149 123 124 #define WI_RSSI_TO_DBM(sc, rssi) (MIN((sc)->sc_max_rssi, \ 125 MAX((sc)->sc_min_rssi, (rssi))) - (sc)->sc_dbm_offset) 126 127 #define WI_SCAN_INQWAIT 3 /* wait sec before inquire */ 128 #define WI_SCAN_WAIT 5 /* maximum scan wait */ 129 130 /* Values for wi_flags. */ 131 #define WI_FLAGS_ATTACHED 0x0001 132 #define WI_FLAGS_INITIALIZED 0x0002 133 #define WI_FLAGS_OUTRANGE 0x0004 134 #define WI_FLAGS_HAS_MOR 0x0010 135 #define WI_FLAGS_HAS_ROAMING 0x0020 136 #define WI_FLAGS_HAS_DIVERSITY 0x0040 137 #define WI_FLAGS_HAS_SYSSCALE 0x0080 138 #define WI_FLAGS_BUG_AUTOINC 0x0100 139 #define WI_FLAGS_HAS_FRAGTHR 0x0200 140 #define WI_FLAGS_HAS_DBMADJUST 0x0400 141 142 struct wi_card_ident { 143 u_int16_t card_id; 144 char *card_name; 145 u_int8_t firm_type; 146 }; 147 148 /* 149 * register space access macros 150 */ 151 #ifdef WI_AT_BIGENDIAN_BUS_HACK 152 /* 153 * XXX - ugly hack for sparc bus_space_* macro deficiencies: 154 * assume the bus we are accessing is big endian. 155 */ 156 157 #define CSR_WRITE_4(sc, reg, val) \ 158 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 159 (sc->sc_pci? reg * 2: reg) , htole32(val)) 160 #define CSR_WRITE_2(sc, reg, val) \ 161 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 162 (sc->sc_pci? reg * 2: reg), htole16(val)) 163 #define CSR_WRITE_1(sc, reg, val) \ 164 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 165 (sc->sc_pci? reg * 2: reg), val) 166 167 #define CSR_READ_4(sc, reg) \ 168 le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 169 (sc->sc_pci? reg * 2: reg))) 170 #define CSR_READ_2(sc, reg) \ 171 le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 172 (sc->sc_pci? reg * 2: reg))) 173 #define CSR_READ_1(sc, reg) \ 174 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 175 (sc->sc_pci? reg * 2: reg)) 176 177 #else 178 179 #define CSR_WRITE_4(sc, reg, val) \ 180 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 181 (sc->sc_pci? reg * 2: reg) , val) 182 #define CSR_WRITE_2(sc, reg, val) \ 183 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 184 (sc->sc_pci? reg * 2: reg), val) 185 #define CSR_WRITE_1(sc, reg, val) \ 186 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 187 (sc->sc_pci? reg * 2: reg), val) 188 189 #define CSR_READ_4(sc, reg) \ 190 bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 191 (sc->sc_pci? reg * 2: reg)) 192 #define CSR_READ_2(sc, reg) \ 193 bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 194 (sc->sc_pci? reg * 2: reg)) 195 #define CSR_READ_1(sc, reg) \ 196 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 197 (sc->sc_pci? reg * 2: reg)) 198 #endif 199 200 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 201 #define bus_space_write_stream_2 bus_space_write_2 202 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 203 #define bus_space_read_stream_2 bus_space_read_2 204 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 205 #endif 206 207 #define CSR_WRITE_STREAM_2(sc, reg, val) \ 208 bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \ 209 (sc->sc_pci? reg * 2: reg), val) 210 #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \ 211 bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 212 (sc->sc_pci? reg * 2: reg), val, count) 213 #define CSR_READ_STREAM_2(sc, reg) \ 214 bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \ 215 (sc->sc_pci? reg * 2: reg)) 216 #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \ 217 bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 218 (sc->sc_pci? reg * 2: reg), buf, count) 219 220 221 int wi_attach(struct wi_softc *); 222 int wi_detach(struct wi_softc *); 223 int wi_activate(struct device *, enum devact); 224 int wi_intr(void *arg); 225 void wi_power(struct wi_softc *, int); 226 void wi_shutdown(struct wi_softc *); 227
Indexes created Mon Sep 29 21:09:56 GMT 2025