z8530tty.c revision 1.3 1 1.3 gwr /* $NetBSD: z8530tty.c,v 1.3 1996/02/19 04:34:01 gwr Exp $ */
2 1.1 gwr
3 1.1 gwr /*
4 1.1 gwr * Copyright (c) 1994 Gordon W. Ross
5 1.1 gwr * Copyright (c) 1992, 1993
6 1.1 gwr * The Regents of the University of California. All rights reserved.
7 1.1 gwr *
8 1.1 gwr * This software was developed by the Computer Systems Engineering group
9 1.1 gwr * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 1.1 gwr * contributed to Berkeley.
11 1.1 gwr *
12 1.1 gwr * All advertising materials mentioning features or use of this software
13 1.1 gwr * must display the following acknowledgement:
14 1.1 gwr * This product includes software developed by the University of
15 1.1 gwr * California, Lawrence Berkeley Laboratory.
16 1.1 gwr *
17 1.1 gwr * Redistribution and use in source and binary forms, with or without
18 1.1 gwr * modification, are permitted provided that the following conditions
19 1.1 gwr * are met:
20 1.1 gwr * 1. Redistributions of source code must retain the above copyright
21 1.1 gwr * notice, this list of conditions and the following disclaimer.
22 1.1 gwr * 2. Redistributions in binary form must reproduce the above copyright
23 1.1 gwr * notice, this list of conditions and the following disclaimer in the
24 1.1 gwr * documentation and/or other materials provided with the distribution.
25 1.1 gwr * 3. All advertising materials mentioning features or use of this software
26 1.1 gwr * must display the following acknowledgement:
27 1.1 gwr * This product includes software developed by the University of
28 1.1 gwr * California, Berkeley and its contributors.
29 1.1 gwr * 4. Neither the name of the University nor the names of its contributors
30 1.1 gwr * may be used to endorse or promote products derived from this software
31 1.1 gwr * without specific prior written permission.
32 1.1 gwr *
33 1.1 gwr * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 1.1 gwr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 1.1 gwr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 1.1 gwr * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 1.1 gwr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 1.1 gwr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 1.1 gwr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 1.1 gwr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 1.1 gwr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 1.1 gwr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 1.1 gwr * SUCH DAMAGE.
44 1.1 gwr *
45 1.1 gwr * @(#)zs.c 8.1 (Berkeley) 7/19/93
46 1.1 gwr */
47 1.1 gwr
48 1.1 gwr /*
49 1.1 gwr * Zilog Z8530 Dual UART driver (tty interface)
50 1.1 gwr *
51 1.1 gwr * This is the "slave" driver that will be attached to
52 1.1 gwr * the "zsc" driver for plain "tty" async. serial lines.
53 1.1 gwr */
54 1.1 gwr
55 1.1 gwr #include <sys/param.h>
56 1.1 gwr #include <sys/systm.h>
57 1.1 gwr #include <sys/proc.h>
58 1.1 gwr #include <sys/device.h>
59 1.1 gwr #include <sys/conf.h>
60 1.1 gwr #include <sys/file.h>
61 1.1 gwr #include <sys/ioctl.h>
62 1.1 gwr #include <sys/tty.h>
63 1.1 gwr #include <sys/time.h>
64 1.1 gwr #include <sys/kernel.h>
65 1.1 gwr #include <sys/syslog.h>
66 1.1 gwr
67 1.1 gwr #include <dev/ic/z8530reg.h>
68 1.1 gwr #include <machine/z8530var.h>
69 1.1 gwr
70 1.1 gwr #ifdef KGDB
71 1.1 gwr extern int zs_check_kgdb();
72 1.1 gwr #endif
73 1.1 gwr
74 1.1 gwr /*
75 1.1 gwr * Allow the MD var.h to override the default CFLAG so that
76 1.1 gwr * console messages during boot come out with correct parity.
77 1.1 gwr */
78 1.1 gwr #ifndef ZSTTY_DEF_CFLAG
79 1.1 gwr #define ZSTTY_DEF_CFLAG TTYDEF_CFLAG
80 1.1 gwr #endif
81 1.1 gwr
82 1.1 gwr /*
83 1.1 gwr * How many input characters we can buffer.
84 1.1 gwr * The port-specific var.h may override this.
85 1.1 gwr * Note: must be a power of two!
86 1.1 gwr */
87 1.1 gwr #ifndef ZSTTY_RING_SIZE
88 1.1 gwr #define ZSTTY_RING_SIZE 1024
89 1.1 gwr #endif
90 1.1 gwr #define ZSTTY_RING_MASK (ZSTTY_RING_SIZE-1)
91 1.1 gwr
92 1.1 gwr struct zstty_softc {
93 1.1 gwr struct device zst_dev; /* required first: base device */
94 1.1 gwr struct tty *zst_tty;
95 1.1 gwr struct zs_chanstate *zst_cs;
96 1.1 gwr
97 1.1 gwr int zst_hwflags; /* see z8530var.h */
98 1.1 gwr int zst_swflags; /* TIOCFLAG_SOFTCAR, ... <ttycom.h> */
99 1.1 gwr
100 1.1 gwr /* Flags to communicate with zstty_softint() */
101 1.1 gwr volatile int zst_intr_flags;
102 1.1 gwr #define INTR_RX_OVERRUN 1
103 1.1 gwr #define INTR_TX_EMPTY 2
104 1.1 gwr #define INTR_ST_CHECK 4
105 1.1 gwr
106 1.1 gwr /*
107 1.1 gwr * The transmit byte count and address are used for pseudo-DMA
108 1.1 gwr * output in the hardware interrupt code. PDMA can be suspended
109 1.1 gwr * to get pending changes done; heldtbc is used for this. It can
110 1.1 gwr * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state.
111 1.1 gwr */
112 1.1 gwr int zst_tbc; /* transmit byte count */
113 1.1 gwr caddr_t zst_tba; /* transmit buffer address */
114 1.1 gwr int zst_heldtbc; /* held tbc while xmission stopped */
115 1.1 gwr
116 1.1 gwr /*
117 1.1 gwr * Printing an overrun error message often takes long enough to
118 1.1 gwr * cause another overrun, so we only print one per second.
119 1.1 gwr */
120 1.1 gwr long zst_rotime; /* time of last ring overrun */
121 1.1 gwr long zst_fotime; /* time of last fifo overrun */
122 1.1 gwr
123 1.1 gwr /*
124 1.1 gwr * The receive ring buffer.
125 1.1 gwr */
126 1.1 gwr u_int zst_rbget; /* ring buffer `get' index */
127 1.1 gwr volatile u_int zst_rbput; /* ring buffer `put' index */
128 1.1 gwr u_short zst_rbuf[ZSTTY_RING_SIZE]; /* rr1, data pairs */
129 1.1 gwr };
130 1.1 gwr
131 1.1 gwr
132 1.1 gwr /* Definition of the driver for autoconfig. */
133 1.1 gwr static int zstty_match(struct device *, void *, void *);
134 1.1 gwr static void zstty_attach(struct device *, struct device *, void *);
135 1.1 gwr
136 1.1 gwr struct cfdriver zsttycd = {
137 1.1 gwr NULL, "zstty", zstty_match, zstty_attach,
138 1.1 gwr DV_TTY, sizeof(struct zstty_softc), NULL,
139 1.1 gwr };
140 1.1 gwr
141 1.1 gwr struct zsops zsops_tty;
142 1.1 gwr
143 1.1 gwr /* Routines called from other code. */
144 1.1 gwr cdev_decl(zs); /* open, close, read, write, ioctl, stop, ... */
145 1.1 gwr
146 1.1 gwr static void zsstart(struct tty *);
147 1.1 gwr static int zsparam(struct tty *, struct termios *);
148 1.1 gwr static void zs_modem(struct zstty_softc *zst, int onoff);
149 1.1 gwr
150 1.1 gwr /*
151 1.1 gwr * zstty_match: how is this zs channel configured?
152 1.1 gwr */
153 1.1 gwr int
154 1.1 gwr zstty_match(parent, match, aux)
155 1.1 gwr struct device *parent;
156 1.1 gwr void *match, *aux;
157 1.1 gwr {
158 1.1 gwr struct cfdata *cf = match;
159 1.1 gwr struct zsc_attach_args *args = aux;
160 1.1 gwr
161 1.1 gwr /* Exact match is better than wildcard. */
162 1.1 gwr if (cf->cf_loc[0] == args->channel)
163 1.1 gwr return 2;
164 1.1 gwr
165 1.1 gwr /* This driver accepts wildcard. */
166 1.1 gwr if (cf->cf_loc[0] == -1)
167 1.1 gwr return 1;
168 1.1 gwr
169 1.1 gwr return 0;
170 1.1 gwr }
171 1.1 gwr
172 1.1 gwr void
173 1.1 gwr zstty_attach(parent, self, aux)
174 1.1 gwr struct device *parent, *self;
175 1.1 gwr void *aux;
176 1.1 gwr
177 1.1 gwr {
178 1.1 gwr struct zsc_softc *zsc = (void *) parent;
179 1.1 gwr struct zstty_softc *zst = (void *) self;
180 1.1 gwr struct zsc_attach_args *args = aux;
181 1.1 gwr struct zs_chanstate *cs;
182 1.1 gwr struct cfdata *cf;
183 1.1 gwr struct tty *tp;
184 1.1 gwr int channel, tty_unit;
185 1.1 gwr dev_t dev;
186 1.1 gwr
187 1.1 gwr cf = zst->zst_dev.dv_cfdata;
188 1.3 gwr tty_unit = zst->zst_dev.dv_unit;
189 1.1 gwr channel = args->channel;
190 1.1 gwr cs = &zsc->zsc_cs[channel];
191 1.1 gwr cs->cs_private = zst;
192 1.1 gwr cs->cs_ops = &zsops_tty;
193 1.1 gwr
194 1.1 gwr zst->zst_cs = cs;
195 1.1 gwr zst->zst_swflags = cf->cf_flags; /* softcar, etc. */
196 1.1 gwr zst->zst_hwflags = args->hwflags;
197 1.1 gwr dev = makedev(ZSTTY_MAJOR, tty_unit);
198 1.1 gwr
199 1.1 gwr if (zst->zst_swflags)
200 1.1 gwr printf(" flags 0x%x", zst->zst_swflags);
201 1.1 gwr
202 1.1 gwr if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE)
203 1.1 gwr printf(" (console)");
204 1.1 gwr else {
205 1.1 gwr #ifdef KGDB
206 1.1 gwr /*
207 1.1 gwr * Allow kgdb to "take over" this port. If this port is
208 1.1 gwr * NOT the kgdb port, zs_check_kgdb() will return zero.
209 1.1 gwr * If it IS the kgdb port, it will print "kgdb,...\n"
210 1.1 gwr * and then return non-zero.
211 1.1 gwr */
212 1.1 gwr if (zs_check_kgdb(cs, dev)) {
213 1.1 gwr /*
214 1.1 gwr * This is the kgdb port (exclusive use)
215 1.1 gwr * so skip the normal attach code.
216 1.1 gwr */
217 1.1 gwr return;
218 1.1 gwr }
219 1.1 gwr #endif
220 1.1 gwr }
221 1.1 gwr printf("\n");
222 1.1 gwr
223 1.1 gwr tp = zst->zst_tty = ttymalloc();
224 1.1 gwr tp->t_dev = dev;
225 1.1 gwr tp->t_oproc = zsstart;
226 1.1 gwr tp->t_param = zsparam;
227 1.1 gwr
228 1.1 gwr /*
229 1.1 gwr * Hardware init
230 1.1 gwr */
231 1.1 gwr if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE) {
232 1.1 gwr /* This unit is the console. */
233 1.1 gwr zst->zst_swflags |= TIOCFLAG_SOFTCAR;
234 1.1 gwr /* Call _param so interrupts get enabled. */
235 1.1 gwr cs->cs_defspeed = zs_getspeed(cs);
236 1.1 gwr tp->t_ispeed = cs->cs_defspeed;
237 1.1 gwr tp->t_ospeed = cs->cs_defspeed;
238 1.1 gwr tp->t_cflag = ZSTTY_DEF_CFLAG;
239 1.1 gwr (void) zsparam(tp, &tp->t_termios);
240 1.1 gwr } else {
241 1.1 gwr /* Not the console; may need reset. */
242 1.1 gwr int reset, s;
243 1.1 gwr reset = (channel == 0) ?
244 1.1 gwr ZSWR9_A_RESET : ZSWR9_B_RESET;
245 1.1 gwr s = splzs();
246 1.2 gwr zs_write_reg(cs, 9, reset);
247 1.1 gwr splx(s);
248 1.1 gwr }
249 1.1 gwr
250 1.1 gwr /*
251 1.1 gwr * Initialize state of modem control lines (DTR).
252 1.1 gwr * If softcar is set, turn on DTR now and leave it.
253 1.1 gwr * otherwise, turn off DTR now, and raise in open.
254 1.1 gwr * (Keeps modem from answering too early.)
255 1.1 gwr */
256 1.1 gwr zs_modem(zst, (zst->zst_swflags & TIOCFLAG_SOFTCAR) ? 1 : 0);
257 1.1 gwr }
258 1.1 gwr
259 1.1 gwr
260 1.1 gwr /*
261 1.1 gwr * Return pointer to our tty.
262 1.1 gwr */
263 1.1 gwr struct tty *
264 1.1 gwr zstty(dev)
265 1.1 gwr dev_t dev;
266 1.1 gwr {
267 1.1 gwr struct zstty_softc *zst;
268 1.1 gwr int unit = minor(dev);
269 1.1 gwr
270 1.1 gwr #ifdef DIAGNOSTIC
271 1.1 gwr if (unit >= zsttycd.cd_ndevs)
272 1.1 gwr panic("zstty");
273 1.1 gwr #endif
274 1.1 gwr zst = zsttycd.cd_devs[unit];
275 1.1 gwr return (zst->zst_tty);
276 1.1 gwr }
277 1.1 gwr
278 1.1 gwr
279 1.1 gwr /*
280 1.1 gwr * Open a zs serial (tty) port.
281 1.1 gwr */
282 1.1 gwr int
283 1.1 gwr zsopen(dev, flags, mode, p)
284 1.1 gwr dev_t dev;
285 1.1 gwr int flags;
286 1.1 gwr int mode;
287 1.1 gwr struct proc *p;
288 1.1 gwr {
289 1.1 gwr register struct tty *tp;
290 1.1 gwr register struct zs_chanstate *cs;
291 1.1 gwr struct zstty_softc *zst;
292 1.1 gwr int error, s, unit;
293 1.1 gwr
294 1.1 gwr unit = minor(dev);
295 1.1 gwr if (unit >= zsttycd.cd_ndevs)
296 1.1 gwr return (ENXIO);
297 1.1 gwr zst = zsttycd.cd_devs[unit];
298 1.1 gwr if (zst == NULL)
299 1.1 gwr return (ENXIO);
300 1.1 gwr tp = zst->zst_tty;
301 1.1 gwr cs = zst->zst_cs;
302 1.1 gwr
303 1.1 gwr /* If KGDB took the line, then tp==NULL */
304 1.1 gwr if (tp == NULL)
305 1.1 gwr return (EBUSY);
306 1.1 gwr
307 1.1 gwr /* It's simpler to do this up here. */
308 1.1 gwr if (((tp->t_state & (TS_ISOPEN | TS_XCLUDE))
309 1.1 gwr == (TS_ISOPEN | TS_XCLUDE))
310 1.1 gwr && (p->p_ucred->cr_uid != 0) )
311 1.1 gwr {
312 1.1 gwr return (EBUSY);
313 1.1 gwr }
314 1.1 gwr
315 1.1 gwr s = spltty();
316 1.1 gwr
317 1.1 gwr if ((tp->t_state & TS_ISOPEN) == 0) {
318 1.1 gwr /* First open. */
319 1.1 gwr ttychars(tp);
320 1.1 gwr tp->t_iflag = TTYDEF_IFLAG;
321 1.1 gwr tp->t_oflag = TTYDEF_OFLAG;
322 1.1 gwr tp->t_cflag = ZSTTY_DEF_CFLAG;
323 1.1 gwr if (zst->zst_swflags & TIOCFLAG_CLOCAL)
324 1.1 gwr tp->t_cflag |= CLOCAL;
325 1.1 gwr if (zst->zst_swflags & TIOCFLAG_CRTSCTS)
326 1.1 gwr tp->t_cflag |= CRTSCTS;
327 1.1 gwr if (zst->zst_swflags & TIOCFLAG_MDMBUF)
328 1.1 gwr tp->t_cflag |= MDMBUF;
329 1.1 gwr tp->t_lflag = TTYDEF_LFLAG;
330 1.1 gwr tp->t_ispeed = tp->t_ospeed = cs->cs_defspeed;
331 1.1 gwr (void) zsparam(tp, &tp->t_termios);
332 1.1 gwr ttsetwater(tp);
333 1.1 gwr /* Flush any pending input. */
334 1.1 gwr zst->zst_rbget = zst->zst_rbput;
335 1.1 gwr zs_iflush(cs); /* XXX */
336 1.1 gwr /* Turn on DTR */
337 1.1 gwr zs_modem(zst, 1);
338 1.1 gwr if (zst->zst_swflags & TIOCFLAG_SOFTCAR) {
339 1.1 gwr tp->t_state |= TS_CARR_ON;
340 1.1 gwr }
341 1.1 gwr }
342 1.1 gwr error = 0;
343 1.1 gwr
344 1.1 gwr /* Wait for carrier. */
345 1.1 gwr for (;;) {
346 1.1 gwr register int rr0;
347 1.1 gwr
348 1.1 gwr /* Might never get status intr if carrier already on. */
349 1.2 gwr rr0 = zs_read_csr(cs);
350 1.1 gwr if (rr0 & ZSRR0_DCD) {
351 1.1 gwr tp->t_state |= TS_CARR_ON;
352 1.1 gwr break;
353 1.1 gwr }
354 1.1 gwr
355 1.1 gwr if ((tp->t_state & TS_CARR_ON) ||
356 1.1 gwr (tp->t_cflag & CLOCAL) ||
357 1.1 gwr (flags & O_NONBLOCK) )
358 1.1 gwr {
359 1.1 gwr break;
360 1.1 gwr }
361 1.1 gwr
362 1.1 gwr tp->t_state |= TS_WOPEN;
363 1.1 gwr error = ttysleep(tp, (caddr_t)&tp->t_rawq,
364 1.1 gwr TTIPRI | PCATCH, ttopen, 0);
365 1.1 gwr if (error) {
366 1.1 gwr if ((tp->t_state & TS_ISOPEN) == 0) {
367 1.1 gwr /* Never get here with softcar */
368 1.1 gwr zs_modem(zst, 0);
369 1.1 gwr tp->t_state &= ~TS_WOPEN;
370 1.1 gwr ttwakeup(tp);
371 1.1 gwr }
372 1.1 gwr break;
373 1.1 gwr }
374 1.1 gwr }
375 1.1 gwr
376 1.1 gwr splx(s);
377 1.1 gwr
378 1.1 gwr if (error == 0)
379 1.1 gwr error = linesw[tp->t_line].l_open(dev, tp);
380 1.1 gwr
381 1.1 gwr return (error);
382 1.1 gwr }
383 1.1 gwr
384 1.1 gwr /*
385 1.1 gwr * Close a zs serial port.
386 1.1 gwr */
387 1.1 gwr int
388 1.1 gwr zsclose(dev, flags, mode, p)
389 1.1 gwr dev_t dev;
390 1.1 gwr int flags;
391 1.1 gwr int mode;
392 1.1 gwr struct proc *p;
393 1.1 gwr {
394 1.1 gwr struct zstty_softc *zst;
395 1.1 gwr register struct zs_chanstate *cs;
396 1.1 gwr register struct tty *tp;
397 1.1 gwr struct zsinfo *zi;
398 1.1 gwr int hup, s;
399 1.1 gwr
400 1.1 gwr zst = zsttycd.cd_devs[minor(dev)];
401 1.1 gwr cs = zst->zst_cs;
402 1.1 gwr tp = zst->zst_tty;
403 1.1 gwr
404 1.1 gwr /* XXX This is for cons.c. */
405 1.1 gwr if ((tp->t_state & TS_ISOPEN) == 0)
406 1.1 gwr return 0;
407 1.1 gwr
408 1.1 gwr (*linesw[tp->t_line].l_close)(tp, flags);
409 1.1 gwr hup = tp->t_cflag & HUPCL;
410 1.1 gwr if (zst->zst_swflags & TIOCFLAG_SOFTCAR)
411 1.1 gwr hup = 0;
412 1.1 gwr if (hup) {
413 1.1 gwr zs_modem(zst, 0);
414 1.1 gwr /* hold low for 1 second */
415 1.1 gwr (void) tsleep((caddr_t)cs, TTIPRI, ttclos, hz);
416 1.1 gwr }
417 1.1 gwr if (cs->cs_creg[5] & ZSWR5_BREAK) {
418 1.1 gwr zs_break(cs, 0);
419 1.1 gwr }
420 1.1 gwr /* XXX - turn off interrupts? */
421 1.1 gwr
422 1.1 gwr ttyclose(tp);
423 1.1 gwr return (0);
424 1.1 gwr }
425 1.1 gwr
426 1.1 gwr /*
427 1.1 gwr * Read/write zs serial port.
428 1.1 gwr */
429 1.1 gwr int
430 1.1 gwr zsread(dev, uio, flags)
431 1.1 gwr dev_t dev;
432 1.1 gwr struct uio *uio;
433 1.1 gwr int flags;
434 1.1 gwr {
435 1.1 gwr register struct zstty_softc *zst;
436 1.1 gwr register struct tty *tp;
437 1.1 gwr
438 1.1 gwr zst = zsttycd.cd_devs[minor(dev)];
439 1.1 gwr tp = zst->zst_tty;
440 1.1 gwr return (linesw[tp->t_line].l_read(tp, uio, flags));
441 1.1 gwr }
442 1.1 gwr
443 1.1 gwr int
444 1.1 gwr zswrite(dev, uio, flags)
445 1.1 gwr dev_t dev;
446 1.1 gwr struct uio *uio;
447 1.1 gwr int flags;
448 1.1 gwr {
449 1.1 gwr register struct zstty_softc *zst;
450 1.1 gwr register struct tty *tp;
451 1.1 gwr
452 1.1 gwr zst = zsttycd.cd_devs[minor(dev)];
453 1.1 gwr tp = zst->zst_tty;
454 1.1 gwr return (linesw[tp->t_line].l_write(tp, uio, flags));
455 1.1 gwr }
456 1.1 gwr
457 1.1 gwr #define TIOCFLAG_ALL (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | \
458 1.1 gwr TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF )
459 1.1 gwr
460 1.1 gwr int
461 1.1 gwr zsioctl(dev, cmd, data, flag, p)
462 1.1 gwr dev_t dev;
463 1.1 gwr u_long cmd;
464 1.1 gwr caddr_t data;
465 1.1 gwr int flag;
466 1.1 gwr struct proc *p;
467 1.1 gwr {
468 1.1 gwr register struct zstty_softc *zst;
469 1.1 gwr register struct zs_chanstate *cs;
470 1.1 gwr register struct tty *tp;
471 1.1 gwr register int error, tmp;
472 1.1 gwr
473 1.1 gwr zst = zsttycd.cd_devs[minor(dev)];
474 1.1 gwr cs = zst->zst_cs;
475 1.1 gwr tp = zst->zst_tty;
476 1.1 gwr
477 1.1 gwr error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
478 1.1 gwr if (error >= 0)
479 1.1 gwr return (error);
480 1.1 gwr error = ttioctl(tp, cmd, data, flag, p);
481 1.1 gwr if (error >= 0)
482 1.1 gwr return (error);
483 1.1 gwr
484 1.1 gwr switch (cmd) {
485 1.1 gwr
486 1.1 gwr case TIOCSBRK:
487 1.1 gwr zs_break(cs, 1);
488 1.1 gwr break;
489 1.1 gwr
490 1.1 gwr case TIOCCBRK:
491 1.1 gwr zs_break(cs, 0);
492 1.1 gwr break;
493 1.1 gwr
494 1.1 gwr case TIOCGFLAGS:
495 1.1 gwr *(int *)data = zst->zst_swflags;
496 1.1 gwr break;
497 1.1 gwr
498 1.1 gwr case TIOCSFLAGS:
499 1.1 gwr error = suser(p->p_ucred, &p->p_acflag);
500 1.1 gwr if (error != 0)
501 1.1 gwr return (EPERM);
502 1.1 gwr tmp = *(int *)data;
503 1.1 gwr /* Check for random bits... */
504 1.1 gwr if (tmp & ~TIOCFLAG_ALL)
505 1.1 gwr return(EINVAL);
506 1.1 gwr /* Silently enforce softcar on the console. */
507 1.1 gwr if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE)
508 1.1 gwr tmp |= TIOCFLAG_SOFTCAR;
509 1.1 gwr /* These flags take effect during open. */
510 1.1 gwr zst->zst_swflags = tmp;
511 1.1 gwr break;
512 1.1 gwr
513 1.1 gwr case TIOCSDTR:
514 1.1 gwr zs_modem(zst, 1);
515 1.1 gwr break;
516 1.1 gwr
517 1.1 gwr case TIOCCDTR:
518 1.1 gwr zs_modem(zst, 0);
519 1.1 gwr break;
520 1.1 gwr
521 1.1 gwr case TIOCMSET:
522 1.1 gwr case TIOCMBIS:
523 1.1 gwr case TIOCMBIC:
524 1.1 gwr case TIOCMGET:
525 1.1 gwr default:
526 1.1 gwr return (ENOTTY);
527 1.1 gwr }
528 1.1 gwr return (0);
529 1.1 gwr }
530 1.1 gwr
531 1.1 gwr /*
532 1.1 gwr * Start or restart transmission.
533 1.1 gwr */
534 1.1 gwr static void
535 1.1 gwr zsstart(tp)
536 1.1 gwr register struct tty *tp;
537 1.1 gwr {
538 1.1 gwr register struct zstty_softc *zst;
539 1.1 gwr register struct zs_chanstate *cs;
540 1.1 gwr register int s, nch;
541 1.1 gwr
542 1.3 gwr zst = zsttycd.cd_devs[minor(tp->t_dev)];
543 1.1 gwr cs = zst->zst_cs;
544 1.1 gwr
545 1.1 gwr s = spltty();
546 1.1 gwr
547 1.1 gwr /*
548 1.1 gwr * If currently active or delaying, no need to do anything.
549 1.1 gwr */
550 1.1 gwr if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP))
551 1.1 gwr goto out;
552 1.1 gwr
553 1.1 gwr /*
554 1.1 gwr * If there are sleepers, and output has drained below low
555 1.1 gwr * water mark, awaken.
556 1.1 gwr */
557 1.1 gwr if (tp->t_outq.c_cc <= tp->t_lowat) {
558 1.1 gwr if (tp->t_state & TS_ASLEEP) {
559 1.1 gwr tp->t_state &= ~TS_ASLEEP;
560 1.1 gwr wakeup((caddr_t)&tp->t_outq);
561 1.1 gwr }
562 1.1 gwr selwakeup(&tp->t_wsel);
563 1.1 gwr }
564 1.1 gwr
565 1.1 gwr nch = ndqb(&tp->t_outq, 0); /* XXX */
566 1.1 gwr if (nch) {
567 1.1 gwr register char *p = tp->t_outq.c_cf;
568 1.1 gwr
569 1.1 gwr /* mark busy, enable tx done interrupts, & send first byte */
570 1.1 gwr tp->t_state |= TS_BUSY;
571 1.1 gwr (void) splzs();
572 1.1 gwr
573 1.1 gwr cs->cs_preg[1] |= ZSWR1_TIE;
574 1.1 gwr cs->cs_creg[1] |= ZSWR1_TIE;
575 1.2 gwr zs_write_reg(cs, 1, cs->cs_creg[1]);
576 1.2 gwr zs_write_data(cs, *p);
577 1.1 gwr zst->zst_tba = p + 1;
578 1.1 gwr zst->zst_tbc = nch - 1;
579 1.1 gwr } else {
580 1.1 gwr /*
581 1.1 gwr * Nothing to send, turn off transmit done interrupts.
582 1.1 gwr * This is useful if something is doing polled output.
583 1.1 gwr */
584 1.1 gwr (void) splzs();
585 1.1 gwr cs->cs_preg[1] &= ~ZSWR1_TIE;
586 1.1 gwr cs->cs_creg[1] &= ~ZSWR1_TIE;
587 1.2 gwr zs_write_reg(cs, 1, cs->cs_creg[1]);
588 1.1 gwr }
589 1.1 gwr out:
590 1.1 gwr splx(s);
591 1.1 gwr }
592 1.1 gwr
593 1.1 gwr /*
594 1.1 gwr * Stop output, e.g., for ^S or output flush.
595 1.1 gwr */
596 1.1 gwr int
597 1.1 gwr zsstop(tp, flag)
598 1.1 gwr struct tty *tp;
599 1.1 gwr int flag;
600 1.1 gwr {
601 1.1 gwr register struct zstty_softc *zst;
602 1.1 gwr register struct zs_chanstate *cs;
603 1.1 gwr register int s;
604 1.1 gwr
605 1.3 gwr zst = zsttycd.cd_devs[minor(tp->t_dev)];
606 1.1 gwr cs = zst->zst_cs;
607 1.1 gwr
608 1.1 gwr s = splzs();
609 1.1 gwr if (tp->t_state & TS_BUSY) {
610 1.1 gwr /*
611 1.1 gwr * Device is transmitting; must stop it.
612 1.1 gwr */
613 1.1 gwr zst->zst_tbc = 0;
614 1.1 gwr if ((tp->t_state & TS_TTSTOP) == 0)
615 1.1 gwr tp->t_state |= TS_FLUSH;
616 1.1 gwr }
617 1.1 gwr splx(s);
618 1.1 gwr return (0);
619 1.1 gwr }
620 1.1 gwr
621 1.1 gwr /*
622 1.1 gwr * Set ZS tty parameters from termios.
623 1.1 gwr * XXX - Should just copy the whole termios after
624 1.1 gwr * making sure all the changes could be done.
625 1.1 gwr * XXX - Only whack the UART when params change...
626 1.1 gwr */
627 1.1 gwr static int
628 1.1 gwr zsparam(tp, t)
629 1.1 gwr register struct tty *tp;
630 1.1 gwr register struct termios *t;
631 1.1 gwr {
632 1.1 gwr register struct zstty_softc *zst;
633 1.1 gwr register struct zs_chanstate *cs;
634 1.1 gwr register int s, bps, cflag, tconst;
635 1.1 gwr u_char tmp3, tmp4, tmp5, reset;
636 1.1 gwr
637 1.3 gwr zst = zsttycd.cd_devs[minor(tp->t_dev)];
638 1.1 gwr cs = zst->zst_cs;
639 1.1 gwr
640 1.1 gwr /*
641 1.1 gwr * Because PCLK is only run at 4.9 MHz, the fastest we
642 1.1 gwr * can go is 51200 baud (this corresponds to TC=1).
643 1.1 gwr * This is somewhat unfortunate as there is no real
644 1.1 gwr * reason we should not be able to handle higher rates.
645 1.1 gwr */
646 1.1 gwr bps = t->c_ospeed;
647 1.1 gwr if (bps < 0 || (t->c_ispeed && t->c_ispeed != bps))
648 1.1 gwr return (EINVAL);
649 1.1 gwr if (bps == 0) {
650 1.1 gwr /* stty 0 => drop DTR and RTS */
651 1.1 gwr zs_modem(zst, 0);
652 1.1 gwr return (0);
653 1.1 gwr }
654 1.1 gwr tconst = BPS_TO_TCONST(cs->cs_pclk_div16, bps);
655 1.1 gwr if (tconst < 0)
656 1.1 gwr return (EINVAL);
657 1.1 gwr
658 1.1 gwr /* Convert back to make sure we can do it. */
659 1.1 gwr bps = TCONST_TO_BPS(cs->cs_pclk_div16, tconst);
660 1.1 gwr if (bps != t->c_ospeed)
661 1.1 gwr return (EINVAL);
662 1.1 gwr tp->t_ispeed = tp->t_ospeed = bps;
663 1.1 gwr
664 1.1 gwr cflag = t->c_cflag;
665 1.1 gwr tp->t_cflag = cflag;
666 1.1 gwr
667 1.1 gwr /*
668 1.1 gwr * Block interrupts so that state will not
669 1.1 gwr * be altered until we are done setting it up.
670 1.1 gwr */
671 1.1 gwr s = splzs();
672 1.1 gwr
673 1.1 gwr /*
674 1.1 gwr * Initial values in cs_preg are set before
675 1.1 gwr * our attach routine is called. The master
676 1.1 gwr * interrupt enable is handled by zsc.c
677 1.1 gwr */
678 1.1 gwr
679 1.1 gwr cs->cs_preg[12] = tconst;
680 1.1 gwr cs->cs_preg[13] = tconst >> 8;
681 1.1 gwr
682 1.1 gwr switch (cflag & CSIZE) {
683 1.1 gwr case CS5:
684 1.1 gwr tmp3 = ZSWR3_RX_5;
685 1.1 gwr tmp5 = ZSWR5_TX_5;
686 1.1 gwr break;
687 1.1 gwr case CS6:
688 1.1 gwr tmp3 = ZSWR3_RX_6;
689 1.1 gwr tmp5 = ZSWR5_TX_6;
690 1.1 gwr break;
691 1.1 gwr case CS7:
692 1.1 gwr tmp3 = ZSWR3_RX_7;
693 1.1 gwr tmp5 = ZSWR5_TX_7;
694 1.1 gwr break;
695 1.1 gwr case CS8:
696 1.1 gwr default:
697 1.1 gwr tmp3 = ZSWR3_RX_8;
698 1.1 gwr tmp5 = ZSWR5_TX_8;
699 1.1 gwr break;
700 1.1 gwr }
701 1.1 gwr
702 1.1 gwr /*
703 1.1 gwr * Output hardware flow control on the chip is horrendous: if
704 1.1 gwr * carrier detect drops, the receiver is disabled. Hence we
705 1.1 gwr * can only do this when the carrier is on.
706 1.1 gwr */
707 1.1 gwr tmp3 |= ZSWR3_RX_ENABLE;
708 1.1 gwr if (cflag & CCTS_OFLOW) {
709 1.2 gwr if (zs_read_csr(cs) & ZSRR0_DCD)
710 1.1 gwr tmp3 |= ZSWR3_HFC;
711 1.1 gwr }
712 1.1 gwr
713 1.1 gwr cs->cs_preg[3] = tmp3;
714 1.1 gwr cs->cs_preg[5] = tmp5 | ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
715 1.1 gwr
716 1.1 gwr tmp4 = ZSWR4_CLK_X16 | (cflag & CSTOPB ? ZSWR4_TWOSB : ZSWR4_ONESB);
717 1.1 gwr if ((cflag & PARODD) == 0)
718 1.1 gwr tmp4 |= ZSWR4_EVENP;
719 1.1 gwr if (cflag & PARENB)
720 1.1 gwr tmp4 |= ZSWR4_PARENB;
721 1.1 gwr cs->cs_preg[4] = tmp4;
722 1.1 gwr
723 1.1 gwr /*
724 1.1 gwr * If nothing is being transmitted, set up new current values,
725 1.1 gwr * else mark them as pending.
726 1.1 gwr */
727 1.1 gwr if (cs->cs_heldchange == 0) {
728 1.1 gwr if (tp->t_state & TS_BUSY) {
729 1.1 gwr zst->zst_heldtbc = zst->zst_tbc;
730 1.1 gwr zst->zst_tbc = 0;
731 1.1 gwr cs->cs_heldchange = 1;
732 1.1 gwr } else {
733 1.1 gwr zs_loadchannelregs(cs);
734 1.1 gwr }
735 1.1 gwr }
736 1.1 gwr splx(s);
737 1.1 gwr return (0);
738 1.1 gwr }
739 1.1 gwr
740 1.1 gwr /*
741 1.1 gwr * Raise or lower modem control (DTR/RTS) signals. If a character is
742 1.1 gwr * in transmission, the change is deferred.
743 1.1 gwr */
744 1.1 gwr static void
745 1.1 gwr zs_modem(zst, onoff)
746 1.1 gwr struct zstty_softc *zst;
747 1.1 gwr int onoff;
748 1.1 gwr {
749 1.1 gwr struct zs_chanstate *cs;
750 1.1 gwr struct tty *tp;
751 1.1 gwr int s, bis, and;
752 1.1 gwr
753 1.1 gwr cs = zst->zst_cs;
754 1.1 gwr tp = zst->zst_tty;
755 1.1 gwr
756 1.1 gwr if (onoff) {
757 1.1 gwr bis = ZSWR5_DTR | ZSWR5_RTS;
758 1.1 gwr and = ~0;
759 1.1 gwr } else {
760 1.1 gwr bis = 0;
761 1.1 gwr and = ~(ZSWR5_DTR | ZSWR5_RTS);
762 1.1 gwr }
763 1.1 gwr s = splzs();
764 1.1 gwr cs->cs_preg[5] = (cs->cs_preg[5] | bis) & and;
765 1.1 gwr if (cs->cs_heldchange == 0) {
766 1.1 gwr if (tp->t_state & TS_BUSY) {
767 1.1 gwr zst->zst_heldtbc = zst->zst_tbc;
768 1.1 gwr zst->zst_tbc = 0;
769 1.1 gwr cs->cs_heldchange = 1;
770 1.1 gwr } else {
771 1.1 gwr cs->cs_creg[5] = (cs->cs_creg[5] | bis) & and;
772 1.2 gwr zs_write_reg(cs, 5, cs->cs_creg[5]);
773 1.1 gwr }
774 1.1 gwr }
775 1.1 gwr splx(s);
776 1.1 gwr }
777 1.1 gwr
778 1.1 gwr
779 1.1 gwr /****************************************************************
780 1.1 gwr * Interface to the lower layer (zscc)
781 1.1 gwr ****************************************************************/
782 1.3 gwr
783 1.3 gwr /*
784 1.3 gwr * XXX: need to do input flow-control to avoid ring overrun.
785 1.3 gwr */
786 1.1 gwr
787 1.1 gwr static int
788 1.1 gwr zstty_rxint(cs)
789 1.1 gwr register struct zs_chanstate *cs;
790 1.1 gwr {
791 1.1 gwr register struct zstty_softc *zst;
792 1.1 gwr register put, put_next;
793 1.1 gwr register u_char c, rr0, rr1;
794 1.1 gwr
795 1.1 gwr zst = cs->cs_private;
796 1.1 gwr put = zst->zst_rbput;
797 1.1 gwr
798 1.1 gwr nextchar:
799 1.1 gwr /* Read the input data ASAP. */
800 1.2 gwr c = zs_read_data(cs);
801 1.1 gwr
802 1.1 gwr /* Save the status register too. */
803 1.2 gwr rr1 = zs_read_reg(cs, 1);
804 1.1 gwr
805 1.1 gwr if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
806 1.1 gwr /* Clear the receive error. */
807 1.2 gwr zs_write_csr(cs, ZSWR0_RESET_ERRORS);
808 1.1 gwr }
809 1.1 gwr
810 1.1 gwr zst->zst_rbuf[put] = (c << 8) | rr1;
811 1.1 gwr put_next = (put + 1) & ZSTTY_RING_MASK;
812 1.1 gwr
813 1.1 gwr /* Would overrun if increment makes (put==get). */
814 1.1 gwr if (put_next == zst->zst_rbget) {
815 1.1 gwr zst->zst_intr_flags |= INTR_RX_OVERRUN;
816 1.1 gwr } else {
817 1.1 gwr /* OK, really increment. */
818 1.1 gwr put = put_next;
819 1.1 gwr }
820 1.1 gwr
821 1.1 gwr /* Keep reading until the FIFO is empty. */
822 1.2 gwr rr0 = zs_read_csr(cs);
823 1.1 gwr if (rr0 & ZSRR0_RX_READY)
824 1.1 gwr goto nextchar;
825 1.1 gwr
826 1.1 gwr /* Done reading. */
827 1.1 gwr zst->zst_rbput = put;
828 1.1 gwr
829 1.1 gwr /* Ask for softint() call. */
830 1.1 gwr cs->cs_softreq = 1;
831 1.1 gwr return(1);
832 1.1 gwr }
833 1.1 gwr
834 1.1 gwr static int
835 1.1 gwr zstty_txint(cs)
836 1.1 gwr register struct zs_chanstate *cs;
837 1.1 gwr {
838 1.1 gwr register struct zstty_softc *zst;
839 1.1 gwr register int count, rval;
840 1.1 gwr
841 1.1 gwr zst = cs->cs_private;
842 1.1 gwr count = zst->zst_tbc;
843 1.1 gwr
844 1.1 gwr if (count > 0) {
845 1.1 gwr /* Send the next char. */
846 1.2 gwr zs_write_data(cs, *zst->zst_tba);
847 1.2 gwr zst->zst_tba++;
848 1.1 gwr zst->zst_tbc = --count;
849 1.1 gwr rval = 0;
850 1.1 gwr } else {
851 1.1 gwr /* Nothing more to send. */
852 1.2 gwr zs_write_csr(cs, ZSWR0_RESET_TXINT);
853 1.1 gwr zst->zst_intr_flags |= INTR_TX_EMPTY;
854 1.1 gwr rval = 1; /* want softcall */
855 1.1 gwr }
856 1.1 gwr
857 1.1 gwr cs->cs_softreq = rval;
858 1.1 gwr return (rval);
859 1.1 gwr }
860 1.1 gwr
861 1.1 gwr static int
862 1.1 gwr zstty_stint(cs)
863 1.1 gwr register struct zs_chanstate *cs;
864 1.1 gwr {
865 1.1 gwr register struct zstty_softc *zst;
866 1.1 gwr register int rr0;
867 1.1 gwr
868 1.1 gwr zst = cs->cs_private;
869 1.1 gwr
870 1.2 gwr rr0 = zs_read_csr(cs);
871 1.2 gwr zs_write_csr(cs, ZSWR0_RESET_STATUS);
872 1.1 gwr
873 1.1 gwr if ((rr0 & ZSRR0_BREAK) &&
874 1.1 gwr (zst->zst_hwflags & ZS_HWFLAG_CONSOLE))
875 1.1 gwr {
876 1.1 gwr zs_abort();
877 1.1 gwr return (0);
878 1.1 gwr }
879 1.1 gwr
880 1.1 gwr zst->zst_intr_flags |= INTR_ST_CHECK;
881 1.1 gwr /* Ask for softint() call. */
882 1.1 gwr cs->cs_softreq = 1;
883 1.1 gwr return (1);
884 1.1 gwr }
885 1.1 gwr
886 1.1 gwr /*
887 1.1 gwr * Print out a ring or fifo overrun error message.
888 1.1 gwr */
889 1.1 gwr static void
890 1.1 gwr zsoverrun(zst, ptime, what)
891 1.1 gwr struct zstty_softc *zst;
892 1.1 gwr long *ptime;
893 1.1 gwr char *what;
894 1.1 gwr {
895 1.1 gwr
896 1.1 gwr if (*ptime != time.tv_sec) {
897 1.1 gwr *ptime = time.tv_sec;
898 1.1 gwr log(LOG_WARNING, "%s: %s overrun\n",
899 1.1 gwr zst->zst_dev.dv_xname, what);
900 1.1 gwr }
901 1.1 gwr }
902 1.1 gwr
903 1.1 gwr static int
904 1.1 gwr zstty_softint(cs)
905 1.1 gwr struct zs_chanstate *cs;
906 1.1 gwr {
907 1.1 gwr register struct zstty_softc *zst;
908 1.1 gwr register struct linesw *line;
909 1.1 gwr register struct tty *tp;
910 1.1 gwr register int get, c, s;
911 1.1 gwr int intr_flags;
912 1.1 gwr register u_short ring_data;
913 1.1 gwr register u_char rr0, rr1;
914 1.1 gwr
915 1.1 gwr zst = cs->cs_private;
916 1.1 gwr tp = zst->zst_tty;
917 1.1 gwr line = &linesw[tp->t_line];
918 1.1 gwr
919 1.1 gwr /* Atomically get and clear flags. */
920 1.1 gwr s = splzs();
921 1.1 gwr intr_flags = zst->zst_intr_flags;
922 1.1 gwr zst->zst_intr_flags = 0;
923 1.1 gwr splx(s);
924 1.1 gwr
925 1.1 gwr if (intr_flags & INTR_RX_OVERRUN) {
926 1.1 gwr /* May turn this on again below. */
927 1.1 gwr intr_flags &= ~INTR_RX_OVERRUN;
928 1.1 gwr zsoverrun(zst, "ring");
929 1.1 gwr }
930 1.1 gwr
931 1.1 gwr /*
932 1.1 gwr * Copy data from the receive ring into the tty layer.
933 1.1 gwr */
934 1.1 gwr get = zst->zst_rbget;
935 1.1 gwr while (get != zst->zst_rbput) {
936 1.1 gwr ring_data = zst->zst_rbuf[get];
937 1.1 gwr get = (get + 1) & ZSTTY_RING_MASK;
938 1.1 gwr
939 1.1 gwr if (ring_data & ZSRR1_DO)
940 1.1 gwr intr_flags |= INTR_RX_OVERRUN;
941 1.1 gwr /* low byte of ring_data is rr1 */
942 1.1 gwr c = (ring_data >> 8) & 0xff;
943 1.1 gwr if (ring_data & ZSRR1_FE)
944 1.1 gwr c |= TTY_FE;
945 1.1 gwr if (ring_data & ZSRR1_PE)
946 1.1 gwr c |= TTY_PE;
947 1.1 gwr
948 1.1 gwr line->l_rint(c, tp);
949 1.1 gwr }
950 1.1 gwr zst->zst_rbget = get;
951 1.1 gwr
952 1.1 gwr /* If set, it is from the loop above. */
953 1.1 gwr if (intr_flags & INTR_RX_OVERRUN) {
954 1.1 gwr zsoverrun(zst, "fifo");
955 1.1 gwr }
956 1.1 gwr
957 1.1 gwr if (intr_flags & INTR_TX_EMPTY) {
958 1.1 gwr /*
959 1.1 gwr * Transmit done. Change registers and resume,
960 1.1 gwr * or just clear BUSY.
961 1.1 gwr */
962 1.1 gwr if (cs->cs_heldchange) {
963 1.1 gwr s = splzs();
964 1.2 gwr rr0 = zs_read_csr(cs);
965 1.1 gwr if ((rr0 & ZSRR0_DCD) == 0)
966 1.1 gwr cs->cs_preg[3] &= ~ZSWR3_HFC;
967 1.1 gwr zs_loadchannelregs(cs);
968 1.1 gwr splx(s);
969 1.1 gwr cs->cs_heldchange = 0;
970 1.1 gwr
971 1.1 gwr if (zst->zst_heldtbc &&
972 1.1 gwr (tp->t_state & TS_TTSTOP) == 0)
973 1.1 gwr {
974 1.1 gwr zst->zst_tbc = zst->zst_heldtbc - 1;
975 1.2 gwr zs_write_data(cs, *zst->zst_tba);
976 1.2 gwr zst->zst_tba++;
977 1.1 gwr goto tx_resumed;
978 1.1 gwr }
979 1.1 gwr }
980 1.1 gwr tp->t_state &= ~TS_BUSY;
981 1.1 gwr if (tp->t_state & TS_FLUSH)
982 1.1 gwr tp->t_state &= ~TS_FLUSH;
983 1.1 gwr else
984 1.1 gwr ndflush(&tp->t_outq, zst->zst_tba -
985 1.1 gwr (caddr_t) tp->t_outq.c_cf);
986 1.1 gwr line->l_start(tp);
987 1.1 gwr tx_resumed:
988 1.1 gwr }
989 1.1 gwr
990 1.1 gwr if (intr_flags & INTR_ST_CHECK) {
991 1.1 gwr /*
992 1.1 gwr * Status line change.
993 1.1 gwr *
994 1.1 gwr * The chip's hardware flow control is, as noted in zsreg.h,
995 1.1 gwr * busted---if the DCD line goes low the chip shuts off the
996 1.1 gwr * receiver (!). If we want hardware CTS flow control but do
997 1.1 gwr * not have it, and carrier is now on, turn HFC on; if we have
998 1.1 gwr * HFC now but carrier has gone low, turn it off.
999 1.1 gwr */
1000 1.1 gwr s = splzs();
1001 1.2 gwr rr0 = zs_read_csr(cs);
1002 1.1 gwr if (rr0 & ZSRR0_DCD) {
1003 1.1 gwr if (tp->t_cflag & CCTS_OFLOW &&
1004 1.1 gwr (cs->cs_creg[3] & ZSWR3_HFC) == 0) {
1005 1.1 gwr cs->cs_creg[3] |= ZSWR3_HFC;
1006 1.2 gwr zs_write_reg(cs, 3, cs->cs_creg[3]);
1007 1.1 gwr }
1008 1.1 gwr } else {
1009 1.1 gwr if (cs->cs_creg[3] & ZSWR3_HFC) {
1010 1.1 gwr cs->cs_creg[3] &= ~ZSWR3_HFC;
1011 1.2 gwr zs_write_reg(cs, 3, cs->cs_creg[3]);
1012 1.1 gwr }
1013 1.1 gwr }
1014 1.1 gwr splx(s);
1015 1.1 gwr
1016 1.1 gwr /* Was there a change on DCD? */
1017 1.1 gwr if ((rr0 ^ cs->cs_rr0) & ZSRR0_DCD) {
1018 1.1 gwr c = ((rr0 & ZSRR0_DCD) != 0);
1019 1.1 gwr if (line->l_modem(tp, c) == 0)
1020 1.1 gwr zs_modem(zst, c);
1021 1.1 gwr }
1022 1.1 gwr cs->cs_rr0 = rr0;
1023 1.1 gwr }
1024 1.1 gwr
1025 1.1 gwr return (1);
1026 1.1 gwr }
1027 1.1 gwr
1028 1.1 gwr struct zsops zsops_tty = {
1029 1.1 gwr zstty_rxint, /* receive char available */
1030 1.1 gwr zstty_stint, /* external/status */
1031 1.1 gwr zstty_txint, /* xmit buffer empty */
1032 1.1 gwr zstty_softint, /* process software interrupt */
1033 1.1 gwr };
1034 1.1 gwr
1035