z8530tty.c revision 1.6 1 1.6 gwr /* $NetBSD: z8530tty.c,v 1.6 1996/04/10 21:44:47 gwr Exp $ */
2 1.1 gwr
3 1.1 gwr /*
4 1.1 gwr * Copyright (c) 1994 Gordon W. Ross
5 1.1 gwr * Copyright (c) 1992, 1993
6 1.1 gwr * The Regents of the University of California. All rights reserved.
7 1.1 gwr *
8 1.1 gwr * This software was developed by the Computer Systems Engineering group
9 1.1 gwr * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 1.1 gwr * contributed to Berkeley.
11 1.1 gwr *
12 1.1 gwr * All advertising materials mentioning features or use of this software
13 1.1 gwr * must display the following acknowledgement:
14 1.1 gwr * This product includes software developed by the University of
15 1.1 gwr * California, Lawrence Berkeley Laboratory.
16 1.1 gwr *
17 1.1 gwr * Redistribution and use in source and binary forms, with or without
18 1.1 gwr * modification, are permitted provided that the following conditions
19 1.1 gwr * are met:
20 1.1 gwr * 1. Redistributions of source code must retain the above copyright
21 1.1 gwr * notice, this list of conditions and the following disclaimer.
22 1.1 gwr * 2. Redistributions in binary form must reproduce the above copyright
23 1.1 gwr * notice, this list of conditions and the following disclaimer in the
24 1.1 gwr * documentation and/or other materials provided with the distribution.
25 1.1 gwr * 3. All advertising materials mentioning features or use of this software
26 1.1 gwr * must display the following acknowledgement:
27 1.1 gwr * This product includes software developed by the University of
28 1.1 gwr * California, Berkeley and its contributors.
29 1.1 gwr * 4. Neither the name of the University nor the names of its contributors
30 1.1 gwr * may be used to endorse or promote products derived from this software
31 1.1 gwr * without specific prior written permission.
32 1.1 gwr *
33 1.1 gwr * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 1.1 gwr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 1.1 gwr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 1.1 gwr * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 1.1 gwr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 1.1 gwr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 1.1 gwr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 1.1 gwr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 1.1 gwr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 1.1 gwr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 1.1 gwr * SUCH DAMAGE.
44 1.1 gwr *
45 1.1 gwr * @(#)zs.c 8.1 (Berkeley) 7/19/93
46 1.1 gwr */
47 1.1 gwr
48 1.1 gwr /*
49 1.1 gwr * Zilog Z8530 Dual UART driver (tty interface)
50 1.1 gwr *
51 1.1 gwr * This is the "slave" driver that will be attached to
52 1.1 gwr * the "zsc" driver for plain "tty" async. serial lines.
53 1.1 gwr */
54 1.1 gwr
55 1.1 gwr #include <sys/param.h>
56 1.1 gwr #include <sys/systm.h>
57 1.1 gwr #include <sys/proc.h>
58 1.1 gwr #include <sys/device.h>
59 1.1 gwr #include <sys/conf.h>
60 1.1 gwr #include <sys/file.h>
61 1.1 gwr #include <sys/ioctl.h>
62 1.6 gwr #include <sys/malloc.h>
63 1.1 gwr #include <sys/tty.h>
64 1.1 gwr #include <sys/time.h>
65 1.1 gwr #include <sys/kernel.h>
66 1.1 gwr #include <sys/syslog.h>
67 1.1 gwr
68 1.1 gwr #include <dev/ic/z8530reg.h>
69 1.1 gwr #include <machine/z8530var.h>
70 1.1 gwr
71 1.1 gwr #ifdef KGDB
72 1.1 gwr extern int zs_check_kgdb();
73 1.1 gwr #endif
74 1.1 gwr
75 1.1 gwr /*
76 1.1 gwr * Allow the MD var.h to override the default CFLAG so that
77 1.1 gwr * console messages during boot come out with correct parity.
78 1.1 gwr */
79 1.1 gwr #ifndef ZSTTY_DEF_CFLAG
80 1.1 gwr #define ZSTTY_DEF_CFLAG TTYDEF_CFLAG
81 1.1 gwr #endif
82 1.1 gwr
83 1.1 gwr /*
84 1.1 gwr * How many input characters we can buffer.
85 1.1 gwr * The port-specific var.h may override this.
86 1.1 gwr * Note: must be a power of two!
87 1.1 gwr */
88 1.1 gwr #ifndef ZSTTY_RING_SIZE
89 1.6 gwr #define ZSTTY_RING_SIZE 2048
90 1.1 gwr #endif
91 1.6 gwr
92 1.6 gwr /*
93 1.6 gwr * Make this an option variable one can patch.
94 1.6 gwr * But be warned: this must be a power of 2!
95 1.6 gwr */
96 1.6 gwr int zstty_rbuf_size = ZSTTY_RING_SIZE;
97 1.1 gwr
98 1.1 gwr struct zstty_softc {
99 1.1 gwr struct device zst_dev; /* required first: base device */
100 1.1 gwr struct tty *zst_tty;
101 1.1 gwr struct zs_chanstate *zst_cs;
102 1.1 gwr
103 1.1 gwr int zst_hwflags; /* see z8530var.h */
104 1.1 gwr int zst_swflags; /* TIOCFLAG_SOFTCAR, ... <ttycom.h> */
105 1.1 gwr
106 1.1 gwr /* Flags to communicate with zstty_softint() */
107 1.1 gwr volatile int zst_intr_flags;
108 1.1 gwr #define INTR_RX_OVERRUN 1
109 1.1 gwr #define INTR_TX_EMPTY 2
110 1.1 gwr #define INTR_ST_CHECK 4
111 1.1 gwr
112 1.1 gwr /*
113 1.1 gwr * The transmit byte count and address are used for pseudo-DMA
114 1.1 gwr * output in the hardware interrupt code. PDMA can be suspended
115 1.1 gwr * to get pending changes done; heldtbc is used for this. It can
116 1.1 gwr * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state.
117 1.1 gwr */
118 1.1 gwr int zst_tbc; /* transmit byte count */
119 1.1 gwr caddr_t zst_tba; /* transmit buffer address */
120 1.1 gwr int zst_heldtbc; /* held tbc while xmission stopped */
121 1.1 gwr
122 1.1 gwr /*
123 1.1 gwr * Printing an overrun error message often takes long enough to
124 1.1 gwr * cause another overrun, so we only print one per second.
125 1.1 gwr */
126 1.1 gwr long zst_rotime; /* time of last ring overrun */
127 1.1 gwr long zst_fotime; /* time of last fifo overrun */
128 1.1 gwr
129 1.1 gwr /*
130 1.1 gwr * The receive ring buffer.
131 1.1 gwr */
132 1.1 gwr u_int zst_rbget; /* ring buffer `get' index */
133 1.1 gwr volatile u_int zst_rbput; /* ring buffer `put' index */
134 1.6 gwr u_int zst_ringmask;
135 1.6 gwr u_short *zst_rbuf; /* rr1, data pairs */
136 1.1 gwr };
137 1.1 gwr
138 1.1 gwr
139 1.1 gwr /* Definition of the driver for autoconfig. */
140 1.1 gwr static int zstty_match(struct device *, void *, void *);
141 1.1 gwr static void zstty_attach(struct device *, struct device *, void *);
142 1.1 gwr
143 1.4 thorpej struct cfattach zstty_ca = {
144 1.4 thorpej sizeof(struct zstty_softc), zstty_match, zstty_attach
145 1.4 thorpej };
146 1.4 thorpej
147 1.4 thorpej struct cfdriver zstty_cd = {
148 1.4 thorpej NULL, "zstty", DV_TTY
149 1.1 gwr };
150 1.1 gwr
151 1.1 gwr struct zsops zsops_tty;
152 1.1 gwr
153 1.1 gwr /* Routines called from other code. */
154 1.1 gwr cdev_decl(zs); /* open, close, read, write, ioctl, stop, ... */
155 1.1 gwr
156 1.1 gwr static void zsstart(struct tty *);
157 1.1 gwr static int zsparam(struct tty *, struct termios *);
158 1.1 gwr static void zs_modem(struct zstty_softc *zst, int onoff);
159 1.1 gwr
160 1.1 gwr /*
161 1.1 gwr * zstty_match: how is this zs channel configured?
162 1.1 gwr */
163 1.1 gwr int
164 1.1 gwr zstty_match(parent, match, aux)
165 1.1 gwr struct device *parent;
166 1.1 gwr void *match, *aux;
167 1.1 gwr {
168 1.1 gwr struct cfdata *cf = match;
169 1.1 gwr struct zsc_attach_args *args = aux;
170 1.1 gwr
171 1.1 gwr /* Exact match is better than wildcard. */
172 1.1 gwr if (cf->cf_loc[0] == args->channel)
173 1.1 gwr return 2;
174 1.1 gwr
175 1.1 gwr /* This driver accepts wildcard. */
176 1.1 gwr if (cf->cf_loc[0] == -1)
177 1.1 gwr return 1;
178 1.1 gwr
179 1.1 gwr return 0;
180 1.1 gwr }
181 1.1 gwr
182 1.1 gwr void
183 1.1 gwr zstty_attach(parent, self, aux)
184 1.1 gwr struct device *parent, *self;
185 1.1 gwr void *aux;
186 1.1 gwr
187 1.1 gwr {
188 1.1 gwr struct zsc_softc *zsc = (void *) parent;
189 1.1 gwr struct zstty_softc *zst = (void *) self;
190 1.1 gwr struct zsc_attach_args *args = aux;
191 1.1 gwr struct zs_chanstate *cs;
192 1.1 gwr struct cfdata *cf;
193 1.1 gwr struct tty *tp;
194 1.1 gwr int channel, tty_unit;
195 1.1 gwr dev_t dev;
196 1.1 gwr
197 1.1 gwr cf = zst->zst_dev.dv_cfdata;
198 1.3 gwr tty_unit = zst->zst_dev.dv_unit;
199 1.1 gwr channel = args->channel;
200 1.1 gwr cs = &zsc->zsc_cs[channel];
201 1.1 gwr cs->cs_private = zst;
202 1.1 gwr cs->cs_ops = &zsops_tty;
203 1.1 gwr
204 1.1 gwr zst->zst_cs = cs;
205 1.1 gwr zst->zst_swflags = cf->cf_flags; /* softcar, etc. */
206 1.1 gwr zst->zst_hwflags = args->hwflags;
207 1.1 gwr dev = makedev(ZSTTY_MAJOR, tty_unit);
208 1.1 gwr
209 1.1 gwr if (zst->zst_swflags)
210 1.1 gwr printf(" flags 0x%x", zst->zst_swflags);
211 1.1 gwr
212 1.1 gwr if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE)
213 1.1 gwr printf(" (console)");
214 1.1 gwr else {
215 1.1 gwr #ifdef KGDB
216 1.1 gwr /*
217 1.1 gwr * Allow kgdb to "take over" this port. If this port is
218 1.1 gwr * NOT the kgdb port, zs_check_kgdb() will return zero.
219 1.1 gwr * If it IS the kgdb port, it will print "kgdb,...\n"
220 1.1 gwr * and then return non-zero.
221 1.1 gwr */
222 1.1 gwr if (zs_check_kgdb(cs, dev)) {
223 1.1 gwr /*
224 1.1 gwr * This is the kgdb port (exclusive use)
225 1.1 gwr * so skip the normal attach code.
226 1.1 gwr */
227 1.1 gwr return;
228 1.1 gwr }
229 1.1 gwr #endif
230 1.1 gwr }
231 1.1 gwr printf("\n");
232 1.1 gwr
233 1.6 gwr tp = ttymalloc();
234 1.1 gwr tp->t_dev = dev;
235 1.1 gwr tp->t_oproc = zsstart;
236 1.1 gwr tp->t_param = zsparam;
237 1.1 gwr
238 1.6 gwr zst->zst_tty = tp;
239 1.6 gwr zst->zst_ringmask = zstty_rbuf_size - 1;
240 1.6 gwr zst->zst_rbuf = malloc(zstty_rbuf_size * sizeof(zst->zst_rbuf[0]),
241 1.6 gwr M_DEVBUF, M_WAITOK);
242 1.6 gwr
243 1.1 gwr /*
244 1.1 gwr * Hardware init
245 1.1 gwr */
246 1.1 gwr if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE) {
247 1.1 gwr /* This unit is the console. */
248 1.1 gwr zst->zst_swflags |= TIOCFLAG_SOFTCAR;
249 1.1 gwr /* Call _param so interrupts get enabled. */
250 1.1 gwr cs->cs_defspeed = zs_getspeed(cs);
251 1.1 gwr tp->t_ispeed = cs->cs_defspeed;
252 1.1 gwr tp->t_ospeed = cs->cs_defspeed;
253 1.1 gwr tp->t_cflag = ZSTTY_DEF_CFLAG;
254 1.1 gwr (void) zsparam(tp, &tp->t_termios);
255 1.1 gwr } else {
256 1.1 gwr /* Not the console; may need reset. */
257 1.1 gwr int reset, s;
258 1.1 gwr reset = (channel == 0) ?
259 1.1 gwr ZSWR9_A_RESET : ZSWR9_B_RESET;
260 1.1 gwr s = splzs();
261 1.2 gwr zs_write_reg(cs, 9, reset);
262 1.1 gwr splx(s);
263 1.1 gwr }
264 1.1 gwr
265 1.1 gwr /*
266 1.1 gwr * Initialize state of modem control lines (DTR).
267 1.1 gwr * If softcar is set, turn on DTR now and leave it.
268 1.1 gwr * otherwise, turn off DTR now, and raise in open.
269 1.1 gwr * (Keeps modem from answering too early.)
270 1.1 gwr */
271 1.1 gwr zs_modem(zst, (zst->zst_swflags & TIOCFLAG_SOFTCAR) ? 1 : 0);
272 1.1 gwr }
273 1.1 gwr
274 1.1 gwr
275 1.1 gwr /*
276 1.1 gwr * Return pointer to our tty.
277 1.1 gwr */
278 1.1 gwr struct tty *
279 1.1 gwr zstty(dev)
280 1.1 gwr dev_t dev;
281 1.1 gwr {
282 1.1 gwr struct zstty_softc *zst;
283 1.1 gwr int unit = minor(dev);
284 1.1 gwr
285 1.1 gwr #ifdef DIAGNOSTIC
286 1.4 thorpej if (unit >= zstty_cd.cd_ndevs)
287 1.1 gwr panic("zstty");
288 1.1 gwr #endif
289 1.4 thorpej zst = zstty_cd.cd_devs[unit];
290 1.1 gwr return (zst->zst_tty);
291 1.1 gwr }
292 1.1 gwr
293 1.1 gwr
294 1.1 gwr /*
295 1.1 gwr * Open a zs serial (tty) port.
296 1.1 gwr */
297 1.1 gwr int
298 1.1 gwr zsopen(dev, flags, mode, p)
299 1.1 gwr dev_t dev;
300 1.1 gwr int flags;
301 1.1 gwr int mode;
302 1.1 gwr struct proc *p;
303 1.1 gwr {
304 1.1 gwr register struct tty *tp;
305 1.1 gwr register struct zs_chanstate *cs;
306 1.1 gwr struct zstty_softc *zst;
307 1.1 gwr int error, s, unit;
308 1.1 gwr
309 1.1 gwr unit = minor(dev);
310 1.4 thorpej if (unit >= zstty_cd.cd_ndevs)
311 1.1 gwr return (ENXIO);
312 1.4 thorpej zst = zstty_cd.cd_devs[unit];
313 1.1 gwr if (zst == NULL)
314 1.1 gwr return (ENXIO);
315 1.1 gwr tp = zst->zst_tty;
316 1.1 gwr cs = zst->zst_cs;
317 1.1 gwr
318 1.1 gwr /* If KGDB took the line, then tp==NULL */
319 1.1 gwr if (tp == NULL)
320 1.1 gwr return (EBUSY);
321 1.1 gwr
322 1.1 gwr /* It's simpler to do this up here. */
323 1.1 gwr if (((tp->t_state & (TS_ISOPEN | TS_XCLUDE))
324 1.1 gwr == (TS_ISOPEN | TS_XCLUDE))
325 1.1 gwr && (p->p_ucred->cr_uid != 0) )
326 1.1 gwr {
327 1.1 gwr return (EBUSY);
328 1.1 gwr }
329 1.1 gwr
330 1.1 gwr s = spltty();
331 1.1 gwr
332 1.1 gwr if ((tp->t_state & TS_ISOPEN) == 0) {
333 1.1 gwr /* First open. */
334 1.1 gwr ttychars(tp);
335 1.1 gwr tp->t_iflag = TTYDEF_IFLAG;
336 1.1 gwr tp->t_oflag = TTYDEF_OFLAG;
337 1.1 gwr tp->t_cflag = ZSTTY_DEF_CFLAG;
338 1.1 gwr if (zst->zst_swflags & TIOCFLAG_CLOCAL)
339 1.1 gwr tp->t_cflag |= CLOCAL;
340 1.1 gwr if (zst->zst_swflags & TIOCFLAG_CRTSCTS)
341 1.1 gwr tp->t_cflag |= CRTSCTS;
342 1.1 gwr if (zst->zst_swflags & TIOCFLAG_MDMBUF)
343 1.1 gwr tp->t_cflag |= MDMBUF;
344 1.1 gwr tp->t_lflag = TTYDEF_LFLAG;
345 1.1 gwr tp->t_ispeed = tp->t_ospeed = cs->cs_defspeed;
346 1.1 gwr (void) zsparam(tp, &tp->t_termios);
347 1.1 gwr ttsetwater(tp);
348 1.1 gwr /* Flush any pending input. */
349 1.1 gwr zst->zst_rbget = zst->zst_rbput;
350 1.1 gwr zs_iflush(cs); /* XXX */
351 1.1 gwr /* Turn on DTR */
352 1.1 gwr zs_modem(zst, 1);
353 1.1 gwr if (zst->zst_swflags & TIOCFLAG_SOFTCAR) {
354 1.1 gwr tp->t_state |= TS_CARR_ON;
355 1.1 gwr }
356 1.1 gwr }
357 1.1 gwr error = 0;
358 1.1 gwr
359 1.1 gwr /* Wait for carrier. */
360 1.1 gwr for (;;) {
361 1.1 gwr
362 1.1 gwr /* Might never get status intr if carrier already on. */
363 1.5 gwr cs->cs_rr0 = zs_read_csr(cs);
364 1.5 gwr if (cs->cs_rr0 & ZSRR0_DCD) {
365 1.1 gwr tp->t_state |= TS_CARR_ON;
366 1.1 gwr break;
367 1.1 gwr }
368 1.1 gwr
369 1.1 gwr if ((tp->t_state & TS_CARR_ON) ||
370 1.1 gwr (tp->t_cflag & CLOCAL) ||
371 1.1 gwr (flags & O_NONBLOCK) )
372 1.1 gwr {
373 1.1 gwr break;
374 1.1 gwr }
375 1.1 gwr
376 1.1 gwr tp->t_state |= TS_WOPEN;
377 1.1 gwr error = ttysleep(tp, (caddr_t)&tp->t_rawq,
378 1.1 gwr TTIPRI | PCATCH, ttopen, 0);
379 1.1 gwr if (error) {
380 1.1 gwr if ((tp->t_state & TS_ISOPEN) == 0) {
381 1.1 gwr /* Never get here with softcar */
382 1.1 gwr zs_modem(zst, 0);
383 1.1 gwr tp->t_state &= ~TS_WOPEN;
384 1.1 gwr ttwakeup(tp);
385 1.1 gwr }
386 1.1 gwr break;
387 1.1 gwr }
388 1.1 gwr }
389 1.1 gwr
390 1.1 gwr splx(s);
391 1.1 gwr
392 1.1 gwr if (error == 0)
393 1.1 gwr error = linesw[tp->t_line].l_open(dev, tp);
394 1.1 gwr
395 1.1 gwr return (error);
396 1.1 gwr }
397 1.1 gwr
398 1.1 gwr /*
399 1.1 gwr * Close a zs serial port.
400 1.1 gwr */
401 1.1 gwr int
402 1.1 gwr zsclose(dev, flags, mode, p)
403 1.1 gwr dev_t dev;
404 1.1 gwr int flags;
405 1.1 gwr int mode;
406 1.1 gwr struct proc *p;
407 1.1 gwr {
408 1.1 gwr struct zstty_softc *zst;
409 1.1 gwr register struct zs_chanstate *cs;
410 1.1 gwr register struct tty *tp;
411 1.1 gwr struct zsinfo *zi;
412 1.1 gwr int hup, s;
413 1.1 gwr
414 1.4 thorpej zst = zstty_cd.cd_devs[minor(dev)];
415 1.1 gwr cs = zst->zst_cs;
416 1.1 gwr tp = zst->zst_tty;
417 1.1 gwr
418 1.1 gwr /* XXX This is for cons.c. */
419 1.1 gwr if ((tp->t_state & TS_ISOPEN) == 0)
420 1.1 gwr return 0;
421 1.1 gwr
422 1.1 gwr (*linesw[tp->t_line].l_close)(tp, flags);
423 1.1 gwr hup = tp->t_cflag & HUPCL;
424 1.1 gwr if (zst->zst_swflags & TIOCFLAG_SOFTCAR)
425 1.1 gwr hup = 0;
426 1.1 gwr if (hup) {
427 1.1 gwr zs_modem(zst, 0);
428 1.1 gwr /* hold low for 1 second */
429 1.1 gwr (void) tsleep((caddr_t)cs, TTIPRI, ttclos, hz);
430 1.1 gwr }
431 1.1 gwr if (cs->cs_creg[5] & ZSWR5_BREAK) {
432 1.1 gwr zs_break(cs, 0);
433 1.1 gwr }
434 1.1 gwr /* XXX - turn off interrupts? */
435 1.1 gwr
436 1.1 gwr ttyclose(tp);
437 1.1 gwr return (0);
438 1.1 gwr }
439 1.1 gwr
440 1.1 gwr /*
441 1.1 gwr * Read/write zs serial port.
442 1.1 gwr */
443 1.1 gwr int
444 1.1 gwr zsread(dev, uio, flags)
445 1.1 gwr dev_t dev;
446 1.1 gwr struct uio *uio;
447 1.1 gwr int flags;
448 1.1 gwr {
449 1.1 gwr register struct zstty_softc *zst;
450 1.1 gwr register struct tty *tp;
451 1.1 gwr
452 1.4 thorpej zst = zstty_cd.cd_devs[minor(dev)];
453 1.1 gwr tp = zst->zst_tty;
454 1.1 gwr return (linesw[tp->t_line].l_read(tp, uio, flags));
455 1.1 gwr }
456 1.1 gwr
457 1.1 gwr int
458 1.1 gwr zswrite(dev, uio, flags)
459 1.1 gwr dev_t dev;
460 1.1 gwr struct uio *uio;
461 1.1 gwr int flags;
462 1.1 gwr {
463 1.1 gwr register struct zstty_softc *zst;
464 1.1 gwr register struct tty *tp;
465 1.1 gwr
466 1.4 thorpej zst = zstty_cd.cd_devs[minor(dev)];
467 1.1 gwr tp = zst->zst_tty;
468 1.1 gwr return (linesw[tp->t_line].l_write(tp, uio, flags));
469 1.1 gwr }
470 1.1 gwr
471 1.1 gwr #define TIOCFLAG_ALL (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | \
472 1.1 gwr TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF )
473 1.1 gwr
474 1.1 gwr int
475 1.1 gwr zsioctl(dev, cmd, data, flag, p)
476 1.1 gwr dev_t dev;
477 1.1 gwr u_long cmd;
478 1.1 gwr caddr_t data;
479 1.1 gwr int flag;
480 1.1 gwr struct proc *p;
481 1.1 gwr {
482 1.1 gwr register struct zstty_softc *zst;
483 1.1 gwr register struct zs_chanstate *cs;
484 1.1 gwr register struct tty *tp;
485 1.1 gwr register int error, tmp;
486 1.1 gwr
487 1.4 thorpej zst = zstty_cd.cd_devs[minor(dev)];
488 1.1 gwr cs = zst->zst_cs;
489 1.1 gwr tp = zst->zst_tty;
490 1.1 gwr
491 1.1 gwr error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
492 1.1 gwr if (error >= 0)
493 1.1 gwr return (error);
494 1.1 gwr error = ttioctl(tp, cmd, data, flag, p);
495 1.1 gwr if (error >= 0)
496 1.1 gwr return (error);
497 1.1 gwr
498 1.1 gwr switch (cmd) {
499 1.1 gwr
500 1.1 gwr case TIOCSBRK:
501 1.1 gwr zs_break(cs, 1);
502 1.1 gwr break;
503 1.1 gwr
504 1.1 gwr case TIOCCBRK:
505 1.1 gwr zs_break(cs, 0);
506 1.1 gwr break;
507 1.1 gwr
508 1.1 gwr case TIOCGFLAGS:
509 1.1 gwr *(int *)data = zst->zst_swflags;
510 1.1 gwr break;
511 1.1 gwr
512 1.1 gwr case TIOCSFLAGS:
513 1.1 gwr error = suser(p->p_ucred, &p->p_acflag);
514 1.1 gwr if (error != 0)
515 1.1 gwr return (EPERM);
516 1.1 gwr tmp = *(int *)data;
517 1.1 gwr /* Check for random bits... */
518 1.1 gwr if (tmp & ~TIOCFLAG_ALL)
519 1.1 gwr return(EINVAL);
520 1.1 gwr /* Silently enforce softcar on the console. */
521 1.1 gwr if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE)
522 1.1 gwr tmp |= TIOCFLAG_SOFTCAR;
523 1.1 gwr /* These flags take effect during open. */
524 1.1 gwr zst->zst_swflags = tmp;
525 1.1 gwr break;
526 1.1 gwr
527 1.1 gwr case TIOCSDTR:
528 1.1 gwr zs_modem(zst, 1);
529 1.1 gwr break;
530 1.1 gwr
531 1.1 gwr case TIOCCDTR:
532 1.1 gwr zs_modem(zst, 0);
533 1.1 gwr break;
534 1.1 gwr
535 1.1 gwr case TIOCMSET:
536 1.1 gwr case TIOCMBIS:
537 1.1 gwr case TIOCMBIC:
538 1.1 gwr case TIOCMGET:
539 1.1 gwr default:
540 1.1 gwr return (ENOTTY);
541 1.1 gwr }
542 1.1 gwr return (0);
543 1.1 gwr }
544 1.1 gwr
545 1.1 gwr /*
546 1.1 gwr * Start or restart transmission.
547 1.1 gwr */
548 1.1 gwr static void
549 1.1 gwr zsstart(tp)
550 1.1 gwr register struct tty *tp;
551 1.1 gwr {
552 1.1 gwr register struct zstty_softc *zst;
553 1.1 gwr register struct zs_chanstate *cs;
554 1.1 gwr register int s, nch;
555 1.1 gwr
556 1.4 thorpej zst = zstty_cd.cd_devs[minor(tp->t_dev)];
557 1.1 gwr cs = zst->zst_cs;
558 1.1 gwr
559 1.1 gwr s = spltty();
560 1.1 gwr
561 1.1 gwr /*
562 1.1 gwr * If currently active or delaying, no need to do anything.
563 1.1 gwr */
564 1.1 gwr if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP))
565 1.1 gwr goto out;
566 1.1 gwr
567 1.1 gwr /*
568 1.1 gwr * If there are sleepers, and output has drained below low
569 1.1 gwr * water mark, awaken.
570 1.1 gwr */
571 1.1 gwr if (tp->t_outq.c_cc <= tp->t_lowat) {
572 1.1 gwr if (tp->t_state & TS_ASLEEP) {
573 1.1 gwr tp->t_state &= ~TS_ASLEEP;
574 1.1 gwr wakeup((caddr_t)&tp->t_outq);
575 1.1 gwr }
576 1.1 gwr selwakeup(&tp->t_wsel);
577 1.1 gwr }
578 1.1 gwr
579 1.1 gwr nch = ndqb(&tp->t_outq, 0); /* XXX */
580 1.1 gwr if (nch) {
581 1.1 gwr register char *p = tp->t_outq.c_cf;
582 1.1 gwr
583 1.1 gwr /* mark busy, enable tx done interrupts, & send first byte */
584 1.1 gwr tp->t_state |= TS_BUSY;
585 1.1 gwr (void) splzs();
586 1.1 gwr
587 1.1 gwr cs->cs_preg[1] |= ZSWR1_TIE;
588 1.1 gwr cs->cs_creg[1] |= ZSWR1_TIE;
589 1.2 gwr zs_write_reg(cs, 1, cs->cs_creg[1]);
590 1.2 gwr zs_write_data(cs, *p);
591 1.1 gwr zst->zst_tba = p + 1;
592 1.1 gwr zst->zst_tbc = nch - 1;
593 1.1 gwr } else {
594 1.1 gwr /*
595 1.1 gwr * Nothing to send, turn off transmit done interrupts.
596 1.1 gwr * This is useful if something is doing polled output.
597 1.1 gwr */
598 1.1 gwr (void) splzs();
599 1.1 gwr cs->cs_preg[1] &= ~ZSWR1_TIE;
600 1.1 gwr cs->cs_creg[1] &= ~ZSWR1_TIE;
601 1.2 gwr zs_write_reg(cs, 1, cs->cs_creg[1]);
602 1.1 gwr }
603 1.1 gwr out:
604 1.1 gwr splx(s);
605 1.1 gwr }
606 1.1 gwr
607 1.1 gwr /*
608 1.1 gwr * Stop output, e.g., for ^S or output flush.
609 1.1 gwr */
610 1.1 gwr int
611 1.1 gwr zsstop(tp, flag)
612 1.1 gwr struct tty *tp;
613 1.1 gwr int flag;
614 1.1 gwr {
615 1.1 gwr register struct zstty_softc *zst;
616 1.1 gwr register struct zs_chanstate *cs;
617 1.1 gwr register int s;
618 1.1 gwr
619 1.4 thorpej zst = zstty_cd.cd_devs[minor(tp->t_dev)];
620 1.1 gwr cs = zst->zst_cs;
621 1.1 gwr
622 1.1 gwr s = splzs();
623 1.1 gwr if (tp->t_state & TS_BUSY) {
624 1.1 gwr /*
625 1.1 gwr * Device is transmitting; must stop it.
626 1.1 gwr */
627 1.1 gwr zst->zst_tbc = 0;
628 1.1 gwr if ((tp->t_state & TS_TTSTOP) == 0)
629 1.1 gwr tp->t_state |= TS_FLUSH;
630 1.1 gwr }
631 1.1 gwr splx(s);
632 1.1 gwr return (0);
633 1.1 gwr }
634 1.1 gwr
635 1.1 gwr /*
636 1.1 gwr * Set ZS tty parameters from termios.
637 1.1 gwr * XXX - Should just copy the whole termios after
638 1.1 gwr * making sure all the changes could be done.
639 1.1 gwr * XXX - Only whack the UART when params change...
640 1.1 gwr */
641 1.1 gwr static int
642 1.1 gwr zsparam(tp, t)
643 1.1 gwr register struct tty *tp;
644 1.1 gwr register struct termios *t;
645 1.1 gwr {
646 1.1 gwr register struct zstty_softc *zst;
647 1.1 gwr register struct zs_chanstate *cs;
648 1.1 gwr register int s, bps, cflag, tconst;
649 1.1 gwr u_char tmp3, tmp4, tmp5, reset;
650 1.1 gwr
651 1.4 thorpej zst = zstty_cd.cd_devs[minor(tp->t_dev)];
652 1.1 gwr cs = zst->zst_cs;
653 1.1 gwr
654 1.1 gwr /*
655 1.1 gwr * Because PCLK is only run at 4.9 MHz, the fastest we
656 1.1 gwr * can go is 51200 baud (this corresponds to TC=1).
657 1.1 gwr * This is somewhat unfortunate as there is no real
658 1.1 gwr * reason we should not be able to handle higher rates.
659 1.1 gwr */
660 1.1 gwr bps = t->c_ospeed;
661 1.1 gwr if (bps < 0 || (t->c_ispeed && t->c_ispeed != bps))
662 1.1 gwr return (EINVAL);
663 1.1 gwr if (bps == 0) {
664 1.1 gwr /* stty 0 => drop DTR and RTS */
665 1.1 gwr zs_modem(zst, 0);
666 1.1 gwr return (0);
667 1.1 gwr }
668 1.1 gwr tconst = BPS_TO_TCONST(cs->cs_pclk_div16, bps);
669 1.1 gwr if (tconst < 0)
670 1.1 gwr return (EINVAL);
671 1.1 gwr
672 1.1 gwr /* Convert back to make sure we can do it. */
673 1.1 gwr bps = TCONST_TO_BPS(cs->cs_pclk_div16, tconst);
674 1.1 gwr if (bps != t->c_ospeed)
675 1.1 gwr return (EINVAL);
676 1.1 gwr tp->t_ispeed = tp->t_ospeed = bps;
677 1.1 gwr
678 1.1 gwr cflag = t->c_cflag;
679 1.1 gwr tp->t_cflag = cflag;
680 1.1 gwr
681 1.1 gwr /*
682 1.1 gwr * Block interrupts so that state will not
683 1.1 gwr * be altered until we are done setting it up.
684 1.1 gwr */
685 1.1 gwr s = splzs();
686 1.1 gwr
687 1.1 gwr /*
688 1.1 gwr * Initial values in cs_preg are set before
689 1.1 gwr * our attach routine is called. The master
690 1.1 gwr * interrupt enable is handled by zsc.c
691 1.1 gwr */
692 1.1 gwr
693 1.1 gwr cs->cs_preg[12] = tconst;
694 1.1 gwr cs->cs_preg[13] = tconst >> 8;
695 1.1 gwr
696 1.1 gwr switch (cflag & CSIZE) {
697 1.1 gwr case CS5:
698 1.1 gwr tmp3 = ZSWR3_RX_5;
699 1.1 gwr tmp5 = ZSWR5_TX_5;
700 1.1 gwr break;
701 1.1 gwr case CS6:
702 1.1 gwr tmp3 = ZSWR3_RX_6;
703 1.1 gwr tmp5 = ZSWR5_TX_6;
704 1.1 gwr break;
705 1.1 gwr case CS7:
706 1.1 gwr tmp3 = ZSWR3_RX_7;
707 1.1 gwr tmp5 = ZSWR5_TX_7;
708 1.1 gwr break;
709 1.1 gwr case CS8:
710 1.1 gwr default:
711 1.1 gwr tmp3 = ZSWR3_RX_8;
712 1.1 gwr tmp5 = ZSWR5_TX_8;
713 1.1 gwr break;
714 1.1 gwr }
715 1.1 gwr
716 1.1 gwr /*
717 1.1 gwr * Output hardware flow control on the chip is horrendous: if
718 1.1 gwr * carrier detect drops, the receiver is disabled. Hence we
719 1.1 gwr * can only do this when the carrier is on.
720 1.1 gwr */
721 1.1 gwr tmp3 |= ZSWR3_RX_ENABLE;
722 1.1 gwr if (cflag & CCTS_OFLOW) {
723 1.2 gwr if (zs_read_csr(cs) & ZSRR0_DCD)
724 1.1 gwr tmp3 |= ZSWR3_HFC;
725 1.1 gwr }
726 1.1 gwr
727 1.1 gwr cs->cs_preg[3] = tmp3;
728 1.1 gwr cs->cs_preg[5] = tmp5 | ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
729 1.1 gwr
730 1.1 gwr tmp4 = ZSWR4_CLK_X16 | (cflag & CSTOPB ? ZSWR4_TWOSB : ZSWR4_ONESB);
731 1.1 gwr if ((cflag & PARODD) == 0)
732 1.1 gwr tmp4 |= ZSWR4_EVENP;
733 1.1 gwr if (cflag & PARENB)
734 1.1 gwr tmp4 |= ZSWR4_PARENB;
735 1.1 gwr cs->cs_preg[4] = tmp4;
736 1.1 gwr
737 1.1 gwr /*
738 1.1 gwr * If nothing is being transmitted, set up new current values,
739 1.1 gwr * else mark them as pending.
740 1.1 gwr */
741 1.1 gwr if (cs->cs_heldchange == 0) {
742 1.1 gwr if (tp->t_state & TS_BUSY) {
743 1.1 gwr zst->zst_heldtbc = zst->zst_tbc;
744 1.1 gwr zst->zst_tbc = 0;
745 1.1 gwr cs->cs_heldchange = 1;
746 1.1 gwr } else {
747 1.1 gwr zs_loadchannelregs(cs);
748 1.1 gwr }
749 1.1 gwr }
750 1.1 gwr splx(s);
751 1.1 gwr return (0);
752 1.1 gwr }
753 1.1 gwr
754 1.1 gwr /*
755 1.1 gwr * Raise or lower modem control (DTR/RTS) signals. If a character is
756 1.1 gwr * in transmission, the change is deferred.
757 1.1 gwr */
758 1.1 gwr static void
759 1.1 gwr zs_modem(zst, onoff)
760 1.1 gwr struct zstty_softc *zst;
761 1.1 gwr int onoff;
762 1.1 gwr {
763 1.1 gwr struct zs_chanstate *cs;
764 1.1 gwr struct tty *tp;
765 1.1 gwr int s, bis, and;
766 1.1 gwr
767 1.1 gwr cs = zst->zst_cs;
768 1.1 gwr tp = zst->zst_tty;
769 1.1 gwr
770 1.1 gwr if (onoff) {
771 1.1 gwr bis = ZSWR5_DTR | ZSWR5_RTS;
772 1.1 gwr and = ~0;
773 1.1 gwr } else {
774 1.1 gwr bis = 0;
775 1.1 gwr and = ~(ZSWR5_DTR | ZSWR5_RTS);
776 1.1 gwr }
777 1.1 gwr s = splzs();
778 1.1 gwr cs->cs_preg[5] = (cs->cs_preg[5] | bis) & and;
779 1.1 gwr if (cs->cs_heldchange == 0) {
780 1.1 gwr if (tp->t_state & TS_BUSY) {
781 1.1 gwr zst->zst_heldtbc = zst->zst_tbc;
782 1.1 gwr zst->zst_tbc = 0;
783 1.1 gwr cs->cs_heldchange = 1;
784 1.1 gwr } else {
785 1.1 gwr cs->cs_creg[5] = (cs->cs_creg[5] | bis) & and;
786 1.2 gwr zs_write_reg(cs, 5, cs->cs_creg[5]);
787 1.1 gwr }
788 1.1 gwr }
789 1.1 gwr splx(s);
790 1.1 gwr }
791 1.1 gwr
792 1.1 gwr
793 1.1 gwr /****************************************************************
794 1.1 gwr * Interface to the lower layer (zscc)
795 1.1 gwr ****************************************************************/
796 1.3 gwr
797 1.3 gwr /*
798 1.3 gwr * XXX: need to do input flow-control to avoid ring overrun.
799 1.3 gwr */
800 1.1 gwr
801 1.6 gwr /*
802 1.6 gwr * receiver ready interrupt. (splzs)
803 1.6 gwr */
804 1.6 gwr static void
805 1.1 gwr zstty_rxint(cs)
806 1.1 gwr register struct zs_chanstate *cs;
807 1.1 gwr {
808 1.1 gwr register struct zstty_softc *zst;
809 1.6 gwr register put, put_next, ringmask;
810 1.1 gwr register u_char c, rr0, rr1;
811 1.1 gwr
812 1.1 gwr zst = cs->cs_private;
813 1.1 gwr put = zst->zst_rbput;
814 1.6 gwr ringmask = zst->zst_ringmask;
815 1.1 gwr
816 1.1 gwr nextchar:
817 1.1 gwr
818 1.5 gwr /*
819 1.5 gwr * First read the status, because reading the received char
820 1.5 gwr * destroys the status of this char.
821 1.5 gwr */
822 1.2 gwr rr1 = zs_read_reg(cs, 1);
823 1.5 gwr c = zs_read_data(cs);
824 1.1 gwr
825 1.1 gwr if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
826 1.1 gwr /* Clear the receive error. */
827 1.2 gwr zs_write_csr(cs, ZSWR0_RESET_ERRORS);
828 1.1 gwr }
829 1.1 gwr
830 1.1 gwr zst->zst_rbuf[put] = (c << 8) | rr1;
831 1.6 gwr put_next = (put + 1) & ringmask;
832 1.1 gwr
833 1.1 gwr /* Would overrun if increment makes (put==get). */
834 1.1 gwr if (put_next == zst->zst_rbget) {
835 1.1 gwr zst->zst_intr_flags |= INTR_RX_OVERRUN;
836 1.1 gwr } else {
837 1.1 gwr /* OK, really increment. */
838 1.1 gwr put = put_next;
839 1.1 gwr }
840 1.1 gwr
841 1.1 gwr /* Keep reading until the FIFO is empty. */
842 1.2 gwr rr0 = zs_read_csr(cs);
843 1.1 gwr if (rr0 & ZSRR0_RX_READY)
844 1.1 gwr goto nextchar;
845 1.1 gwr
846 1.1 gwr /* Done reading. */
847 1.1 gwr zst->zst_rbput = put;
848 1.1 gwr
849 1.1 gwr /* Ask for softint() call. */
850 1.1 gwr cs->cs_softreq = 1;
851 1.1 gwr }
852 1.1 gwr
853 1.6 gwr /*
854 1.6 gwr * transmitter ready interrupt. (splzs)
855 1.6 gwr */
856 1.6 gwr static void
857 1.1 gwr zstty_txint(cs)
858 1.1 gwr register struct zs_chanstate *cs;
859 1.1 gwr {
860 1.1 gwr register struct zstty_softc *zst;
861 1.6 gwr register int count;
862 1.1 gwr
863 1.1 gwr zst = cs->cs_private;
864 1.1 gwr count = zst->zst_tbc;
865 1.1 gwr
866 1.6 gwr /*
867 1.6 gwr * If our transmit buffer still has data,
868 1.6 gwr * just send the next character.
869 1.6 gwr */
870 1.1 gwr if (count > 0) {
871 1.1 gwr /* Send the next char. */
872 1.6 gwr zst->zst_tbc = --count;
873 1.2 gwr zs_write_data(cs, *zst->zst_tba);
874 1.2 gwr zst->zst_tba++;
875 1.6 gwr return;
876 1.1 gwr }
877 1.1 gwr
878 1.6 gwr zs_write_csr(cs, ZSWR0_RESET_TXINT);
879 1.6 gwr
880 1.6 gwr /* Ask the softint routine for more output. */
881 1.6 gwr zst->zst_intr_flags |= INTR_TX_EMPTY;
882 1.6 gwr cs->cs_softreq = 1;
883 1.1 gwr }
884 1.1 gwr
885 1.6 gwr /*
886 1.6 gwr * status change interrupt. (splzs)
887 1.6 gwr */
888 1.6 gwr static void
889 1.1 gwr zstty_stint(cs)
890 1.1 gwr register struct zs_chanstate *cs;
891 1.1 gwr {
892 1.1 gwr register struct zstty_softc *zst;
893 1.6 gwr register struct tty *tp;
894 1.6 gwr register u_char rr0;
895 1.1 gwr
896 1.1 gwr zst = cs->cs_private;
897 1.6 gwr tp = zst->zst_tty;
898 1.1 gwr
899 1.2 gwr rr0 = zs_read_csr(cs);
900 1.2 gwr zs_write_csr(cs, ZSWR0_RESET_STATUS);
901 1.1 gwr
902 1.6 gwr /*
903 1.6 gwr * The chip's hardware flow control is, as noted in zsreg.h,
904 1.6 gwr * busted---if the DCD line goes low the chip shuts off the
905 1.6 gwr * receiver (!). If we want hardware CTS flow control but do
906 1.6 gwr * not have it, and carrier is now on, turn HFC on; if we have
907 1.6 gwr * HFC now but carrier has gone low, turn it off.
908 1.6 gwr */
909 1.6 gwr if (rr0 & ZSRR0_DCD) {
910 1.6 gwr if (tp->t_cflag & CCTS_OFLOW &&
911 1.6 gwr (cs->cs_creg[3] & ZSWR3_HFC) == 0) {
912 1.6 gwr cs->cs_creg[3] |= ZSWR3_HFC;
913 1.6 gwr zs_write_reg(cs, 3, cs->cs_creg[3]);
914 1.6 gwr }
915 1.6 gwr } else {
916 1.6 gwr if (cs->cs_creg[3] & ZSWR3_HFC) {
917 1.6 gwr cs->cs_creg[3] &= ~ZSWR3_HFC;
918 1.6 gwr zs_write_reg(cs, 3, cs->cs_creg[3]);
919 1.6 gwr }
920 1.6 gwr }
921 1.6 gwr
922 1.6 gwr /*
923 1.6 gwr * Check here for console break, so that we can abort
924 1.6 gwr * even when interrupts are locking up the machine.
925 1.6 gwr */
926 1.6 gwr if ((rr0 & ZSRR0_BREAK) &&
927 1.1 gwr (zst->zst_hwflags & ZS_HWFLAG_CONSOLE))
928 1.1 gwr {
929 1.1 gwr zs_abort();
930 1.6 gwr return;
931 1.1 gwr }
932 1.1 gwr
933 1.6 gwr cs->cs_rr0_new = rr0;
934 1.1 gwr zst->zst_intr_flags |= INTR_ST_CHECK;
935 1.6 gwr
936 1.1 gwr /* Ask for softint() call. */
937 1.1 gwr cs->cs_softreq = 1;
938 1.1 gwr }
939 1.1 gwr
940 1.1 gwr /*
941 1.1 gwr * Print out a ring or fifo overrun error message.
942 1.1 gwr */
943 1.1 gwr static void
944 1.1 gwr zsoverrun(zst, ptime, what)
945 1.1 gwr struct zstty_softc *zst;
946 1.1 gwr long *ptime;
947 1.1 gwr char *what;
948 1.1 gwr {
949 1.1 gwr
950 1.1 gwr if (*ptime != time.tv_sec) {
951 1.1 gwr *ptime = time.tv_sec;
952 1.1 gwr log(LOG_WARNING, "%s: %s overrun\n",
953 1.1 gwr zst->zst_dev.dv_xname, what);
954 1.1 gwr }
955 1.1 gwr }
956 1.1 gwr
957 1.6 gwr /*
958 1.6 gwr * Software interrupt. Called at zssoft
959 1.6 gwr */
960 1.6 gwr static void
961 1.1 gwr zstty_softint(cs)
962 1.1 gwr struct zs_chanstate *cs;
963 1.1 gwr {
964 1.1 gwr register struct zstty_softc *zst;
965 1.1 gwr register struct linesw *line;
966 1.1 gwr register struct tty *tp;
967 1.1 gwr register int get, c, s;
968 1.6 gwr int intr_flags, ringmask;
969 1.1 gwr register u_short ring_data;
970 1.1 gwr register u_char rr0, rr1;
971 1.1 gwr
972 1.1 gwr zst = cs->cs_private;
973 1.1 gwr tp = zst->zst_tty;
974 1.1 gwr line = &linesw[tp->t_line];
975 1.6 gwr ringmask = zst->zst_ringmask;
976 1.1 gwr
977 1.1 gwr /* Atomically get and clear flags. */
978 1.1 gwr s = splzs();
979 1.1 gwr intr_flags = zst->zst_intr_flags;
980 1.1 gwr zst->zst_intr_flags = 0;
981 1.6 gwr
982 1.6 gwr /*
983 1.6 gwr * Lower to tty priority while servicing the ring.
984 1.6 gwr */
985 1.6 gwr (void) spltty();
986 1.1 gwr
987 1.1 gwr if (intr_flags & INTR_RX_OVERRUN) {
988 1.1 gwr /* May turn this on again below. */
989 1.1 gwr intr_flags &= ~INTR_RX_OVERRUN;
990 1.6 gwr zsoverrun(zst, &zst->zst_rotime, "ring");
991 1.1 gwr }
992 1.1 gwr
993 1.1 gwr /*
994 1.1 gwr * Copy data from the receive ring into the tty layer.
995 1.1 gwr */
996 1.1 gwr get = zst->zst_rbget;
997 1.1 gwr while (get != zst->zst_rbput) {
998 1.1 gwr ring_data = zst->zst_rbuf[get];
999 1.6 gwr get = (get + 1) & ringmask;
1000 1.1 gwr
1001 1.1 gwr if (ring_data & ZSRR1_DO)
1002 1.1 gwr intr_flags |= INTR_RX_OVERRUN;
1003 1.1 gwr /* low byte of ring_data is rr1 */
1004 1.1 gwr c = (ring_data >> 8) & 0xff;
1005 1.1 gwr if (ring_data & ZSRR1_FE)
1006 1.1 gwr c |= TTY_FE;
1007 1.1 gwr if (ring_data & ZSRR1_PE)
1008 1.1 gwr c |= TTY_PE;
1009 1.1 gwr
1010 1.1 gwr line->l_rint(c, tp);
1011 1.1 gwr }
1012 1.1 gwr zst->zst_rbget = get;
1013 1.1 gwr
1014 1.6 gwr /*
1015 1.6 gwr * If the overrun flag is set now, it was set while
1016 1.6 gwr * copying char/status pairs from the ring, which
1017 1.6 gwr * means this was a hardware (fifo) overrun.
1018 1.6 gwr */
1019 1.1 gwr if (intr_flags & INTR_RX_OVERRUN) {
1020 1.6 gwr zsoverrun(zst, &zst->zst_fotime, "fifo");
1021 1.1 gwr }
1022 1.1 gwr
1023 1.1 gwr if (intr_flags & INTR_TX_EMPTY) {
1024 1.1 gwr /*
1025 1.6 gwr * The transmitter output buffer count is zero.
1026 1.6 gwr * If we suspended output for a "held" change,
1027 1.6 gwr * then handle that now and resume. Otherwise,
1028 1.6 gwr * try to start a new output chunk.
1029 1.1 gwr */
1030 1.1 gwr if (cs->cs_heldchange) {
1031 1.6 gwr (void) splzs();
1032 1.2 gwr rr0 = zs_read_csr(cs);
1033 1.1 gwr if ((rr0 & ZSRR0_DCD) == 0)
1034 1.1 gwr cs->cs_preg[3] &= ~ZSWR3_HFC;
1035 1.1 gwr zs_loadchannelregs(cs);
1036 1.6 gwr (void) spltty();
1037 1.1 gwr cs->cs_heldchange = 0;
1038 1.1 gwr if (zst->zst_heldtbc &&
1039 1.1 gwr (tp->t_state & TS_TTSTOP) == 0)
1040 1.1 gwr {
1041 1.1 gwr zst->zst_tbc = zst->zst_heldtbc - 1;
1042 1.2 gwr zs_write_data(cs, *zst->zst_tba);
1043 1.2 gwr zst->zst_tba++;
1044 1.1 gwr goto tx_resumed;
1045 1.1 gwr }
1046 1.1 gwr }
1047 1.1 gwr tp->t_state &= ~TS_BUSY;
1048 1.1 gwr if (tp->t_state & TS_FLUSH)
1049 1.1 gwr tp->t_state &= ~TS_FLUSH;
1050 1.1 gwr else
1051 1.1 gwr ndflush(&tp->t_outq, zst->zst_tba -
1052 1.1 gwr (caddr_t) tp->t_outq.c_cf);
1053 1.1 gwr line->l_start(tp);
1054 1.1 gwr tx_resumed:
1055 1.1 gwr }
1056 1.1 gwr
1057 1.1 gwr if (intr_flags & INTR_ST_CHECK) {
1058 1.1 gwr /*
1059 1.6 gwr * Status line change. HFC bit is run in
1060 1.6 gwr * hardware interrupt, to avoid locking
1061 1.6 gwr * at splzs here.
1062 1.1 gwr */
1063 1.6 gwr rr0 = cs->cs_rr0_new;
1064 1.1 gwr if ((rr0 ^ cs->cs_rr0) & ZSRR0_DCD) {
1065 1.1 gwr c = ((rr0 & ZSRR0_DCD) != 0);
1066 1.1 gwr if (line->l_modem(tp, c) == 0)
1067 1.1 gwr zs_modem(zst, c);
1068 1.1 gwr }
1069 1.1 gwr cs->cs_rr0 = rr0;
1070 1.1 gwr }
1071 1.1 gwr
1072 1.6 gwr splx(s);
1073 1.1 gwr }
1074 1.1 gwr
1075 1.1 gwr struct zsops zsops_tty = {
1076 1.1 gwr zstty_rxint, /* receive char available */
1077 1.1 gwr zstty_stint, /* external/status */
1078 1.1 gwr zstty_txint, /* xmit buffer empty */
1079 1.1 gwr zstty_softint, /* process software interrupt */
1080 1.1 gwr };
1081 1.1 gwr
1082