fwohci.c revision 1.105.2.2
1 /* $NetBSD: fwohci.c,v 1.105.2.2 2007/05/07 10:55:28 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.86 2007/03/19 03:35:45 simokawa Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.105.2.2 2007/05/07 10:55:28 yamt Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 107 #include "ioconf.h" 108 #endif 109 110 #undef OHCI_DEBUG 111 112 static int nocyclemaster = 0; 113 #if defined(__FreeBSD__) 114 SYSCTL_DECL(_hw_firewire); 115 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 116 "Do not send cycle start packets"); 117 #elif defined(__NetBSD__) 118 /* 119 * Setup sysctl(3) MIB, hw.fwohci.* 120 * 121 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 122 */ 123 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 124 { 125 int rc; 126 const struct sysctlnode *node; 127 128 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 130 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 131 goto err; 132 } 133 134 if ((rc = sysctl_createv(clog, 0, NULL, &node, 135 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 136 SYSCTL_DESCR("fwohci controls"), 137 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 138 goto err; 139 } 140 141 /* fwohci no cyclemaster flag */ 142 if ((rc = sysctl_createv(clog, 0, NULL, &node, 143 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 144 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 145 NULL, 0, &nocyclemaster, 146 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 147 goto err; 148 } 149 return; 150 151 err: 152 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 153 } 154 #endif 155 156 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 157 "STOR","LOAD","NOP ","STOP", 158 "", "", "", "", "", "", "", ""}; 159 160 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 161 "UNDEF","REG","SYS","DEV"}; 162 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 163 static const char * const fwohcicode[32] = { 164 "No stat","Undef","long","miss Ack err", 165 "underrun","overrun","desc err", "data read err", 166 "data write err","bus reset","timeout","tcode err", 167 "Undef","Undef","unknown event","flushed", 168 "Undef","ack complete","ack pend","Undef", 169 "ack busy_X","ack busy_A","ack busy_B","Undef", 170 "Undef","Undef","Undef","ack tardy", 171 "Undef","ack data_err","ack type_err",""}; 172 173 #define MAX_SPEED 3 174 extern const char *fw_linkspeed[]; 175 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 176 177 static const struct tcode_info tinfo[] = { 178 /* hdr_len block flag*/ 179 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 180 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 181 /* 2 WRES */ {12, FWTI_RES}, 182 /* 3 XXX */ { 0, 0}, 183 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 184 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 185 /* 6 RRESQ */ {16, FWTI_RES}, 186 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 187 /* 8 CYCS */ { 0, 0}, 188 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 189 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 190 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 191 /* c XXX */ { 0, 0}, 192 /* d XXX */ { 0, 0}, 193 /* e PHY */ {12, FWTI_REQ}, 194 /* f XXX */ { 0, 0} 195 }; 196 197 #define OHCI_WRITE_SIGMASK 0xffff0000 198 #define OHCI_READ_SIGMASK 0xffff0000 199 200 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 201 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 202 203 static void fwohci_ibr (struct firewire_comm *); 204 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 205 static void fwohci_db_free (struct fwohci_dbch *); 206 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 207 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 208 static void fwohci_start_atq (struct firewire_comm *); 209 static void fwohci_start_ats (struct firewire_comm *); 210 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 211 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 212 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 213 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 214 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 215 static int fwohci_irx_enable (struct firewire_comm *, int); 216 static int fwohci_irx_disable (struct firewire_comm *, int); 217 #if BYTE_ORDER == BIG_ENDIAN 218 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 219 #endif 220 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 221 static int fwohci_itx_disable (struct firewire_comm *, int); 222 static void fwohci_timeout (void *); 223 static void fwohci_set_intr (struct firewire_comm *, int); 224 225 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 226 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 227 static void dump_db (struct fwohci_softc *, uint32_t); 228 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 229 static void dump_dma (struct fwohci_softc *, uint32_t); 230 static uint32_t fwohci_cyctimer (struct firewire_comm *); 231 static void fwohci_rbuf_update (struct fwohci_softc *, int); 232 static void fwohci_tbuf_update (struct fwohci_softc *, int); 233 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 234 #if FWOHCI_TASKQUEUE 235 static void fwohci_complete(void *, int); 236 #endif 237 #if defined(__NetBSD__) 238 static void fwohci_power(int, void *); 239 int fwohci_print(void *, const char *); 240 #endif 241 242 /* 243 * memory allocated for DMA programs 244 */ 245 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 246 247 #define NDB FWMAXQUEUE 248 249 #define OHCI_VERSION 0x00 250 #define OHCI_ATRETRY 0x08 251 #define OHCI_CROMHDR 0x18 252 #define OHCI_BUS_OPT 0x20 253 #define OHCI_BUSIRMC (1 << 31) 254 #define OHCI_BUSCMC (1 << 30) 255 #define OHCI_BUSISC (1 << 29) 256 #define OHCI_BUSBMC (1 << 28) 257 #define OHCI_BUSPMC (1 << 27) 258 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 259 OHCI_BUSBMC | OHCI_BUSPMC 260 261 #define OHCI_EUID_HI 0x24 262 #define OHCI_EUID_LO 0x28 263 264 #define OHCI_CROMPTR 0x34 265 #define OHCI_HCCCTL 0x50 266 #define OHCI_HCCCTLCLR 0x54 267 #define OHCI_AREQHI 0x100 268 #define OHCI_AREQHICLR 0x104 269 #define OHCI_AREQLO 0x108 270 #define OHCI_AREQLOCLR 0x10c 271 #define OHCI_PREQHI 0x110 272 #define OHCI_PREQHICLR 0x114 273 #define OHCI_PREQLO 0x118 274 #define OHCI_PREQLOCLR 0x11c 275 #define OHCI_PREQUPPER 0x120 276 277 #define OHCI_SID_BUF 0x64 278 #define OHCI_SID_CNT 0x68 279 #define OHCI_SID_ERR (1 << 31) 280 #define OHCI_SID_CNT_MASK 0xffc 281 282 #define OHCI_IT_STAT 0x90 283 #define OHCI_IT_STATCLR 0x94 284 #define OHCI_IT_MASK 0x98 285 #define OHCI_IT_MASKCLR 0x9c 286 287 #define OHCI_IR_STAT 0xa0 288 #define OHCI_IR_STATCLR 0xa4 289 #define OHCI_IR_MASK 0xa8 290 #define OHCI_IR_MASKCLR 0xac 291 292 #define OHCI_LNKCTL 0xe0 293 #define OHCI_LNKCTLCLR 0xe4 294 295 #define OHCI_PHYACCESS 0xec 296 #define OHCI_CYCLETIMER 0xf0 297 298 #define OHCI_DMACTL(off) (off) 299 #define OHCI_DMACTLCLR(off) (off + 4) 300 #define OHCI_DMACMD(off) (off + 0xc) 301 #define OHCI_DMAMATCH(off) (off + 0x10) 302 303 #define OHCI_ATQOFF 0x180 304 #define OHCI_ATQCTL OHCI_ATQOFF 305 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 306 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 307 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 308 309 #define OHCI_ATSOFF 0x1a0 310 #define OHCI_ATSCTL OHCI_ATSOFF 311 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 312 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 313 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 314 315 #define OHCI_ARQOFF 0x1c0 316 #define OHCI_ARQCTL OHCI_ARQOFF 317 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 318 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 319 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 320 321 #define OHCI_ARSOFF 0x1e0 322 #define OHCI_ARSCTL OHCI_ARSOFF 323 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 324 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 325 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 326 327 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 328 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 329 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 330 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 331 332 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 333 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 334 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 335 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 336 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 337 338 #if defined(__FreeBSD__) 339 d_ioctl_t fwohci_ioctl; 340 #elif defined(__NetBSD__) 341 dev_type_ioctl(fwohci_ioctl); 342 #endif 343 344 /* 345 * Communication with PHY device 346 */ 347 static uint32_t 348 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 349 { 350 uint32_t fun; 351 352 addr &= 0xf; 353 data &= 0xff; 354 355 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 356 OWRITE(sc, OHCI_PHYACCESS, fun); 357 DELAY(100); 358 359 return(fwphy_rddata( sc, addr)); 360 } 361 362 static uint32_t 363 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 364 { 365 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 366 int i; 367 uint32_t bm; 368 369 #define OHCI_CSR_DATA 0x0c 370 #define OHCI_CSR_COMP 0x10 371 #define OHCI_CSR_CONT 0x14 372 #define OHCI_BUS_MANAGER_ID 0 373 374 OWRITE(sc, OHCI_CSR_DATA, node); 375 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 376 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 377 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 378 DELAY(10); 379 bm = OREAD(sc, OHCI_CSR_DATA); 380 if((bm & 0x3f) == 0x3f) 381 bm = node; 382 if (firewire_debug) 383 device_printf(sc->fc.dev, 384 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 385 386 return(bm); 387 } 388 389 static uint32_t 390 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 391 { 392 uint32_t fun, stat; 393 u_int i, retry = 0; 394 395 addr &= 0xf; 396 #define MAX_RETRY 100 397 again: 398 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 399 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 400 OWRITE(sc, OHCI_PHYACCESS, fun); 401 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 402 fun = OREAD(sc, OHCI_PHYACCESS); 403 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 404 break; 405 DELAY(100); 406 } 407 if(i >= MAX_RETRY) { 408 if (firewire_debug) 409 device_printf(sc->fc.dev, "phy read failed(1).\n"); 410 if (++retry < MAX_RETRY) { 411 DELAY(100); 412 goto again; 413 } 414 } 415 /* Make sure that SCLK is started */ 416 stat = OREAD(sc, FWOHCI_INTSTAT); 417 if ((stat & OHCI_INT_REG_FAIL) != 0 || 418 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 419 if (firewire_debug) 420 device_printf(sc->fc.dev, "phy read failed(2).\n"); 421 if (++retry < MAX_RETRY) { 422 DELAY(100); 423 goto again; 424 } 425 } 426 if (firewire_debug || retry >= MAX_RETRY) 427 device_printf(sc->fc.dev, 428 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 429 #undef MAX_RETRY 430 return((fun >> PHYDEV_RDDATA )& 0xff); 431 } 432 /* Device specific ioctl. */ 433 FW_IOCTL(fwohci) 434 { 435 FW_IOCTL_START; 436 struct fwohci_softc *fc; 437 int err = 0; 438 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 439 uint32_t *dmach = (uint32_t *) data; 440 441 if(sc == NULL){ 442 return(EINVAL); 443 } 444 fc = (struct fwohci_softc *)sc->fc; 445 446 if (!data) 447 return(EINVAL); 448 449 switch (cmd) { 450 case FWOHCI_WRREG: 451 #define OHCI_MAX_REG 0x800 452 if(reg->addr <= OHCI_MAX_REG){ 453 OWRITE(fc, reg->addr, reg->data); 454 reg->data = OREAD(fc, reg->addr); 455 }else{ 456 err = EINVAL; 457 } 458 break; 459 case FWOHCI_RDREG: 460 if(reg->addr <= OHCI_MAX_REG){ 461 reg->data = OREAD(fc, reg->addr); 462 }else{ 463 err = EINVAL; 464 } 465 break; 466 /* Read DMA descriptors for debug */ 467 case DUMPDMA: 468 if(*dmach <= OHCI_MAX_DMA_CH ){ 469 dump_dma(fc, *dmach); 470 dump_db(fc, *dmach); 471 }else{ 472 err = EINVAL; 473 } 474 break; 475 /* Read/Write Phy registers */ 476 #define OHCI_MAX_PHY_REG 0xf 477 case FWOHCI_RDPHYREG: 478 if (reg->addr <= OHCI_MAX_PHY_REG) 479 reg->data = fwphy_rddata(fc, reg->addr); 480 else 481 err = EINVAL; 482 break; 483 case FWOHCI_WRPHYREG: 484 if (reg->addr <= OHCI_MAX_PHY_REG) 485 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 486 else 487 err = EINVAL; 488 break; 489 default: 490 err = EINVAL; 491 break; 492 } 493 return err; 494 } 495 496 static int 497 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 498 { 499 uint32_t reg, reg2; 500 int e1394a = 1; 501 /* 502 * probe PHY parameters 503 * 0. to prove PHY version, whether compliance of 1394a. 504 * 1. to probe maximum speed supported by the PHY and 505 * number of port supported by core-logic. 506 * It is not actually available port on your PC . 507 */ 508 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 509 DELAY(500); 510 511 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 512 513 if((reg >> 5) != 7 ){ 514 sc->fc.mode &= ~FWPHYASYST; 515 sc->fc.nport = reg & FW_PHY_NP; 516 sc->fc.speed = reg & FW_PHY_SPD >> 6; 517 if (sc->fc.speed > MAX_SPEED) { 518 device_printf(dev, "invalid speed %d (fixed to %d).\n", 519 sc->fc.speed, MAX_SPEED); 520 sc->fc.speed = MAX_SPEED; 521 } 522 device_printf(dev, 523 "Phy 1394 only %s, %d ports.\n", 524 fw_linkspeed[sc->fc.speed], sc->fc.nport); 525 }else{ 526 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 527 sc->fc.mode |= FWPHYASYST; 528 sc->fc.nport = reg & FW_PHY_NP; 529 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 530 if (sc->fc.speed > MAX_SPEED) { 531 device_printf(dev, "invalid speed %d (fixed to %d).\n", 532 sc->fc.speed, MAX_SPEED); 533 sc->fc.speed = MAX_SPEED; 534 } 535 device_printf(dev, 536 "Phy 1394a available %s, %d ports.\n", 537 fw_linkspeed[sc->fc.speed], sc->fc.nport); 538 539 /* check programPhyEnable */ 540 reg2 = fwphy_rddata(sc, 5); 541 #if 0 542 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 543 #else /* XXX force to enable 1394a */ 544 if (e1394a) { 545 #endif 546 if (firewire_debug) 547 device_printf(dev, 548 "Enable 1394a Enhancements\n"); 549 /* enable EAA EMC */ 550 reg2 |= 0x03; 551 /* set aPhyEnhanceEnable */ 552 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 553 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 554 } 555 #if 0 556 else { 557 /* for safe */ 558 reg2 &= ~0x83; 559 } 560 #endif 561 reg2 = fwphy_wrdata(sc, 5, reg2); 562 } 563 564 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 565 if((reg >> 5) == 7 ){ 566 reg = fwphy_rddata(sc, 4); 567 reg |= 1 << 6; 568 fwphy_wrdata(sc, 4, reg); 569 reg = fwphy_rddata(sc, 4); 570 } 571 return 0; 572 } 573 574 575 void 576 fwohci_reset(struct fwohci_softc *sc, device_t dev) 577 { 578 int i, max_rec, speed; 579 uint32_t reg, reg2; 580 struct fwohcidb_tr *db_tr; 581 582 /* Disable interrupts */ 583 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 584 585 /* Now stopping all DMA channels */ 586 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 587 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 588 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 589 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 590 591 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 592 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 593 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 594 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 595 } 596 597 /* FLUSH FIFO and reset Transmitter/Reciever */ 598 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 599 if (firewire_debug) 600 device_printf(dev, "resetting OHCI..."); 601 i = 0; 602 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 603 if (i++ > 100) break; 604 DELAY(1000); 605 } 606 if (firewire_debug) 607 printf("done (loop=%d)\n", i); 608 609 /* Probe phy */ 610 fwohci_probe_phy(sc, dev); 611 612 /* Probe link */ 613 reg = OREAD(sc, OHCI_BUS_OPT); 614 reg2 = reg | OHCI_BUSFNC; 615 max_rec = (reg & 0x0000f000) >> 12; 616 speed = (reg & 0x00000007); 617 device_printf(dev, "Link %s, max_rec %d bytes.\n", 618 fw_linkspeed[speed], MAXREC(max_rec)); 619 /* XXX fix max_rec */ 620 sc->fc.maxrec = sc->fc.speed + 8; 621 if (max_rec != sc->fc.maxrec) { 622 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 623 device_printf(dev, "max_rec %d -> %d\n", 624 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 625 } 626 if (firewire_debug) 627 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 628 OWRITE(sc, OHCI_BUS_OPT, reg2); 629 630 /* Initialize registers */ 631 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 632 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 633 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 634 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 635 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 636 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 637 638 /* Enable link */ 639 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 640 641 /* Force to start async RX DMA */ 642 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 643 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 644 fwohci_rx_enable(sc, &sc->arrq); 645 fwohci_rx_enable(sc, &sc->arrs); 646 647 /* Initialize async TX */ 648 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 649 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 650 651 /* AT Retries */ 652 OWRITE(sc, FWOHCI_RETRY, 653 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 654 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 655 656 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 657 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 658 sc->atrq.bottom = sc->atrq.top; 659 sc->atrs.bottom = sc->atrs.top; 660 661 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 662 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 663 db_tr->xfer = NULL; 664 } 665 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 666 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 667 db_tr->xfer = NULL; 668 } 669 670 671 /* Enable interrupts */ 672 OWRITE(sc, FWOHCI_INTMASK, 673 OHCI_INT_ERR | OHCI_INT_PHY_SID 674 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 675 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 676 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 677 fwohci_set_intr(&sc->fc, 1); 678 679 } 680 681 int 682 fwohci_init(struct fwohci_softc *sc, device_t dev) 683 { 684 int i, mver; 685 uint32_t reg; 686 uint8_t ui[8]; 687 688 #if FWOHCI_TASKQUEUE 689 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 690 #endif 691 692 /* OHCI version */ 693 reg = OREAD(sc, OHCI_VERSION); 694 mver = (reg >> 16) & 0xff; 695 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 696 mver, reg & 0xff, (reg>>24) & 1); 697 if (mver < 1 || mver > 9) { 698 device_printf(dev, "invalid OHCI version\n"); 699 return (ENXIO); 700 } 701 702 /* Available Isochronous DMA channel probe */ 703 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 704 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 705 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 706 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 707 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 708 for (i = 0; i < 0x20; i++) 709 if ((reg & (1 << i)) == 0) 710 break; 711 sc->fc.nisodma = i; 712 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 713 if (i == 0) 714 return (ENXIO); 715 716 sc->fc.arq = &sc->arrq.xferq; 717 sc->fc.ars = &sc->arrs.xferq; 718 sc->fc.atq = &sc->atrq.xferq; 719 sc->fc.ats = &sc->atrs.xferq; 720 721 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 722 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 723 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 724 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 725 726 sc->arrq.xferq.start = NULL; 727 sc->arrs.xferq.start = NULL; 728 sc->atrq.xferq.start = fwohci_start_atq; 729 sc->atrs.xferq.start = fwohci_start_ats; 730 731 sc->arrq.xferq.buf = NULL; 732 sc->arrs.xferq.buf = NULL; 733 sc->atrq.xferq.buf = NULL; 734 sc->atrs.xferq.buf = NULL; 735 736 sc->arrq.xferq.dmach = -1; 737 sc->arrs.xferq.dmach = -1; 738 sc->atrq.xferq.dmach = -1; 739 sc->atrs.xferq.dmach = -1; 740 741 sc->arrq.ndesc = 1; 742 sc->arrs.ndesc = 1; 743 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 744 sc->atrs.ndesc = 2; 745 746 sc->arrq.ndb = NDB; 747 sc->arrs.ndb = NDB / 2; 748 sc->atrq.ndb = NDB; 749 sc->atrs.ndb = NDB / 2; 750 751 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 752 sc->fc.it[i] = &sc->it[i].xferq; 753 sc->fc.ir[i] = &sc->ir[i].xferq; 754 sc->it[i].xferq.dmach = i; 755 sc->ir[i].xferq.dmach = i; 756 sc->it[i].ndb = 0; 757 sc->ir[i].ndb = 0; 758 } 759 760 sc->fc.tcode = tinfo; 761 sc->fc.dev = dev; 762 763 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 764 &sc->crom_dma, BUS_DMA_WAITOK); 765 if(sc->fc.config_rom == NULL){ 766 device_printf(dev, "config_rom alloc failed."); 767 return ENOMEM; 768 } 769 770 #if 0 771 bzero(&sc->fc.config_rom[0], CROMSIZE); 772 sc->fc.config_rom[1] = 0x31333934; 773 sc->fc.config_rom[2] = 0xf000a002; 774 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 775 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 776 sc->fc.config_rom[5] = 0; 777 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 778 779 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 780 #endif 781 782 783 /* SID recieve buffer must align 2^11 */ 784 #define OHCI_SIDSIZE (1 << 11) 785 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 786 &sc->sid_dma, BUS_DMA_WAITOK); 787 if (sc->sid_buf == NULL) { 788 device_printf(dev, "sid_buf alloc failed."); 789 return ENOMEM; 790 } 791 792 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 793 &sc->dummy_dma, BUS_DMA_WAITOK); 794 795 if (sc->dummy_dma.v_addr == NULL) { 796 device_printf(dev, "dummy_dma alloc failed."); 797 return ENOMEM; 798 } 799 800 fwohci_db_init(sc, &sc->arrq); 801 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 802 return ENOMEM; 803 804 fwohci_db_init(sc, &sc->arrs); 805 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 806 return ENOMEM; 807 808 fwohci_db_init(sc, &sc->atrq); 809 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 810 return ENOMEM; 811 812 fwohci_db_init(sc, &sc->atrs); 813 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 814 return ENOMEM; 815 816 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 817 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 818 for( i = 0 ; i < 8 ; i ++) 819 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 820 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 821 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 822 823 sc->fc.ioctl = fwohci_ioctl; 824 sc->fc.cyctimer = fwohci_cyctimer; 825 sc->fc.set_bmr = fwohci_set_bus_manager; 826 sc->fc.ibr = fwohci_ibr; 827 sc->fc.irx_enable = fwohci_irx_enable; 828 sc->fc.irx_disable = fwohci_irx_disable; 829 830 sc->fc.itx_enable = fwohci_itxbuf_enable; 831 sc->fc.itx_disable = fwohci_itx_disable; 832 #if BYTE_ORDER == BIG_ENDIAN 833 sc->fc.irx_post = fwohci_irx_post; 834 #else 835 sc->fc.irx_post = NULL; 836 #endif 837 sc->fc.itx_post = NULL; 838 sc->fc.timeout = fwohci_timeout; 839 sc->fc.poll = fwohci_poll; 840 sc->fc.set_intr = fwohci_set_intr; 841 842 sc->intmask = sc->irstat = sc->itstat = 0; 843 844 fw_init(&sc->fc); 845 fwohci_reset(sc, dev); 846 FWOHCI_INIT_END; 847 848 return 0; 849 } 850 851 void 852 fwohci_timeout(void *arg) 853 { 854 struct fwohci_softc *sc; 855 856 sc = (struct fwohci_softc *)arg; 857 } 858 859 uint32_t 860 fwohci_cyctimer(struct firewire_comm *fc) 861 { 862 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 863 return(OREAD(sc, OHCI_CYCLETIMER)); 864 } 865 866 FWOHCI_DETACH() 867 { 868 int i; 869 870 FWOHCI_DETACH_START; 871 if (sc->sid_buf != NULL) 872 fwdma_free(&sc->fc, &sc->sid_dma); 873 if (sc->fc.config_rom != NULL) 874 fwdma_free(&sc->fc, &sc->crom_dma); 875 876 fwohci_db_free(&sc->arrq); 877 fwohci_db_free(&sc->arrs); 878 879 fwohci_db_free(&sc->atrq); 880 fwohci_db_free(&sc->atrs); 881 882 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 883 fwohci_db_free(&sc->it[i]); 884 fwohci_db_free(&sc->ir[i]); 885 } 886 FWOHCI_DETACH_END; 887 888 return 0; 889 } 890 891 #define LAST_DB(dbtr, db) do { \ 892 struct fwohcidb_tr *_dbtr = (dbtr); \ 893 int _cnt = _dbtr->dbcnt; \ 894 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 895 } while (0) 896 897 static void 898 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 899 { 900 struct fwohcidb_tr *db_tr; 901 struct fwohcidb *db; 902 bus_dma_segment_t *s; 903 int i; 904 905 db_tr = (struct fwohcidb_tr *)arg; 906 db = &db_tr->db[db_tr->dbcnt]; 907 if (error) { 908 if (firewire_debug || error != EFBIG) 909 printf("fwohci_execute_db: error=%d\n", error); 910 return; 911 } 912 for (i = 0; i < nseg; i++) { 913 s = &segs[i]; 914 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 915 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 916 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 917 db++; 918 db_tr->dbcnt++; 919 } 920 } 921 922 static void 923 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 924 bus_size_t size, int error) 925 { 926 fwohci_execute_db(arg, segs, nseg, error); 927 } 928 929 static void 930 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 931 { 932 int i, s; 933 int tcode, hdr_len, pl_off; 934 int fsegment = -1; 935 uint32_t off; 936 struct fw_xfer *xfer; 937 struct fw_pkt *fp; 938 struct fwohci_txpkthdr *ohcifp; 939 struct fwohcidb_tr *db_tr; 940 struct fwohcidb *db; 941 uint32_t *ld; 942 const struct tcode_info *info; 943 static int maxdesc=0; 944 945 if(&sc->atrq == dbch){ 946 off = OHCI_ATQOFF; 947 }else if(&sc->atrs == dbch){ 948 off = OHCI_ATSOFF; 949 }else{ 950 return; 951 } 952 953 if (dbch->flags & FWOHCI_DBCH_FULL) 954 return; 955 956 s = splfw(); 957 fwdma_sync_multiseg_all(dbch->am, 958 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 959 db_tr = dbch->top; 960 txloop: 961 xfer = STAILQ_FIRST(&dbch->xferq.q); 962 if(xfer == NULL){ 963 goto kick; 964 } 965 if(dbch->xferq.queued == 0 ){ 966 device_printf(sc->fc.dev, "TX queue empty\n"); 967 } 968 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 969 db_tr->xfer = xfer; 970 xfer->state = FWXF_START; 971 972 fp = &xfer->send.hdr; 973 tcode = fp->mode.common.tcode; 974 975 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 976 info = &tinfo[tcode]; 977 hdr_len = pl_off = info->hdr_len; 978 979 ld = &ohcifp->mode.ld[0]; 980 ld[0] = ld[1] = ld[2] = ld[3] = 0; 981 for( i = 0 ; i < pl_off ; i+= 4) 982 ld[i/4] = fp->mode.ld[i/4]; 983 984 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 985 if (tcode == FWTCODE_STREAM ){ 986 hdr_len = 8; 987 ohcifp->mode.stream.len = fp->mode.stream.len; 988 } else if (tcode == FWTCODE_PHY) { 989 hdr_len = 12; 990 ld[1] = fp->mode.ld[1]; 991 ld[2] = fp->mode.ld[2]; 992 ohcifp->mode.common.spd = 0; 993 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 994 } else { 995 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 996 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 997 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 998 } 999 db = &db_tr->db[0]; 1000 FWOHCI_DMA_WRITE(db->db.desc.cmd, 1001 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 1002 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1003 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1004 /* Specify bound timer of asy. responce */ 1005 if(&sc->atrs == dbch){ 1006 FWOHCI_DMA_WRITE(db->db.desc.res, 1007 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1008 } 1009 #if BYTE_ORDER == BIG_ENDIAN 1010 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1011 hdr_len = 12; 1012 for (i = 0; i < hdr_len/4; i ++) 1013 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1014 #endif 1015 1016 again: 1017 db_tr->dbcnt = 2; 1018 db = &db_tr->db[db_tr->dbcnt]; 1019 if (xfer->send.pay_len > 0) { 1020 int err; 1021 /* handle payload */ 1022 if (xfer->mbuf == NULL) { 1023 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1024 &xfer->send.payload[0], xfer->send.pay_len, 1025 fwohci_execute_db, db_tr, 1026 BUS_DMA_WAITOK); 1027 } else { 1028 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1029 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1030 db_tr->dma_map, xfer->mbuf, 1031 fwohci_execute_db2, db_tr, 1032 BUS_DMA_WAITOK); 1033 if (err == EFBIG) { 1034 struct mbuf *m0; 1035 1036 if (firewire_debug) 1037 device_printf(sc->fc.dev, "EFBIG.\n"); 1038 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1039 if (m0 != NULL) { 1040 m_copydata(xfer->mbuf, 0, 1041 xfer->mbuf->m_pkthdr.len, 1042 mtod(m0, void *)); 1043 m0->m_len = m0->m_pkthdr.len = 1044 xfer->mbuf->m_pkthdr.len; 1045 m_freem(xfer->mbuf); 1046 xfer->mbuf = m0; 1047 goto again; 1048 } 1049 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1050 } 1051 } 1052 if (err) 1053 printf("dmamap_load: err=%d\n", err); 1054 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1055 BUS_DMASYNC_PREWRITE); 1056 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1057 for (i = 2; i < db_tr->dbcnt; i++) 1058 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1059 OHCI_OUTPUT_MORE); 1060 #endif 1061 } 1062 if (maxdesc < db_tr->dbcnt) { 1063 maxdesc = db_tr->dbcnt; 1064 if (firewire_debug) 1065 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1066 } 1067 /* last db */ 1068 LAST_DB(db_tr, db); 1069 FWOHCI_DMA_SET(db->db.desc.cmd, 1070 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1071 FWOHCI_DMA_WRITE(db->db.desc.depend, 1072 STAILQ_NEXT(db_tr, link)->bus_addr); 1073 1074 if(fsegment == -1 ) 1075 fsegment = db_tr->dbcnt; 1076 if (dbch->pdb_tr != NULL) { 1077 LAST_DB(dbch->pdb_tr, db); 1078 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1079 } 1080 dbch->pdb_tr = db_tr; 1081 db_tr = STAILQ_NEXT(db_tr, link); 1082 if(db_tr != dbch->bottom){ 1083 goto txloop; 1084 } else { 1085 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1086 dbch->flags |= FWOHCI_DBCH_FULL; 1087 } 1088 kick: 1089 /* kick asy q */ 1090 fwdma_sync_multiseg_all(dbch->am, 1091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1092 1093 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1094 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1095 } else { 1096 if (firewire_debug) 1097 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1098 OREAD(sc, OHCI_DMACTL(off))); 1099 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1100 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1101 dbch->xferq.flag |= FWXFERQ_RUNNING; 1102 } 1103 CTR0(KTR_DEV, "start kick done"); 1104 CTR0(KTR_DEV, "start kick done2"); 1105 1106 dbch->top = db_tr; 1107 splx(s); 1108 return; 1109 } 1110 1111 static void 1112 fwohci_start_atq(struct firewire_comm *fc) 1113 { 1114 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1115 fwohci_start( sc, &(sc->atrq)); 1116 return; 1117 } 1118 1119 static void 1120 fwohci_start_ats(struct firewire_comm *fc) 1121 { 1122 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1123 fwohci_start( sc, &(sc->atrs)); 1124 return; 1125 } 1126 1127 void 1128 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1129 { 1130 int s, ch, err = 0; 1131 struct fwohcidb_tr *tr; 1132 struct fwohcidb *db; 1133 struct fw_xfer *xfer; 1134 uint32_t off; 1135 u_int stat, status; 1136 int packets; 1137 struct firewire_comm *fc = (struct firewire_comm *)sc; 1138 1139 if(&sc->atrq == dbch){ 1140 off = OHCI_ATQOFF; 1141 ch = ATRQ_CH; 1142 }else if(&sc->atrs == dbch){ 1143 off = OHCI_ATSOFF; 1144 ch = ATRS_CH; 1145 }else{ 1146 return; 1147 } 1148 s = splfw(); 1149 tr = dbch->bottom; 1150 packets = 0; 1151 fwdma_sync_multiseg_all(dbch->am, 1152 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1153 while(dbch->xferq.queued > 0){ 1154 LAST_DB(tr, db); 1155 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1156 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1157 if (fc->status != FWBUSRESET) 1158 /* maybe out of order?? */ 1159 goto out; 1160 } 1161 if (tr->xfer->send.pay_len > 0) { 1162 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1163 BUS_DMASYNC_POSTWRITE); 1164 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1165 } 1166 #if 1 1167 if (firewire_debug > 1) 1168 dump_db(sc, ch); 1169 #endif 1170 if(status & OHCI_CNTL_DMA_DEAD) { 1171 /* Stop DMA */ 1172 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1173 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1174 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1175 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1176 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1177 } 1178 stat = status & FWOHCIEV_MASK; 1179 switch(stat){ 1180 case FWOHCIEV_ACKPEND: 1181 CTR0(KTR_DEV, "txd: ack pending"); 1182 /* fall through */ 1183 case FWOHCIEV_ACKCOMPL: 1184 err = 0; 1185 break; 1186 case FWOHCIEV_ACKBSA: 1187 case FWOHCIEV_ACKBSB: 1188 case FWOHCIEV_ACKBSX: 1189 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1190 err = EBUSY; 1191 break; 1192 case FWOHCIEV_FLUSHED: 1193 case FWOHCIEV_ACKTARD: 1194 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1195 err = EAGAIN; 1196 break; 1197 case FWOHCIEV_MISSACK: 1198 case FWOHCIEV_UNDRRUN: 1199 case FWOHCIEV_OVRRUN: 1200 case FWOHCIEV_DESCERR: 1201 case FWOHCIEV_DTRDERR: 1202 case FWOHCIEV_TIMEOUT: 1203 case FWOHCIEV_TCODERR: 1204 case FWOHCIEV_UNKNOWN: 1205 case FWOHCIEV_ACKDERR: 1206 case FWOHCIEV_ACKTERR: 1207 default: 1208 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1209 stat, fwohcicode[stat]); 1210 err = EINVAL; 1211 break; 1212 } 1213 if (tr->xfer != NULL) { 1214 xfer = tr->xfer; 1215 CTR0(KTR_DEV, "txd"); 1216 if (xfer->state == FWXF_RCVD) { 1217 #if 0 1218 if (firewire_debug) 1219 printf("already rcvd\n"); 1220 #endif 1221 fw_xfer_done(xfer); 1222 } else { 1223 xfer->state = FWXF_SENT; 1224 if (err == EBUSY && fc->status != FWBUSRESET) { 1225 xfer->state = FWXF_BUSY; 1226 xfer->resp = err; 1227 xfer->recv.pay_len = 0; 1228 fw_xfer_done(xfer); 1229 } else if (stat != FWOHCIEV_ACKPEND) { 1230 if (stat != FWOHCIEV_ACKCOMPL) 1231 xfer->state = FWXF_SENTERR; 1232 xfer->resp = err; 1233 xfer->recv.pay_len = 0; 1234 fw_xfer_done(xfer); 1235 } 1236 } 1237 /* 1238 * The watchdog timer takes care of split 1239 * transcation timeout for ACKPEND case. 1240 */ 1241 } else { 1242 printf("this shouldn't happen\n"); 1243 } 1244 dbch->xferq.queued --; 1245 tr->xfer = NULL; 1246 1247 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1248 packets ++; 1249 tr = STAILQ_NEXT(tr, link); 1250 dbch->bottom = tr; 1251 if (dbch->bottom == dbch->top) { 1252 /* we reaches the end of context program */ 1253 if (firewire_debug && dbch->xferq.queued > 0) 1254 printf("queued > 0\n"); 1255 break; 1256 } 1257 } 1258 out: 1259 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1260 printf("make free slot\n"); 1261 dbch->flags &= ~FWOHCI_DBCH_FULL; 1262 fwohci_start(sc, dbch); 1263 } 1264 fwdma_sync_multiseg_all( 1265 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1266 splx(s); 1267 } 1268 1269 static void 1270 fwohci_db_free(struct fwohci_dbch *dbch) 1271 { 1272 struct fwohcidb_tr *db_tr; 1273 int idb; 1274 1275 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1276 return; 1277 1278 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1279 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1280 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1281 db_tr->buf != NULL) { 1282 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1283 db_tr->buf, dbch->xferq.psize); 1284 db_tr->buf = NULL; 1285 } else if (db_tr->dma_map != NULL) 1286 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1287 } 1288 dbch->ndb = 0; 1289 db_tr = STAILQ_FIRST(&dbch->db_trq); 1290 fwdma_free_multiseg(dbch->am); 1291 free(db_tr, M_FW); 1292 STAILQ_INIT(&dbch->db_trq); 1293 dbch->flags &= ~FWOHCI_DBCH_INIT; 1294 } 1295 1296 static void 1297 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1298 { 1299 int idb; 1300 struct fwohcidb_tr *db_tr; 1301 1302 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1303 goto out; 1304 1305 /* create dma_tag for buffers */ 1306 #define MAX_REQCOUNT 0xffff 1307 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1308 /*alignment*/ 1, /*boundary*/ 0, 1309 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1310 /*highaddr*/ BUS_SPACE_MAXADDR, 1311 /*filter*/NULL, /*filterarg*/NULL, 1312 /*maxsize*/ dbch->xferq.psize, 1313 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1314 /*maxsegsz*/ MAX_REQCOUNT, 1315 /*flags*/ 0, 1316 /*lockfunc*/busdma_lock_mutex, 1317 /*lockarg*/&Giant, 1318 &dbch->dmat)) 1319 return; 1320 1321 /* allocate DB entries and attach one to each DMA channels */ 1322 /* DB entry must start at 16 bytes bounary. */ 1323 STAILQ_INIT(&dbch->db_trq); 1324 db_tr = (struct fwohcidb_tr *) 1325 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1326 M_FW, M_WAITOK | M_ZERO); 1327 if(db_tr == NULL){ 1328 printf("fwohci_db_init: malloc(1) failed\n"); 1329 return; 1330 } 1331 1332 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1333 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1334 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1335 if (dbch->am == NULL) { 1336 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1337 free(db_tr, M_FW); 1338 return; 1339 } 1340 /* Attach DB to DMA ch. */ 1341 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1342 db_tr->dbcnt = 0; 1343 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1344 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1345 /* create dmamap for buffers */ 1346 /* XXX do we need 4bytes alignment tag? */ 1347 /* XXX don't alloc dma_map for AR */ 1348 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1349 printf("fw_bus_dmamap_create failed\n"); 1350 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1351 fwohci_db_free(dbch); 1352 return; 1353 } 1354 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1355 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1356 if (idb % dbch->xferq.bnpacket == 0) 1357 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1358 ].start = (void *)db_tr; 1359 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1360 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1361 ].end = (void *)db_tr; 1362 } 1363 db_tr++; 1364 } 1365 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1366 = STAILQ_FIRST(&dbch->db_trq); 1367 out: 1368 dbch->xferq.queued = 0; 1369 dbch->pdb_tr = NULL; 1370 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1371 dbch->bottom = dbch->top; 1372 dbch->flags = FWOHCI_DBCH_INIT; 1373 } 1374 1375 static int 1376 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1377 { 1378 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1379 int sleepch; 1380 1381 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1382 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1383 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1384 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1385 /* XXX we cannot free buffers until the DMA really stops */ 1386 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1387 fwohci_db_free(&sc->it[dmach]); 1388 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1389 return 0; 1390 } 1391 1392 static int 1393 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1394 { 1395 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1396 int sleepch; 1397 1398 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1399 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1400 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1401 /* XXX we cannot free buffers until the DMA really stops */ 1402 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1403 fwohci_db_free(&sc->ir[dmach]); 1404 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1405 return 0; 1406 } 1407 1408 #if BYTE_ORDER == BIG_ENDIAN 1409 static void 1410 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1411 { 1412 qld[0] = FWOHCI_DMA_READ(qld[0]); 1413 return; 1414 } 1415 #endif 1416 1417 static int 1418 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1419 { 1420 int err = 0; 1421 int idb, z, i, dmach = 0, ldesc; 1422 uint32_t off = 0; 1423 struct fwohcidb_tr *db_tr; 1424 struct fwohcidb *db; 1425 1426 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1427 err = EINVAL; 1428 return err; 1429 } 1430 z = dbch->ndesc; 1431 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1432 if( &sc->it[dmach] == dbch){ 1433 off = OHCI_ITOFF(dmach); 1434 break; 1435 } 1436 } 1437 if(off == 0){ 1438 err = EINVAL; 1439 return err; 1440 } 1441 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1442 return err; 1443 dbch->xferq.flag |= FWXFERQ_RUNNING; 1444 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1445 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1446 } 1447 db_tr = dbch->top; 1448 for (idb = 0; idb < dbch->ndb; idb ++) { 1449 fwohci_add_tx_buf(dbch, db_tr, idb); 1450 if(STAILQ_NEXT(db_tr, link) == NULL){ 1451 break; 1452 } 1453 db = db_tr->db; 1454 ldesc = db_tr->dbcnt - 1; 1455 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1456 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1457 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1458 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1459 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1460 FWOHCI_DMA_SET( 1461 db[ldesc].db.desc.cmd, 1462 OHCI_INTERRUPT_ALWAYS); 1463 /* OHCI 1.1 and above */ 1464 FWOHCI_DMA_SET( 1465 db[0].db.desc.cmd, 1466 OHCI_INTERRUPT_ALWAYS); 1467 } 1468 } 1469 db_tr = STAILQ_NEXT(db_tr, link); 1470 } 1471 FWOHCI_DMA_CLEAR( 1472 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1473 return err; 1474 } 1475 1476 static int 1477 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1478 { 1479 int err = 0; 1480 int idb, z, i, dmach = 0, ldesc; 1481 uint32_t off = 0; 1482 struct fwohcidb_tr *db_tr; 1483 struct fwohcidb *db; 1484 1485 z = dbch->ndesc; 1486 if(&sc->arrq == dbch){ 1487 off = OHCI_ARQOFF; 1488 }else if(&sc->arrs == dbch){ 1489 off = OHCI_ARSOFF; 1490 }else{ 1491 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1492 if( &sc->ir[dmach] == dbch){ 1493 off = OHCI_IROFF(dmach); 1494 break; 1495 } 1496 } 1497 } 1498 if(off == 0){ 1499 err = EINVAL; 1500 return err; 1501 } 1502 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1503 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1504 return err; 1505 }else{ 1506 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1507 err = EBUSY; 1508 return err; 1509 } 1510 } 1511 dbch->xferq.flag |= FWXFERQ_RUNNING; 1512 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1513 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1514 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1515 } 1516 db_tr = dbch->top; 1517 for (idb = 0; idb < dbch->ndb; idb ++) { 1518 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1519 if (STAILQ_NEXT(db_tr, link) == NULL) 1520 break; 1521 db = db_tr->db; 1522 ldesc = db_tr->dbcnt - 1; 1523 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1524 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1525 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1526 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1527 FWOHCI_DMA_SET( 1528 db[ldesc].db.desc.cmd, 1529 OHCI_INTERRUPT_ALWAYS); 1530 FWOHCI_DMA_CLEAR( 1531 db[ldesc].db.desc.depend, 1532 0xf); 1533 } 1534 } 1535 db_tr = STAILQ_NEXT(db_tr, link); 1536 } 1537 FWOHCI_DMA_CLEAR( 1538 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1539 dbch->buf_offset = 0; 1540 fwdma_sync_multiseg_all(dbch->am, 1541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1542 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1543 return err; 1544 }else{ 1545 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1546 } 1547 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1548 return err; 1549 } 1550 1551 static int 1552 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1553 { 1554 int sec, cycle, cycle_match; 1555 1556 cycle = cycle_now & 0x1fff; 1557 sec = cycle_now >> 13; 1558 #define CYCLE_MOD 0x10 1559 #if 1 1560 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1561 #else 1562 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1563 #endif 1564 cycle = cycle + CYCLE_DELAY; 1565 if (cycle >= 8000) { 1566 sec ++; 1567 cycle -= 8000; 1568 } 1569 cycle = roundup2(cycle, CYCLE_MOD); 1570 if (cycle >= 8000) { 1571 sec ++; 1572 if (cycle == 8000) 1573 cycle = 0; 1574 else 1575 cycle = CYCLE_MOD; 1576 } 1577 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1578 1579 return(cycle_match); 1580 } 1581 1582 static int 1583 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1584 { 1585 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1586 int err = 0; 1587 unsigned short tag, ich; 1588 struct fwohci_dbch *dbch; 1589 int cycle_match, cycle_now, s, ldesc; 1590 uint32_t stat; 1591 struct fw_bulkxfer *first, *chunk, *prev; 1592 struct fw_xferq *it; 1593 1594 dbch = &sc->it[dmach]; 1595 it = &dbch->xferq; 1596 1597 tag = (it->flag >> 6) & 3; 1598 ich = it->flag & 0x3f; 1599 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1600 dbch->ndb = it->bnpacket * it->bnchunk; 1601 dbch->ndesc = 3; 1602 fwohci_db_init(sc, dbch); 1603 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1604 return ENOMEM; 1605 err = fwohci_tx_enable(sc, dbch); 1606 } 1607 if(err) 1608 return err; 1609 1610 ldesc = dbch->ndesc - 1; 1611 s = splfw(); 1612 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1613 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1614 struct fwohcidb *db; 1615 1616 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1617 BUS_DMASYNC_PREWRITE); 1618 fwohci_txbufdb(sc, dmach, chunk); 1619 if (prev != NULL) { 1620 db = ((struct fwohcidb_tr *)(prev->end))->db; 1621 #if 0 /* XXX necessary? */ 1622 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1623 OHCI_BRANCH_ALWAYS); 1624 #endif 1625 #if 0 /* if bulkxfer->npacket changes */ 1626 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1627 ((struct fwohcidb_tr *) 1628 (chunk->start))->bus_addr | dbch->ndesc; 1629 #else 1630 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1631 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1632 #endif 1633 } 1634 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1635 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1636 prev = chunk; 1637 } 1638 fwdma_sync_multiseg_all(dbch->am, 1639 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1640 splx(s); 1641 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1642 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1643 printf("stat 0x%x\n", stat); 1644 1645 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1646 return 0; 1647 1648 #if 0 1649 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1650 #endif 1651 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1652 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1653 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1654 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1655 1656 first = STAILQ_FIRST(&it->stdma); 1657 OWRITE(sc, OHCI_ITCMD(dmach), 1658 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1659 if (firewire_debug > 1) { 1660 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1661 #if 1 1662 dump_dma(sc, ITX_CH + dmach); 1663 #endif 1664 } 1665 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1666 #if 1 1667 /* Don't start until all chunks are buffered */ 1668 if (STAILQ_FIRST(&it->stfree) != NULL) 1669 goto out; 1670 #endif 1671 #if 1 1672 /* Clear cycle match counter bits */ 1673 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1674 1675 /* 2bit second + 13bit cycle */ 1676 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1677 cycle_match = fwohci_next_cycle(fc, cycle_now); 1678 1679 OWRITE(sc, OHCI_ITCTL(dmach), 1680 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1681 | OHCI_CNTL_DMA_RUN); 1682 #else 1683 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1684 #endif 1685 if (firewire_debug > 1) { 1686 printf("cycle_match: 0x%04x->0x%04x\n", 1687 cycle_now, cycle_match); 1688 dump_dma(sc, ITX_CH + dmach); 1689 dump_db(sc, ITX_CH + dmach); 1690 } 1691 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1692 device_printf(sc->fc.dev, 1693 "IT DMA underrun (0x%08x)\n", stat); 1694 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1695 } 1696 out: 1697 return err; 1698 } 1699 1700 static int 1701 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1702 { 1703 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1704 int err = 0, s, ldesc; 1705 unsigned short tag, ich; 1706 uint32_t stat; 1707 struct fwohci_dbch *dbch; 1708 struct fwohcidb_tr *db_tr; 1709 struct fw_bulkxfer *first, *prev, *chunk; 1710 struct fw_xferq *ir; 1711 1712 dbch = &sc->ir[dmach]; 1713 ir = &dbch->xferq; 1714 1715 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1716 tag = (ir->flag >> 6) & 3; 1717 ich = ir->flag & 0x3f; 1718 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1719 1720 ir->queued = 0; 1721 dbch->ndb = ir->bnpacket * ir->bnchunk; 1722 dbch->ndesc = 2; 1723 fwohci_db_init(sc, dbch); 1724 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1725 return ENOMEM; 1726 err = fwohci_rx_enable(sc, dbch); 1727 } 1728 if(err) 1729 return err; 1730 1731 first = STAILQ_FIRST(&ir->stfree); 1732 if (first == NULL) { 1733 device_printf(fc->dev, "IR DMA no free chunk\n"); 1734 return 0; 1735 } 1736 1737 ldesc = dbch->ndesc - 1; 1738 s = splfw(); 1739 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1740 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1741 struct fwohcidb *db; 1742 1743 #if 1 /* XXX for if_fwe */ 1744 if (chunk->mbuf != NULL) { 1745 db_tr = (struct fwohcidb_tr *)(chunk->start); 1746 db_tr->dbcnt = 1; 1747 err = fw_bus_dmamap_load_mbuf( 1748 dbch->dmat, db_tr->dma_map, 1749 chunk->mbuf, fwohci_execute_db2, db_tr, 1750 BUS_DMA_WAITOK); 1751 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1752 OHCI_UPDATE | OHCI_INPUT_LAST | 1753 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1754 } 1755 #endif 1756 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1757 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1758 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1759 if (prev != NULL) { 1760 db = ((struct fwohcidb_tr *)(prev->end))->db; 1761 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1762 } 1763 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1764 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1765 prev = chunk; 1766 } 1767 fwdma_sync_multiseg_all(dbch->am, 1768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1769 splx(s); 1770 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1771 if (stat & OHCI_CNTL_DMA_ACTIVE) 1772 return 0; 1773 if (stat & OHCI_CNTL_DMA_RUN) { 1774 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1775 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1776 } 1777 1778 if (firewire_debug) 1779 printf("start IR DMA 0x%x\n", stat); 1780 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1781 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1782 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1783 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1784 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1785 OWRITE(sc, OHCI_IRCMD(dmach), 1786 ((struct fwohcidb_tr *)(first->start))->bus_addr 1787 | dbch->ndesc); 1788 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1789 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1790 #if 0 1791 dump_db(sc, IRX_CH + dmach); 1792 #endif 1793 return err; 1794 } 1795 1796 FWOHCI_STOP() 1797 { 1798 FWOHCI_STOP_START; 1799 u_int i; 1800 1801 /* Now stopping all DMA channel */ 1802 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1803 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1804 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1805 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1806 1807 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1808 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1809 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1810 } 1811 1812 /* FLUSH FIFO and reset Transmitter/Reciever */ 1813 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1814 1815 /* Stop interrupt */ 1816 OWRITE(sc, FWOHCI_INTMASKCLR, 1817 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1818 | OHCI_INT_PHY_INT 1819 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1820 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1821 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1822 | OHCI_INT_PHY_BUS_R); 1823 1824 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1825 fw_drain_txq(&sc->fc); 1826 1827 /* XXX Link down? Bus reset? */ 1828 FWOHCI_STOP_RETURN(0); 1829 } 1830 1831 #if defined(__NetBSD__) 1832 static void 1833 fwohci_power(int why, void *arg) 1834 { 1835 struct fwohci_softc *sc = arg; 1836 int s; 1837 1838 s = splbio(); 1839 switch (why) { 1840 case PWR_SUSPEND: 1841 case PWR_STANDBY: 1842 fwohci_stop(arg); 1843 break; 1844 case PWR_RESUME: 1845 fwohci_resume(sc, sc->fc.dev); 1846 break; 1847 case PWR_SOFTSUSPEND: 1848 case PWR_SOFTSTANDBY: 1849 case PWR_SOFTRESUME: 1850 break; 1851 } 1852 splx(s); 1853 } 1854 #endif 1855 1856 int 1857 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1858 { 1859 int i; 1860 struct fw_xferq *ir; 1861 struct fw_bulkxfer *chunk; 1862 1863 fwohci_reset(sc, dev); 1864 /* XXX resume isochronous receive automatically. (how about TX?) */ 1865 for(i = 0; i < sc->fc.nisodma; i ++) { 1866 ir = &sc->ir[i].xferq; 1867 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1868 device_printf(sc->fc.dev, 1869 "resume iso receive ch: %d\n", i); 1870 ir->flag &= ~FWXFERQ_RUNNING; 1871 /* requeue stdma to stfree */ 1872 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1873 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1874 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1875 } 1876 sc->fc.irx_enable(&sc->fc, i); 1877 } 1878 } 1879 1880 #if defined(__FreeBSD__) 1881 bus_generic_resume(dev); 1882 #endif 1883 sc->fc.ibr(&sc->fc); 1884 return 0; 1885 } 1886 1887 #define ACK_ALL 1888 static void 1889 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1890 { 1891 uint32_t irstat, itstat; 1892 u_int i; 1893 struct firewire_comm *fc = (struct firewire_comm *)sc; 1894 1895 CTR0(KTR_DEV, "fwohci_intr_body"); 1896 #ifdef OHCI_DEBUG 1897 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1898 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1899 stat & OHCI_INT_EN ? "DMA_EN ":"", 1900 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1901 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1902 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1903 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1904 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1905 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1906 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1907 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1908 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1909 stat & OHCI_INT_PHY_SID ? "SID ":"", 1910 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1911 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1912 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1913 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1914 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1915 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1916 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1917 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1918 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1919 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1920 stat, OREAD(sc, FWOHCI_INTMASK) 1921 ); 1922 #endif 1923 /* Bus reset */ 1924 if(stat & OHCI_INT_PHY_BUS_R ){ 1925 if (fc->status == FWBUSRESET) 1926 goto busresetout; 1927 /* Disable bus reset interrupt until sid recv. */ 1928 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1929 1930 device_printf(fc->dev, "BUS reset\n"); 1931 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1932 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1933 1934 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1935 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1936 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1937 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1938 1939 #ifndef ACK_ALL 1940 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1941 #endif 1942 fw_busreset(fc); 1943 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1944 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1945 } 1946 busresetout: 1947 if((stat & OHCI_INT_DMA_IR )){ 1948 #ifndef ACK_ALL 1949 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1950 #endif 1951 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1952 irstat = sc->irstat; 1953 sc->irstat = 0; 1954 #else 1955 irstat = atomic_readandclear_int(&sc->irstat); 1956 #endif 1957 for(i = 0; i < fc->nisodma ; i++){ 1958 struct fwohci_dbch *dbch; 1959 1960 if((irstat & (1 << i)) != 0){ 1961 dbch = &sc->ir[i]; 1962 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1963 device_printf(sc->fc.dev, 1964 "dma(%d) not active\n", i); 1965 continue; 1966 } 1967 fwohci_rbuf_update(sc, i); 1968 } 1969 } 1970 } 1971 if((stat & OHCI_INT_DMA_IT )){ 1972 #ifndef ACK_ALL 1973 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1974 #endif 1975 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1976 itstat = sc->itstat; 1977 sc->itstat = 0; 1978 #else 1979 itstat = atomic_readandclear_int(&sc->itstat); 1980 #endif 1981 for(i = 0; i < fc->nisodma ; i++){ 1982 if((itstat & (1 << i)) != 0){ 1983 fwohci_tbuf_update(sc, i); 1984 } 1985 } 1986 } 1987 if((stat & OHCI_INT_DMA_PRRS )){ 1988 #ifndef ACK_ALL 1989 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1990 #endif 1991 #if 0 1992 dump_dma(sc, ARRS_CH); 1993 dump_db(sc, ARRS_CH); 1994 #endif 1995 fwohci_arcv(sc, &sc->arrs, count); 1996 } 1997 if((stat & OHCI_INT_DMA_PRRQ )){ 1998 #ifndef ACK_ALL 1999 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 2000 #endif 2001 #if 0 2002 dump_dma(sc, ARRQ_CH); 2003 dump_db(sc, ARRQ_CH); 2004 #endif 2005 fwohci_arcv(sc, &sc->arrq, count); 2006 } 2007 if (stat & OHCI_INT_CYC_LOST) { 2008 if (sc->cycle_lost >= 0) 2009 sc->cycle_lost ++; 2010 if (sc->cycle_lost > 10) { 2011 sc->cycle_lost = -1; 2012 #if 0 2013 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2014 #endif 2015 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2016 device_printf(fc->dev, "too many cycle lost, " 2017 "no cycle master presents?\n"); 2018 } 2019 } 2020 if(stat & OHCI_INT_PHY_SID){ 2021 uint32_t *buf, node_id; 2022 int plen; 2023 2024 #ifndef ACK_ALL 2025 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2026 #endif 2027 /* Enable bus reset interrupt */ 2028 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2029 /* Allow async. request to us */ 2030 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2031 /* XXX insecure ?? */ 2032 /* allow from all nodes */ 2033 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2034 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2035 /* 0 to 4GB regison */ 2036 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2037 /* Set ATRetries register */ 2038 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2039 /* 2040 ** Checking whether the node is root or not. If root, turn on 2041 ** cycle master. 2042 */ 2043 node_id = OREAD(sc, FWOHCI_NODEID); 2044 plen = OREAD(sc, OHCI_SID_CNT); 2045 2046 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2047 node_id, (plen >> 16) & 0xff); 2048 if (!(node_id & OHCI_NODE_VALID)) { 2049 printf("Bus reset failure\n"); 2050 goto sidout; 2051 } 2052 2053 /* cycle timer */ 2054 sc->cycle_lost = 0; 2055 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2056 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2057 printf("CYCLEMASTER mode\n"); 2058 OWRITE(sc, OHCI_LNKCTL, 2059 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2060 } else { 2061 printf("non CYCLEMASTER mode\n"); 2062 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2063 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2064 } 2065 2066 fc->nodeid = node_id & 0x3f; 2067 2068 if (plen & OHCI_SID_ERR) { 2069 device_printf(fc->dev, "SID Error\n"); 2070 goto sidout; 2071 } 2072 plen &= OHCI_SID_CNT_MASK; 2073 if (plen < 4 || plen > OHCI_SIDSIZE) { 2074 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2075 goto sidout; 2076 } 2077 plen -= 4; /* chop control info */ 2078 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2079 if (buf == NULL) { 2080 device_printf(fc->dev, "malloc failed\n"); 2081 goto sidout; 2082 } 2083 for (i = 0; i < plen / 4; i ++) 2084 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2085 #if defined(__NetBSD__) && defined(macppc) 2086 /* XXX required as bootdisk for macppc. */ 2087 delay(500000); 2088 #endif 2089 #if 1 /* XXX needed?? */ 2090 /* pending all pre-bus_reset packets */ 2091 fwohci_txd(sc, &sc->atrq); 2092 fwohci_txd(sc, &sc->atrs); 2093 fwohci_arcv(sc, &sc->arrs, -1); 2094 fwohci_arcv(sc, &sc->arrq, -1); 2095 fw_drain_txq(fc); 2096 #endif 2097 fw_sidrcv(fc, buf, plen); 2098 free(buf, M_FW); 2099 } 2100 sidout: 2101 if((stat & OHCI_INT_DMA_ATRQ )){ 2102 #ifndef ACK_ALL 2103 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2104 #endif 2105 fwohci_txd(sc, &(sc->atrq)); 2106 } 2107 if((stat & OHCI_INT_DMA_ATRS )){ 2108 #ifndef ACK_ALL 2109 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2110 #endif 2111 fwohci_txd(sc, &(sc->atrs)); 2112 } 2113 if((stat & OHCI_INT_PW_ERR )){ 2114 #ifndef ACK_ALL 2115 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2116 #endif 2117 device_printf(fc->dev, "posted write error\n"); 2118 } 2119 if((stat & OHCI_INT_ERR )){ 2120 #ifndef ACK_ALL 2121 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2122 #endif 2123 device_printf(fc->dev, "unrecoverable error\n"); 2124 } 2125 if((stat & OHCI_INT_PHY_INT)) { 2126 #ifndef ACK_ALL 2127 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2128 #endif 2129 device_printf(fc->dev, "phy int\n"); 2130 } 2131 2132 CTR0(KTR_DEV, "fwohci_intr_body done"); 2133 return; 2134 } 2135 2136 #if FWOHCI_TASKQUEUE 2137 static void 2138 fwohci_complete(void *arg, int pending) 2139 { 2140 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2141 uint32_t stat; 2142 2143 again: 2144 stat = atomic_readandclear_int(&sc->intstat); 2145 if (stat) { 2146 FW_LOCK; 2147 fwohci_intr_body(sc, stat, -1); 2148 FW_UNLOCK; 2149 } else 2150 return; 2151 goto again; 2152 } 2153 #endif 2154 2155 static uint32_t 2156 fwochi_check_stat(struct fwohci_softc *sc) 2157 { 2158 uint32_t stat, irstat, itstat; 2159 2160 stat = OREAD(sc, FWOHCI_INTSTAT); 2161 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2162 if (stat == 0xffffffff) { 2163 device_printf(sc->fc.dev, 2164 "device physically ejected?\n"); 2165 return(stat); 2166 } 2167 #ifdef ACK_ALL 2168 if (stat) 2169 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2170 #endif 2171 if (stat & OHCI_INT_DMA_IR) { 2172 irstat = OREAD(sc, OHCI_IR_STAT); 2173 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2174 atomic_set_int(&sc->irstat, irstat); 2175 } 2176 if (stat & OHCI_INT_DMA_IT) { 2177 itstat = OREAD(sc, OHCI_IT_STAT); 2178 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2179 atomic_set_int(&sc->itstat, itstat); 2180 } 2181 return(stat); 2182 } 2183 2184 FW_INTR(fwohci) 2185 { 2186 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2187 uint32_t stat; 2188 #if !FWOHCI_TASKQUEUE 2189 uint32_t bus_reset = 0; 2190 #endif 2191 2192 if (!(sc->intmask & OHCI_INT_EN)) { 2193 /* polling mode */ 2194 FW_INTR_RETURN(0); 2195 } 2196 2197 #if !FWOHCI_TASKQUEUE 2198 again: 2199 #endif 2200 CTR0(KTR_DEV, "fwohci_intr"); 2201 stat = fwochi_check_stat(sc); 2202 if (stat == 0 || stat == 0xffffffff) 2203 FW_INTR_RETURN(1); 2204 #if FWOHCI_TASKQUEUE 2205 atomic_set_int(&sc->intstat, stat); 2206 /* XXX mask bus reset intr. during bus reset phase */ 2207 if (stat) 2208 #if 1 2209 taskqueue_enqueue_fast(taskqueue_fast, 2210 &sc->fwohci_task_complete); 2211 #else 2212 taskqueue_enqueue(taskqueue_swi, 2213 &sc->fwohci_task_complete); 2214 #endif 2215 #else 2216 /* We cannot clear bus reset event during bus reset phase */ 2217 if ((stat & ~bus_reset) == 0) 2218 FW_INTR_RETURN(1); 2219 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2220 fwohci_intr_body(sc, stat, -1); 2221 goto again; 2222 #endif 2223 CTR0(KTR_DEV, "fwohci_intr end"); 2224 } 2225 2226 void 2227 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2228 { 2229 int s; 2230 uint32_t stat; 2231 struct fwohci_softc *sc; 2232 2233 2234 sc = (struct fwohci_softc *)fc; 2235 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2236 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2237 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2238 #if 0 2239 if (!quick) { 2240 #else 2241 if (1) { 2242 #endif 2243 stat = fwochi_check_stat(sc); 2244 if (stat == 0 || stat == 0xffffffff) 2245 return; 2246 } 2247 s = splfw(); 2248 fwohci_intr_body(sc, stat, count); 2249 splx(s); 2250 } 2251 2252 static void 2253 fwohci_set_intr(struct firewire_comm *fc, int enable) 2254 { 2255 struct fwohci_softc *sc; 2256 2257 sc = (struct fwohci_softc *)fc; 2258 if (firewire_debug) 2259 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2260 if (enable) { 2261 sc->intmask |= OHCI_INT_EN; 2262 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2263 } else { 2264 sc->intmask &= ~OHCI_INT_EN; 2265 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2266 } 2267 } 2268 2269 static void 2270 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2271 { 2272 struct firewire_comm *fc = &sc->fc; 2273 struct fwohcidb *db; 2274 struct fw_bulkxfer *chunk; 2275 struct fw_xferq *it; 2276 uint32_t stat, count; 2277 int s, w=0, ldesc; 2278 2279 it = fc->it[dmach]; 2280 ldesc = sc->it[dmach].ndesc - 1; 2281 s = splfw(); /* unnecessary ? */ 2282 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2283 if (firewire_debug) 2284 dump_db(sc, ITX_CH + dmach); 2285 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2286 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2287 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2288 >> OHCI_STATUS_SHIFT; 2289 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2290 /* timestamp */ 2291 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2292 & OHCI_COUNT_MASK; 2293 if (stat == 0) 2294 break; 2295 STAILQ_REMOVE_HEAD(&it->stdma, link); 2296 switch (stat & FWOHCIEV_MASK){ 2297 case FWOHCIEV_ACKCOMPL: 2298 #if 0 2299 device_printf(fc->dev, "0x%08x\n", count); 2300 #endif 2301 break; 2302 default: 2303 device_printf(fc->dev, 2304 "Isochronous transmit err %02x(%s)\n", 2305 stat, fwohcicode[stat & 0x1f]); 2306 } 2307 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2308 w++; 2309 } 2310 splx(s); 2311 if (w) 2312 wakeup(it); 2313 } 2314 2315 static void 2316 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2317 { 2318 struct firewire_comm *fc = &sc->fc; 2319 struct fwohcidb_tr *db_tr; 2320 struct fw_bulkxfer *chunk; 2321 struct fw_xferq *ir; 2322 uint32_t stat; 2323 int s, w=0, ldesc; 2324 2325 ir = fc->ir[dmach]; 2326 ldesc = sc->ir[dmach].ndesc - 1; 2327 #if 0 2328 dump_db(sc, dmach); 2329 #endif 2330 s = splfw(); 2331 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2332 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2333 db_tr = (struct fwohcidb_tr *)chunk->end; 2334 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2335 >> OHCI_STATUS_SHIFT; 2336 if (stat == 0) 2337 break; 2338 2339 if (chunk->mbuf != NULL) { 2340 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2341 BUS_DMASYNC_POSTREAD); 2342 fw_bus_dmamap_unload( 2343 sc->ir[dmach].dmat, db_tr->dma_map); 2344 } else if (ir->buf != NULL) { 2345 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2346 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2347 } else { 2348 /* XXX */ 2349 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2350 } 2351 2352 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2353 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2354 switch (stat & FWOHCIEV_MASK) { 2355 case FWOHCIEV_ACKCOMPL: 2356 chunk->resp = 0; 2357 break; 2358 default: 2359 chunk->resp = EINVAL; 2360 device_printf(fc->dev, 2361 "Isochronous receive err %02x(%s)\n", 2362 stat, fwohcicode[stat & 0x1f]); 2363 } 2364 w++; 2365 } 2366 splx(s); 2367 if (w) { 2368 if (ir->flag & FWXFERQ_HANDLER) 2369 ir->hand(ir); 2370 else 2371 wakeup(ir); 2372 } 2373 } 2374 2375 void 2376 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2377 { 2378 uint32_t off, cntl, stat, cmd, match; 2379 2380 if(ch == 0){ 2381 off = OHCI_ATQOFF; 2382 }else if(ch == 1){ 2383 off = OHCI_ATSOFF; 2384 }else if(ch == 2){ 2385 off = OHCI_ARQOFF; 2386 }else if(ch == 3){ 2387 off = OHCI_ARSOFF; 2388 }else if(ch < IRX_CH){ 2389 off = OHCI_ITCTL(ch - ITX_CH); 2390 }else{ 2391 off = OHCI_IRCTL(ch - IRX_CH); 2392 } 2393 cntl = stat = OREAD(sc, off); 2394 cmd = OREAD(sc, off + 0xc); 2395 match = OREAD(sc, off + 0x10); 2396 2397 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2398 ch, 2399 cntl, 2400 cmd, 2401 match); 2402 stat &= 0xffff ; 2403 if (stat) { 2404 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2405 ch, 2406 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2407 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2408 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2409 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2410 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2411 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2412 fwohcicode[stat & 0x1f], 2413 stat & 0x1f 2414 ); 2415 }else{ 2416 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2417 } 2418 } 2419 2420 void 2421 dump_db(struct fwohci_softc *sc, uint32_t ch) 2422 { 2423 struct fwohci_dbch *dbch; 2424 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2425 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2426 int idb, jdb; 2427 uint32_t cmd, off; 2428 if(ch == 0){ 2429 off = OHCI_ATQOFF; 2430 dbch = &sc->atrq; 2431 }else if(ch == 1){ 2432 off = OHCI_ATSOFF; 2433 dbch = &sc->atrs; 2434 }else if(ch == 2){ 2435 off = OHCI_ARQOFF; 2436 dbch = &sc->arrq; 2437 }else if(ch == 3){ 2438 off = OHCI_ARSOFF; 2439 dbch = &sc->arrs; 2440 }else if(ch < IRX_CH){ 2441 off = OHCI_ITCTL(ch - ITX_CH); 2442 dbch = &sc->it[ch - ITX_CH]; 2443 }else { 2444 off = OHCI_IRCTL(ch - IRX_CH); 2445 dbch = &sc->ir[ch - IRX_CH]; 2446 } 2447 cmd = OREAD(sc, off + 0xc); 2448 2449 if( dbch->ndb == 0 ){ 2450 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2451 return; 2452 } 2453 pp = dbch->top; 2454 prev = pp->db; 2455 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2456 cp = STAILQ_NEXT(pp, link); 2457 if(cp == NULL){ 2458 curr = NULL; 2459 goto outdb; 2460 } 2461 np = STAILQ_NEXT(cp, link); 2462 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2463 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2464 curr = cp->db; 2465 if(np != NULL){ 2466 next = np->db; 2467 }else{ 2468 next = NULL; 2469 } 2470 goto outdb; 2471 } 2472 } 2473 pp = STAILQ_NEXT(pp, link); 2474 if(pp == NULL){ 2475 curr = NULL; 2476 goto outdb; 2477 } 2478 prev = pp->db; 2479 } 2480 outdb: 2481 if( curr != NULL){ 2482 #if 0 2483 printf("Prev DB %d\n", ch); 2484 print_db(pp, prev, ch, dbch->ndesc); 2485 #endif 2486 printf("Current DB %d\n", ch); 2487 print_db(cp, curr, ch, dbch->ndesc); 2488 #if 0 2489 printf("Next DB %d\n", ch); 2490 print_db(np, next, ch, dbch->ndesc); 2491 #endif 2492 }else{ 2493 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2494 } 2495 return; 2496 } 2497 2498 void 2499 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2500 uint32_t ch, uint32_t hogemax) 2501 { 2502 fwohcireg_t stat; 2503 int i, key; 2504 uint32_t cmd, res; 2505 2506 if(db == NULL){ 2507 printf("No Descriptor is found\n"); 2508 return; 2509 } 2510 2511 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2512 ch, 2513 "Current", 2514 "OP ", 2515 "KEY", 2516 "INT", 2517 "BR ", 2518 "len", 2519 "Addr", 2520 "Depend", 2521 "Stat", 2522 "Cnt"); 2523 for( i = 0 ; i <= hogemax ; i ++){ 2524 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2525 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2526 key = cmd & OHCI_KEY_MASK; 2527 stat = res >> OHCI_STATUS_SHIFT; 2528 #if defined(__DragonFly__) || \ 2529 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2530 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2531 db_tr->bus_addr, 2532 #else 2533 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2534 (uintmax_t)db_tr->bus_addr, 2535 #endif 2536 dbcode[(cmd >> 28) & 0xf], 2537 dbkey[(cmd >> 24) & 0x7], 2538 dbcond[(cmd >> 20) & 0x3], 2539 dbcond[(cmd >> 18) & 0x3], 2540 cmd & OHCI_COUNT_MASK, 2541 FWOHCI_DMA_READ(db[i].db.desc.addr), 2542 FWOHCI_DMA_READ(db[i].db.desc.depend), 2543 stat, 2544 res & OHCI_COUNT_MASK); 2545 if(stat & 0xff00){ 2546 printf(" %s%s%s%s%s%s %s(%x)\n", 2547 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2548 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2549 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2550 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2551 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2552 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2553 fwohcicode[stat & 0x1f], 2554 stat & 0x1f 2555 ); 2556 }else{ 2557 printf(" Nostat\n"); 2558 } 2559 if(key == OHCI_KEY_ST2 ){ 2560 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2561 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2562 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2563 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2564 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2565 } 2566 if(key == OHCI_KEY_DEVICE){ 2567 return; 2568 } 2569 if((cmd & OHCI_BRANCH_MASK) 2570 == OHCI_BRANCH_ALWAYS){ 2571 return; 2572 } 2573 if((cmd & OHCI_CMD_MASK) 2574 == OHCI_OUTPUT_LAST){ 2575 return; 2576 } 2577 if((cmd & OHCI_CMD_MASK) 2578 == OHCI_INPUT_LAST){ 2579 return; 2580 } 2581 if(key == OHCI_KEY_ST2 ){ 2582 i++; 2583 } 2584 } 2585 return; 2586 } 2587 2588 void 2589 fwohci_ibr(struct firewire_comm *fc) 2590 { 2591 struct fwohci_softc *sc; 2592 uint32_t fun; 2593 2594 device_printf(fc->dev, "Initiate bus reset\n"); 2595 sc = (struct fwohci_softc *)fc; 2596 2597 /* 2598 * Make sure our cached values from the config rom are 2599 * initialised. 2600 */ 2601 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2602 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2603 2604 /* 2605 * Set root hold-off bit so that non cyclemaster capable node 2606 * shouldn't became the root node. 2607 */ 2608 #if 1 2609 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2610 fun |= FW_PHY_IBR | FW_PHY_RHB; 2611 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2612 #else /* Short bus reset */ 2613 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2614 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2615 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2616 #endif 2617 } 2618 2619 void 2620 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2621 { 2622 struct fwohcidb_tr *db_tr, *fdb_tr; 2623 struct fwohci_dbch *dbch; 2624 struct fwohcidb *db; 2625 struct fw_pkt *fp; 2626 struct fwohci_txpkthdr *ohcifp; 2627 unsigned short chtag; 2628 int idb; 2629 2630 dbch = &sc->it[dmach]; 2631 chtag = sc->it[dmach].xferq.flag & 0xff; 2632 2633 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2634 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2635 /* 2636 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2637 */ 2638 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2639 db = db_tr->db; 2640 fp = (struct fw_pkt *)db_tr->buf; 2641 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2642 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2643 ohcifp->mode.common.spd = 0 & 0x7; 2644 ohcifp->mode.stream.len = fp->mode.stream.len; 2645 ohcifp->mode.stream.chtag = chtag; 2646 ohcifp->mode.stream.tcode = 0xa; 2647 #if BYTE_ORDER == BIG_ENDIAN 2648 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2649 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2650 #endif 2651 2652 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2653 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2654 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2655 #if 0 /* if bulkxfer->npackets changes */ 2656 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2657 | OHCI_UPDATE 2658 | OHCI_BRANCH_ALWAYS; 2659 db[0].db.desc.depend = 2660 = db[dbch->ndesc - 1].db.desc.depend 2661 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2662 #else 2663 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2664 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2665 #endif 2666 bulkxfer->end = (void *)db_tr; 2667 db_tr = STAILQ_NEXT(db_tr, link); 2668 } 2669 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2670 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2671 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2672 #if 0 /* if bulkxfer->npackets changes */ 2673 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2674 /* OHCI 1.1 and above */ 2675 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2676 #endif 2677 /* 2678 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2679 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2680 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2681 */ 2682 return; 2683 } 2684 2685 static int 2686 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2687 int poffset) 2688 { 2689 struct fwohcidb *db = db_tr->db; 2690 struct fw_xferq *it; 2691 int err = 0; 2692 2693 it = &dbch->xferq; 2694 if(it->buf == 0){ 2695 err = EINVAL; 2696 return err; 2697 } 2698 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2699 db_tr->dbcnt = 3; 2700 2701 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2702 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2703 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2704 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2705 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2706 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2707 2708 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2709 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2710 #if 1 2711 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2712 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2713 #endif 2714 return 0; 2715 } 2716 2717 int 2718 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2719 int poffset, struct fwdma_alloc *dummy_dma) 2720 { 2721 struct fwohcidb *db = db_tr->db; 2722 struct fw_xferq *ir; 2723 int i, ldesc; 2724 bus_addr_t dbuf[2]; 2725 int dsiz[2]; 2726 2727 ir = &dbch->xferq; 2728 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2729 if (db_tr->buf == NULL) 2730 db_tr->buf = fwdma_malloc_size( 2731 dbch->dmat, &db_tr->dma_map, 2732 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2733 if (db_tr->buf == NULL) 2734 return(ENOMEM); 2735 db_tr->dbcnt = 1; 2736 dsiz[0] = ir->psize; 2737 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2738 BUS_DMASYNC_PREREAD); 2739 } else { 2740 db_tr->dbcnt = 0; 2741 if (dummy_dma != NULL) { 2742 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2743 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2744 } 2745 dsiz[db_tr->dbcnt] = ir->psize; 2746 if (ir->buf != NULL) { 2747 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2748 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2749 } 2750 db_tr->dbcnt++; 2751 } 2752 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2753 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2754 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2755 if (ir->flag & FWXFERQ_STREAM) { 2756 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2757 } 2758 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2759 } 2760 ldesc = db_tr->dbcnt - 1; 2761 if (ir->flag & FWXFERQ_STREAM) { 2762 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2763 } 2764 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2765 return 0; 2766 } 2767 2768 2769 static int 2770 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2771 { 2772 struct fw_pkt *fp0; 2773 uint32_t ld0; 2774 int slen, hlen; 2775 #if BYTE_ORDER == BIG_ENDIAN 2776 int i; 2777 #endif 2778 2779 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2780 #if 0 2781 printf("ld0: x%08x\n", ld0); 2782 #endif 2783 fp0 = (struct fw_pkt *)&ld0; 2784 /* determine length to swap */ 2785 switch (fp0->mode.common.tcode) { 2786 case FWTCODE_WRES: 2787 CTR0(KTR_DEV, "WRES"); 2788 case FWTCODE_RREQQ: 2789 case FWTCODE_WREQQ: 2790 case FWTCODE_RRESQ: 2791 case FWOHCITCODE_PHY: 2792 slen = 12; 2793 break; 2794 case FWTCODE_RREQB: 2795 case FWTCODE_WREQB: 2796 case FWTCODE_LREQ: 2797 case FWTCODE_RRESB: 2798 case FWTCODE_LRES: 2799 slen = 16; 2800 break; 2801 default: 2802 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2803 return(0); 2804 } 2805 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2806 if (hlen > len) { 2807 if (firewire_debug) 2808 printf("splitted header\n"); 2809 return(-hlen); 2810 } 2811 #if BYTE_ORDER == BIG_ENDIAN 2812 for(i = 0; i < slen/4; i ++) 2813 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2814 #endif 2815 return(hlen); 2816 } 2817 2818 static int 2819 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2820 { 2821 const struct tcode_info *info; 2822 int r; 2823 2824 info = &tinfo[fp->mode.common.tcode]; 2825 r = info->hdr_len + sizeof(uint32_t); 2826 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2827 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2828 2829 if (r == sizeof(uint32_t)) { 2830 /* XXX */ 2831 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2832 fp->mode.common.tcode); 2833 return (-1); 2834 } 2835 2836 if (r > dbch->xferq.psize) { 2837 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2838 return (-1); 2839 /* panic ? */ 2840 } 2841 2842 return r; 2843 } 2844 2845 static void 2846 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2847 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2848 { 2849 struct fwohcidb *db = &db_tr->db[0]; 2850 2851 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2852 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2853 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2854 fwdma_sync_multiseg_all(dbch->am, 2855 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2856 dbch->bottom = db_tr; 2857 2858 if (wake) 2859 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2860 } 2861 2862 static void 2863 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2864 { 2865 struct fwohcidb_tr *db_tr; 2866 struct iovec vec[2]; 2867 struct fw_pkt pktbuf; 2868 int nvec; 2869 struct fw_pkt *fp; 2870 uint8_t *ld; 2871 uint32_t stat, off, status, event; 2872 u_int spd; 2873 int len, plen, hlen, pcnt, offset; 2874 int s; 2875 void *buf; 2876 int resCount; 2877 2878 CTR0(KTR_DEV, "fwohci_arv"); 2879 2880 if(&sc->arrq == dbch){ 2881 off = OHCI_ARQOFF; 2882 }else if(&sc->arrs == dbch){ 2883 off = OHCI_ARSOFF; 2884 }else{ 2885 return; 2886 } 2887 2888 s = splfw(); 2889 db_tr = dbch->top; 2890 pcnt = 0; 2891 /* XXX we cannot handle a packet which lies in more than two buf */ 2892 fwdma_sync_multiseg_all(dbch->am, 2893 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2894 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2895 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2896 while (status & OHCI_CNTL_DMA_ACTIVE) { 2897 #if 0 2898 2899 if (off == OHCI_ARQOFF) 2900 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2901 db_tr->bus_addr, status, resCount); 2902 #endif 2903 len = dbch->xferq.psize - resCount; 2904 ld = (uint8_t *)db_tr->buf; 2905 if (dbch->pdb_tr == NULL) { 2906 len -= dbch->buf_offset; 2907 ld += dbch->buf_offset; 2908 } 2909 if (len > 0) 2910 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2911 BUS_DMASYNC_POSTREAD); 2912 while (len > 0 ) { 2913 if (count >= 0 && count-- == 0) 2914 goto out; 2915 if(dbch->pdb_tr != NULL){ 2916 /* we have a fragment in previous buffer */ 2917 int rlen; 2918 2919 offset = dbch->buf_offset; 2920 if (offset < 0) 2921 offset = - offset; 2922 buf = (char *)dbch->pdb_tr->buf + offset; 2923 rlen = dbch->xferq.psize - offset; 2924 if (firewire_debug) 2925 printf("rlen=%d, offset=%d\n", 2926 rlen, dbch->buf_offset); 2927 if (dbch->buf_offset < 0) { 2928 /* splitted in header, pull up */ 2929 char *p; 2930 2931 p = (char *)&pktbuf; 2932 bcopy(buf, p, rlen); 2933 p += rlen; 2934 /* this must be too long but harmless */ 2935 rlen = sizeof(pktbuf) - rlen; 2936 if (rlen < 0) 2937 printf("why rlen < 0\n"); 2938 bcopy(db_tr->buf, p, rlen); 2939 ld += rlen; 2940 len -= rlen; 2941 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2942 if (hlen <= 0) { 2943 printf("hlen < 0 shouldn't happen"); 2944 goto err; 2945 } 2946 offset = sizeof(pktbuf); 2947 vec[0].iov_base = (char *)&pktbuf; 2948 vec[0].iov_len = offset; 2949 } else { 2950 /* splitted in payload */ 2951 offset = rlen; 2952 vec[0].iov_base = buf; 2953 vec[0].iov_len = rlen; 2954 } 2955 fp=(struct fw_pkt *)vec[0].iov_base; 2956 nvec = 1; 2957 } else { 2958 /* no fragment in previous buffer */ 2959 fp=(struct fw_pkt *)ld; 2960 hlen = fwohci_arcv_swap(fp, len); 2961 if (hlen == 0) 2962 goto err; 2963 if (hlen < 0) { 2964 dbch->pdb_tr = db_tr; 2965 dbch->buf_offset = - dbch->buf_offset; 2966 /* sanity check */ 2967 if (resCount != 0) { 2968 printf("resCount=%d hlen=%d\n", 2969 resCount, hlen); 2970 goto err; 2971 } 2972 goto out; 2973 } 2974 offset = 0; 2975 nvec = 0; 2976 } 2977 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2978 if (plen < 0) { 2979 /* minimum header size + trailer 2980 = sizeof(fw_pkt) so this shouldn't happens */ 2981 printf("plen(%d) is negative! offset=%d\n", 2982 plen, offset); 2983 goto err; 2984 } 2985 if (plen > 0) { 2986 len -= plen; 2987 if (len < 0) { 2988 dbch->pdb_tr = db_tr; 2989 if (firewire_debug) 2990 printf("splitted payload\n"); 2991 /* sanity check */ 2992 if (resCount != 0) { 2993 printf("resCount=%d plen=%d" 2994 " len=%d\n", 2995 resCount, plen, len); 2996 goto err; 2997 } 2998 goto out; 2999 } 3000 vec[nvec].iov_base = ld; 3001 vec[nvec].iov_len = plen; 3002 nvec ++; 3003 ld += plen; 3004 } 3005 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3006 if (nvec == 0) 3007 printf("nvec == 0\n"); 3008 3009 /* DMA result-code will be written at the tail of packet */ 3010 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3011 #if 0 3012 printf("plen: %d, stat %x\n", 3013 plen ,stat); 3014 #endif 3015 spd = (stat >> 21) & 0x3; 3016 event = (stat >> 16) & 0x1f; 3017 switch (event) { 3018 case FWOHCIEV_ACKPEND: 3019 #if 0 3020 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3021 #endif 3022 /* fall through */ 3023 case FWOHCIEV_ACKCOMPL: 3024 { 3025 struct fw_rcv_buf rb; 3026 3027 if ((vec[nvec-1].iov_len -= 3028 sizeof(struct fwohci_trailer)) == 0) 3029 nvec--; 3030 rb.fc = &sc->fc; 3031 rb.vec = vec; 3032 rb.nvec = nvec; 3033 rb.spd = spd; 3034 fw_rcv(&rb); 3035 break; 3036 } 3037 case FWOHCIEV_BUSRST: 3038 if (sc->fc.status != FWBUSRESET) 3039 printf("got BUSRST packet!?\n"); 3040 break; 3041 default: 3042 device_printf(sc->fc.dev, 3043 "Async DMA Receive error err=%02x %s" 3044 " plen=%d offset=%d len=%d status=0x%08x" 3045 " tcode=0x%x, stat=0x%08x\n", 3046 event, fwohcicode[event], plen, 3047 dbch->buf_offset, len, 3048 OREAD(sc, OHCI_DMACTL(off)), 3049 fp->mode.common.tcode, stat); 3050 #if 1 /* XXX */ 3051 goto err; 3052 #endif 3053 break; 3054 } 3055 pcnt ++; 3056 if (dbch->pdb_tr != NULL) { 3057 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3058 off, 1); 3059 dbch->pdb_tr = NULL; 3060 } 3061 3062 } 3063 out: 3064 if (resCount == 0) { 3065 /* done on this buffer */ 3066 if (dbch->pdb_tr == NULL) { 3067 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3068 dbch->buf_offset = 0; 3069 } else 3070 if (dbch->pdb_tr != db_tr) 3071 printf("pdb_tr != db_tr\n"); 3072 db_tr = STAILQ_NEXT(db_tr, link); 3073 fwdma_sync_multiseg_all(dbch->am, 3074 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3075 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3076 >> OHCI_STATUS_SHIFT; 3077 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3078 & OHCI_COUNT_MASK; 3079 /* XXX check buffer overrun */ 3080 dbch->top = db_tr; 3081 } else { 3082 dbch->buf_offset = dbch->xferq.psize - resCount; 3083 fw_bus_dmamap_sync( 3084 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3085 break; 3086 } 3087 /* XXX make sure DMA is not dead */ 3088 } 3089 #if 0 3090 if (pcnt < 1) 3091 printf("fwohci_arcv: no packets\n"); 3092 #endif 3093 fwdma_sync_multiseg_all(dbch->am, 3094 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3095 splx(s); 3096 return; 3097 3098 err: 3099 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3100 OREAD(sc, OHCI_DMACTL(off))); 3101 dbch->pdb_tr = NULL; 3102 /* skip until resCount != 0 */ 3103 printf(" skip buffer"); 3104 while (resCount == 0) { 3105 printf(" #"); 3106 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3107 db_tr = STAILQ_NEXT(db_tr, link); 3108 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3109 & OHCI_COUNT_MASK; 3110 } 3111 printf(" done\n"); 3112 dbch->top = db_tr; 3113 dbch->buf_offset = dbch->xferq.psize - resCount; 3114 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3115 fwdma_sync_multiseg_all( 3116 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3117 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3118 splx(s); 3119 } 3120 #if defined(__NetBSD__) 3121 3122 int 3123 fwohci_print(void *aux, const char *pnp) 3124 { 3125 struct fw_attach_args *fwa = (struct fw_attach_args *)aux; 3126 3127 if (pnp) 3128 aprint_normal("%s at %s", fwa->name, pnp); 3129 3130 return UNCONF; 3131 } 3132 #endif 3133
Indexes created Mon Oct 13 05:10:05 GMT 2025