fwohci.c revision 1.106
1 /* $NetBSD: fwohci.c,v 1.106 2007/03/04 06:02:05 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.106 2007/03/04 06:02:05 christos Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 107 #include "ioconf.h" 108 #endif 109 110 #undef OHCI_DEBUG 111 112 static int nocyclemaster = 0; 113 #if defined(__FreeBSD__) 114 SYSCTL_DECL(_hw_firewire); 115 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 116 "Do not send cycle start packets"); 117 #elif defined(__NetBSD__) 118 /* 119 * Setup sysctl(3) MIB, hw.fwohci.* 120 * 121 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 122 */ 123 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 124 { 125 int rc; 126 const struct sysctlnode *node; 127 128 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 130 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 131 goto err; 132 } 133 134 if ((rc = sysctl_createv(clog, 0, NULL, &node, 135 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 136 SYSCTL_DESCR("fwohci controls"), 137 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 138 goto err; 139 } 140 141 /* fwohci no cyclemaster flag */ 142 if ((rc = sysctl_createv(clog, 0, NULL, &node, 143 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 144 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 145 NULL, 0, &nocyclemaster, 146 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 147 goto err; 148 } 149 return; 150 151 err: 152 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 153 } 154 #endif 155 156 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 157 "STOR","LOAD","NOP ","STOP", 158 "", "", "", "", "", "", "", ""}; 159 160 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 161 "UNDEF","REG","SYS","DEV"}; 162 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 163 static const char * const fwohcicode[32] = { 164 "No stat","Undef","long","miss Ack err", 165 "underrun","overrun","desc err", "data read err", 166 "data write err","bus reset","timeout","tcode err", 167 "Undef","Undef","unknown event","flushed", 168 "Undef","ack complete","ack pend","Undef", 169 "ack busy_X","ack busy_A","ack busy_B","Undef", 170 "Undef","Undef","Undef","ack tardy", 171 "Undef","ack data_err","ack type_err",""}; 172 173 #define MAX_SPEED 3 174 extern const char *fw_linkspeed[]; 175 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 176 177 static const struct tcode_info tinfo[] = { 178 /* hdr_len block flag*/ 179 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 180 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 181 /* 2 WRES */ {12, FWTI_RES}, 182 /* 3 XXX */ { 0, 0}, 183 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 184 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 185 /* 6 RRESQ */ {16, FWTI_RES}, 186 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 187 /* 8 CYCS */ { 0, 0}, 188 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 189 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 190 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 191 /* c XXX */ { 0, 0}, 192 /* d XXX */ { 0, 0}, 193 /* e PHY */ {12, FWTI_REQ}, 194 /* f XXX */ { 0, 0} 195 }; 196 197 #define OHCI_WRITE_SIGMASK 0xffff0000 198 #define OHCI_READ_SIGMASK 0xffff0000 199 200 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 201 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 202 203 static void fwohci_ibr (struct firewire_comm *); 204 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 205 static void fwohci_db_free (struct fwohci_dbch *); 206 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 207 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 208 static void fwohci_start_atq (struct firewire_comm *); 209 static void fwohci_start_ats (struct firewire_comm *); 210 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 211 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 212 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 213 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 214 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 215 static int fwohci_irx_enable (struct firewire_comm *, int); 216 static int fwohci_irx_disable (struct firewire_comm *, int); 217 #if BYTE_ORDER == BIG_ENDIAN 218 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 219 #endif 220 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 221 static int fwohci_itx_disable (struct firewire_comm *, int); 222 static void fwohci_timeout (void *); 223 static void fwohci_set_intr (struct firewire_comm *, int); 224 225 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 226 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 227 static void dump_db (struct fwohci_softc *, uint32_t); 228 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 229 static void dump_dma (struct fwohci_softc *, uint32_t); 230 static uint32_t fwohci_cyctimer (struct firewire_comm *); 231 static void fwohci_rbuf_update (struct fwohci_softc *, int); 232 static void fwohci_tbuf_update (struct fwohci_softc *, int); 233 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 234 #if FWOHCI_TASKQUEUE 235 static void fwohci_complete(void *, int); 236 #endif 237 #if defined(__NetBSD__) 238 static void fwohci_power(int, void *); 239 int fwohci_print(void *, const char *); 240 #endif 241 242 /* 243 * memory allocated for DMA programs 244 */ 245 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 246 247 #define NDB FWMAXQUEUE 248 249 #define OHCI_VERSION 0x00 250 #define OHCI_ATRETRY 0x08 251 #define OHCI_CROMHDR 0x18 252 #define OHCI_BUS_OPT 0x20 253 #define OHCI_BUSIRMC (1 << 31) 254 #define OHCI_BUSCMC (1 << 30) 255 #define OHCI_BUSISC (1 << 29) 256 #define OHCI_BUSBMC (1 << 28) 257 #define OHCI_BUSPMC (1 << 27) 258 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 259 OHCI_BUSBMC | OHCI_BUSPMC 260 261 #define OHCI_EUID_HI 0x24 262 #define OHCI_EUID_LO 0x28 263 264 #define OHCI_CROMPTR 0x34 265 #define OHCI_HCCCTL 0x50 266 #define OHCI_HCCCTLCLR 0x54 267 #define OHCI_AREQHI 0x100 268 #define OHCI_AREQHICLR 0x104 269 #define OHCI_AREQLO 0x108 270 #define OHCI_AREQLOCLR 0x10c 271 #define OHCI_PREQHI 0x110 272 #define OHCI_PREQHICLR 0x114 273 #define OHCI_PREQLO 0x118 274 #define OHCI_PREQLOCLR 0x11c 275 #define OHCI_PREQUPPER 0x120 276 277 #define OHCI_SID_BUF 0x64 278 #define OHCI_SID_CNT 0x68 279 #define OHCI_SID_ERR (1 << 31) 280 #define OHCI_SID_CNT_MASK 0xffc 281 282 #define OHCI_IT_STAT 0x90 283 #define OHCI_IT_STATCLR 0x94 284 #define OHCI_IT_MASK 0x98 285 #define OHCI_IT_MASKCLR 0x9c 286 287 #define OHCI_IR_STAT 0xa0 288 #define OHCI_IR_STATCLR 0xa4 289 #define OHCI_IR_MASK 0xa8 290 #define OHCI_IR_MASKCLR 0xac 291 292 #define OHCI_LNKCTL 0xe0 293 #define OHCI_LNKCTLCLR 0xe4 294 295 #define OHCI_PHYACCESS 0xec 296 #define OHCI_CYCLETIMER 0xf0 297 298 #define OHCI_DMACTL(off) (off) 299 #define OHCI_DMACTLCLR(off) (off + 4) 300 #define OHCI_DMACMD(off) (off + 0xc) 301 #define OHCI_DMAMATCH(off) (off + 0x10) 302 303 #define OHCI_ATQOFF 0x180 304 #define OHCI_ATQCTL OHCI_ATQOFF 305 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 306 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 307 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 308 309 #define OHCI_ATSOFF 0x1a0 310 #define OHCI_ATSCTL OHCI_ATSOFF 311 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 312 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 313 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 314 315 #define OHCI_ARQOFF 0x1c0 316 #define OHCI_ARQCTL OHCI_ARQOFF 317 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 318 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 319 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 320 321 #define OHCI_ARSOFF 0x1e0 322 #define OHCI_ARSCTL OHCI_ARSOFF 323 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 324 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 325 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 326 327 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 328 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 329 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 330 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 331 332 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 333 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 334 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 335 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 336 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 337 338 #if defined(__FreeBSD__) 339 d_ioctl_t fwohci_ioctl; 340 #elif defined(__NetBSD__) 341 dev_type_ioctl(fwohci_ioctl); 342 #endif 343 344 /* 345 * Communication with PHY device 346 */ 347 static uint32_t 348 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 349 { 350 uint32_t fun; 351 352 addr &= 0xf; 353 data &= 0xff; 354 355 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 356 OWRITE(sc, OHCI_PHYACCESS, fun); 357 DELAY(100); 358 359 return(fwphy_rddata( sc, addr)); 360 } 361 362 static uint32_t 363 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 364 { 365 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 366 int i; 367 uint32_t bm; 368 369 #define OHCI_CSR_DATA 0x0c 370 #define OHCI_CSR_COMP 0x10 371 #define OHCI_CSR_CONT 0x14 372 #define OHCI_BUS_MANAGER_ID 0 373 374 OWRITE(sc, OHCI_CSR_DATA, node); 375 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 376 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 377 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 378 DELAY(10); 379 bm = OREAD(sc, OHCI_CSR_DATA); 380 if((bm & 0x3f) == 0x3f) 381 bm = node; 382 if (firewire_debug) 383 device_printf(sc->fc.dev, 384 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 385 386 return(bm); 387 } 388 389 static uint32_t 390 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 391 { 392 uint32_t fun, stat; 393 u_int i, retry = 0; 394 395 addr &= 0xf; 396 #define MAX_RETRY 100 397 again: 398 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 399 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 400 OWRITE(sc, OHCI_PHYACCESS, fun); 401 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 402 fun = OREAD(sc, OHCI_PHYACCESS); 403 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 404 break; 405 DELAY(100); 406 } 407 if(i >= MAX_RETRY) { 408 if (firewire_debug) 409 device_printf(sc->fc.dev, "phy read failed(1).\n"); 410 if (++retry < MAX_RETRY) { 411 DELAY(100); 412 goto again; 413 } 414 } 415 /* Make sure that SCLK is started */ 416 stat = OREAD(sc, FWOHCI_INTSTAT); 417 if ((stat & OHCI_INT_REG_FAIL) != 0 || 418 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 419 if (firewire_debug) 420 device_printf(sc->fc.dev, "phy read failed(2).\n"); 421 if (++retry < MAX_RETRY) { 422 DELAY(100); 423 goto again; 424 } 425 } 426 if (firewire_debug || retry >= MAX_RETRY) 427 device_printf(sc->fc.dev, 428 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 429 #undef MAX_RETRY 430 return((fun >> PHYDEV_RDDATA )& 0xff); 431 } 432 /* Device specific ioctl. */ 433 FW_IOCTL(fwohci) 434 { 435 FW_IOCTL_START; 436 struct fwohci_softc *fc; 437 int err = 0; 438 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 439 uint32_t *dmach = (uint32_t *) data; 440 441 if(sc == NULL){ 442 return(EINVAL); 443 } 444 fc = (struct fwohci_softc *)sc->fc; 445 446 if (!data) 447 return(EINVAL); 448 449 switch (cmd) { 450 case FWOHCI_WRREG: 451 #define OHCI_MAX_REG 0x800 452 if(reg->addr <= OHCI_MAX_REG){ 453 OWRITE(fc, reg->addr, reg->data); 454 reg->data = OREAD(fc, reg->addr); 455 }else{ 456 err = EINVAL; 457 } 458 break; 459 case FWOHCI_RDREG: 460 if(reg->addr <= OHCI_MAX_REG){ 461 reg->data = OREAD(fc, reg->addr); 462 }else{ 463 err = EINVAL; 464 } 465 break; 466 /* Read DMA descriptors for debug */ 467 case DUMPDMA: 468 if(*dmach <= OHCI_MAX_DMA_CH ){ 469 dump_dma(fc, *dmach); 470 dump_db(fc, *dmach); 471 }else{ 472 err = EINVAL; 473 } 474 break; 475 /* Read/Write Phy registers */ 476 #define OHCI_MAX_PHY_REG 0xf 477 case FWOHCI_RDPHYREG: 478 if (reg->addr <= OHCI_MAX_PHY_REG) 479 reg->data = fwphy_rddata(fc, reg->addr); 480 else 481 err = EINVAL; 482 break; 483 case FWOHCI_WRPHYREG: 484 if (reg->addr <= OHCI_MAX_PHY_REG) 485 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 486 else 487 err = EINVAL; 488 break; 489 default: 490 err = EINVAL; 491 break; 492 } 493 return err; 494 } 495 496 static int 497 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 498 { 499 uint32_t reg, reg2; 500 int e1394a = 1; 501 /* 502 * probe PHY parameters 503 * 0. to prove PHY version, whether compliance of 1394a. 504 * 1. to probe maximum speed supported by the PHY and 505 * number of port supported by core-logic. 506 * It is not actually available port on your PC . 507 */ 508 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 509 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 510 511 if((reg >> 5) != 7 ){ 512 sc->fc.mode &= ~FWPHYASYST; 513 sc->fc.nport = reg & FW_PHY_NP; 514 sc->fc.speed = reg & FW_PHY_SPD >> 6; 515 if (sc->fc.speed > MAX_SPEED) { 516 device_printf(dev, "invalid speed %d (fixed to %d).\n", 517 sc->fc.speed, MAX_SPEED); 518 sc->fc.speed = MAX_SPEED; 519 } 520 device_printf(dev, 521 "Phy 1394 only %s, %d ports.\n", 522 fw_linkspeed[sc->fc.speed], sc->fc.nport); 523 }else{ 524 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 525 sc->fc.mode |= FWPHYASYST; 526 sc->fc.nport = reg & FW_PHY_NP; 527 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 528 if (sc->fc.speed > MAX_SPEED) { 529 device_printf(dev, "invalid speed %d (fixed to %d).\n", 530 sc->fc.speed, MAX_SPEED); 531 sc->fc.speed = MAX_SPEED; 532 } 533 device_printf(dev, 534 "Phy 1394a available %s, %d ports.\n", 535 fw_linkspeed[sc->fc.speed], sc->fc.nport); 536 537 /* check programPhyEnable */ 538 reg2 = fwphy_rddata(sc, 5); 539 #if 0 540 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 541 #else /* XXX force to enable 1394a */ 542 if (e1394a) { 543 #endif 544 if (firewire_debug) 545 device_printf(dev, 546 "Enable 1394a Enhancements\n"); 547 /* enable EAA EMC */ 548 reg2 |= 0x03; 549 /* set aPhyEnhanceEnable */ 550 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 551 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 552 } 553 #if 0 554 else { 555 /* for safe */ 556 reg2 &= ~0x83; 557 } 558 #endif 559 reg2 = fwphy_wrdata(sc, 5, reg2); 560 } 561 562 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 563 if((reg >> 5) == 7 ){ 564 reg = fwphy_rddata(sc, 4); 565 reg |= 1 << 6; 566 fwphy_wrdata(sc, 4, reg); 567 reg = fwphy_rddata(sc, 4); 568 } 569 return 0; 570 } 571 572 573 void 574 fwohci_reset(struct fwohci_softc *sc, device_t dev) 575 { 576 int i, max_rec, speed; 577 uint32_t reg, reg2; 578 struct fwohcidb_tr *db_tr; 579 580 /* Disable interrupts */ 581 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 582 583 /* Now stopping all DMA channels */ 584 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 585 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 586 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 587 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 588 589 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 590 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 591 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 592 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 593 } 594 595 /* FLUSH FIFO and reset Transmitter/Reciever */ 596 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 597 if (firewire_debug) 598 device_printf(dev, "resetting OHCI..."); 599 i = 0; 600 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 601 if (i++ > 100) break; 602 DELAY(1000); 603 } 604 if (firewire_debug) 605 printf("done (loop=%d)\n", i); 606 607 /* Probe phy */ 608 fwohci_probe_phy(sc, dev); 609 610 /* Probe link */ 611 reg = OREAD(sc, OHCI_BUS_OPT); 612 reg2 = reg | OHCI_BUSFNC; 613 max_rec = (reg & 0x0000f000) >> 12; 614 speed = (reg & 0x00000007); 615 device_printf(dev, "Link %s, max_rec %d bytes.\n", 616 fw_linkspeed[speed], MAXREC(max_rec)); 617 /* XXX fix max_rec */ 618 sc->fc.maxrec = sc->fc.speed + 8; 619 if (max_rec != sc->fc.maxrec) { 620 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 621 device_printf(dev, "max_rec %d -> %d\n", 622 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 623 } 624 if (firewire_debug) 625 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 626 OWRITE(sc, OHCI_BUS_OPT, reg2); 627 628 /* Initialize registers */ 629 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 630 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 631 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 632 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 633 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 634 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 635 636 /* Enable link */ 637 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 638 639 /* Force to start async RX DMA */ 640 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 641 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 642 fwohci_rx_enable(sc, &sc->arrq); 643 fwohci_rx_enable(sc, &sc->arrs); 644 645 /* Initialize async TX */ 646 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 647 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 648 649 /* AT Retries */ 650 OWRITE(sc, FWOHCI_RETRY, 651 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 652 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 653 654 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 655 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 656 sc->atrq.bottom = sc->atrq.top; 657 sc->atrs.bottom = sc->atrs.top; 658 659 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 660 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 661 db_tr->xfer = NULL; 662 } 663 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 664 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 665 db_tr->xfer = NULL; 666 } 667 668 669 /* Enable interrupts */ 670 OWRITE(sc, FWOHCI_INTMASK, 671 OHCI_INT_ERR | OHCI_INT_PHY_SID 672 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 673 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 674 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 675 fwohci_set_intr(&sc->fc, 1); 676 677 } 678 679 int 680 fwohci_init(struct fwohci_softc *sc, device_t dev) 681 { 682 int i, mver; 683 uint32_t reg; 684 uint8_t ui[8]; 685 686 #if FWOHCI_TASKQUEUE 687 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 688 #endif 689 690 /* OHCI version */ 691 reg = OREAD(sc, OHCI_VERSION); 692 mver = (reg >> 16) & 0xff; 693 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 694 mver, reg & 0xff, (reg>>24) & 1); 695 if (mver < 1 || mver > 9) { 696 device_printf(dev, "invalid OHCI version\n"); 697 return (ENXIO); 698 } 699 700 /* Available Isochronous DMA channel probe */ 701 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 702 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 703 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 704 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 705 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 706 for (i = 0; i < 0x20; i++) 707 if ((reg & (1 << i)) == 0) 708 break; 709 sc->fc.nisodma = i; 710 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 711 if (i == 0) 712 return (ENXIO); 713 714 sc->fc.arq = &sc->arrq.xferq; 715 sc->fc.ars = &sc->arrs.xferq; 716 sc->fc.atq = &sc->atrq.xferq; 717 sc->fc.ats = &sc->atrs.xferq; 718 719 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 720 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 721 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 722 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 723 724 sc->arrq.xferq.start = NULL; 725 sc->arrs.xferq.start = NULL; 726 sc->atrq.xferq.start = fwohci_start_atq; 727 sc->atrs.xferq.start = fwohci_start_ats; 728 729 sc->arrq.xferq.buf = NULL; 730 sc->arrs.xferq.buf = NULL; 731 sc->atrq.xferq.buf = NULL; 732 sc->atrs.xferq.buf = NULL; 733 734 sc->arrq.xferq.dmach = -1; 735 sc->arrs.xferq.dmach = -1; 736 sc->atrq.xferq.dmach = -1; 737 sc->atrs.xferq.dmach = -1; 738 739 sc->arrq.ndesc = 1; 740 sc->arrs.ndesc = 1; 741 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 742 sc->atrs.ndesc = 2; 743 744 sc->arrq.ndb = NDB; 745 sc->arrs.ndb = NDB / 2; 746 sc->atrq.ndb = NDB; 747 sc->atrs.ndb = NDB / 2; 748 749 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 750 sc->fc.it[i] = &sc->it[i].xferq; 751 sc->fc.ir[i] = &sc->ir[i].xferq; 752 sc->it[i].xferq.dmach = i; 753 sc->ir[i].xferq.dmach = i; 754 sc->it[i].ndb = 0; 755 sc->ir[i].ndb = 0; 756 } 757 758 sc->fc.tcode = tinfo; 759 sc->fc.dev = dev; 760 761 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 762 &sc->crom_dma, BUS_DMA_WAITOK); 763 if(sc->fc.config_rom == NULL){ 764 device_printf(dev, "config_rom alloc failed."); 765 return ENOMEM; 766 } 767 768 #if 0 769 bzero(&sc->fc.config_rom[0], CROMSIZE); 770 sc->fc.config_rom[1] = 0x31333934; 771 sc->fc.config_rom[2] = 0xf000a002; 772 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 773 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 774 sc->fc.config_rom[5] = 0; 775 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 776 777 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 778 #endif 779 780 781 /* SID recieve buffer must align 2^11 */ 782 #define OHCI_SIDSIZE (1 << 11) 783 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 784 &sc->sid_dma, BUS_DMA_WAITOK); 785 if (sc->sid_buf == NULL) { 786 device_printf(dev, "sid_buf alloc failed."); 787 return ENOMEM; 788 } 789 790 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 791 &sc->dummy_dma, BUS_DMA_WAITOK); 792 793 if (sc->dummy_dma.v_addr == NULL) { 794 device_printf(dev, "dummy_dma alloc failed."); 795 return ENOMEM; 796 } 797 798 fwohci_db_init(sc, &sc->arrq); 799 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 800 return ENOMEM; 801 802 fwohci_db_init(sc, &sc->arrs); 803 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 804 return ENOMEM; 805 806 fwohci_db_init(sc, &sc->atrq); 807 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 808 return ENOMEM; 809 810 fwohci_db_init(sc, &sc->atrs); 811 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 812 return ENOMEM; 813 814 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 815 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 816 for( i = 0 ; i < 8 ; i ++) 817 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 818 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 819 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 820 821 sc->fc.ioctl = fwohci_ioctl; 822 sc->fc.cyctimer = fwohci_cyctimer; 823 sc->fc.set_bmr = fwohci_set_bus_manager; 824 sc->fc.ibr = fwohci_ibr; 825 sc->fc.irx_enable = fwohci_irx_enable; 826 sc->fc.irx_disable = fwohci_irx_disable; 827 828 sc->fc.itx_enable = fwohci_itxbuf_enable; 829 sc->fc.itx_disable = fwohci_itx_disable; 830 #if BYTE_ORDER == BIG_ENDIAN 831 sc->fc.irx_post = fwohci_irx_post; 832 #else 833 sc->fc.irx_post = NULL; 834 #endif 835 sc->fc.itx_post = NULL; 836 sc->fc.timeout = fwohci_timeout; 837 sc->fc.poll = fwohci_poll; 838 sc->fc.set_intr = fwohci_set_intr; 839 840 sc->intmask = sc->irstat = sc->itstat = 0; 841 842 fw_init(&sc->fc); 843 fwohci_reset(sc, dev); 844 FWOHCI_INIT_END; 845 846 return 0; 847 } 848 849 void 850 fwohci_timeout(void *arg) 851 { 852 struct fwohci_softc *sc; 853 854 sc = (struct fwohci_softc *)arg; 855 } 856 857 uint32_t 858 fwohci_cyctimer(struct firewire_comm *fc) 859 { 860 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 861 return(OREAD(sc, OHCI_CYCLETIMER)); 862 } 863 864 FWOHCI_DETACH() 865 { 866 int i; 867 868 FWOHCI_DETACH_START; 869 if (sc->sid_buf != NULL) 870 fwdma_free(&sc->fc, &sc->sid_dma); 871 if (sc->fc.config_rom != NULL) 872 fwdma_free(&sc->fc, &sc->crom_dma); 873 874 fwohci_db_free(&sc->arrq); 875 fwohci_db_free(&sc->arrs); 876 877 fwohci_db_free(&sc->atrq); 878 fwohci_db_free(&sc->atrs); 879 880 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 881 fwohci_db_free(&sc->it[i]); 882 fwohci_db_free(&sc->ir[i]); 883 } 884 FWOHCI_DETACH_END; 885 886 return 0; 887 } 888 889 #define LAST_DB(dbtr, db) do { \ 890 struct fwohcidb_tr *_dbtr = (dbtr); \ 891 int _cnt = _dbtr->dbcnt; \ 892 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 893 } while (0) 894 895 static void 896 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 897 { 898 struct fwohcidb_tr *db_tr; 899 struct fwohcidb *db; 900 bus_dma_segment_t *s; 901 int i; 902 903 db_tr = (struct fwohcidb_tr *)arg; 904 db = &db_tr->db[db_tr->dbcnt]; 905 if (error) { 906 if (firewire_debug || error != EFBIG) 907 printf("fwohci_execute_db: error=%d\n", error); 908 return; 909 } 910 for (i = 0; i < nseg; i++) { 911 s = &segs[i]; 912 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 913 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 914 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 915 db++; 916 db_tr->dbcnt++; 917 } 918 } 919 920 static void 921 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 922 bus_size_t size, int error) 923 { 924 fwohci_execute_db(arg, segs, nseg, error); 925 } 926 927 static void 928 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 929 { 930 int i, s; 931 int tcode, hdr_len, pl_off; 932 int fsegment = -1; 933 uint32_t off; 934 struct fw_xfer *xfer; 935 struct fw_pkt *fp; 936 struct fwohci_txpkthdr *ohcifp; 937 struct fwohcidb_tr *db_tr; 938 struct fwohcidb *db; 939 uint32_t *ld; 940 const struct tcode_info *info; 941 static int maxdesc=0; 942 943 if(&sc->atrq == dbch){ 944 off = OHCI_ATQOFF; 945 }else if(&sc->atrs == dbch){ 946 off = OHCI_ATSOFF; 947 }else{ 948 return; 949 } 950 951 if (dbch->flags & FWOHCI_DBCH_FULL) 952 return; 953 954 s = splfw(); 955 fwdma_sync_multiseg_all(dbch->am, 956 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 957 db_tr = dbch->top; 958 txloop: 959 xfer = STAILQ_FIRST(&dbch->xferq.q); 960 if(xfer == NULL){ 961 goto kick; 962 } 963 if(dbch->xferq.queued == 0 ){ 964 device_printf(sc->fc.dev, "TX queue empty\n"); 965 } 966 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 967 db_tr->xfer = xfer; 968 xfer->state = FWXF_START; 969 970 fp = &xfer->send.hdr; 971 tcode = fp->mode.common.tcode; 972 973 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 974 info = &tinfo[tcode]; 975 hdr_len = pl_off = info->hdr_len; 976 977 ld = &ohcifp->mode.ld[0]; 978 ld[0] = ld[1] = ld[2] = ld[3] = 0; 979 for( i = 0 ; i < pl_off ; i+= 4) 980 ld[i/4] = fp->mode.ld[i/4]; 981 982 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 983 if (tcode == FWTCODE_STREAM ){ 984 hdr_len = 8; 985 ohcifp->mode.stream.len = fp->mode.stream.len; 986 } else if (tcode == FWTCODE_PHY) { 987 hdr_len = 12; 988 ld[1] = fp->mode.ld[1]; 989 ld[2] = fp->mode.ld[2]; 990 ohcifp->mode.common.spd = 0; 991 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 992 } else { 993 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 994 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 995 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 996 } 997 db = &db_tr->db[0]; 998 FWOHCI_DMA_WRITE(db->db.desc.cmd, 999 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 1000 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1001 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1002 /* Specify bound timer of asy. responce */ 1003 if(&sc->atrs == dbch){ 1004 FWOHCI_DMA_WRITE(db->db.desc.res, 1005 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1006 } 1007 #if BYTE_ORDER == BIG_ENDIAN 1008 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1009 hdr_len = 12; 1010 for (i = 0; i < hdr_len/4; i ++) 1011 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1012 #endif 1013 1014 again: 1015 db_tr->dbcnt = 2; 1016 db = &db_tr->db[db_tr->dbcnt]; 1017 if (xfer->send.pay_len > 0) { 1018 int err; 1019 /* handle payload */ 1020 if (xfer->mbuf == NULL) { 1021 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1022 &xfer->send.payload[0], xfer->send.pay_len, 1023 fwohci_execute_db, db_tr, 1024 BUS_DMA_WAITOK); 1025 } else { 1026 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1027 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1028 db_tr->dma_map, xfer->mbuf, 1029 fwohci_execute_db2, db_tr, 1030 BUS_DMA_WAITOK); 1031 if (err == EFBIG) { 1032 struct mbuf *m0; 1033 1034 if (firewire_debug) 1035 device_printf(sc->fc.dev, "EFBIG.\n"); 1036 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1037 if (m0 != NULL) { 1038 m_copydata(xfer->mbuf, 0, 1039 xfer->mbuf->m_pkthdr.len, 1040 mtod(m0, void *)); 1041 m0->m_len = m0->m_pkthdr.len = 1042 xfer->mbuf->m_pkthdr.len; 1043 m_freem(xfer->mbuf); 1044 xfer->mbuf = m0; 1045 goto again; 1046 } 1047 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1048 } 1049 } 1050 if (err) 1051 printf("dmamap_load: err=%d\n", err); 1052 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1053 BUS_DMASYNC_PREWRITE); 1054 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1055 for (i = 2; i < db_tr->dbcnt; i++) 1056 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1057 OHCI_OUTPUT_MORE); 1058 #endif 1059 } 1060 if (maxdesc < db_tr->dbcnt) { 1061 maxdesc = db_tr->dbcnt; 1062 if (firewire_debug) 1063 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1064 } 1065 /* last db */ 1066 LAST_DB(db_tr, db); 1067 FWOHCI_DMA_SET(db->db.desc.cmd, 1068 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1069 FWOHCI_DMA_WRITE(db->db.desc.depend, 1070 STAILQ_NEXT(db_tr, link)->bus_addr); 1071 1072 if(fsegment == -1 ) 1073 fsegment = db_tr->dbcnt; 1074 if (dbch->pdb_tr != NULL) { 1075 LAST_DB(dbch->pdb_tr, db); 1076 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1077 } 1078 dbch->pdb_tr = db_tr; 1079 db_tr = STAILQ_NEXT(db_tr, link); 1080 if(db_tr != dbch->bottom){ 1081 goto txloop; 1082 } else { 1083 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1084 dbch->flags |= FWOHCI_DBCH_FULL; 1085 } 1086 kick: 1087 /* kick asy q */ 1088 fwdma_sync_multiseg_all(dbch->am, 1089 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1090 1091 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1092 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1093 } else { 1094 if (firewire_debug) 1095 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1096 OREAD(sc, OHCI_DMACTL(off))); 1097 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1098 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1099 dbch->xferq.flag |= FWXFERQ_RUNNING; 1100 } 1101 CTR0(KTR_DEV, "start kick done"); 1102 CTR0(KTR_DEV, "start kick done2"); 1103 1104 dbch->top = db_tr; 1105 splx(s); 1106 return; 1107 } 1108 1109 static void 1110 fwohci_start_atq(struct firewire_comm *fc) 1111 { 1112 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1113 fwohci_start( sc, &(sc->atrq)); 1114 return; 1115 } 1116 1117 static void 1118 fwohci_start_ats(struct firewire_comm *fc) 1119 { 1120 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1121 fwohci_start( sc, &(sc->atrs)); 1122 return; 1123 } 1124 1125 void 1126 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1127 { 1128 int s, ch, err = 0; 1129 struct fwohcidb_tr *tr; 1130 struct fwohcidb *db; 1131 struct fw_xfer *xfer; 1132 uint32_t off; 1133 u_int stat, status; 1134 int packets; 1135 struct firewire_comm *fc = (struct firewire_comm *)sc; 1136 1137 if(&sc->atrq == dbch){ 1138 off = OHCI_ATQOFF; 1139 ch = ATRQ_CH; 1140 }else if(&sc->atrs == dbch){ 1141 off = OHCI_ATSOFF; 1142 ch = ATRS_CH; 1143 }else{ 1144 return; 1145 } 1146 s = splfw(); 1147 tr = dbch->bottom; 1148 packets = 0; 1149 fwdma_sync_multiseg_all(dbch->am, 1150 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1151 while(dbch->xferq.queued > 0){ 1152 LAST_DB(tr, db); 1153 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1154 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1155 if (fc->status != FWBUSRESET) 1156 /* maybe out of order?? */ 1157 goto out; 1158 } 1159 if (tr->xfer->send.pay_len > 0) { 1160 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1161 BUS_DMASYNC_POSTWRITE); 1162 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1163 } 1164 #if 1 1165 if (firewire_debug > 1) 1166 dump_db(sc, ch); 1167 #endif 1168 if(status & OHCI_CNTL_DMA_DEAD) { 1169 /* Stop DMA */ 1170 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1171 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1172 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1173 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1174 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1175 } 1176 stat = status & FWOHCIEV_MASK; 1177 switch(stat){ 1178 case FWOHCIEV_ACKPEND: 1179 CTR0(KTR_DEV, "txd: ack pending"); 1180 /* fall through */ 1181 case FWOHCIEV_ACKCOMPL: 1182 err = 0; 1183 break; 1184 case FWOHCIEV_ACKBSA: 1185 case FWOHCIEV_ACKBSB: 1186 case FWOHCIEV_ACKBSX: 1187 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1188 err = EBUSY; 1189 break; 1190 case FWOHCIEV_FLUSHED: 1191 case FWOHCIEV_ACKTARD: 1192 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1193 err = EAGAIN; 1194 break; 1195 case FWOHCIEV_MISSACK: 1196 case FWOHCIEV_UNDRRUN: 1197 case FWOHCIEV_OVRRUN: 1198 case FWOHCIEV_DESCERR: 1199 case FWOHCIEV_DTRDERR: 1200 case FWOHCIEV_TIMEOUT: 1201 case FWOHCIEV_TCODERR: 1202 case FWOHCIEV_UNKNOWN: 1203 case FWOHCIEV_ACKDERR: 1204 case FWOHCIEV_ACKTERR: 1205 default: 1206 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1207 stat, fwohcicode[stat]); 1208 err = EINVAL; 1209 break; 1210 } 1211 if (tr->xfer != NULL) { 1212 xfer = tr->xfer; 1213 CTR0(KTR_DEV, "txd"); 1214 if (xfer->state == FWXF_RCVD) { 1215 #if 0 1216 if (firewire_debug) 1217 printf("already rcvd\n"); 1218 #endif 1219 fw_xfer_done(xfer); 1220 } else { 1221 xfer->state = FWXF_SENT; 1222 if (err == EBUSY && fc->status != FWBUSRESET) { 1223 xfer->state = FWXF_BUSY; 1224 xfer->resp = err; 1225 xfer->recv.pay_len = 0; 1226 fw_xfer_done(xfer); 1227 } else if (stat != FWOHCIEV_ACKPEND) { 1228 if (stat != FWOHCIEV_ACKCOMPL) 1229 xfer->state = FWXF_SENTERR; 1230 xfer->resp = err; 1231 xfer->recv.pay_len = 0; 1232 fw_xfer_done(xfer); 1233 } 1234 } 1235 /* 1236 * The watchdog timer takes care of split 1237 * transcation timeout for ACKPEND case. 1238 */ 1239 } else { 1240 printf("this shouldn't happen\n"); 1241 } 1242 dbch->xferq.queued --; 1243 tr->xfer = NULL; 1244 1245 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1246 packets ++; 1247 tr = STAILQ_NEXT(tr, link); 1248 dbch->bottom = tr; 1249 if (dbch->bottom == dbch->top) { 1250 /* we reaches the end of context program */ 1251 if (firewire_debug && dbch->xferq.queued > 0) 1252 printf("queued > 0\n"); 1253 break; 1254 } 1255 } 1256 out: 1257 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1258 printf("make free slot\n"); 1259 dbch->flags &= ~FWOHCI_DBCH_FULL; 1260 fwohci_start(sc, dbch); 1261 } 1262 fwdma_sync_multiseg_all( 1263 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1264 splx(s); 1265 } 1266 1267 static void 1268 fwohci_db_free(struct fwohci_dbch *dbch) 1269 { 1270 struct fwohcidb_tr *db_tr; 1271 int idb; 1272 1273 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1274 return; 1275 1276 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1277 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1278 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1279 db_tr->buf != NULL) { 1280 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1281 db_tr->buf, dbch->xferq.psize); 1282 db_tr->buf = NULL; 1283 } else if (db_tr->dma_map != NULL) 1284 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1285 } 1286 dbch->ndb = 0; 1287 db_tr = STAILQ_FIRST(&dbch->db_trq); 1288 fwdma_free_multiseg(dbch->am); 1289 free(db_tr, M_FW); 1290 STAILQ_INIT(&dbch->db_trq); 1291 dbch->flags &= ~FWOHCI_DBCH_INIT; 1292 } 1293 1294 static void 1295 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1296 { 1297 int idb; 1298 struct fwohcidb_tr *db_tr; 1299 1300 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1301 goto out; 1302 1303 /* create dma_tag for buffers */ 1304 #define MAX_REQCOUNT 0xffff 1305 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1306 /*alignment*/ 1, /*boundary*/ 0, 1307 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1308 /*highaddr*/ BUS_SPACE_MAXADDR, 1309 /*filter*/NULL, /*filterarg*/NULL, 1310 /*maxsize*/ dbch->xferq.psize, 1311 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1312 /*maxsegsz*/ MAX_REQCOUNT, 1313 /*flags*/ 0, 1314 /*lockfunc*/busdma_lock_mutex, 1315 /*lockarg*/&Giant, 1316 &dbch->dmat)) 1317 return; 1318 1319 /* allocate DB entries and attach one to each DMA channels */ 1320 /* DB entry must start at 16 bytes bounary. */ 1321 STAILQ_INIT(&dbch->db_trq); 1322 db_tr = (struct fwohcidb_tr *) 1323 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1324 M_FW, M_WAITOK | M_ZERO); 1325 if(db_tr == NULL){ 1326 printf("fwohci_db_init: malloc(1) failed\n"); 1327 return; 1328 } 1329 1330 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1331 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1332 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1333 if (dbch->am == NULL) { 1334 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1335 free(db_tr, M_FW); 1336 return; 1337 } 1338 /* Attach DB to DMA ch. */ 1339 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1340 db_tr->dbcnt = 0; 1341 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1342 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1343 /* create dmamap for buffers */ 1344 /* XXX do we need 4bytes alignment tag? */ 1345 /* XXX don't alloc dma_map for AR */ 1346 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1347 printf("fw_bus_dmamap_create failed\n"); 1348 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1349 fwohci_db_free(dbch); 1350 return; 1351 } 1352 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1353 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1354 if (idb % dbch->xferq.bnpacket == 0) 1355 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1356 ].start = (void *)db_tr; 1357 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1358 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1359 ].end = (void *)db_tr; 1360 } 1361 db_tr++; 1362 } 1363 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1364 = STAILQ_FIRST(&dbch->db_trq); 1365 out: 1366 dbch->xferq.queued = 0; 1367 dbch->pdb_tr = NULL; 1368 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1369 dbch->bottom = dbch->top; 1370 dbch->flags = FWOHCI_DBCH_INIT; 1371 } 1372 1373 static int 1374 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1375 { 1376 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1377 int sleepch; 1378 1379 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1380 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1381 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1382 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1383 /* XXX we cannot free buffers until the DMA really stops */ 1384 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1385 fwohci_db_free(&sc->it[dmach]); 1386 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1387 return 0; 1388 } 1389 1390 static int 1391 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1392 { 1393 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1394 int sleepch; 1395 1396 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1397 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1398 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1399 /* XXX we cannot free buffers until the DMA really stops */ 1400 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1401 fwohci_db_free(&sc->ir[dmach]); 1402 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1403 return 0; 1404 } 1405 1406 #if BYTE_ORDER == BIG_ENDIAN 1407 static void 1408 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1409 { 1410 qld[0] = FWOHCI_DMA_READ(qld[0]); 1411 return; 1412 } 1413 #endif 1414 1415 static int 1416 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1417 { 1418 int err = 0; 1419 int idb, z, i, dmach = 0, ldesc; 1420 uint32_t off = 0; 1421 struct fwohcidb_tr *db_tr; 1422 struct fwohcidb *db; 1423 1424 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1425 err = EINVAL; 1426 return err; 1427 } 1428 z = dbch->ndesc; 1429 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1430 if( &sc->it[dmach] == dbch){ 1431 off = OHCI_ITOFF(dmach); 1432 break; 1433 } 1434 } 1435 if(off == 0){ 1436 err = EINVAL; 1437 return err; 1438 } 1439 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1440 return err; 1441 dbch->xferq.flag |= FWXFERQ_RUNNING; 1442 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1443 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1444 } 1445 db_tr = dbch->top; 1446 for (idb = 0; idb < dbch->ndb; idb ++) { 1447 fwohci_add_tx_buf(dbch, db_tr, idb); 1448 if(STAILQ_NEXT(db_tr, link) == NULL){ 1449 break; 1450 } 1451 db = db_tr->db; 1452 ldesc = db_tr->dbcnt - 1; 1453 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1454 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1455 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1456 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1457 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1458 FWOHCI_DMA_SET( 1459 db[ldesc].db.desc.cmd, 1460 OHCI_INTERRUPT_ALWAYS); 1461 /* OHCI 1.1 and above */ 1462 FWOHCI_DMA_SET( 1463 db[0].db.desc.cmd, 1464 OHCI_INTERRUPT_ALWAYS); 1465 } 1466 } 1467 db_tr = STAILQ_NEXT(db_tr, link); 1468 } 1469 FWOHCI_DMA_CLEAR( 1470 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1471 return err; 1472 } 1473 1474 static int 1475 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1476 { 1477 int err = 0; 1478 int idb, z, i, dmach = 0, ldesc; 1479 uint32_t off = 0; 1480 struct fwohcidb_tr *db_tr; 1481 struct fwohcidb *db; 1482 1483 z = dbch->ndesc; 1484 if(&sc->arrq == dbch){ 1485 off = OHCI_ARQOFF; 1486 }else if(&sc->arrs == dbch){ 1487 off = OHCI_ARSOFF; 1488 }else{ 1489 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1490 if( &sc->ir[dmach] == dbch){ 1491 off = OHCI_IROFF(dmach); 1492 break; 1493 } 1494 } 1495 } 1496 if(off == 0){ 1497 err = EINVAL; 1498 return err; 1499 } 1500 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1501 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1502 return err; 1503 }else{ 1504 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1505 err = EBUSY; 1506 return err; 1507 } 1508 } 1509 dbch->xferq.flag |= FWXFERQ_RUNNING; 1510 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1511 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1512 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1513 } 1514 db_tr = dbch->top; 1515 for (idb = 0; idb < dbch->ndb; idb ++) { 1516 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1517 if (STAILQ_NEXT(db_tr, link) == NULL) 1518 break; 1519 db = db_tr->db; 1520 ldesc = db_tr->dbcnt - 1; 1521 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1522 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1523 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1524 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1525 FWOHCI_DMA_SET( 1526 db[ldesc].db.desc.cmd, 1527 OHCI_INTERRUPT_ALWAYS); 1528 FWOHCI_DMA_CLEAR( 1529 db[ldesc].db.desc.depend, 1530 0xf); 1531 } 1532 } 1533 db_tr = STAILQ_NEXT(db_tr, link); 1534 } 1535 FWOHCI_DMA_CLEAR( 1536 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1537 dbch->buf_offset = 0; 1538 fwdma_sync_multiseg_all(dbch->am, 1539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1540 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1541 return err; 1542 }else{ 1543 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1544 } 1545 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1546 return err; 1547 } 1548 1549 static int 1550 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1551 { 1552 int sec, cycle, cycle_match; 1553 1554 cycle = cycle_now & 0x1fff; 1555 sec = cycle_now >> 13; 1556 #define CYCLE_MOD 0x10 1557 #if 1 1558 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1559 #else 1560 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1561 #endif 1562 cycle = cycle + CYCLE_DELAY; 1563 if (cycle >= 8000) { 1564 sec ++; 1565 cycle -= 8000; 1566 } 1567 cycle = roundup2(cycle, CYCLE_MOD); 1568 if (cycle >= 8000) { 1569 sec ++; 1570 if (cycle == 8000) 1571 cycle = 0; 1572 else 1573 cycle = CYCLE_MOD; 1574 } 1575 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1576 1577 return(cycle_match); 1578 } 1579 1580 static int 1581 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1582 { 1583 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1584 int err = 0; 1585 unsigned short tag, ich; 1586 struct fwohci_dbch *dbch; 1587 int cycle_match, cycle_now, s, ldesc; 1588 uint32_t stat; 1589 struct fw_bulkxfer *first, *chunk, *prev; 1590 struct fw_xferq *it; 1591 1592 dbch = &sc->it[dmach]; 1593 it = &dbch->xferq; 1594 1595 tag = (it->flag >> 6) & 3; 1596 ich = it->flag & 0x3f; 1597 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1598 dbch->ndb = it->bnpacket * it->bnchunk; 1599 dbch->ndesc = 3; 1600 fwohci_db_init(sc, dbch); 1601 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1602 return ENOMEM; 1603 err = fwohci_tx_enable(sc, dbch); 1604 } 1605 if(err) 1606 return err; 1607 1608 ldesc = dbch->ndesc - 1; 1609 s = splfw(); 1610 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1611 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1612 struct fwohcidb *db; 1613 1614 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1615 BUS_DMASYNC_PREWRITE); 1616 fwohci_txbufdb(sc, dmach, chunk); 1617 if (prev != NULL) { 1618 db = ((struct fwohcidb_tr *)(prev->end))->db; 1619 #if 0 /* XXX necessary? */ 1620 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1621 OHCI_BRANCH_ALWAYS); 1622 #endif 1623 #if 0 /* if bulkxfer->npacket changes */ 1624 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1625 ((struct fwohcidb_tr *) 1626 (chunk->start))->bus_addr | dbch->ndesc; 1627 #else 1628 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1629 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1630 #endif 1631 } 1632 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1633 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1634 prev = chunk; 1635 } 1636 fwdma_sync_multiseg_all(dbch->am, 1637 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1638 splx(s); 1639 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1640 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1641 printf("stat 0x%x\n", stat); 1642 1643 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1644 return 0; 1645 1646 #if 0 1647 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1648 #endif 1649 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1650 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1651 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1652 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1653 1654 first = STAILQ_FIRST(&it->stdma); 1655 OWRITE(sc, OHCI_ITCMD(dmach), 1656 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1657 if (firewire_debug > 1) { 1658 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1659 #if 1 1660 dump_dma(sc, ITX_CH + dmach); 1661 #endif 1662 } 1663 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1664 #if 1 1665 /* Don't start until all chunks are buffered */ 1666 if (STAILQ_FIRST(&it->stfree) != NULL) 1667 goto out; 1668 #endif 1669 #if 1 1670 /* Clear cycle match counter bits */ 1671 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1672 1673 /* 2bit second + 13bit cycle */ 1674 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1675 cycle_match = fwohci_next_cycle(fc, cycle_now); 1676 1677 OWRITE(sc, OHCI_ITCTL(dmach), 1678 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1679 | OHCI_CNTL_DMA_RUN); 1680 #else 1681 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1682 #endif 1683 if (firewire_debug > 1) { 1684 printf("cycle_match: 0x%04x->0x%04x\n", 1685 cycle_now, cycle_match); 1686 dump_dma(sc, ITX_CH + dmach); 1687 dump_db(sc, ITX_CH + dmach); 1688 } 1689 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1690 device_printf(sc->fc.dev, 1691 "IT DMA underrun (0x%08x)\n", stat); 1692 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1693 } 1694 out: 1695 return err; 1696 } 1697 1698 static int 1699 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1700 { 1701 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1702 int err = 0, s, ldesc; 1703 unsigned short tag, ich; 1704 uint32_t stat; 1705 struct fwohci_dbch *dbch; 1706 struct fwohcidb_tr *db_tr; 1707 struct fw_bulkxfer *first, *prev, *chunk; 1708 struct fw_xferq *ir; 1709 1710 dbch = &sc->ir[dmach]; 1711 ir = &dbch->xferq; 1712 1713 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1714 tag = (ir->flag >> 6) & 3; 1715 ich = ir->flag & 0x3f; 1716 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1717 1718 ir->queued = 0; 1719 dbch->ndb = ir->bnpacket * ir->bnchunk; 1720 dbch->ndesc = 2; 1721 fwohci_db_init(sc, dbch); 1722 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1723 return ENOMEM; 1724 err = fwohci_rx_enable(sc, dbch); 1725 } 1726 if(err) 1727 return err; 1728 1729 first = STAILQ_FIRST(&ir->stfree); 1730 if (first == NULL) { 1731 device_printf(fc->dev, "IR DMA no free chunk\n"); 1732 return 0; 1733 } 1734 1735 ldesc = dbch->ndesc - 1; 1736 s = splfw(); 1737 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1738 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1739 struct fwohcidb *db; 1740 1741 #if 1 /* XXX for if_fwe */ 1742 if (chunk->mbuf != NULL) { 1743 db_tr = (struct fwohcidb_tr *)(chunk->start); 1744 db_tr->dbcnt = 1; 1745 err = fw_bus_dmamap_load_mbuf( 1746 dbch->dmat, db_tr->dma_map, 1747 chunk->mbuf, fwohci_execute_db2, db_tr, 1748 BUS_DMA_WAITOK); 1749 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1750 OHCI_UPDATE | OHCI_INPUT_LAST | 1751 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1752 } 1753 #endif 1754 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1755 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1756 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1757 if (prev != NULL) { 1758 db = ((struct fwohcidb_tr *)(prev->end))->db; 1759 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1760 } 1761 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1762 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1763 prev = chunk; 1764 } 1765 fwdma_sync_multiseg_all(dbch->am, 1766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1767 splx(s); 1768 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1769 if (stat & OHCI_CNTL_DMA_ACTIVE) 1770 return 0; 1771 if (stat & OHCI_CNTL_DMA_RUN) { 1772 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1773 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1774 } 1775 1776 if (firewire_debug) 1777 printf("start IR DMA 0x%x\n", stat); 1778 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1779 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1780 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1781 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1782 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1783 OWRITE(sc, OHCI_IRCMD(dmach), 1784 ((struct fwohcidb_tr *)(first->start))->bus_addr 1785 | dbch->ndesc); 1786 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1787 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1788 #if 0 1789 dump_db(sc, IRX_CH + dmach); 1790 #endif 1791 return err; 1792 } 1793 1794 FWOHCI_STOP() 1795 { 1796 FWOHCI_STOP_START; 1797 u_int i; 1798 1799 /* Now stopping all DMA channel */ 1800 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1801 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1802 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1803 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1804 1805 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1806 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1807 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1808 } 1809 1810 /* FLUSH FIFO and reset Transmitter/Reciever */ 1811 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1812 1813 /* Stop interrupt */ 1814 OWRITE(sc, FWOHCI_INTMASKCLR, 1815 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1816 | OHCI_INT_PHY_INT 1817 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1818 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1819 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1820 | OHCI_INT_PHY_BUS_R); 1821 1822 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1823 fw_drain_txq(&sc->fc); 1824 1825 /* XXX Link down? Bus reset? */ 1826 FWOHCI_STOP_RETURN(0); 1827 } 1828 1829 #if defined(__NetBSD__) 1830 static void 1831 fwohci_power(int why, void *arg) 1832 { 1833 struct fwohci_softc *sc = arg; 1834 int s; 1835 1836 s = splbio(); 1837 switch (why) { 1838 case PWR_SUSPEND: 1839 case PWR_STANDBY: 1840 fwohci_stop(arg); 1841 break; 1842 case PWR_RESUME: 1843 fwohci_resume(sc, sc->fc.dev); 1844 break; 1845 case PWR_SOFTSUSPEND: 1846 case PWR_SOFTSTANDBY: 1847 case PWR_SOFTRESUME: 1848 break; 1849 } 1850 splx(s); 1851 } 1852 #endif 1853 1854 int 1855 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1856 { 1857 int i; 1858 struct fw_xferq *ir; 1859 struct fw_bulkxfer *chunk; 1860 1861 fwohci_reset(sc, dev); 1862 /* XXX resume isochronous receive automatically. (how about TX?) */ 1863 for(i = 0; i < sc->fc.nisodma; i ++) { 1864 ir = &sc->ir[i].xferq; 1865 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1866 device_printf(sc->fc.dev, 1867 "resume iso receive ch: %d\n", i); 1868 ir->flag &= ~FWXFERQ_RUNNING; 1869 /* requeue stdma to stfree */ 1870 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1871 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1872 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1873 } 1874 sc->fc.irx_enable(&sc->fc, i); 1875 } 1876 } 1877 1878 #if defined(__FreeBSD__) 1879 bus_generic_resume(dev); 1880 #endif 1881 sc->fc.ibr(&sc->fc); 1882 return 0; 1883 } 1884 1885 #define ACK_ALL 1886 static void 1887 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1888 { 1889 uint32_t irstat, itstat; 1890 u_int i; 1891 struct firewire_comm *fc = (struct firewire_comm *)sc; 1892 1893 CTR0(KTR_DEV, "fwohci_intr_body"); 1894 #ifdef OHCI_DEBUG 1895 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1896 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1897 stat & OHCI_INT_EN ? "DMA_EN ":"", 1898 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1899 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1900 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1901 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1902 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1903 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1904 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1905 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1906 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1907 stat & OHCI_INT_PHY_SID ? "SID ":"", 1908 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1909 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1910 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1911 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1912 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1913 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1914 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1915 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1916 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1917 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1918 stat, OREAD(sc, FWOHCI_INTMASK) 1919 ); 1920 #endif 1921 /* Bus reset */ 1922 if(stat & OHCI_INT_PHY_BUS_R ){ 1923 if (fc->status == FWBUSRESET) 1924 goto busresetout; 1925 /* Disable bus reset interrupt until sid recv. */ 1926 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1927 1928 device_printf(fc->dev, "BUS reset\n"); 1929 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1930 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1931 1932 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1933 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1934 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1935 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1936 1937 #ifndef ACK_ALL 1938 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1939 #endif 1940 fw_busreset(fc); 1941 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1942 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1943 } 1944 busresetout: 1945 if((stat & OHCI_INT_DMA_IR )){ 1946 #ifndef ACK_ALL 1947 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1948 #endif 1949 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1950 irstat = sc->irstat; 1951 sc->irstat = 0; 1952 #else 1953 irstat = atomic_readandclear_int(&sc->irstat); 1954 #endif 1955 for(i = 0; i < fc->nisodma ; i++){ 1956 struct fwohci_dbch *dbch; 1957 1958 if((irstat & (1 << i)) != 0){ 1959 dbch = &sc->ir[i]; 1960 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1961 device_printf(sc->fc.dev, 1962 "dma(%d) not active\n", i); 1963 continue; 1964 } 1965 fwohci_rbuf_update(sc, i); 1966 } 1967 } 1968 } 1969 if((stat & OHCI_INT_DMA_IT )){ 1970 #ifndef ACK_ALL 1971 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1972 #endif 1973 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1974 itstat = sc->itstat; 1975 sc->itstat = 0; 1976 #else 1977 itstat = atomic_readandclear_int(&sc->itstat); 1978 #endif 1979 for(i = 0; i < fc->nisodma ; i++){ 1980 if((itstat & (1 << i)) != 0){ 1981 fwohci_tbuf_update(sc, i); 1982 } 1983 } 1984 } 1985 if((stat & OHCI_INT_DMA_PRRS )){ 1986 #ifndef ACK_ALL 1987 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1988 #endif 1989 #if 0 1990 dump_dma(sc, ARRS_CH); 1991 dump_db(sc, ARRS_CH); 1992 #endif 1993 fwohci_arcv(sc, &sc->arrs, count); 1994 } 1995 if((stat & OHCI_INT_DMA_PRRQ )){ 1996 #ifndef ACK_ALL 1997 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1998 #endif 1999 #if 0 2000 dump_dma(sc, ARRQ_CH); 2001 dump_db(sc, ARRQ_CH); 2002 #endif 2003 fwohci_arcv(sc, &sc->arrq, count); 2004 } 2005 if (stat & OHCI_INT_CYC_LOST) { 2006 if (sc->cycle_lost >= 0) 2007 sc->cycle_lost ++; 2008 if (sc->cycle_lost > 10) { 2009 sc->cycle_lost = -1; 2010 #if 0 2011 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2012 #endif 2013 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2014 device_printf(fc->dev, "too many cycle lost, " 2015 "no cycle master presents?\n"); 2016 } 2017 } 2018 if(stat & OHCI_INT_PHY_SID){ 2019 uint32_t *buf, node_id; 2020 int plen; 2021 2022 #ifndef ACK_ALL 2023 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2024 #endif 2025 /* Enable bus reset interrupt */ 2026 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2027 /* Allow async. request to us */ 2028 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2029 /* XXX insecure ?? */ 2030 /* allow from all nodes */ 2031 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2032 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2033 /* 0 to 4GB regison */ 2034 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2035 /* Set ATRetries register */ 2036 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2037 /* 2038 ** Checking whether the node is root or not. If root, turn on 2039 ** cycle master. 2040 */ 2041 node_id = OREAD(sc, FWOHCI_NODEID); 2042 plen = OREAD(sc, OHCI_SID_CNT); 2043 2044 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2045 node_id, (plen >> 16) & 0xff); 2046 if (!(node_id & OHCI_NODE_VALID)) { 2047 printf("Bus reset failure\n"); 2048 goto sidout; 2049 } 2050 2051 /* cycle timer */ 2052 sc->cycle_lost = 0; 2053 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2054 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2055 printf("CYCLEMASTER mode\n"); 2056 OWRITE(sc, OHCI_LNKCTL, 2057 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2058 } else { 2059 printf("non CYCLEMASTER mode\n"); 2060 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2061 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2062 } 2063 2064 fc->nodeid = node_id & 0x3f; 2065 2066 if (plen & OHCI_SID_ERR) { 2067 device_printf(fc->dev, "SID Error\n"); 2068 goto sidout; 2069 } 2070 plen &= OHCI_SID_CNT_MASK; 2071 if (plen < 4 || plen > OHCI_SIDSIZE) { 2072 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2073 goto sidout; 2074 } 2075 plen -= 4; /* chop control info */ 2076 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2077 if (buf == NULL) { 2078 device_printf(fc->dev, "malloc failed\n"); 2079 goto sidout; 2080 } 2081 for (i = 0; i < plen / 4; i ++) 2082 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2083 #if defined(__NetBSD__) && defined(macppc) 2084 /* XXX required as bootdisk for macppc. */ 2085 delay(500000); 2086 #endif 2087 #if 1 /* XXX needed?? */ 2088 /* pending all pre-bus_reset packets */ 2089 fwohci_txd(sc, &sc->atrq); 2090 fwohci_txd(sc, &sc->atrs); 2091 fwohci_arcv(sc, &sc->arrs, -1); 2092 fwohci_arcv(sc, &sc->arrq, -1); 2093 fw_drain_txq(fc); 2094 #endif 2095 fw_sidrcv(fc, buf, plen); 2096 free(buf, M_FW); 2097 } 2098 sidout: 2099 if((stat & OHCI_INT_DMA_ATRQ )){ 2100 #ifndef ACK_ALL 2101 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2102 #endif 2103 fwohci_txd(sc, &(sc->atrq)); 2104 } 2105 if((stat & OHCI_INT_DMA_ATRS )){ 2106 #ifndef ACK_ALL 2107 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2108 #endif 2109 fwohci_txd(sc, &(sc->atrs)); 2110 } 2111 if((stat & OHCI_INT_PW_ERR )){ 2112 #ifndef ACK_ALL 2113 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2114 #endif 2115 device_printf(fc->dev, "posted write error\n"); 2116 } 2117 if((stat & OHCI_INT_ERR )){ 2118 #ifndef ACK_ALL 2119 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2120 #endif 2121 device_printf(fc->dev, "unrecoverable error\n"); 2122 } 2123 if((stat & OHCI_INT_PHY_INT)) { 2124 #ifndef ACK_ALL 2125 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2126 #endif 2127 device_printf(fc->dev, "phy int\n"); 2128 } 2129 2130 CTR0(KTR_DEV, "fwohci_intr_body done"); 2131 return; 2132 } 2133 2134 #if FWOHCI_TASKQUEUE 2135 static void 2136 fwohci_complete(void *arg, int pending) 2137 { 2138 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2139 uint32_t stat; 2140 2141 again: 2142 stat = atomic_readandclear_int(&sc->intstat); 2143 if (stat) { 2144 FW_LOCK; 2145 fwohci_intr_body(sc, stat, -1); 2146 FW_UNLOCK; 2147 } else 2148 return; 2149 goto again; 2150 } 2151 #endif 2152 2153 static uint32_t 2154 fwochi_check_stat(struct fwohci_softc *sc) 2155 { 2156 uint32_t stat, irstat, itstat; 2157 2158 stat = OREAD(sc, FWOHCI_INTSTAT); 2159 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2160 if (stat == 0xffffffff) { 2161 device_printf(sc->fc.dev, 2162 "device physically ejected?\n"); 2163 return(stat); 2164 } 2165 #ifdef ACK_ALL 2166 if (stat) 2167 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2168 #endif 2169 if (stat & OHCI_INT_DMA_IR) { 2170 irstat = OREAD(sc, OHCI_IR_STAT); 2171 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2172 atomic_set_int(&sc->irstat, irstat); 2173 } 2174 if (stat & OHCI_INT_DMA_IT) { 2175 itstat = OREAD(sc, OHCI_IT_STAT); 2176 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2177 atomic_set_int(&sc->itstat, itstat); 2178 } 2179 return(stat); 2180 } 2181 2182 FW_INTR(fwohci) 2183 { 2184 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2185 uint32_t stat; 2186 #if !FWOHCI_TASKQUEUE 2187 uint32_t bus_reset = 0; 2188 #endif 2189 2190 if (!(sc->intmask & OHCI_INT_EN)) { 2191 /* polling mode */ 2192 FW_INTR_RETURN(0); 2193 } 2194 2195 #if !FWOHCI_TASKQUEUE 2196 again: 2197 #endif 2198 CTR0(KTR_DEV, "fwohci_intr"); 2199 stat = fwochi_check_stat(sc); 2200 if (stat == 0 || stat == 0xffffffff) 2201 FW_INTR_RETURN(1); 2202 #if FWOHCI_TASKQUEUE 2203 atomic_set_int(&sc->intstat, stat); 2204 /* XXX mask bus reset intr. during bus reset phase */ 2205 if (stat) 2206 #if 1 2207 taskqueue_enqueue_fast(taskqueue_fast, 2208 &sc->fwohci_task_complete); 2209 #else 2210 taskqueue_enqueue(taskqueue_swi, 2211 &sc->fwohci_task_complete); 2212 #endif 2213 #else 2214 /* We cannot clear bus reset event during bus reset phase */ 2215 if ((stat & ~bus_reset) == 0) 2216 FW_INTR_RETURN(1); 2217 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2218 fwohci_intr_body(sc, stat, -1); 2219 goto again; 2220 #endif 2221 CTR0(KTR_DEV, "fwohci_intr end"); 2222 } 2223 2224 void 2225 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2226 { 2227 int s; 2228 uint32_t stat; 2229 struct fwohci_softc *sc; 2230 2231 2232 sc = (struct fwohci_softc *)fc; 2233 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2234 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2235 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2236 #if 0 2237 if (!quick) { 2238 #else 2239 if (1) { 2240 #endif 2241 stat = fwochi_check_stat(sc); 2242 if (stat == 0 || stat == 0xffffffff) 2243 return; 2244 } 2245 s = splfw(); 2246 fwohci_intr_body(sc, stat, count); 2247 splx(s); 2248 } 2249 2250 static void 2251 fwohci_set_intr(struct firewire_comm *fc, int enable) 2252 { 2253 struct fwohci_softc *sc; 2254 2255 sc = (struct fwohci_softc *)fc; 2256 if (firewire_debug) 2257 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2258 if (enable) { 2259 sc->intmask |= OHCI_INT_EN; 2260 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2261 } else { 2262 sc->intmask &= ~OHCI_INT_EN; 2263 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2264 } 2265 } 2266 2267 static void 2268 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2269 { 2270 struct firewire_comm *fc = &sc->fc; 2271 struct fwohcidb *db; 2272 struct fw_bulkxfer *chunk; 2273 struct fw_xferq *it; 2274 uint32_t stat, count; 2275 int s, w=0, ldesc; 2276 2277 it = fc->it[dmach]; 2278 ldesc = sc->it[dmach].ndesc - 1; 2279 s = splfw(); /* unnecessary ? */ 2280 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2281 if (firewire_debug) 2282 dump_db(sc, ITX_CH + dmach); 2283 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2284 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2285 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2286 >> OHCI_STATUS_SHIFT; 2287 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2288 /* timestamp */ 2289 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2290 & OHCI_COUNT_MASK; 2291 if (stat == 0) 2292 break; 2293 STAILQ_REMOVE_HEAD(&it->stdma, link); 2294 switch (stat & FWOHCIEV_MASK){ 2295 case FWOHCIEV_ACKCOMPL: 2296 #if 0 2297 device_printf(fc->dev, "0x%08x\n", count); 2298 #endif 2299 break; 2300 default: 2301 device_printf(fc->dev, 2302 "Isochronous transmit err %02x(%s)\n", 2303 stat, fwohcicode[stat & 0x1f]); 2304 } 2305 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2306 w++; 2307 } 2308 splx(s); 2309 if (w) 2310 wakeup(it); 2311 } 2312 2313 static void 2314 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2315 { 2316 struct firewire_comm *fc = &sc->fc; 2317 struct fwohcidb_tr *db_tr; 2318 struct fw_bulkxfer *chunk; 2319 struct fw_xferq *ir; 2320 uint32_t stat; 2321 int s, w=0, ldesc; 2322 2323 ir = fc->ir[dmach]; 2324 ldesc = sc->ir[dmach].ndesc - 1; 2325 #if 0 2326 dump_db(sc, dmach); 2327 #endif 2328 s = splfw(); 2329 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2330 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2331 db_tr = (struct fwohcidb_tr *)chunk->end; 2332 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2333 >> OHCI_STATUS_SHIFT; 2334 if (stat == 0) 2335 break; 2336 2337 if (chunk->mbuf != NULL) { 2338 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2339 BUS_DMASYNC_POSTREAD); 2340 fw_bus_dmamap_unload( 2341 sc->ir[dmach].dmat, db_tr->dma_map); 2342 } else if (ir->buf != NULL) { 2343 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2344 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2345 } else { 2346 /* XXX */ 2347 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2348 } 2349 2350 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2351 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2352 switch (stat & FWOHCIEV_MASK) { 2353 case FWOHCIEV_ACKCOMPL: 2354 chunk->resp = 0; 2355 break; 2356 default: 2357 chunk->resp = EINVAL; 2358 device_printf(fc->dev, 2359 "Isochronous receive err %02x(%s)\n", 2360 stat, fwohcicode[stat & 0x1f]); 2361 } 2362 w++; 2363 } 2364 splx(s); 2365 if (w) { 2366 if (ir->flag & FWXFERQ_HANDLER) 2367 ir->hand(ir); 2368 else 2369 wakeup(ir); 2370 } 2371 } 2372 2373 void 2374 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2375 { 2376 uint32_t off, cntl, stat, cmd, match; 2377 2378 if(ch == 0){ 2379 off = OHCI_ATQOFF; 2380 }else if(ch == 1){ 2381 off = OHCI_ATSOFF; 2382 }else if(ch == 2){ 2383 off = OHCI_ARQOFF; 2384 }else if(ch == 3){ 2385 off = OHCI_ARSOFF; 2386 }else if(ch < IRX_CH){ 2387 off = OHCI_ITCTL(ch - ITX_CH); 2388 }else{ 2389 off = OHCI_IRCTL(ch - IRX_CH); 2390 } 2391 cntl = stat = OREAD(sc, off); 2392 cmd = OREAD(sc, off + 0xc); 2393 match = OREAD(sc, off + 0x10); 2394 2395 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2396 ch, 2397 cntl, 2398 cmd, 2399 match); 2400 stat &= 0xffff ; 2401 if (stat) { 2402 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2403 ch, 2404 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2405 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2406 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2407 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2408 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2409 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2410 fwohcicode[stat & 0x1f], 2411 stat & 0x1f 2412 ); 2413 }else{ 2414 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2415 } 2416 } 2417 2418 void 2419 dump_db(struct fwohci_softc *sc, uint32_t ch) 2420 { 2421 struct fwohci_dbch *dbch; 2422 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2423 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2424 int idb, jdb; 2425 uint32_t cmd, off; 2426 if(ch == 0){ 2427 off = OHCI_ATQOFF; 2428 dbch = &sc->atrq; 2429 }else if(ch == 1){ 2430 off = OHCI_ATSOFF; 2431 dbch = &sc->atrs; 2432 }else if(ch == 2){ 2433 off = OHCI_ARQOFF; 2434 dbch = &sc->arrq; 2435 }else if(ch == 3){ 2436 off = OHCI_ARSOFF; 2437 dbch = &sc->arrs; 2438 }else if(ch < IRX_CH){ 2439 off = OHCI_ITCTL(ch - ITX_CH); 2440 dbch = &sc->it[ch - ITX_CH]; 2441 }else { 2442 off = OHCI_IRCTL(ch - IRX_CH); 2443 dbch = &sc->ir[ch - IRX_CH]; 2444 } 2445 cmd = OREAD(sc, off + 0xc); 2446 2447 if( dbch->ndb == 0 ){ 2448 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2449 return; 2450 } 2451 pp = dbch->top; 2452 prev = pp->db; 2453 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2454 cp = STAILQ_NEXT(pp, link); 2455 if(cp == NULL){ 2456 curr = NULL; 2457 goto outdb; 2458 } 2459 np = STAILQ_NEXT(cp, link); 2460 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2461 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2462 curr = cp->db; 2463 if(np != NULL){ 2464 next = np->db; 2465 }else{ 2466 next = NULL; 2467 } 2468 goto outdb; 2469 } 2470 } 2471 pp = STAILQ_NEXT(pp, link); 2472 if(pp == NULL){ 2473 curr = NULL; 2474 goto outdb; 2475 } 2476 prev = pp->db; 2477 } 2478 outdb: 2479 if( curr != NULL){ 2480 #if 0 2481 printf("Prev DB %d\n", ch); 2482 print_db(pp, prev, ch, dbch->ndesc); 2483 #endif 2484 printf("Current DB %d\n", ch); 2485 print_db(cp, curr, ch, dbch->ndesc); 2486 #if 0 2487 printf("Next DB %d\n", ch); 2488 print_db(np, next, ch, dbch->ndesc); 2489 #endif 2490 }else{ 2491 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2492 } 2493 return; 2494 } 2495 2496 void 2497 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2498 uint32_t ch, uint32_t hogemax) 2499 { 2500 fwohcireg_t stat; 2501 int i, key; 2502 uint32_t cmd, res; 2503 2504 if(db == NULL){ 2505 printf("No Descriptor is found\n"); 2506 return; 2507 } 2508 2509 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2510 ch, 2511 "Current", 2512 "OP ", 2513 "KEY", 2514 "INT", 2515 "BR ", 2516 "len", 2517 "Addr", 2518 "Depend", 2519 "Stat", 2520 "Cnt"); 2521 for( i = 0 ; i <= hogemax ; i ++){ 2522 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2523 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2524 key = cmd & OHCI_KEY_MASK; 2525 stat = res >> OHCI_STATUS_SHIFT; 2526 #if defined(__DragonFly__) || \ 2527 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2528 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2529 db_tr->bus_addr, 2530 #else 2531 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2532 (uintmax_t)db_tr->bus_addr, 2533 #endif 2534 dbcode[(cmd >> 28) & 0xf], 2535 dbkey[(cmd >> 24) & 0x7], 2536 dbcond[(cmd >> 20) & 0x3], 2537 dbcond[(cmd >> 18) & 0x3], 2538 cmd & OHCI_COUNT_MASK, 2539 FWOHCI_DMA_READ(db[i].db.desc.addr), 2540 FWOHCI_DMA_READ(db[i].db.desc.depend), 2541 stat, 2542 res & OHCI_COUNT_MASK); 2543 if(stat & 0xff00){ 2544 printf(" %s%s%s%s%s%s %s(%x)\n", 2545 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2546 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2547 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2548 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2549 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2550 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2551 fwohcicode[stat & 0x1f], 2552 stat & 0x1f 2553 ); 2554 }else{ 2555 printf(" Nostat\n"); 2556 } 2557 if(key == OHCI_KEY_ST2 ){ 2558 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2559 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2560 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2561 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2562 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2563 } 2564 if(key == OHCI_KEY_DEVICE){ 2565 return; 2566 } 2567 if((cmd & OHCI_BRANCH_MASK) 2568 == OHCI_BRANCH_ALWAYS){ 2569 return; 2570 } 2571 if((cmd & OHCI_CMD_MASK) 2572 == OHCI_OUTPUT_LAST){ 2573 return; 2574 } 2575 if((cmd & OHCI_CMD_MASK) 2576 == OHCI_INPUT_LAST){ 2577 return; 2578 } 2579 if(key == OHCI_KEY_ST2 ){ 2580 i++; 2581 } 2582 } 2583 return; 2584 } 2585 2586 void 2587 fwohci_ibr(struct firewire_comm *fc) 2588 { 2589 struct fwohci_softc *sc; 2590 uint32_t fun; 2591 2592 device_printf(fc->dev, "Initiate bus reset\n"); 2593 sc = (struct fwohci_softc *)fc; 2594 2595 /* 2596 * Make sure our cached values from the config rom are 2597 * initialised. 2598 */ 2599 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2600 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2601 2602 /* 2603 * Set root hold-off bit so that non cyclemaster capable node 2604 * shouldn't became the root node. 2605 */ 2606 #if 1 2607 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2608 fun |= FW_PHY_IBR | FW_PHY_RHB; 2609 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2610 #else /* Short bus reset */ 2611 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2612 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2613 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2614 #endif 2615 } 2616 2617 void 2618 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2619 { 2620 struct fwohcidb_tr *db_tr, *fdb_tr; 2621 struct fwohci_dbch *dbch; 2622 struct fwohcidb *db; 2623 struct fw_pkt *fp; 2624 struct fwohci_txpkthdr *ohcifp; 2625 unsigned short chtag; 2626 int idb; 2627 2628 dbch = &sc->it[dmach]; 2629 chtag = sc->it[dmach].xferq.flag & 0xff; 2630 2631 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2632 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2633 /* 2634 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2635 */ 2636 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2637 db = db_tr->db; 2638 fp = (struct fw_pkt *)db_tr->buf; 2639 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2640 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2641 ohcifp->mode.common.spd = 0 & 0x7; 2642 ohcifp->mode.stream.len = fp->mode.stream.len; 2643 ohcifp->mode.stream.chtag = chtag; 2644 ohcifp->mode.stream.tcode = 0xa; 2645 #if BYTE_ORDER == BIG_ENDIAN 2646 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2647 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2648 #endif 2649 2650 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2651 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2652 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2653 #if 0 /* if bulkxfer->npackets changes */ 2654 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2655 | OHCI_UPDATE 2656 | OHCI_BRANCH_ALWAYS; 2657 db[0].db.desc.depend = 2658 = db[dbch->ndesc - 1].db.desc.depend 2659 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2660 #else 2661 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2662 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2663 #endif 2664 bulkxfer->end = (void *)db_tr; 2665 db_tr = STAILQ_NEXT(db_tr, link); 2666 } 2667 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2668 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2669 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2670 #if 0 /* if bulkxfer->npackets changes */ 2671 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2672 /* OHCI 1.1 and above */ 2673 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2674 #endif 2675 /* 2676 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2677 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2678 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2679 */ 2680 return; 2681 } 2682 2683 static int 2684 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2685 int poffset) 2686 { 2687 struct fwohcidb *db = db_tr->db; 2688 struct fw_xferq *it; 2689 int err = 0; 2690 2691 it = &dbch->xferq; 2692 if(it->buf == 0){ 2693 err = EINVAL; 2694 return err; 2695 } 2696 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2697 db_tr->dbcnt = 3; 2698 2699 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2700 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2701 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2702 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2703 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2704 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2705 2706 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2707 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2708 #if 1 2709 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2710 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2711 #endif 2712 return 0; 2713 } 2714 2715 int 2716 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2717 int poffset, struct fwdma_alloc *dummy_dma) 2718 { 2719 struct fwohcidb *db = db_tr->db; 2720 struct fw_xferq *ir; 2721 int i, ldesc; 2722 bus_addr_t dbuf[2]; 2723 int dsiz[2]; 2724 2725 ir = &dbch->xferq; 2726 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2727 if (db_tr->buf == NULL) 2728 db_tr->buf = fwdma_malloc_size( 2729 dbch->dmat, &db_tr->dma_map, 2730 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2731 if (db_tr->buf == NULL) 2732 return(ENOMEM); 2733 db_tr->dbcnt = 1; 2734 dsiz[0] = ir->psize; 2735 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2736 BUS_DMASYNC_PREREAD); 2737 } else { 2738 db_tr->dbcnt = 0; 2739 if (dummy_dma != NULL) { 2740 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2741 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2742 } 2743 dsiz[db_tr->dbcnt] = ir->psize; 2744 if (ir->buf != NULL) { 2745 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2746 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2747 } 2748 db_tr->dbcnt++; 2749 } 2750 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2751 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2752 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2753 if (ir->flag & FWXFERQ_STREAM) { 2754 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2755 } 2756 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2757 } 2758 ldesc = db_tr->dbcnt - 1; 2759 if (ir->flag & FWXFERQ_STREAM) { 2760 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2761 } 2762 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2763 return 0; 2764 } 2765 2766 2767 static int 2768 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2769 { 2770 struct fw_pkt *fp0; 2771 uint32_t ld0; 2772 int slen, hlen; 2773 #if BYTE_ORDER == BIG_ENDIAN 2774 int i; 2775 #endif 2776 2777 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2778 #if 0 2779 printf("ld0: x%08x\n", ld0); 2780 #endif 2781 fp0 = (struct fw_pkt *)&ld0; 2782 /* determine length to swap */ 2783 switch (fp0->mode.common.tcode) { 2784 case FWTCODE_WRES: 2785 CTR0(KTR_DEV, "WRES"); 2786 case FWTCODE_RREQQ: 2787 case FWTCODE_WREQQ: 2788 case FWTCODE_RRESQ: 2789 case FWOHCITCODE_PHY: 2790 slen = 12; 2791 break; 2792 case FWTCODE_RREQB: 2793 case FWTCODE_WREQB: 2794 case FWTCODE_LREQ: 2795 case FWTCODE_RRESB: 2796 case FWTCODE_LRES: 2797 slen = 16; 2798 break; 2799 default: 2800 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2801 return(0); 2802 } 2803 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2804 if (hlen > len) { 2805 if (firewire_debug) 2806 printf("splitted header\n"); 2807 return(-hlen); 2808 } 2809 #if BYTE_ORDER == BIG_ENDIAN 2810 for(i = 0; i < slen/4; i ++) 2811 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2812 #endif 2813 return(hlen); 2814 } 2815 2816 static int 2817 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2818 { 2819 const struct tcode_info *info; 2820 int r; 2821 2822 info = &tinfo[fp->mode.common.tcode]; 2823 r = info->hdr_len + sizeof(uint32_t); 2824 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2825 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2826 2827 if (r == sizeof(uint32_t)) { 2828 /* XXX */ 2829 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2830 fp->mode.common.tcode); 2831 return (-1); 2832 } 2833 2834 if (r > dbch->xferq.psize) { 2835 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2836 return (-1); 2837 /* panic ? */ 2838 } 2839 2840 return r; 2841 } 2842 2843 static void 2844 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2845 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2846 { 2847 struct fwohcidb *db = &db_tr->db[0]; 2848 2849 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2850 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2851 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2852 fwdma_sync_multiseg_all(dbch->am, 2853 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2854 dbch->bottom = db_tr; 2855 2856 if (wake) 2857 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2858 } 2859 2860 static void 2861 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2862 { 2863 struct fwohcidb_tr *db_tr; 2864 struct iovec vec[2]; 2865 struct fw_pkt pktbuf; 2866 int nvec; 2867 struct fw_pkt *fp; 2868 uint8_t *ld; 2869 uint32_t stat, off, status, event; 2870 u_int spd; 2871 int len, plen, hlen, pcnt, offset; 2872 int s; 2873 void *buf; 2874 int resCount; 2875 2876 CTR0(KTR_DEV, "fwohci_arv"); 2877 2878 if(&sc->arrq == dbch){ 2879 off = OHCI_ARQOFF; 2880 }else if(&sc->arrs == dbch){ 2881 off = OHCI_ARSOFF; 2882 }else{ 2883 return; 2884 } 2885 2886 s = splfw(); 2887 db_tr = dbch->top; 2888 pcnt = 0; 2889 /* XXX we cannot handle a packet which lies in more than two buf */ 2890 fwdma_sync_multiseg_all(dbch->am, 2891 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2892 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2893 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2894 while (status & OHCI_CNTL_DMA_ACTIVE) { 2895 #if 0 2896 2897 if (off == OHCI_ARQOFF) 2898 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2899 db_tr->bus_addr, status, resCount); 2900 #endif 2901 len = dbch->xferq.psize - resCount; 2902 ld = (uint8_t *)db_tr->buf; 2903 if (dbch->pdb_tr == NULL) { 2904 len -= dbch->buf_offset; 2905 ld += dbch->buf_offset; 2906 } 2907 if (len > 0) 2908 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2909 BUS_DMASYNC_POSTREAD); 2910 while (len > 0 ) { 2911 if (count >= 0 && count-- == 0) 2912 goto out; 2913 if(dbch->pdb_tr != NULL){ 2914 /* we have a fragment in previous buffer */ 2915 int rlen; 2916 2917 offset = dbch->buf_offset; 2918 if (offset < 0) 2919 offset = - offset; 2920 buf = (char *)dbch->pdb_tr->buf + offset; 2921 rlen = dbch->xferq.psize - offset; 2922 if (firewire_debug) 2923 printf("rlen=%d, offset=%d\n", 2924 rlen, dbch->buf_offset); 2925 if (dbch->buf_offset < 0) { 2926 /* splitted in header, pull up */ 2927 char *p; 2928 2929 p = (char *)&pktbuf; 2930 bcopy(buf, p, rlen); 2931 p += rlen; 2932 /* this must be too long but harmless */ 2933 rlen = sizeof(pktbuf) - rlen; 2934 if (rlen < 0) 2935 printf("why rlen < 0\n"); 2936 bcopy(db_tr->buf, p, rlen); 2937 ld += rlen; 2938 len -= rlen; 2939 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2940 if (hlen <= 0) { 2941 printf("hlen < 0 shouldn't happen"); 2942 goto err; 2943 } 2944 offset = sizeof(pktbuf); 2945 vec[0].iov_base = (char *)&pktbuf; 2946 vec[0].iov_len = offset; 2947 } else { 2948 /* splitted in payload */ 2949 offset = rlen; 2950 vec[0].iov_base = buf; 2951 vec[0].iov_len = rlen; 2952 } 2953 fp=(struct fw_pkt *)vec[0].iov_base; 2954 nvec = 1; 2955 } else { 2956 /* no fragment in previous buffer */ 2957 fp=(struct fw_pkt *)ld; 2958 hlen = fwohci_arcv_swap(fp, len); 2959 if (hlen == 0) 2960 goto err; 2961 if (hlen < 0) { 2962 dbch->pdb_tr = db_tr; 2963 dbch->buf_offset = - dbch->buf_offset; 2964 /* sanity check */ 2965 if (resCount != 0) { 2966 printf("resCount=%d hlen=%d\n", 2967 resCount, hlen); 2968 goto err; 2969 } 2970 goto out; 2971 } 2972 offset = 0; 2973 nvec = 0; 2974 } 2975 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2976 if (plen < 0) { 2977 /* minimum header size + trailer 2978 = sizeof(fw_pkt) so this shouldn't happens */ 2979 printf("plen(%d) is negative! offset=%d\n", 2980 plen, offset); 2981 goto err; 2982 } 2983 if (plen > 0) { 2984 len -= plen; 2985 if (len < 0) { 2986 dbch->pdb_tr = db_tr; 2987 if (firewire_debug) 2988 printf("splitted payload\n"); 2989 /* sanity check */ 2990 if (resCount != 0) { 2991 printf("resCount=%d plen=%d" 2992 " len=%d\n", 2993 resCount, plen, len); 2994 goto err; 2995 } 2996 goto out; 2997 } 2998 vec[nvec].iov_base = ld; 2999 vec[nvec].iov_len = plen; 3000 nvec ++; 3001 ld += plen; 3002 } 3003 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3004 if (nvec == 0) 3005 printf("nvec == 0\n"); 3006 3007 /* DMA result-code will be written at the tail of packet */ 3008 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3009 #if 0 3010 printf("plen: %d, stat %x\n", 3011 plen ,stat); 3012 #endif 3013 spd = (stat >> 21) & 0x3; 3014 event = (stat >> 16) & 0x1f; 3015 switch (event) { 3016 case FWOHCIEV_ACKPEND: 3017 #if 0 3018 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3019 #endif 3020 /* fall through */ 3021 case FWOHCIEV_ACKCOMPL: 3022 { 3023 struct fw_rcv_buf rb; 3024 3025 if ((vec[nvec-1].iov_len -= 3026 sizeof(struct fwohci_trailer)) == 0) 3027 nvec--; 3028 rb.fc = &sc->fc; 3029 rb.vec = vec; 3030 rb.nvec = nvec; 3031 rb.spd = spd; 3032 fw_rcv(&rb); 3033 break; 3034 } 3035 case FWOHCIEV_BUSRST: 3036 if (sc->fc.status != FWBUSRESET) 3037 printf("got BUSRST packet!?\n"); 3038 break; 3039 default: 3040 device_printf(sc->fc.dev, 3041 "Async DMA Receive error err=%02x %s" 3042 " plen=%d offset=%d len=%d status=0x%08x" 3043 " tcode=0x%x, stat=0x%08x\n", 3044 event, fwohcicode[event], plen, 3045 dbch->buf_offset, len, 3046 OREAD(sc, OHCI_DMACTL(off)), 3047 fp->mode.common.tcode, stat); 3048 #if 1 /* XXX */ 3049 goto err; 3050 #endif 3051 break; 3052 } 3053 pcnt ++; 3054 if (dbch->pdb_tr != NULL) { 3055 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3056 off, 1); 3057 dbch->pdb_tr = NULL; 3058 } 3059 3060 } 3061 out: 3062 if (resCount == 0) { 3063 /* done on this buffer */ 3064 if (dbch->pdb_tr == NULL) { 3065 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3066 dbch->buf_offset = 0; 3067 } else 3068 if (dbch->pdb_tr != db_tr) 3069 printf("pdb_tr != db_tr\n"); 3070 db_tr = STAILQ_NEXT(db_tr, link); 3071 fwdma_sync_multiseg_all(dbch->am, 3072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3073 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3074 >> OHCI_STATUS_SHIFT; 3075 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3076 & OHCI_COUNT_MASK; 3077 /* XXX check buffer overrun */ 3078 dbch->top = db_tr; 3079 } else { 3080 dbch->buf_offset = dbch->xferq.psize - resCount; 3081 fw_bus_dmamap_sync( 3082 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3083 break; 3084 } 3085 /* XXX make sure DMA is not dead */ 3086 } 3087 #if 0 3088 if (pcnt < 1) 3089 printf("fwohci_arcv: no packets\n"); 3090 #endif 3091 fwdma_sync_multiseg_all(dbch->am, 3092 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3093 splx(s); 3094 return; 3095 3096 err: 3097 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3098 OREAD(sc, OHCI_DMACTL(off))); 3099 dbch->pdb_tr = NULL; 3100 /* skip until resCount != 0 */ 3101 printf(" skip buffer"); 3102 while (resCount == 0) { 3103 printf(" #"); 3104 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3105 db_tr = STAILQ_NEXT(db_tr, link); 3106 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3107 & OHCI_COUNT_MASK; 3108 } 3109 printf(" done\n"); 3110 dbch->top = db_tr; 3111 dbch->buf_offset = dbch->xferq.psize - resCount; 3112 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3113 fwdma_sync_multiseg_all( 3114 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3115 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3116 splx(s); 3117 } 3118 #if defined(__NetBSD__) 3119 3120 int 3121 fwohci_print(void *aux, const char *pnp) 3122 { 3123 struct fw_attach_args *fwa = (struct fw_attach_args *)aux; 3124 3125 if (pnp) 3126 aprint_normal("%s at %s", fwa->name, pnp); 3127 3128 return UNCONF; 3129 } 3130 #endif 3131
Indexes created Thu Sep 25 16:09:42 GMT 2025