fwohci.c revision 1.108
1 /* $NetBSD: fwohci.c,v 1.108 2007/09/25 14:13:34 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.86 2007/03/19 03:35:45 simokawa Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.108 2007/09/25 14:13:34 ad Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 107 #include "ioconf.h" 108 #endif 109 110 #undef OHCI_DEBUG 111 112 static int nocyclemaster = 0; 113 #if defined(__FreeBSD__) 114 SYSCTL_DECL(_hw_firewire); 115 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 116 "Do not send cycle start packets"); 117 #elif defined(__NetBSD__) 118 /* 119 * Setup sysctl(3) MIB, hw.fwohci.* 120 * 121 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 122 */ 123 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 124 { 125 int rc; 126 const struct sysctlnode *node; 127 128 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 129 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 130 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 131 goto err; 132 } 133 134 if ((rc = sysctl_createv(clog, 0, NULL, &node, 135 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 136 SYSCTL_DESCR("fwohci controls"), 137 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 138 goto err; 139 } 140 141 /* fwohci no cyclemaster flag */ 142 if ((rc = sysctl_createv(clog, 0, NULL, &node, 143 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 144 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 145 NULL, 0, &nocyclemaster, 146 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 147 goto err; 148 } 149 return; 150 151 err: 152 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 153 } 154 #endif 155 156 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 157 "STOR","LOAD","NOP ","STOP", 158 "", "", "", "", "", "", "", ""}; 159 160 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 161 "UNDEF","REG","SYS","DEV"}; 162 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 163 static const char * const fwohcicode[32] = { 164 "No stat","Undef","long","miss Ack err", 165 "underrun","overrun","desc err", "data read err", 166 "data write err","bus reset","timeout","tcode err", 167 "Undef","Undef","unknown event","flushed", 168 "Undef","ack complete","ack pend","Undef", 169 "ack busy_X","ack busy_A","ack busy_B","Undef", 170 "Undef","Undef","Undef","ack tardy", 171 "Undef","ack data_err","ack type_err",""}; 172 173 #define MAX_SPEED 3 174 extern const char *fw_linkspeed[]; 175 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 176 177 static const struct tcode_info tinfo[] = { 178 /* hdr_len block flag*/ 179 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 180 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 181 /* 2 WRES */ {12, FWTI_RES}, 182 /* 3 XXX */ { 0, 0}, 183 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 184 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 185 /* 6 RRESQ */ {16, FWTI_RES}, 186 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 187 /* 8 CYCS */ { 0, 0}, 188 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 189 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 190 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 191 /* c XXX */ { 0, 0}, 192 /* d XXX */ { 0, 0}, 193 /* e PHY */ {12, FWTI_REQ}, 194 /* f XXX */ { 0, 0} 195 }; 196 197 #define OHCI_WRITE_SIGMASK 0xffff0000 198 #define OHCI_READ_SIGMASK 0xffff0000 199 200 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 201 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 202 203 static void fwohci_ibr (struct firewire_comm *); 204 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 205 static void fwohci_db_free (struct fwohci_dbch *); 206 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 207 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 208 static void fwohci_start_atq (struct firewire_comm *); 209 static void fwohci_start_ats (struct firewire_comm *); 210 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 211 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 212 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 213 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 214 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 215 static int fwohci_irx_enable (struct firewire_comm *, int); 216 static int fwohci_irx_disable (struct firewire_comm *, int); 217 #if BYTE_ORDER == BIG_ENDIAN 218 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 219 #endif 220 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 221 static int fwohci_itx_disable (struct firewire_comm *, int); 222 static void fwohci_timeout (void *); 223 static void fwohci_set_intr (struct firewire_comm *, int); 224 225 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 226 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 227 static void dump_db (struct fwohci_softc *, uint32_t); 228 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 229 static void dump_dma (struct fwohci_softc *, uint32_t); 230 static uint32_t fwohci_cyctimer (struct firewire_comm *); 231 static void fwohci_rbuf_update (struct fwohci_softc *, int); 232 static void fwohci_tbuf_update (struct fwohci_softc *, int); 233 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 234 #if FWOHCI_TASKQUEUE 235 static void fwohci_complete(void *, int); 236 #endif 237 #if defined(__NetBSD__) 238 static void fwohci_power(int, void *); 239 int fwohci_print(void *, const char *); 240 #endif 241 242 /* 243 * memory allocated for DMA programs 244 */ 245 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 246 247 #define NDB FWMAXQUEUE 248 249 #define OHCI_VERSION 0x00 250 #define OHCI_ATRETRY 0x08 251 #define OHCI_CROMHDR 0x18 252 #define OHCI_BUS_OPT 0x20 253 #define OHCI_BUSIRMC (1 << 31) 254 #define OHCI_BUSCMC (1 << 30) 255 #define OHCI_BUSISC (1 << 29) 256 #define OHCI_BUSBMC (1 << 28) 257 #define OHCI_BUSPMC (1 << 27) 258 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 259 OHCI_BUSBMC | OHCI_BUSPMC 260 261 #define OHCI_EUID_HI 0x24 262 #define OHCI_EUID_LO 0x28 263 264 #define OHCI_CROMPTR 0x34 265 #define OHCI_HCCCTL 0x50 266 #define OHCI_HCCCTLCLR 0x54 267 #define OHCI_AREQHI 0x100 268 #define OHCI_AREQHICLR 0x104 269 #define OHCI_AREQLO 0x108 270 #define OHCI_AREQLOCLR 0x10c 271 #define OHCI_PREQHI 0x110 272 #define OHCI_PREQHICLR 0x114 273 #define OHCI_PREQLO 0x118 274 #define OHCI_PREQLOCLR 0x11c 275 #define OHCI_PREQUPPER 0x120 276 277 #define OHCI_SID_BUF 0x64 278 #define OHCI_SID_CNT 0x68 279 #define OHCI_SID_ERR (1 << 31) 280 #define OHCI_SID_CNT_MASK 0xffc 281 282 #define OHCI_IT_STAT 0x90 283 #define OHCI_IT_STATCLR 0x94 284 #define OHCI_IT_MASK 0x98 285 #define OHCI_IT_MASKCLR 0x9c 286 287 #define OHCI_IR_STAT 0xa0 288 #define OHCI_IR_STATCLR 0xa4 289 #define OHCI_IR_MASK 0xa8 290 #define OHCI_IR_MASKCLR 0xac 291 292 #define OHCI_LNKCTL 0xe0 293 #define OHCI_LNKCTLCLR 0xe4 294 295 #define OHCI_PHYACCESS 0xec 296 #define OHCI_CYCLETIMER 0xf0 297 298 #define OHCI_DMACTL(off) (off) 299 #define OHCI_DMACTLCLR(off) (off + 4) 300 #define OHCI_DMACMD(off) (off + 0xc) 301 #define OHCI_DMAMATCH(off) (off + 0x10) 302 303 #define OHCI_ATQOFF 0x180 304 #define OHCI_ATQCTL OHCI_ATQOFF 305 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 306 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 307 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 308 309 #define OHCI_ATSOFF 0x1a0 310 #define OHCI_ATSCTL OHCI_ATSOFF 311 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 312 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 313 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 314 315 #define OHCI_ARQOFF 0x1c0 316 #define OHCI_ARQCTL OHCI_ARQOFF 317 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 318 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 319 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 320 321 #define OHCI_ARSOFF 0x1e0 322 #define OHCI_ARSCTL OHCI_ARSOFF 323 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 324 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 325 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 326 327 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 328 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 329 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 330 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 331 332 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 333 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 334 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 335 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 336 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 337 338 #if defined(__FreeBSD__) 339 d_ioctl_t fwohci_ioctl; 340 #elif defined(__NetBSD__) 341 dev_type_ioctl(fwohci_ioctl); 342 #endif 343 344 /* 345 * Communication with PHY device 346 */ 347 static uint32_t 348 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 349 { 350 uint32_t fun; 351 352 addr &= 0xf; 353 data &= 0xff; 354 355 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 356 OWRITE(sc, OHCI_PHYACCESS, fun); 357 DELAY(100); 358 359 return(fwphy_rddata( sc, addr)); 360 } 361 362 static uint32_t 363 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 364 { 365 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 366 int i; 367 uint32_t bm; 368 369 #define OHCI_CSR_DATA 0x0c 370 #define OHCI_CSR_COMP 0x10 371 #define OHCI_CSR_CONT 0x14 372 #define OHCI_BUS_MANAGER_ID 0 373 374 OWRITE(sc, OHCI_CSR_DATA, node); 375 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 376 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 377 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 378 DELAY(10); 379 bm = OREAD(sc, OHCI_CSR_DATA); 380 if((bm & 0x3f) == 0x3f) 381 bm = node; 382 if (firewire_debug) 383 device_printf(sc->fc.dev, 384 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 385 386 return(bm); 387 } 388 389 static uint32_t 390 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 391 { 392 uint32_t fun, stat; 393 u_int i, retry = 0; 394 395 addr &= 0xf; 396 #define MAX_RETRY 100 397 again: 398 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 399 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 400 OWRITE(sc, OHCI_PHYACCESS, fun); 401 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 402 fun = OREAD(sc, OHCI_PHYACCESS); 403 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 404 break; 405 DELAY(100); 406 } 407 if(i >= MAX_RETRY) { 408 if (firewire_debug) 409 device_printf(sc->fc.dev, "phy read failed(1).\n"); 410 if (++retry < MAX_RETRY) { 411 DELAY(100); 412 goto again; 413 } 414 } 415 /* Make sure that SCLK is started */ 416 stat = OREAD(sc, FWOHCI_INTSTAT); 417 if ((stat & OHCI_INT_REG_FAIL) != 0 || 418 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 419 if (firewire_debug) 420 device_printf(sc->fc.dev, "phy read failed(2).\n"); 421 if (++retry < MAX_RETRY) { 422 DELAY(100); 423 goto again; 424 } 425 } 426 if (firewire_debug || retry >= MAX_RETRY) 427 device_printf(sc->fc.dev, 428 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 429 #undef MAX_RETRY 430 return((fun >> PHYDEV_RDDATA )& 0xff); 431 } 432 /* Device specific ioctl. */ 433 FW_IOCTL(fwohci) 434 { 435 FW_IOCTL_START; 436 struct fwohci_softc *fc; 437 int err = 0; 438 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 439 uint32_t *dmach = (uint32_t *) data; 440 441 if(sc == NULL){ 442 return(EINVAL); 443 } 444 fc = (struct fwohci_softc *)sc->fc; 445 446 if (!data) 447 return(EINVAL); 448 449 switch (cmd) { 450 case FWOHCI_WRREG: 451 #define OHCI_MAX_REG 0x800 452 if(reg->addr <= OHCI_MAX_REG){ 453 OWRITE(fc, reg->addr, reg->data); 454 reg->data = OREAD(fc, reg->addr); 455 }else{ 456 err = EINVAL; 457 } 458 break; 459 case FWOHCI_RDREG: 460 if(reg->addr <= OHCI_MAX_REG){ 461 reg->data = OREAD(fc, reg->addr); 462 }else{ 463 err = EINVAL; 464 } 465 break; 466 /* Read DMA descriptors for debug */ 467 case DUMPDMA: 468 if(*dmach <= OHCI_MAX_DMA_CH ){ 469 dump_dma(fc, *dmach); 470 dump_db(fc, *dmach); 471 }else{ 472 err = EINVAL; 473 } 474 break; 475 /* Read/Write Phy registers */ 476 #define OHCI_MAX_PHY_REG 0xf 477 case FWOHCI_RDPHYREG: 478 if (reg->addr <= OHCI_MAX_PHY_REG) 479 reg->data = fwphy_rddata(fc, reg->addr); 480 else 481 err = EINVAL; 482 break; 483 case FWOHCI_WRPHYREG: 484 if (reg->addr <= OHCI_MAX_PHY_REG) 485 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 486 else 487 err = EINVAL; 488 break; 489 default: 490 err = EINVAL; 491 break; 492 } 493 return err; 494 } 495 496 static int 497 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 498 { 499 uint32_t reg, reg2; 500 int e1394a = 1; 501 /* 502 * probe PHY parameters 503 * 0. to prove PHY version, whether compliance of 1394a. 504 * 1. to probe maximum speed supported by the PHY and 505 * number of port supported by core-logic. 506 * It is not actually available port on your PC . 507 */ 508 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 509 DELAY(500); 510 511 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 512 513 if((reg >> 5) != 7 ){ 514 sc->fc.mode &= ~FWPHYASYST; 515 sc->fc.nport = reg & FW_PHY_NP; 516 sc->fc.speed = reg & FW_PHY_SPD >> 6; 517 if (sc->fc.speed > MAX_SPEED) { 518 device_printf(dev, "invalid speed %d (fixed to %d).\n", 519 sc->fc.speed, MAX_SPEED); 520 sc->fc.speed = MAX_SPEED; 521 } 522 device_printf(dev, 523 "Phy 1394 only %s, %d ports.\n", 524 fw_linkspeed[sc->fc.speed], sc->fc.nport); 525 }else{ 526 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 527 sc->fc.mode |= FWPHYASYST; 528 sc->fc.nport = reg & FW_PHY_NP; 529 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 530 if (sc->fc.speed > MAX_SPEED) { 531 device_printf(dev, "invalid speed %d (fixed to %d).\n", 532 sc->fc.speed, MAX_SPEED); 533 sc->fc.speed = MAX_SPEED; 534 } 535 device_printf(dev, 536 "Phy 1394a available %s, %d ports.\n", 537 fw_linkspeed[sc->fc.speed], sc->fc.nport); 538 539 /* check programPhyEnable */ 540 reg2 = fwphy_rddata(sc, 5); 541 #if 0 542 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 543 #else /* XXX force to enable 1394a */ 544 if (e1394a) { 545 #endif 546 if (firewire_debug) 547 device_printf(dev, 548 "Enable 1394a Enhancements\n"); 549 /* enable EAA EMC */ 550 reg2 |= 0x03; 551 /* set aPhyEnhanceEnable */ 552 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 553 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 554 } 555 #if 0 556 else { 557 /* for safe */ 558 reg2 &= ~0x83; 559 } 560 #endif 561 reg2 = fwphy_wrdata(sc, 5, reg2); 562 } 563 564 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 565 if((reg >> 5) == 7 ){ 566 reg = fwphy_rddata(sc, 4); 567 reg |= 1 << 6; 568 fwphy_wrdata(sc, 4, reg); 569 reg = fwphy_rddata(sc, 4); 570 } 571 return 0; 572 } 573 574 575 void 576 fwohci_reset(struct fwohci_softc *sc, device_t dev) 577 { 578 int i, max_rec, speed; 579 uint32_t reg, reg2; 580 struct fwohcidb_tr *db_tr; 581 582 /* Disable interrupts */ 583 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 584 585 /* Now stopping all DMA channels */ 586 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 587 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 588 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 589 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 590 591 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 592 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 593 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 594 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 595 } 596 597 /* FLUSH FIFO and reset Transmitter/Reciever */ 598 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 599 if (firewire_debug) 600 device_printf(dev, "resetting OHCI..."); 601 i = 0; 602 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 603 if (i++ > 100) break; 604 DELAY(1000); 605 } 606 if (firewire_debug) 607 printf("done (loop=%d)\n", i); 608 609 /* Probe phy */ 610 fwohci_probe_phy(sc, dev); 611 612 /* Probe link */ 613 reg = OREAD(sc, OHCI_BUS_OPT); 614 reg2 = reg | OHCI_BUSFNC; 615 max_rec = (reg & 0x0000f000) >> 12; 616 speed = (reg & 0x00000007); 617 device_printf(dev, "Link %s, max_rec %d bytes.\n", 618 fw_linkspeed[speed], MAXREC(max_rec)); 619 /* XXX fix max_rec */ 620 sc->fc.maxrec = sc->fc.speed + 8; 621 if (max_rec != sc->fc.maxrec) { 622 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 623 device_printf(dev, "max_rec %d -> %d\n", 624 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 625 } 626 if (firewire_debug) 627 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 628 OWRITE(sc, OHCI_BUS_OPT, reg2); 629 630 /* Initialize registers */ 631 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 632 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 633 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 634 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 635 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 636 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 637 638 /* Enable link */ 639 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 640 641 /* Force to start async RX DMA */ 642 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 643 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 644 fwohci_rx_enable(sc, &sc->arrq); 645 fwohci_rx_enable(sc, &sc->arrs); 646 647 /* Initialize async TX */ 648 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 649 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 650 651 /* AT Retries */ 652 OWRITE(sc, FWOHCI_RETRY, 653 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 654 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 655 656 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 657 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 658 sc->atrq.bottom = sc->atrq.top; 659 sc->atrs.bottom = sc->atrs.top; 660 661 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 662 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 663 db_tr->xfer = NULL; 664 } 665 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 666 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 667 db_tr->xfer = NULL; 668 } 669 670 671 /* Enable interrupts */ 672 OWRITE(sc, FWOHCI_INTMASK, 673 OHCI_INT_ERR | OHCI_INT_PHY_SID 674 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 675 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 676 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 677 fwohci_set_intr(&sc->fc, 1); 678 679 } 680 681 int 682 fwohci_init(struct fwohci_softc *sc, device_t dev) 683 { 684 int i, mver; 685 uint32_t reg; 686 uint8_t ui[8]; 687 688 #if FWOHCI_TASKQUEUE 689 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 690 #endif 691 692 /* OHCI version */ 693 reg = OREAD(sc, OHCI_VERSION); 694 mver = (reg >> 16) & 0xff; 695 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 696 mver, reg & 0xff, (reg>>24) & 1); 697 if (mver < 1 || mver > 9) { 698 device_printf(dev, "invalid OHCI version\n"); 699 return (ENXIO); 700 } 701 702 /* Available Isochronous DMA channel probe */ 703 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 704 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 705 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 706 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 707 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 708 for (i = 0; i < 0x20; i++) 709 if ((reg & (1 << i)) == 0) 710 break; 711 sc->fc.nisodma = i; 712 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 713 if (i == 0) 714 return (ENXIO); 715 716 sc->fc.arq = &sc->arrq.xferq; 717 sc->fc.ars = &sc->arrs.xferq; 718 sc->fc.atq = &sc->atrq.xferq; 719 sc->fc.ats = &sc->atrs.xferq; 720 721 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 722 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 723 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 724 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 725 726 sc->arrq.xferq.start = NULL; 727 sc->arrs.xferq.start = NULL; 728 sc->atrq.xferq.start = fwohci_start_atq; 729 sc->atrs.xferq.start = fwohci_start_ats; 730 731 sc->arrq.xferq.buf = NULL; 732 sc->arrs.xferq.buf = NULL; 733 sc->atrq.xferq.buf = NULL; 734 sc->atrs.xferq.buf = NULL; 735 736 sc->arrq.xferq.dmach = -1; 737 sc->arrs.xferq.dmach = -1; 738 sc->atrq.xferq.dmach = -1; 739 sc->atrs.xferq.dmach = -1; 740 741 sc->arrq.ndesc = 1; 742 sc->arrs.ndesc = 1; 743 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 744 sc->atrs.ndesc = 2; 745 746 sc->arrq.ndb = NDB; 747 sc->arrs.ndb = NDB / 2; 748 sc->atrq.ndb = NDB; 749 sc->atrs.ndb = NDB / 2; 750 751 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 752 sc->fc.it[i] = &sc->it[i].xferq; 753 sc->fc.ir[i] = &sc->ir[i].xferq; 754 sc->it[i].xferq.dmach = i; 755 sc->ir[i].xferq.dmach = i; 756 sc->it[i].ndb = 0; 757 sc->ir[i].ndb = 0; 758 } 759 760 sc->fc.tcode = tinfo; 761 sc->fc.dev = dev; 762 763 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 764 &sc->crom_dma, BUS_DMA_WAITOK); 765 if(sc->fc.config_rom == NULL){ 766 device_printf(dev, "config_rom alloc failed."); 767 return ENOMEM; 768 } 769 770 #if 0 771 bzero(&sc->fc.config_rom[0], CROMSIZE); 772 sc->fc.config_rom[1] = 0x31333934; 773 sc->fc.config_rom[2] = 0xf000a002; 774 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 775 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 776 sc->fc.config_rom[5] = 0; 777 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 778 779 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 780 #endif 781 782 783 /* SID recieve buffer must align 2^11 */ 784 #define OHCI_SIDSIZE (1 << 11) 785 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 786 &sc->sid_dma, BUS_DMA_WAITOK); 787 if (sc->sid_buf == NULL) { 788 device_printf(dev, "sid_buf alloc failed."); 789 return ENOMEM; 790 } 791 792 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 793 &sc->dummy_dma, BUS_DMA_WAITOK); 794 795 if (sc->dummy_dma.v_addr == NULL) { 796 device_printf(dev, "dummy_dma alloc failed."); 797 return ENOMEM; 798 } 799 800 fwohci_db_init(sc, &sc->arrq); 801 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 802 return ENOMEM; 803 804 fwohci_db_init(sc, &sc->arrs); 805 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 806 return ENOMEM; 807 808 fwohci_db_init(sc, &sc->atrq); 809 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 810 return ENOMEM; 811 812 fwohci_db_init(sc, &sc->atrs); 813 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 814 return ENOMEM; 815 816 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 817 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 818 for( i = 0 ; i < 8 ; i ++) 819 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 820 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 821 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 822 823 sc->fc.ioctl = fwohci_ioctl; 824 sc->fc.cyctimer = fwohci_cyctimer; 825 sc->fc.set_bmr = fwohci_set_bus_manager; 826 sc->fc.ibr = fwohci_ibr; 827 sc->fc.irx_enable = fwohci_irx_enable; 828 sc->fc.irx_disable = fwohci_irx_disable; 829 830 sc->fc.itx_enable = fwohci_itxbuf_enable; 831 sc->fc.itx_disable = fwohci_itx_disable; 832 #if BYTE_ORDER == BIG_ENDIAN 833 sc->fc.irx_post = fwohci_irx_post; 834 #else 835 sc->fc.irx_post = NULL; 836 #endif 837 sc->fc.itx_post = NULL; 838 sc->fc.timeout = fwohci_timeout; 839 sc->fc.poll = fwohci_poll; 840 sc->fc.set_intr = fwohci_set_intr; 841 842 sc->intmask = sc->irstat = sc->itstat = 0; 843 844 fw_init(&sc->fc); 845 fwohci_reset(sc, dev); 846 FWOHCI_INIT_END; 847 848 return 0; 849 } 850 851 void 852 fwohci_timeout(void *arg) 853 { 854 struct fwohci_softc *sc; 855 856 sc = (struct fwohci_softc *)arg; 857 } 858 859 uint32_t 860 fwohci_cyctimer(struct firewire_comm *fc) 861 { 862 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 863 return(OREAD(sc, OHCI_CYCLETIMER)); 864 } 865 866 FWOHCI_DETACH() 867 { 868 int i; 869 870 FWOHCI_DETACH_START; 871 if (sc->sid_buf != NULL) 872 fwdma_free(&sc->fc, &sc->sid_dma); 873 if (sc->fc.config_rom != NULL) 874 fwdma_free(&sc->fc, &sc->crom_dma); 875 876 fwohci_db_free(&sc->arrq); 877 fwohci_db_free(&sc->arrs); 878 879 fwohci_db_free(&sc->atrq); 880 fwohci_db_free(&sc->atrs); 881 882 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 883 fwohci_db_free(&sc->it[i]); 884 fwohci_db_free(&sc->ir[i]); 885 } 886 FWOHCI_DETACH_END; 887 888 return 0; 889 } 890 891 #define LAST_DB(dbtr, db) do { \ 892 struct fwohcidb_tr *_dbtr = (dbtr); \ 893 int _cnt = _dbtr->dbcnt; \ 894 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 895 } while (0) 896 897 static void 898 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 899 { 900 struct fwohcidb_tr *db_tr; 901 struct fwohcidb *db; 902 bus_dma_segment_t *s; 903 int i; 904 905 db_tr = (struct fwohcidb_tr *)arg; 906 db = &db_tr->db[db_tr->dbcnt]; 907 if (error) { 908 if (firewire_debug || error != EFBIG) 909 printf("fwohci_execute_db: error=%d\n", error); 910 return; 911 } 912 for (i = 0; i < nseg; i++) { 913 s = &segs[i]; 914 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 915 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 916 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 917 db++; 918 db_tr->dbcnt++; 919 } 920 } 921 922 static void 923 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 924 bus_size_t size, int error) 925 { 926 fwohci_execute_db(arg, segs, nseg, error); 927 } 928 929 static void 930 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 931 { 932 int i, s; 933 int tcode, hdr_len, pl_off; 934 int fsegment = -1; 935 uint32_t off; 936 struct fw_xfer *xfer; 937 struct fw_pkt *fp; 938 struct fwohci_txpkthdr *ohcifp; 939 struct fwohcidb_tr *db_tr; 940 struct fwohcidb *db; 941 uint32_t *ld; 942 const struct tcode_info *info; 943 static int maxdesc=0; 944 945 if(&sc->atrq == dbch){ 946 off = OHCI_ATQOFF; 947 }else if(&sc->atrs == dbch){ 948 off = OHCI_ATSOFF; 949 }else{ 950 return; 951 } 952 953 if (dbch->flags & FWOHCI_DBCH_FULL) 954 return; 955 956 s = splfw(); 957 fwdma_sync_multiseg_all(dbch->am, 958 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 959 db_tr = dbch->top; 960 txloop: 961 xfer = STAILQ_FIRST(&dbch->xferq.q); 962 if(xfer == NULL){ 963 goto kick; 964 } 965 if(dbch->xferq.queued == 0 ){ 966 device_printf(sc->fc.dev, "TX queue empty\n"); 967 } 968 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 969 db_tr->xfer = xfer; 970 xfer->state = FWXF_START; 971 972 fp = &xfer->send.hdr; 973 tcode = fp->mode.common.tcode; 974 975 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 976 info = &tinfo[tcode]; 977 hdr_len = pl_off = info->hdr_len; 978 979 ld = &ohcifp->mode.ld[0]; 980 ld[0] = ld[1] = ld[2] = ld[3] = 0; 981 for( i = 0 ; i < pl_off ; i+= 4) 982 ld[i/4] = fp->mode.ld[i/4]; 983 984 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 985 if (tcode == FWTCODE_STREAM ){ 986 hdr_len = 8; 987 ohcifp->mode.stream.len = fp->mode.stream.len; 988 } else if (tcode == FWTCODE_PHY) { 989 hdr_len = 12; 990 ld[1] = fp->mode.ld[1]; 991 ld[2] = fp->mode.ld[2]; 992 ohcifp->mode.common.spd = 0; 993 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 994 } else { 995 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 996 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 997 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 998 } 999 db = &db_tr->db[0]; 1000 FWOHCI_DMA_WRITE(db->db.desc.cmd, 1001 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 1002 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1003 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1004 /* Specify bound timer of asy. responce */ 1005 if(&sc->atrs == dbch){ 1006 FWOHCI_DMA_WRITE(db->db.desc.res, 1007 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1008 } 1009 #if BYTE_ORDER == BIG_ENDIAN 1010 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1011 hdr_len = 12; 1012 for (i = 0; i < hdr_len/4; i ++) 1013 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1014 #endif 1015 1016 again: 1017 db_tr->dbcnt = 2; 1018 db = &db_tr->db[db_tr->dbcnt]; 1019 if (xfer->send.pay_len > 0) { 1020 int err; 1021 /* handle payload */ 1022 if (xfer->mbuf == NULL) { 1023 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1024 &xfer->send.payload[0], xfer->send.pay_len, 1025 fwohci_execute_db, db_tr, 1026 BUS_DMA_WAITOK); 1027 } else { 1028 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1029 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1030 db_tr->dma_map, xfer->mbuf, 1031 fwohci_execute_db2, db_tr, 1032 BUS_DMA_WAITOK); 1033 if (err == EFBIG) { 1034 struct mbuf *m0; 1035 1036 if (firewire_debug) 1037 device_printf(sc->fc.dev, "EFBIG.\n"); 1038 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1039 if (m0 != NULL) { 1040 m_copydata(xfer->mbuf, 0, 1041 xfer->mbuf->m_pkthdr.len, 1042 mtod(m0, void *)); 1043 m0->m_len = m0->m_pkthdr.len = 1044 xfer->mbuf->m_pkthdr.len; 1045 m_freem(xfer->mbuf); 1046 xfer->mbuf = m0; 1047 goto again; 1048 } 1049 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1050 } 1051 } 1052 if (err) 1053 printf("dmamap_load: err=%d\n", err); 1054 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1055 BUS_DMASYNC_PREWRITE); 1056 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1057 for (i = 2; i < db_tr->dbcnt; i++) 1058 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1059 OHCI_OUTPUT_MORE); 1060 #endif 1061 } 1062 if (maxdesc < db_tr->dbcnt) { 1063 maxdesc = db_tr->dbcnt; 1064 if (firewire_debug) 1065 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1066 } 1067 /* last db */ 1068 LAST_DB(db_tr, db); 1069 FWOHCI_DMA_SET(db->db.desc.cmd, 1070 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1071 FWOHCI_DMA_WRITE(db->db.desc.depend, 1072 STAILQ_NEXT(db_tr, link)->bus_addr); 1073 1074 if(fsegment == -1 ) 1075 fsegment = db_tr->dbcnt; 1076 if (dbch->pdb_tr != NULL) { 1077 LAST_DB(dbch->pdb_tr, db); 1078 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1079 } 1080 dbch->pdb_tr = db_tr; 1081 db_tr = STAILQ_NEXT(db_tr, link); 1082 if(db_tr != dbch->bottom){ 1083 goto txloop; 1084 } else { 1085 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1086 dbch->flags |= FWOHCI_DBCH_FULL; 1087 } 1088 kick: 1089 /* kick asy q */ 1090 fwdma_sync_multiseg_all(dbch->am, 1091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1092 1093 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1094 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1095 } else { 1096 if (firewire_debug) 1097 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1098 OREAD(sc, OHCI_DMACTL(off))); 1099 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1100 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1101 dbch->xferq.flag |= FWXFERQ_RUNNING; 1102 } 1103 CTR0(KTR_DEV, "start kick done"); 1104 CTR0(KTR_DEV, "start kick done2"); 1105 1106 dbch->top = db_tr; 1107 splx(s); 1108 return; 1109 } 1110 1111 static void 1112 fwohci_start_atq(struct firewire_comm *fc) 1113 { 1114 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1115 fwohci_start( sc, &(sc->atrq)); 1116 return; 1117 } 1118 1119 static void 1120 fwohci_start_ats(struct firewire_comm *fc) 1121 { 1122 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1123 fwohci_start( sc, &(sc->atrs)); 1124 return; 1125 } 1126 1127 void 1128 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1129 { 1130 int s, ch, err = 0; 1131 struct fwohcidb_tr *tr; 1132 struct fwohcidb *db; 1133 struct fw_xfer *xfer; 1134 uint32_t off; 1135 u_int stat, status; 1136 int packets; 1137 struct firewire_comm *fc = (struct firewire_comm *)sc; 1138 1139 if(&sc->atrq == dbch){ 1140 off = OHCI_ATQOFF; 1141 ch = ATRQ_CH; 1142 }else if(&sc->atrs == dbch){ 1143 off = OHCI_ATSOFF; 1144 ch = ATRS_CH; 1145 }else{ 1146 return; 1147 } 1148 s = splfw(); 1149 tr = dbch->bottom; 1150 packets = 0; 1151 fwdma_sync_multiseg_all(dbch->am, 1152 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1153 while(dbch->xferq.queued > 0){ 1154 LAST_DB(tr, db); 1155 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1156 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1157 if (fc->status != FWBUSRESET) 1158 /* maybe out of order?? */ 1159 goto out; 1160 } 1161 if (tr->xfer->send.pay_len > 0) { 1162 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1163 BUS_DMASYNC_POSTWRITE); 1164 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1165 } 1166 #if 1 1167 if (firewire_debug > 1) 1168 dump_db(sc, ch); 1169 #endif 1170 if(status & OHCI_CNTL_DMA_DEAD) { 1171 /* Stop DMA */ 1172 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1173 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1174 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1175 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1176 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1177 } 1178 stat = status & FWOHCIEV_MASK; 1179 switch(stat){ 1180 case FWOHCIEV_ACKPEND: 1181 CTR0(KTR_DEV, "txd: ack pending"); 1182 /* fall through */ 1183 case FWOHCIEV_ACKCOMPL: 1184 err = 0; 1185 break; 1186 case FWOHCIEV_ACKBSA: 1187 case FWOHCIEV_ACKBSB: 1188 case FWOHCIEV_ACKBSX: 1189 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1190 err = EBUSY; 1191 break; 1192 case FWOHCIEV_FLUSHED: 1193 case FWOHCIEV_ACKTARD: 1194 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1195 err = EAGAIN; 1196 break; 1197 case FWOHCIEV_MISSACK: 1198 case FWOHCIEV_UNDRRUN: 1199 case FWOHCIEV_OVRRUN: 1200 case FWOHCIEV_DESCERR: 1201 case FWOHCIEV_DTRDERR: 1202 case FWOHCIEV_TIMEOUT: 1203 case FWOHCIEV_TCODERR: 1204 case FWOHCIEV_UNKNOWN: 1205 case FWOHCIEV_ACKDERR: 1206 case FWOHCIEV_ACKTERR: 1207 default: 1208 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1209 stat, fwohcicode[stat]); 1210 err = EINVAL; 1211 break; 1212 } 1213 if (tr->xfer != NULL) { 1214 xfer = tr->xfer; 1215 CTR0(KTR_DEV, "txd"); 1216 if (xfer->state == FWXF_RCVD) { 1217 #if 0 1218 if (firewire_debug) 1219 printf("already rcvd\n"); 1220 #endif 1221 fw_xfer_done(xfer); 1222 } else { 1223 xfer->state = FWXF_SENT; 1224 if (err == EBUSY && fc->status != FWBUSRESET) { 1225 xfer->state = FWXF_BUSY; 1226 xfer->resp = err; 1227 xfer->recv.pay_len = 0; 1228 fw_xfer_done(xfer); 1229 } else if (stat != FWOHCIEV_ACKPEND) { 1230 if (stat != FWOHCIEV_ACKCOMPL) 1231 xfer->state = FWXF_SENTERR; 1232 xfer->resp = err; 1233 xfer->recv.pay_len = 0; 1234 fw_xfer_done(xfer); 1235 } 1236 } 1237 /* 1238 * The watchdog timer takes care of split 1239 * transcation timeout for ACKPEND case. 1240 */ 1241 } else { 1242 printf("this shouldn't happen\n"); 1243 } 1244 dbch->xferq.queued --; 1245 tr->xfer = NULL; 1246 1247 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1248 packets ++; 1249 tr = STAILQ_NEXT(tr, link); 1250 dbch->bottom = tr; 1251 if (dbch->bottom == dbch->top) { 1252 /* we reaches the end of context program */ 1253 if (firewire_debug && dbch->xferq.queued > 0) 1254 printf("queued > 0\n"); 1255 break; 1256 } 1257 } 1258 out: 1259 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1260 printf("make free slot\n"); 1261 dbch->flags &= ~FWOHCI_DBCH_FULL; 1262 fwohci_start(sc, dbch); 1263 } 1264 fwdma_sync_multiseg_all( 1265 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1266 splx(s); 1267 } 1268 1269 static void 1270 fwohci_db_free(struct fwohci_dbch *dbch) 1271 { 1272 struct fwohcidb_tr *db_tr; 1273 int idb; 1274 1275 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1276 return; 1277 1278 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1279 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1280 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1281 db_tr->buf != NULL) { 1282 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1283 db_tr->buf, dbch->xferq.psize); 1284 db_tr->buf = NULL; 1285 } else if (db_tr->dma_map != NULL) 1286 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1287 } 1288 dbch->ndb = 0; 1289 db_tr = STAILQ_FIRST(&dbch->db_trq); 1290 fwdma_free_multiseg(dbch->am); 1291 free(db_tr, M_FW); 1292 STAILQ_INIT(&dbch->db_trq); 1293 dbch->flags &= ~FWOHCI_DBCH_INIT; 1294 seldestroy(&dbch->xferq.rsel); 1295 } 1296 1297 static void 1298 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1299 { 1300 int idb; 1301 struct fwohcidb_tr *db_tr; 1302 1303 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1304 goto out; 1305 1306 /* create dma_tag for buffers */ 1307 #define MAX_REQCOUNT 0xffff 1308 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1309 /*alignment*/ 1, /*boundary*/ 0, 1310 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1311 /*highaddr*/ BUS_SPACE_MAXADDR, 1312 /*filter*/NULL, /*filterarg*/NULL, 1313 /*maxsize*/ dbch->xferq.psize, 1314 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1315 /*maxsegsz*/ MAX_REQCOUNT, 1316 /*flags*/ 0, 1317 /*lockfunc*/busdma_lock_mutex, 1318 /*lockarg*/&Giant, 1319 &dbch->dmat)) 1320 return; 1321 1322 /* allocate DB entries and attach one to each DMA channels */ 1323 /* DB entry must start at 16 bytes bounary. */ 1324 STAILQ_INIT(&dbch->db_trq); 1325 db_tr = (struct fwohcidb_tr *) 1326 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1327 M_FW, M_WAITOK | M_ZERO); 1328 if(db_tr == NULL){ 1329 printf("fwohci_db_init: malloc(1) failed\n"); 1330 return; 1331 } 1332 1333 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1334 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1335 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1336 if (dbch->am == NULL) { 1337 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1338 free(db_tr, M_FW); 1339 return; 1340 } 1341 /* Attach DB to DMA ch. */ 1342 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1343 db_tr->dbcnt = 0; 1344 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1345 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1346 /* create dmamap for buffers */ 1347 /* XXX do we need 4bytes alignment tag? */ 1348 /* XXX don't alloc dma_map for AR */ 1349 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1350 printf("fw_bus_dmamap_create failed\n"); 1351 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1352 fwohci_db_free(dbch); 1353 return; 1354 } 1355 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1356 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1357 if (idb % dbch->xferq.bnpacket == 0) 1358 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1359 ].start = (void *)db_tr; 1360 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1361 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1362 ].end = (void *)db_tr; 1363 } 1364 db_tr++; 1365 } 1366 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1367 = STAILQ_FIRST(&dbch->db_trq); 1368 out: 1369 dbch->xferq.queued = 0; 1370 dbch->pdb_tr = NULL; 1371 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1372 dbch->bottom = dbch->top; 1373 dbch->flags = FWOHCI_DBCH_INIT; 1374 selinit(&dbch->xferq.rsel); 1375 } 1376 1377 static int 1378 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1379 { 1380 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1381 int sleepch; 1382 1383 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1384 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1385 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1386 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1387 /* XXX we cannot free buffers until the DMA really stops */ 1388 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1389 fwohci_db_free(&sc->it[dmach]); 1390 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1391 return 0; 1392 } 1393 1394 static int 1395 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1396 { 1397 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1398 int sleepch; 1399 1400 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1401 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1402 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1403 /* XXX we cannot free buffers until the DMA really stops */ 1404 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1405 fwohci_db_free(&sc->ir[dmach]); 1406 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1407 return 0; 1408 } 1409 1410 #if BYTE_ORDER == BIG_ENDIAN 1411 static void 1412 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1413 { 1414 qld[0] = FWOHCI_DMA_READ(qld[0]); 1415 return; 1416 } 1417 #endif 1418 1419 static int 1420 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1421 { 1422 int err = 0; 1423 int idb, z, i, dmach = 0, ldesc; 1424 uint32_t off = 0; 1425 struct fwohcidb_tr *db_tr; 1426 struct fwohcidb *db; 1427 1428 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1429 err = EINVAL; 1430 return err; 1431 } 1432 z = dbch->ndesc; 1433 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1434 if( &sc->it[dmach] == dbch){ 1435 off = OHCI_ITOFF(dmach); 1436 break; 1437 } 1438 } 1439 if(off == 0){ 1440 err = EINVAL; 1441 return err; 1442 } 1443 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1444 return err; 1445 dbch->xferq.flag |= FWXFERQ_RUNNING; 1446 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1447 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1448 } 1449 db_tr = dbch->top; 1450 for (idb = 0; idb < dbch->ndb; idb ++) { 1451 fwohci_add_tx_buf(dbch, db_tr, idb); 1452 if(STAILQ_NEXT(db_tr, link) == NULL){ 1453 break; 1454 } 1455 db = db_tr->db; 1456 ldesc = db_tr->dbcnt - 1; 1457 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1458 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1459 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1460 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1461 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1462 FWOHCI_DMA_SET( 1463 db[ldesc].db.desc.cmd, 1464 OHCI_INTERRUPT_ALWAYS); 1465 /* OHCI 1.1 and above */ 1466 FWOHCI_DMA_SET( 1467 db[0].db.desc.cmd, 1468 OHCI_INTERRUPT_ALWAYS); 1469 } 1470 } 1471 db_tr = STAILQ_NEXT(db_tr, link); 1472 } 1473 FWOHCI_DMA_CLEAR( 1474 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1475 return err; 1476 } 1477 1478 static int 1479 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1480 { 1481 int err = 0; 1482 int idb, z, i, dmach = 0, ldesc; 1483 uint32_t off = 0; 1484 struct fwohcidb_tr *db_tr; 1485 struct fwohcidb *db; 1486 1487 z = dbch->ndesc; 1488 if(&sc->arrq == dbch){ 1489 off = OHCI_ARQOFF; 1490 }else if(&sc->arrs == dbch){ 1491 off = OHCI_ARSOFF; 1492 }else{ 1493 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1494 if( &sc->ir[dmach] == dbch){ 1495 off = OHCI_IROFF(dmach); 1496 break; 1497 } 1498 } 1499 } 1500 if(off == 0){ 1501 err = EINVAL; 1502 return err; 1503 } 1504 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1505 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1506 return err; 1507 }else{ 1508 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1509 err = EBUSY; 1510 return err; 1511 } 1512 } 1513 dbch->xferq.flag |= FWXFERQ_RUNNING; 1514 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1515 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1516 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1517 } 1518 db_tr = dbch->top; 1519 for (idb = 0; idb < dbch->ndb; idb ++) { 1520 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1521 if (STAILQ_NEXT(db_tr, link) == NULL) 1522 break; 1523 db = db_tr->db; 1524 ldesc = db_tr->dbcnt - 1; 1525 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1526 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1527 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1528 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1529 FWOHCI_DMA_SET( 1530 db[ldesc].db.desc.cmd, 1531 OHCI_INTERRUPT_ALWAYS); 1532 FWOHCI_DMA_CLEAR( 1533 db[ldesc].db.desc.depend, 1534 0xf); 1535 } 1536 } 1537 db_tr = STAILQ_NEXT(db_tr, link); 1538 } 1539 FWOHCI_DMA_CLEAR( 1540 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1541 dbch->buf_offset = 0; 1542 fwdma_sync_multiseg_all(dbch->am, 1543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1544 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1545 return err; 1546 }else{ 1547 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1548 } 1549 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1550 return err; 1551 } 1552 1553 static int 1554 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1555 { 1556 int sec, cycle, cycle_match; 1557 1558 cycle = cycle_now & 0x1fff; 1559 sec = cycle_now >> 13; 1560 #define CYCLE_MOD 0x10 1561 #if 1 1562 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1563 #else 1564 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1565 #endif 1566 cycle = cycle + CYCLE_DELAY; 1567 if (cycle >= 8000) { 1568 sec ++; 1569 cycle -= 8000; 1570 } 1571 cycle = roundup2(cycle, CYCLE_MOD); 1572 if (cycle >= 8000) { 1573 sec ++; 1574 if (cycle == 8000) 1575 cycle = 0; 1576 else 1577 cycle = CYCLE_MOD; 1578 } 1579 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1580 1581 return(cycle_match); 1582 } 1583 1584 static int 1585 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1586 { 1587 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1588 int err = 0; 1589 unsigned short tag, ich; 1590 struct fwohci_dbch *dbch; 1591 int cycle_match, cycle_now, s, ldesc; 1592 uint32_t stat; 1593 struct fw_bulkxfer *first, *chunk, *prev; 1594 struct fw_xferq *it; 1595 1596 dbch = &sc->it[dmach]; 1597 it = &dbch->xferq; 1598 1599 tag = (it->flag >> 6) & 3; 1600 ich = it->flag & 0x3f; 1601 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1602 dbch->ndb = it->bnpacket * it->bnchunk; 1603 dbch->ndesc = 3; 1604 fwohci_db_init(sc, dbch); 1605 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1606 return ENOMEM; 1607 err = fwohci_tx_enable(sc, dbch); 1608 } 1609 if(err) 1610 return err; 1611 1612 ldesc = dbch->ndesc - 1; 1613 s = splfw(); 1614 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1615 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1616 struct fwohcidb *db; 1617 1618 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1619 BUS_DMASYNC_PREWRITE); 1620 fwohci_txbufdb(sc, dmach, chunk); 1621 if (prev != NULL) { 1622 db = ((struct fwohcidb_tr *)(prev->end))->db; 1623 #if 0 /* XXX necessary? */ 1624 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1625 OHCI_BRANCH_ALWAYS); 1626 #endif 1627 #if 0 /* if bulkxfer->npacket changes */ 1628 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1629 ((struct fwohcidb_tr *) 1630 (chunk->start))->bus_addr | dbch->ndesc; 1631 #else 1632 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1633 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1634 #endif 1635 } 1636 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1637 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1638 prev = chunk; 1639 } 1640 fwdma_sync_multiseg_all(dbch->am, 1641 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1642 splx(s); 1643 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1644 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1645 printf("stat 0x%x\n", stat); 1646 1647 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1648 return 0; 1649 1650 #if 0 1651 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1652 #endif 1653 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1654 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1655 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1656 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1657 1658 first = STAILQ_FIRST(&it->stdma); 1659 OWRITE(sc, OHCI_ITCMD(dmach), 1660 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1661 if (firewire_debug > 1) { 1662 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1663 #if 1 1664 dump_dma(sc, ITX_CH + dmach); 1665 #endif 1666 } 1667 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1668 #if 1 1669 /* Don't start until all chunks are buffered */ 1670 if (STAILQ_FIRST(&it->stfree) != NULL) 1671 goto out; 1672 #endif 1673 #if 1 1674 /* Clear cycle match counter bits */ 1675 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1676 1677 /* 2bit second + 13bit cycle */ 1678 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1679 cycle_match = fwohci_next_cycle(fc, cycle_now); 1680 1681 OWRITE(sc, OHCI_ITCTL(dmach), 1682 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1683 | OHCI_CNTL_DMA_RUN); 1684 #else 1685 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1686 #endif 1687 if (firewire_debug > 1) { 1688 printf("cycle_match: 0x%04x->0x%04x\n", 1689 cycle_now, cycle_match); 1690 dump_dma(sc, ITX_CH + dmach); 1691 dump_db(sc, ITX_CH + dmach); 1692 } 1693 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1694 device_printf(sc->fc.dev, 1695 "IT DMA underrun (0x%08x)\n", stat); 1696 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1697 } 1698 out: 1699 return err; 1700 } 1701 1702 static int 1703 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1704 { 1705 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1706 int err = 0, s, ldesc; 1707 unsigned short tag, ich; 1708 uint32_t stat; 1709 struct fwohci_dbch *dbch; 1710 struct fwohcidb_tr *db_tr; 1711 struct fw_bulkxfer *first, *prev, *chunk; 1712 struct fw_xferq *ir; 1713 1714 dbch = &sc->ir[dmach]; 1715 ir = &dbch->xferq; 1716 1717 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1718 tag = (ir->flag >> 6) & 3; 1719 ich = ir->flag & 0x3f; 1720 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1721 1722 ir->queued = 0; 1723 dbch->ndb = ir->bnpacket * ir->bnchunk; 1724 dbch->ndesc = 2; 1725 fwohci_db_init(sc, dbch); 1726 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1727 return ENOMEM; 1728 err = fwohci_rx_enable(sc, dbch); 1729 } 1730 if(err) 1731 return err; 1732 1733 first = STAILQ_FIRST(&ir->stfree); 1734 if (first == NULL) { 1735 device_printf(fc->dev, "IR DMA no free chunk\n"); 1736 return 0; 1737 } 1738 1739 ldesc = dbch->ndesc - 1; 1740 s = splfw(); 1741 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1742 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1743 struct fwohcidb *db; 1744 1745 #if 1 /* XXX for if_fwe */ 1746 if (chunk->mbuf != NULL) { 1747 db_tr = (struct fwohcidb_tr *)(chunk->start); 1748 db_tr->dbcnt = 1; 1749 err = fw_bus_dmamap_load_mbuf( 1750 dbch->dmat, db_tr->dma_map, 1751 chunk->mbuf, fwohci_execute_db2, db_tr, 1752 BUS_DMA_WAITOK); 1753 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1754 OHCI_UPDATE | OHCI_INPUT_LAST | 1755 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1756 } 1757 #endif 1758 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1759 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1760 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1761 if (prev != NULL) { 1762 db = ((struct fwohcidb_tr *)(prev->end))->db; 1763 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1764 } 1765 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1766 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1767 prev = chunk; 1768 } 1769 fwdma_sync_multiseg_all(dbch->am, 1770 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1771 splx(s); 1772 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1773 if (stat & OHCI_CNTL_DMA_ACTIVE) 1774 return 0; 1775 if (stat & OHCI_CNTL_DMA_RUN) { 1776 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1777 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1778 } 1779 1780 if (firewire_debug) 1781 printf("start IR DMA 0x%x\n", stat); 1782 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1783 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1784 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1785 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1786 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1787 OWRITE(sc, OHCI_IRCMD(dmach), 1788 ((struct fwohcidb_tr *)(first->start))->bus_addr 1789 | dbch->ndesc); 1790 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1791 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1792 #if 0 1793 dump_db(sc, IRX_CH + dmach); 1794 #endif 1795 return err; 1796 } 1797 1798 FWOHCI_STOP() 1799 { 1800 FWOHCI_STOP_START; 1801 u_int i; 1802 1803 /* Now stopping all DMA channel */ 1804 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1805 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1806 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1807 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1808 1809 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1810 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1811 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1812 } 1813 1814 /* FLUSH FIFO and reset Transmitter/Reciever */ 1815 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1816 1817 /* Stop interrupt */ 1818 OWRITE(sc, FWOHCI_INTMASKCLR, 1819 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1820 | OHCI_INT_PHY_INT 1821 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1822 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1823 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1824 | OHCI_INT_PHY_BUS_R); 1825 1826 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1827 fw_drain_txq(&sc->fc); 1828 1829 /* XXX Link down? Bus reset? */ 1830 FWOHCI_STOP_RETURN(0); 1831 } 1832 1833 #if defined(__NetBSD__) 1834 static void 1835 fwohci_power(int why, void *arg) 1836 { 1837 struct fwohci_softc *sc = arg; 1838 int s; 1839 1840 s = splbio(); 1841 switch (why) { 1842 case PWR_SUSPEND: 1843 case PWR_STANDBY: 1844 fwohci_stop(arg); 1845 break; 1846 case PWR_RESUME: 1847 fwohci_resume(sc, sc->fc.dev); 1848 break; 1849 case PWR_SOFTSUSPEND: 1850 case PWR_SOFTSTANDBY: 1851 case PWR_SOFTRESUME: 1852 break; 1853 } 1854 splx(s); 1855 } 1856 #endif 1857 1858 int 1859 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1860 { 1861 int i; 1862 struct fw_xferq *ir; 1863 struct fw_bulkxfer *chunk; 1864 1865 fwohci_reset(sc, dev); 1866 /* XXX resume isochronous receive automatically. (how about TX?) */ 1867 for(i = 0; i < sc->fc.nisodma; i ++) { 1868 ir = &sc->ir[i].xferq; 1869 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1870 device_printf(sc->fc.dev, 1871 "resume iso receive ch: %d\n", i); 1872 ir->flag &= ~FWXFERQ_RUNNING; 1873 /* requeue stdma to stfree */ 1874 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1875 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1876 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1877 } 1878 sc->fc.irx_enable(&sc->fc, i); 1879 } 1880 } 1881 1882 #if defined(__FreeBSD__) 1883 bus_generic_resume(dev); 1884 #endif 1885 sc->fc.ibr(&sc->fc); 1886 return 0; 1887 } 1888 1889 #define ACK_ALL 1890 static void 1891 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1892 { 1893 uint32_t irstat, itstat; 1894 u_int i; 1895 struct firewire_comm *fc = (struct firewire_comm *)sc; 1896 1897 CTR0(KTR_DEV, "fwohci_intr_body"); 1898 #ifdef OHCI_DEBUG 1899 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1900 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1901 stat & OHCI_INT_EN ? "DMA_EN ":"", 1902 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1903 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1904 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1905 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1906 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1907 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1908 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1909 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1910 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1911 stat & OHCI_INT_PHY_SID ? "SID ":"", 1912 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1913 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1914 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1915 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1916 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1917 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1918 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1919 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1920 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1921 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1922 stat, OREAD(sc, FWOHCI_INTMASK) 1923 ); 1924 #endif 1925 /* Bus reset */ 1926 if(stat & OHCI_INT_PHY_BUS_R ){ 1927 if (fc->status == FWBUSRESET) 1928 goto busresetout; 1929 /* Disable bus reset interrupt until sid recv. */ 1930 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1931 1932 device_printf(fc->dev, "BUS reset\n"); 1933 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1934 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1935 1936 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1937 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1938 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1939 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1940 1941 #ifndef ACK_ALL 1942 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1943 #endif 1944 fw_busreset(fc); 1945 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1946 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1947 } 1948 busresetout: 1949 if((stat & OHCI_INT_DMA_IR )){ 1950 #ifndef ACK_ALL 1951 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1952 #endif 1953 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1954 irstat = sc->irstat; 1955 sc->irstat = 0; 1956 #else 1957 irstat = atomic_readandclear_int(&sc->irstat); 1958 #endif 1959 for(i = 0; i < fc->nisodma ; i++){ 1960 struct fwohci_dbch *dbch; 1961 1962 if((irstat & (1 << i)) != 0){ 1963 dbch = &sc->ir[i]; 1964 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1965 device_printf(sc->fc.dev, 1966 "dma(%d) not active\n", i); 1967 continue; 1968 } 1969 fwohci_rbuf_update(sc, i); 1970 } 1971 } 1972 } 1973 if((stat & OHCI_INT_DMA_IT )){ 1974 #ifndef ACK_ALL 1975 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1976 #endif 1977 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1978 itstat = sc->itstat; 1979 sc->itstat = 0; 1980 #else 1981 itstat = atomic_readandclear_int(&sc->itstat); 1982 #endif 1983 for(i = 0; i < fc->nisodma ; i++){ 1984 if((itstat & (1 << i)) != 0){ 1985 fwohci_tbuf_update(sc, i); 1986 } 1987 } 1988 } 1989 if((stat & OHCI_INT_DMA_PRRS )){ 1990 #ifndef ACK_ALL 1991 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1992 #endif 1993 #if 0 1994 dump_dma(sc, ARRS_CH); 1995 dump_db(sc, ARRS_CH); 1996 #endif 1997 fwohci_arcv(sc, &sc->arrs, count); 1998 } 1999 if((stat & OHCI_INT_DMA_PRRQ )){ 2000 #ifndef ACK_ALL 2001 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 2002 #endif 2003 #if 0 2004 dump_dma(sc, ARRQ_CH); 2005 dump_db(sc, ARRQ_CH); 2006 #endif 2007 fwohci_arcv(sc, &sc->arrq, count); 2008 } 2009 if (stat & OHCI_INT_CYC_LOST) { 2010 if (sc->cycle_lost >= 0) 2011 sc->cycle_lost ++; 2012 if (sc->cycle_lost > 10) { 2013 sc->cycle_lost = -1; 2014 #if 0 2015 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2016 #endif 2017 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2018 device_printf(fc->dev, "too many cycle lost, " 2019 "no cycle master presents?\n"); 2020 } 2021 } 2022 if(stat & OHCI_INT_PHY_SID){ 2023 uint32_t *buf, node_id; 2024 int plen; 2025 2026 #ifndef ACK_ALL 2027 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2028 #endif 2029 /* Enable bus reset interrupt */ 2030 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2031 /* Allow async. request to us */ 2032 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2033 /* XXX insecure ?? */ 2034 /* allow from all nodes */ 2035 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2036 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2037 /* 0 to 4GB regison */ 2038 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2039 /* Set ATRetries register */ 2040 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2041 /* 2042 ** Checking whether the node is root or not. If root, turn on 2043 ** cycle master. 2044 */ 2045 node_id = OREAD(sc, FWOHCI_NODEID); 2046 plen = OREAD(sc, OHCI_SID_CNT); 2047 2048 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2049 node_id, (plen >> 16) & 0xff); 2050 if (!(node_id & OHCI_NODE_VALID)) { 2051 printf("Bus reset failure\n"); 2052 goto sidout; 2053 } 2054 2055 /* cycle timer */ 2056 sc->cycle_lost = 0; 2057 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2058 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2059 printf("CYCLEMASTER mode\n"); 2060 OWRITE(sc, OHCI_LNKCTL, 2061 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2062 } else { 2063 printf("non CYCLEMASTER mode\n"); 2064 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2065 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2066 } 2067 2068 fc->nodeid = node_id & 0x3f; 2069 2070 if (plen & OHCI_SID_ERR) { 2071 device_printf(fc->dev, "SID Error\n"); 2072 goto sidout; 2073 } 2074 plen &= OHCI_SID_CNT_MASK; 2075 if (plen < 4 || plen > OHCI_SIDSIZE) { 2076 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2077 goto sidout; 2078 } 2079 plen -= 4; /* chop control info */ 2080 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2081 if (buf == NULL) { 2082 device_printf(fc->dev, "malloc failed\n"); 2083 goto sidout; 2084 } 2085 for (i = 0; i < plen / 4; i ++) 2086 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2087 #if defined(__NetBSD__) && defined(macppc) 2088 /* XXX required as bootdisk for macppc. */ 2089 delay(500000); 2090 #endif 2091 #if 1 /* XXX needed?? */ 2092 /* pending all pre-bus_reset packets */ 2093 fwohci_txd(sc, &sc->atrq); 2094 fwohci_txd(sc, &sc->atrs); 2095 fwohci_arcv(sc, &sc->arrs, -1); 2096 fwohci_arcv(sc, &sc->arrq, -1); 2097 fw_drain_txq(fc); 2098 #endif 2099 fw_sidrcv(fc, buf, plen); 2100 free(buf, M_FW); 2101 } 2102 sidout: 2103 if((stat & OHCI_INT_DMA_ATRQ )){ 2104 #ifndef ACK_ALL 2105 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2106 #endif 2107 fwohci_txd(sc, &(sc->atrq)); 2108 } 2109 if((stat & OHCI_INT_DMA_ATRS )){ 2110 #ifndef ACK_ALL 2111 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2112 #endif 2113 fwohci_txd(sc, &(sc->atrs)); 2114 } 2115 if((stat & OHCI_INT_PW_ERR )){ 2116 #ifndef ACK_ALL 2117 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2118 #endif 2119 device_printf(fc->dev, "posted write error\n"); 2120 } 2121 if((stat & OHCI_INT_ERR )){ 2122 #ifndef ACK_ALL 2123 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2124 #endif 2125 device_printf(fc->dev, "unrecoverable error\n"); 2126 } 2127 if((stat & OHCI_INT_PHY_INT)) { 2128 #ifndef ACK_ALL 2129 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2130 #endif 2131 device_printf(fc->dev, "phy int\n"); 2132 } 2133 2134 CTR0(KTR_DEV, "fwohci_intr_body done"); 2135 return; 2136 } 2137 2138 #if FWOHCI_TASKQUEUE 2139 static void 2140 fwohci_complete(void *arg, int pending) 2141 { 2142 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2143 uint32_t stat; 2144 2145 again: 2146 stat = atomic_readandclear_int(&sc->intstat); 2147 if (stat) { 2148 FW_LOCK; 2149 fwohci_intr_body(sc, stat, -1); 2150 FW_UNLOCK; 2151 } else 2152 return; 2153 goto again; 2154 } 2155 #endif 2156 2157 static uint32_t 2158 fwochi_check_stat(struct fwohci_softc *sc) 2159 { 2160 uint32_t stat, irstat, itstat; 2161 2162 stat = OREAD(sc, FWOHCI_INTSTAT); 2163 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2164 if (stat == 0xffffffff) { 2165 device_printf(sc->fc.dev, 2166 "device physically ejected?\n"); 2167 return(stat); 2168 } 2169 #ifdef ACK_ALL 2170 if (stat) 2171 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2172 #endif 2173 if (stat & OHCI_INT_DMA_IR) { 2174 irstat = OREAD(sc, OHCI_IR_STAT); 2175 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2176 atomic_set_int(&sc->irstat, irstat); 2177 } 2178 if (stat & OHCI_INT_DMA_IT) { 2179 itstat = OREAD(sc, OHCI_IT_STAT); 2180 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2181 atomic_set_int(&sc->itstat, itstat); 2182 } 2183 return(stat); 2184 } 2185 2186 FW_INTR(fwohci) 2187 { 2188 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2189 uint32_t stat; 2190 #if !FWOHCI_TASKQUEUE 2191 uint32_t bus_reset = 0; 2192 #endif 2193 2194 if (!(sc->intmask & OHCI_INT_EN)) { 2195 /* polling mode */ 2196 FW_INTR_RETURN(0); 2197 } 2198 2199 #if !FWOHCI_TASKQUEUE 2200 again: 2201 #endif 2202 CTR0(KTR_DEV, "fwohci_intr"); 2203 stat = fwochi_check_stat(sc); 2204 if (stat == 0 || stat == 0xffffffff) 2205 FW_INTR_RETURN(1); 2206 #if FWOHCI_TASKQUEUE 2207 atomic_set_int(&sc->intstat, stat); 2208 /* XXX mask bus reset intr. during bus reset phase */ 2209 if (stat) 2210 #if 1 2211 taskqueue_enqueue_fast(taskqueue_fast, 2212 &sc->fwohci_task_complete); 2213 #else 2214 taskqueue_enqueue(taskqueue_swi, 2215 &sc->fwohci_task_complete); 2216 #endif 2217 #else 2218 /* We cannot clear bus reset event during bus reset phase */ 2219 if ((stat & ~bus_reset) == 0) 2220 FW_INTR_RETURN(1); 2221 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2222 fwohci_intr_body(sc, stat, -1); 2223 goto again; 2224 #endif 2225 CTR0(KTR_DEV, "fwohci_intr end"); 2226 } 2227 2228 void 2229 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2230 { 2231 int s; 2232 uint32_t stat; 2233 struct fwohci_softc *sc; 2234 2235 2236 sc = (struct fwohci_softc *)fc; 2237 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2238 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2239 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2240 #if 0 2241 if (!quick) { 2242 #else 2243 if (1) { 2244 #endif 2245 stat = fwochi_check_stat(sc); 2246 if (stat == 0 || stat == 0xffffffff) 2247 return; 2248 } 2249 s = splfw(); 2250 fwohci_intr_body(sc, stat, count); 2251 splx(s); 2252 } 2253 2254 static void 2255 fwohci_set_intr(struct firewire_comm *fc, int enable) 2256 { 2257 struct fwohci_softc *sc; 2258 2259 sc = (struct fwohci_softc *)fc; 2260 if (firewire_debug) 2261 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2262 if (enable) { 2263 sc->intmask |= OHCI_INT_EN; 2264 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2265 } else { 2266 sc->intmask &= ~OHCI_INT_EN; 2267 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2268 } 2269 } 2270 2271 static void 2272 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2273 { 2274 struct firewire_comm *fc = &sc->fc; 2275 struct fwohcidb *db; 2276 struct fw_bulkxfer *chunk; 2277 struct fw_xferq *it; 2278 uint32_t stat, count; 2279 int s, w=0, ldesc; 2280 2281 it = fc->it[dmach]; 2282 ldesc = sc->it[dmach].ndesc - 1; 2283 s = splfw(); /* unnecessary ? */ 2284 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2285 if (firewire_debug) 2286 dump_db(sc, ITX_CH + dmach); 2287 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2288 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2289 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2290 >> OHCI_STATUS_SHIFT; 2291 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2292 /* timestamp */ 2293 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2294 & OHCI_COUNT_MASK; 2295 if (stat == 0) 2296 break; 2297 STAILQ_REMOVE_HEAD(&it->stdma, link); 2298 switch (stat & FWOHCIEV_MASK){ 2299 case FWOHCIEV_ACKCOMPL: 2300 #if 0 2301 device_printf(fc->dev, "0x%08x\n", count); 2302 #endif 2303 break; 2304 default: 2305 device_printf(fc->dev, 2306 "Isochronous transmit err %02x(%s)\n", 2307 stat, fwohcicode[stat & 0x1f]); 2308 } 2309 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2310 w++; 2311 } 2312 splx(s); 2313 if (w) 2314 wakeup(it); 2315 } 2316 2317 static void 2318 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2319 { 2320 struct firewire_comm *fc = &sc->fc; 2321 struct fwohcidb_tr *db_tr; 2322 struct fw_bulkxfer *chunk; 2323 struct fw_xferq *ir; 2324 uint32_t stat; 2325 int s, w=0, ldesc; 2326 2327 ir = fc->ir[dmach]; 2328 ldesc = sc->ir[dmach].ndesc - 1; 2329 #if 0 2330 dump_db(sc, dmach); 2331 #endif 2332 s = splfw(); 2333 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2334 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2335 db_tr = (struct fwohcidb_tr *)chunk->end; 2336 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2337 >> OHCI_STATUS_SHIFT; 2338 if (stat == 0) 2339 break; 2340 2341 if (chunk->mbuf != NULL) { 2342 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2343 BUS_DMASYNC_POSTREAD); 2344 fw_bus_dmamap_unload( 2345 sc->ir[dmach].dmat, db_tr->dma_map); 2346 } else if (ir->buf != NULL) { 2347 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2348 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2349 } else { 2350 /* XXX */ 2351 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2352 } 2353 2354 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2355 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2356 switch (stat & FWOHCIEV_MASK) { 2357 case FWOHCIEV_ACKCOMPL: 2358 chunk->resp = 0; 2359 break; 2360 default: 2361 chunk->resp = EINVAL; 2362 device_printf(fc->dev, 2363 "Isochronous receive err %02x(%s)\n", 2364 stat, fwohcicode[stat & 0x1f]); 2365 } 2366 w++; 2367 } 2368 splx(s); 2369 if (w) { 2370 if (ir->flag & FWXFERQ_HANDLER) 2371 ir->hand(ir); 2372 else 2373 wakeup(ir); 2374 } 2375 } 2376 2377 void 2378 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2379 { 2380 uint32_t off, cntl, stat, cmd, match; 2381 2382 if(ch == 0){ 2383 off = OHCI_ATQOFF; 2384 }else if(ch == 1){ 2385 off = OHCI_ATSOFF; 2386 }else if(ch == 2){ 2387 off = OHCI_ARQOFF; 2388 }else if(ch == 3){ 2389 off = OHCI_ARSOFF; 2390 }else if(ch < IRX_CH){ 2391 off = OHCI_ITCTL(ch - ITX_CH); 2392 }else{ 2393 off = OHCI_IRCTL(ch - IRX_CH); 2394 } 2395 cntl = stat = OREAD(sc, off); 2396 cmd = OREAD(sc, off + 0xc); 2397 match = OREAD(sc, off + 0x10); 2398 2399 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2400 ch, 2401 cntl, 2402 cmd, 2403 match); 2404 stat &= 0xffff ; 2405 if (stat) { 2406 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2407 ch, 2408 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2409 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2410 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2411 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2412 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2413 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2414 fwohcicode[stat & 0x1f], 2415 stat & 0x1f 2416 ); 2417 }else{ 2418 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2419 } 2420 } 2421 2422 void 2423 dump_db(struct fwohci_softc *sc, uint32_t ch) 2424 { 2425 struct fwohci_dbch *dbch; 2426 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2427 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2428 int idb, jdb; 2429 uint32_t cmd, off; 2430 if(ch == 0){ 2431 off = OHCI_ATQOFF; 2432 dbch = &sc->atrq; 2433 }else if(ch == 1){ 2434 off = OHCI_ATSOFF; 2435 dbch = &sc->atrs; 2436 }else if(ch == 2){ 2437 off = OHCI_ARQOFF; 2438 dbch = &sc->arrq; 2439 }else if(ch == 3){ 2440 off = OHCI_ARSOFF; 2441 dbch = &sc->arrs; 2442 }else if(ch < IRX_CH){ 2443 off = OHCI_ITCTL(ch - ITX_CH); 2444 dbch = &sc->it[ch - ITX_CH]; 2445 }else { 2446 off = OHCI_IRCTL(ch - IRX_CH); 2447 dbch = &sc->ir[ch - IRX_CH]; 2448 } 2449 cmd = OREAD(sc, off + 0xc); 2450 2451 if( dbch->ndb == 0 ){ 2452 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2453 return; 2454 } 2455 pp = dbch->top; 2456 prev = pp->db; 2457 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2458 cp = STAILQ_NEXT(pp, link); 2459 if(cp == NULL){ 2460 curr = NULL; 2461 goto outdb; 2462 } 2463 np = STAILQ_NEXT(cp, link); 2464 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2465 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2466 curr = cp->db; 2467 if(np != NULL){ 2468 next = np->db; 2469 }else{ 2470 next = NULL; 2471 } 2472 goto outdb; 2473 } 2474 } 2475 pp = STAILQ_NEXT(pp, link); 2476 if(pp == NULL){ 2477 curr = NULL; 2478 goto outdb; 2479 } 2480 prev = pp->db; 2481 } 2482 outdb: 2483 if( curr != NULL){ 2484 #if 0 2485 printf("Prev DB %d\n", ch); 2486 print_db(pp, prev, ch, dbch->ndesc); 2487 #endif 2488 printf("Current DB %d\n", ch); 2489 print_db(cp, curr, ch, dbch->ndesc); 2490 #if 0 2491 printf("Next DB %d\n", ch); 2492 print_db(np, next, ch, dbch->ndesc); 2493 #endif 2494 }else{ 2495 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2496 } 2497 return; 2498 } 2499 2500 void 2501 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2502 uint32_t ch, uint32_t hogemax) 2503 { 2504 fwohcireg_t stat; 2505 int i, key; 2506 uint32_t cmd, res; 2507 2508 if(db == NULL){ 2509 printf("No Descriptor is found\n"); 2510 return; 2511 } 2512 2513 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2514 ch, 2515 "Current", 2516 "OP ", 2517 "KEY", 2518 "INT", 2519 "BR ", 2520 "len", 2521 "Addr", 2522 "Depend", 2523 "Stat", 2524 "Cnt"); 2525 for( i = 0 ; i <= hogemax ; i ++){ 2526 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2527 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2528 key = cmd & OHCI_KEY_MASK; 2529 stat = res >> OHCI_STATUS_SHIFT; 2530 #if defined(__DragonFly__) || \ 2531 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2532 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2533 db_tr->bus_addr, 2534 #else 2535 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2536 (uintmax_t)db_tr->bus_addr, 2537 #endif 2538 dbcode[(cmd >> 28) & 0xf], 2539 dbkey[(cmd >> 24) & 0x7], 2540 dbcond[(cmd >> 20) & 0x3], 2541 dbcond[(cmd >> 18) & 0x3], 2542 cmd & OHCI_COUNT_MASK, 2543 FWOHCI_DMA_READ(db[i].db.desc.addr), 2544 FWOHCI_DMA_READ(db[i].db.desc.depend), 2545 stat, 2546 res & OHCI_COUNT_MASK); 2547 if(stat & 0xff00){ 2548 printf(" %s%s%s%s%s%s %s(%x)\n", 2549 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2550 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2551 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2552 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2553 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2554 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2555 fwohcicode[stat & 0x1f], 2556 stat & 0x1f 2557 ); 2558 }else{ 2559 printf(" Nostat\n"); 2560 } 2561 if(key == OHCI_KEY_ST2 ){ 2562 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2563 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2564 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2565 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2566 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2567 } 2568 if(key == OHCI_KEY_DEVICE){ 2569 return; 2570 } 2571 if((cmd & OHCI_BRANCH_MASK) 2572 == OHCI_BRANCH_ALWAYS){ 2573 return; 2574 } 2575 if((cmd & OHCI_CMD_MASK) 2576 == OHCI_OUTPUT_LAST){ 2577 return; 2578 } 2579 if((cmd & OHCI_CMD_MASK) 2580 == OHCI_INPUT_LAST){ 2581 return; 2582 } 2583 if(key == OHCI_KEY_ST2 ){ 2584 i++; 2585 } 2586 } 2587 return; 2588 } 2589 2590 void 2591 fwohci_ibr(struct firewire_comm *fc) 2592 { 2593 struct fwohci_softc *sc; 2594 uint32_t fun; 2595 2596 device_printf(fc->dev, "Initiate bus reset\n"); 2597 sc = (struct fwohci_softc *)fc; 2598 2599 /* 2600 * Make sure our cached values from the config rom are 2601 * initialised. 2602 */ 2603 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2604 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2605 2606 /* 2607 * Set root hold-off bit so that non cyclemaster capable node 2608 * shouldn't became the root node. 2609 */ 2610 #if 1 2611 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2612 fun |= FW_PHY_IBR | FW_PHY_RHB; 2613 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2614 #else /* Short bus reset */ 2615 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2616 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2617 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2618 #endif 2619 } 2620 2621 void 2622 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2623 { 2624 struct fwohcidb_tr *db_tr, *fdb_tr; 2625 struct fwohci_dbch *dbch; 2626 struct fwohcidb *db; 2627 struct fw_pkt *fp; 2628 struct fwohci_txpkthdr *ohcifp; 2629 unsigned short chtag; 2630 int idb; 2631 2632 dbch = &sc->it[dmach]; 2633 chtag = sc->it[dmach].xferq.flag & 0xff; 2634 2635 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2636 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2637 /* 2638 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2639 */ 2640 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2641 db = db_tr->db; 2642 fp = (struct fw_pkt *)db_tr->buf; 2643 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2644 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2645 ohcifp->mode.common.spd = 0 & 0x7; 2646 ohcifp->mode.stream.len = fp->mode.stream.len; 2647 ohcifp->mode.stream.chtag = chtag; 2648 ohcifp->mode.stream.tcode = 0xa; 2649 #if BYTE_ORDER == BIG_ENDIAN 2650 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2651 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2652 #endif 2653 2654 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2655 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2656 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2657 #if 0 /* if bulkxfer->npackets changes */ 2658 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2659 | OHCI_UPDATE 2660 | OHCI_BRANCH_ALWAYS; 2661 db[0].db.desc.depend = 2662 = db[dbch->ndesc - 1].db.desc.depend 2663 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2664 #else 2665 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2666 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2667 #endif 2668 bulkxfer->end = (void *)db_tr; 2669 db_tr = STAILQ_NEXT(db_tr, link); 2670 } 2671 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2672 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2673 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2674 #if 0 /* if bulkxfer->npackets changes */ 2675 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2676 /* OHCI 1.1 and above */ 2677 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2678 #endif 2679 /* 2680 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2681 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2682 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2683 */ 2684 return; 2685 } 2686 2687 static int 2688 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2689 int poffset) 2690 { 2691 struct fwohcidb *db = db_tr->db; 2692 struct fw_xferq *it; 2693 int err = 0; 2694 2695 it = &dbch->xferq; 2696 if(it->buf == 0){ 2697 err = EINVAL; 2698 return err; 2699 } 2700 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2701 db_tr->dbcnt = 3; 2702 2703 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2704 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2705 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2706 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2707 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2708 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2709 2710 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2711 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2712 #if 1 2713 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2714 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2715 #endif 2716 return 0; 2717 } 2718 2719 int 2720 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2721 int poffset, struct fwdma_alloc *dummy_dma) 2722 { 2723 struct fwohcidb *db = db_tr->db; 2724 struct fw_xferq *ir; 2725 int i, ldesc; 2726 bus_addr_t dbuf[2]; 2727 int dsiz[2]; 2728 2729 ir = &dbch->xferq; 2730 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2731 if (db_tr->buf == NULL) 2732 db_tr->buf = fwdma_malloc_size( 2733 dbch->dmat, &db_tr->dma_map, 2734 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2735 if (db_tr->buf == NULL) 2736 return(ENOMEM); 2737 db_tr->dbcnt = 1; 2738 dsiz[0] = ir->psize; 2739 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2740 BUS_DMASYNC_PREREAD); 2741 } else { 2742 db_tr->dbcnt = 0; 2743 if (dummy_dma != NULL) { 2744 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2745 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2746 } 2747 dsiz[db_tr->dbcnt] = ir->psize; 2748 if (ir->buf != NULL) { 2749 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2750 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2751 } 2752 db_tr->dbcnt++; 2753 } 2754 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2755 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2756 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2757 if (ir->flag & FWXFERQ_STREAM) { 2758 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2759 } 2760 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2761 } 2762 ldesc = db_tr->dbcnt - 1; 2763 if (ir->flag & FWXFERQ_STREAM) { 2764 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2765 } 2766 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2767 return 0; 2768 } 2769 2770 2771 static int 2772 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2773 { 2774 struct fw_pkt *fp0; 2775 uint32_t ld0; 2776 int slen, hlen; 2777 #if BYTE_ORDER == BIG_ENDIAN 2778 int i; 2779 #endif 2780 2781 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2782 #if 0 2783 printf("ld0: x%08x\n", ld0); 2784 #endif 2785 fp0 = (struct fw_pkt *)&ld0; 2786 /* determine length to swap */ 2787 switch (fp0->mode.common.tcode) { 2788 case FWTCODE_WRES: 2789 CTR0(KTR_DEV, "WRES"); 2790 case FWTCODE_RREQQ: 2791 case FWTCODE_WREQQ: 2792 case FWTCODE_RRESQ: 2793 case FWOHCITCODE_PHY: 2794 slen = 12; 2795 break; 2796 case FWTCODE_RREQB: 2797 case FWTCODE_WREQB: 2798 case FWTCODE_LREQ: 2799 case FWTCODE_RRESB: 2800 case FWTCODE_LRES: 2801 slen = 16; 2802 break; 2803 default: 2804 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2805 return(0); 2806 } 2807 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2808 if (hlen > len) { 2809 if (firewire_debug) 2810 printf("splitted header\n"); 2811 return(-hlen); 2812 } 2813 #if BYTE_ORDER == BIG_ENDIAN 2814 for(i = 0; i < slen/4; i ++) 2815 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2816 #endif 2817 return(hlen); 2818 } 2819 2820 static int 2821 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2822 { 2823 const struct tcode_info *info; 2824 int r; 2825 2826 info = &tinfo[fp->mode.common.tcode]; 2827 r = info->hdr_len + sizeof(uint32_t); 2828 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2829 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2830 2831 if (r == sizeof(uint32_t)) { 2832 /* XXX */ 2833 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2834 fp->mode.common.tcode); 2835 return (-1); 2836 } 2837 2838 if (r > dbch->xferq.psize) { 2839 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2840 return (-1); 2841 /* panic ? */ 2842 } 2843 2844 return r; 2845 } 2846 2847 static void 2848 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2849 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2850 { 2851 struct fwohcidb *db = &db_tr->db[0]; 2852 2853 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2854 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2855 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2856 fwdma_sync_multiseg_all(dbch->am, 2857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2858 dbch->bottom = db_tr; 2859 2860 if (wake) 2861 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2862 } 2863 2864 static void 2865 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2866 { 2867 struct fwohcidb_tr *db_tr; 2868 struct iovec vec[2]; 2869 struct fw_pkt pktbuf; 2870 int nvec; 2871 struct fw_pkt *fp; 2872 uint8_t *ld; 2873 uint32_t stat, off, status, event; 2874 u_int spd; 2875 int len, plen, hlen, pcnt, offset; 2876 int s; 2877 void *buf; 2878 int resCount; 2879 2880 CTR0(KTR_DEV, "fwohci_arv"); 2881 2882 if(&sc->arrq == dbch){ 2883 off = OHCI_ARQOFF; 2884 }else if(&sc->arrs == dbch){ 2885 off = OHCI_ARSOFF; 2886 }else{ 2887 return; 2888 } 2889 2890 s = splfw(); 2891 db_tr = dbch->top; 2892 pcnt = 0; 2893 /* XXX we cannot handle a packet which lies in more than two buf */ 2894 fwdma_sync_multiseg_all(dbch->am, 2895 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2896 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2897 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2898 while (status & OHCI_CNTL_DMA_ACTIVE) { 2899 #if 0 2900 2901 if (off == OHCI_ARQOFF) 2902 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2903 db_tr->bus_addr, status, resCount); 2904 #endif 2905 len = dbch->xferq.psize - resCount; 2906 ld = (uint8_t *)db_tr->buf; 2907 if (dbch->pdb_tr == NULL) { 2908 len -= dbch->buf_offset; 2909 ld += dbch->buf_offset; 2910 } 2911 if (len > 0) 2912 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2913 BUS_DMASYNC_POSTREAD); 2914 while (len > 0 ) { 2915 if (count >= 0 && count-- == 0) 2916 goto out; 2917 if(dbch->pdb_tr != NULL){ 2918 /* we have a fragment in previous buffer */ 2919 int rlen; 2920 2921 offset = dbch->buf_offset; 2922 if (offset < 0) 2923 offset = - offset; 2924 buf = (char *)dbch->pdb_tr->buf + offset; 2925 rlen = dbch->xferq.psize - offset; 2926 if (firewire_debug) 2927 printf("rlen=%d, offset=%d\n", 2928 rlen, dbch->buf_offset); 2929 if (dbch->buf_offset < 0) { 2930 /* splitted in header, pull up */ 2931 char *p; 2932 2933 p = (char *)&pktbuf; 2934 bcopy(buf, p, rlen); 2935 p += rlen; 2936 /* this must be too long but harmless */ 2937 rlen = sizeof(pktbuf) - rlen; 2938 if (rlen < 0) 2939 printf("why rlen < 0\n"); 2940 bcopy(db_tr->buf, p, rlen); 2941 ld += rlen; 2942 len -= rlen; 2943 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2944 if (hlen <= 0) { 2945 printf("hlen < 0 shouldn't happen"); 2946 goto err; 2947 } 2948 offset = sizeof(pktbuf); 2949 vec[0].iov_base = (char *)&pktbuf; 2950 vec[0].iov_len = offset; 2951 } else { 2952 /* splitted in payload */ 2953 offset = rlen; 2954 vec[0].iov_base = buf; 2955 vec[0].iov_len = rlen; 2956 } 2957 fp=(struct fw_pkt *)vec[0].iov_base; 2958 nvec = 1; 2959 } else { 2960 /* no fragment in previous buffer */ 2961 fp=(struct fw_pkt *)ld; 2962 hlen = fwohci_arcv_swap(fp, len); 2963 if (hlen == 0) 2964 goto err; 2965 if (hlen < 0) { 2966 dbch->pdb_tr = db_tr; 2967 dbch->buf_offset = - dbch->buf_offset; 2968 /* sanity check */ 2969 if (resCount != 0) { 2970 printf("resCount=%d hlen=%d\n", 2971 resCount, hlen); 2972 goto err; 2973 } 2974 goto out; 2975 } 2976 offset = 0; 2977 nvec = 0; 2978 } 2979 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2980 if (plen < 0) { 2981 /* minimum header size + trailer 2982 = sizeof(fw_pkt) so this shouldn't happens */ 2983 printf("plen(%d) is negative! offset=%d\n", 2984 plen, offset); 2985 goto err; 2986 } 2987 if (plen > 0) { 2988 len -= plen; 2989 if (len < 0) { 2990 dbch->pdb_tr = db_tr; 2991 if (firewire_debug) 2992 printf("splitted payload\n"); 2993 /* sanity check */ 2994 if (resCount != 0) { 2995 printf("resCount=%d plen=%d" 2996 " len=%d\n", 2997 resCount, plen, len); 2998 goto err; 2999 } 3000 goto out; 3001 } 3002 vec[nvec].iov_base = ld; 3003 vec[nvec].iov_len = plen; 3004 nvec ++; 3005 ld += plen; 3006 } 3007 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3008 if (nvec == 0) 3009 printf("nvec == 0\n"); 3010 3011 /* DMA result-code will be written at the tail of packet */ 3012 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3013 #if 0 3014 printf("plen: %d, stat %x\n", 3015 plen ,stat); 3016 #endif 3017 spd = (stat >> 21) & 0x3; 3018 event = (stat >> 16) & 0x1f; 3019 switch (event) { 3020 case FWOHCIEV_ACKPEND: 3021 #if 0 3022 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3023 #endif 3024 /* fall through */ 3025 case FWOHCIEV_ACKCOMPL: 3026 { 3027 struct fw_rcv_buf rb; 3028 3029 if ((vec[nvec-1].iov_len -= 3030 sizeof(struct fwohci_trailer)) == 0) 3031 nvec--; 3032 rb.fc = &sc->fc; 3033 rb.vec = vec; 3034 rb.nvec = nvec; 3035 rb.spd = spd; 3036 fw_rcv(&rb); 3037 break; 3038 } 3039 case FWOHCIEV_BUSRST: 3040 if (sc->fc.status != FWBUSRESET) 3041 printf("got BUSRST packet!?\n"); 3042 break; 3043 default: 3044 device_printf(sc->fc.dev, 3045 "Async DMA Receive error err=%02x %s" 3046 " plen=%d offset=%d len=%d status=0x%08x" 3047 " tcode=0x%x, stat=0x%08x\n", 3048 event, fwohcicode[event], plen, 3049 dbch->buf_offset, len, 3050 OREAD(sc, OHCI_DMACTL(off)), 3051 fp->mode.common.tcode, stat); 3052 #if 1 /* XXX */ 3053 goto err; 3054 #endif 3055 break; 3056 } 3057 pcnt ++; 3058 if (dbch->pdb_tr != NULL) { 3059 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3060 off, 1); 3061 dbch->pdb_tr = NULL; 3062 } 3063 3064 } 3065 out: 3066 if (resCount == 0) { 3067 /* done on this buffer */ 3068 if (dbch->pdb_tr == NULL) { 3069 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3070 dbch->buf_offset = 0; 3071 } else 3072 if (dbch->pdb_tr != db_tr) 3073 printf("pdb_tr != db_tr\n"); 3074 db_tr = STAILQ_NEXT(db_tr, link); 3075 fwdma_sync_multiseg_all(dbch->am, 3076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3077 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3078 >> OHCI_STATUS_SHIFT; 3079 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3080 & OHCI_COUNT_MASK; 3081 /* XXX check buffer overrun */ 3082 dbch->top = db_tr; 3083 } else { 3084 dbch->buf_offset = dbch->xferq.psize - resCount; 3085 fw_bus_dmamap_sync( 3086 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3087 break; 3088 } 3089 /* XXX make sure DMA is not dead */ 3090 } 3091 #if 0 3092 if (pcnt < 1) 3093 printf("fwohci_arcv: no packets\n"); 3094 #endif 3095 fwdma_sync_multiseg_all(dbch->am, 3096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3097 splx(s); 3098 return; 3099 3100 err: 3101 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3102 OREAD(sc, OHCI_DMACTL(off))); 3103 dbch->pdb_tr = NULL; 3104 /* skip until resCount != 0 */ 3105 printf(" skip buffer"); 3106 while (resCount == 0) { 3107 printf(" #"); 3108 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3109 db_tr = STAILQ_NEXT(db_tr, link); 3110 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3111 & OHCI_COUNT_MASK; 3112 } 3113 printf(" done\n"); 3114 dbch->top = db_tr; 3115 dbch->buf_offset = dbch->xferq.psize - resCount; 3116 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3117 fwdma_sync_multiseg_all( 3118 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3119 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3120 splx(s); 3121 } 3122 #if defined(__NetBSD__) 3123 3124 int 3125 fwohci_print(void *aux, const char *pnp) 3126 { 3127 struct fw_attach_args *fwa = (struct fw_attach_args *)aux; 3128 3129 if (pnp) 3130 aprint_normal("%s at %s", fwa->name, pnp); 3131 3132 return UNCONF; 3133 } 3134 #endif 3135
Indexes created Thu Sep 25 16:09:42 GMT 2025