fwohci.c revision 1.11
1 /*- 2 * Copyright (c) 2000 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * IEEE1394 Open Host Controller Interface 39 * based on OHCI Specification 1.1 (January 6, 2000) 40 * The first version to support network interface part is wrtten by 41 * Atsushi Onoe <onoe (at) netbsd.org>. 42 */ 43 44 #include "opt_inet.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/socket.h> 50 #include <sys/callout.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/mbuf.h> 55 56 #if __NetBSD_Version__ >= 105010000 57 #include <uvm/uvm_extern.h> 58 #else 59 #include <vm/vm.h> 60 #endif 61 62 #include <machine/bus.h> 63 64 #include <dev/ieee1394/ieee1394reg.h> 65 #include <dev/ieee1394/fwohcireg.h> 66 67 #include <dev/ieee1394/ieee1394var.h> 68 #include <dev/ieee1394/fwohcivar.h> 69 70 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 71 72 #if 0 73 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 74 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 75 #endif 76 static void fwohci_hw_init(struct fwohci_softc *); 77 static void fwohci_power(int, void *); 78 static void fwohci_shutdown(void *); 79 80 static int fwohci_desc_alloc(struct fwohci_softc *); 81 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 82 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 83 84 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 85 int, int); 86 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 87 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 88 89 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 90 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 91 static void fwohci_buf_init(struct fwohci_softc *); 92 static void fwohci_buf_start(struct fwohci_softc *); 93 static void fwohci_buf_stop(struct fwohci_softc *); 94 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 95 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 96 caddr_t *, int); 97 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 98 struct fwohci_pkt *); 99 100 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 101 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 102 static void fwohci_phy_busreset(struct fwohci_softc *); 103 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 104 105 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 106 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 107 void *); 108 109 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 110 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 111 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 112 113 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 114 struct fwohci_pkt *); 115 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 116 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 117 struct fwohci_pkt *); 118 119 static void fwohci_configrom_init(struct fwohci_softc *); 120 121 static void fwohci_selfid_init(struct fwohci_softc *); 122 static int fwohci_selfid_input(struct fwohci_softc *); 123 124 static void fwohci_csr_init(struct fwohci_softc *); 125 static int fwohci_csr_input(struct fwohci_softc *, void *, 126 struct fwohci_pkt *); 127 128 static void fwohci_uid_collect(struct fwohci_softc *); 129 static int fwohci_uid_input(struct fwohci_softc *, void *, 130 struct fwohci_pkt *); 131 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 132 133 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 134 void (*)(struct device *, struct mbuf *)); 135 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 136 static int fwohci_if_output(struct device *, struct mbuf *, 137 void (*)(struct device *, struct mbuf *)); 138 139 #ifdef FW_DEBUG 140 int fw_verbose = 0; 141 int fw_dump = 0; 142 #endif 143 144 int 145 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 146 { 147 int i; 148 u_int32_t val; 149 #if 0 150 int error; 151 #endif 152 153 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 154 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 155 156 /* 157 * Wait for reset completion 158 */ 159 for (i = 0; i < OHCI_LOOP; i++) { 160 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 161 if ((val & OHCI_HCControl_SoftReset) == 0) 162 break; 163 } 164 165 /* What dialect of OHCI is this device? 166 */ 167 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 168 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 169 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 170 171 /* Is the Global UID ROM present? 172 */ 173 if ((val & OHCI_Version_GUID_ROM) == 0) { 174 printf("\n%s: fatal: no global UID ROM\n", sc->sc_sc1394.sc1394_dev.dv_xname); 175 return -1; 176 } else { 177 178 /* Extract the Global UID 179 */ 180 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 181 sc->sc_sc1394.sc1394_guid[0] = (val >> 24) & 0xff; 182 sc->sc_sc1394.sc1394_guid[1] = (val >> 16) & 0xff; 183 sc->sc_sc1394.sc1394_guid[2] = (val >> 8) & 0xff; 184 sc->sc_sc1394.sc1394_guid[3] = (val >> 0) & 0xff; 185 186 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 187 sc->sc_sc1394.sc1394_guid[4] = (val >> 24) & 0xff; 188 sc->sc_sc1394.sc1394_guid[5] = (val >> 16) & 0xff; 189 sc->sc_sc1394.sc1394_guid[6] = (val >> 8) & 0xff; 190 sc->sc_sc1394.sc1394_guid[7] = (val >> 0) & 0xff; 191 } 192 193 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 194 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 195 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 196 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 197 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 198 199 /* Get the maximum link speed and receive size 200 */ 201 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 202 sc->sc_sc1394.sc1394_link_speed = 203 (val & OHCI_BusOptions_LinkSpd_MASK) 204 >> OHCI_BusOptions_LinkSpd_BITPOS; 205 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 206 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 207 } else { 208 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 209 } 210 211 /* MaxRec is encoded as log2(max_rec_octets)-1 212 */ 213 sc->sc_sc1394.sc1394_max_receive = 214 1 << (((val & OHCI_BusOptions_MaxRec_MASK) 215 >> OHCI_BusOptions_MaxRec_BITPOS) + 1); 216 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 217 218 /* 219 * Count how many isochronous ctx we have. 220 */ 221 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 222 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 223 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 224 for (i = 0; val != 0; val >>= 1) { 225 if (val & 0x1) 226 i++; 227 } 228 sc->sc_isoctx = i; 229 printf(", %d iso_ctx", sc->sc_isoctx); 230 231 printf("\n"); 232 233 #if 0 234 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 235 &sc->sc_configrom_map, 236 (caddr_t *) &sc->sc_configrom, 237 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 238 return error; 239 #endif 240 241 /* 242 * Enable Link Power 243 */ 244 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 245 246 /* 247 * Allocate descriptors 248 */ 249 if (fwohci_desc_alloc(sc)) 250 return -1; 251 252 /* 253 * Allocate DMA Context 254 */ 255 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 256 OHCI_CTX_ASYNC_RX_REQUEST); 257 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 258 OHCI_CTX_ASYNC_RX_RESPONSE); 259 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 260 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 261 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 262 M_DEVBUF, M_WAITOK); 263 for (i = 0; i < sc->sc_isoctx; i++) { 264 sc->sc_ctx_ir[i] = NULL; 265 #if 0 266 fwohci_ctx_alloc(sc, &sc->sc_ctx_ir[i], OHCI_BUF_IR_CNT, i); 267 sc->sc_ctx_ir[i]->fc_isoch = 1; 268 #endif 269 } 270 271 /* 272 * Allocate buffer for configuration ROM and SelfID buffer 273 */ 274 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 275 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 276 277 /* 278 * establish hooks for shutdown and suspend/resume 279 */ 280 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 281 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 282 callout_init(&sc->sc_selfid_callout); 283 284 /* 285 * Initialize hardware registers. 286 */ 287 fwohci_hw_init(sc); 288 289 /* 290 * Initiate Bus Reset 291 */ 292 config_defer(&sc->sc_sc1394.sc1394_dev, 293 (void (*)(struct device *))fwohci_phy_busreset); 294 295 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 296 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 297 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 298 "fw", fwohci_print); 299 300 return 0; 301 } 302 303 int 304 fwohci_intr(void *arg) 305 { 306 struct fwohci_softc * const sc = arg; 307 int i; 308 int progress = 0; 309 u_int32_t intmask, iso; 310 311 for (;;) { 312 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 313 if (intmask == 0) 314 return progress; 315 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 316 intmask & ~OHCI_Int_BusReset); 317 #ifdef FW_DEBUG 318 if (fw_verbose) { 319 printf("%s: intmask=0x%08x:", 320 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 321 if (intmask & OHCI_Int_CycleTooLong) 322 printf(" CycleTooLong"); 323 if (intmask & OHCI_Int_UnrecoverableError) 324 printf(" UnrecoverableError"); 325 if (intmask & OHCI_Int_CycleInconsistent) 326 printf(" CycleInconsistent"); 327 if (intmask & OHCI_Int_BusReset) 328 printf(" BusReset"); 329 if (intmask & OHCI_Int_SelfIDComplete) 330 printf(" SelfIDComplete"); 331 if (intmask & OHCI_Int_LockRespErr) 332 printf(" LockRespErr"); 333 if (intmask & OHCI_Int_PostedWriteErr) 334 printf(" PostedWriteErr"); 335 if (intmask & OHCI_Int_ReqTxComplete) 336 printf(" ReqTxComplete(0x%04x)", 337 OHCI_ASYNC_DMA_READ(sc, 338 OHCI_CTX_ASYNC_TX_REQUEST, 339 OHCI_SUBREG_ContextControlClear)); 340 if (intmask & OHCI_Int_RespTxComplete) 341 printf(" RespTxComplete(0x%04x)", 342 OHCI_ASYNC_DMA_READ(sc, 343 OHCI_CTX_ASYNC_TX_RESPONSE, 344 OHCI_SUBREG_ContextControlClear)); 345 if (intmask & OHCI_Int_ARRS) 346 printf(" ARRS(0x%04x)", 347 OHCI_ASYNC_DMA_READ(sc, 348 OHCI_CTX_ASYNC_RX_RESPONSE, 349 OHCI_SUBREG_ContextControlClear)); 350 if (intmask & OHCI_Int_ARRQ) 351 printf(" ARRQ(0x%04x)", 352 OHCI_ASYNC_DMA_READ(sc, 353 OHCI_CTX_ASYNC_RX_REQUEST, 354 OHCI_SUBREG_ContextControlClear)); 355 if (intmask & OHCI_Int_IsochRx) 356 printf(" IsochRx(0x%08x)", 357 OHCI_CSR_READ(sc, 358 OHCI_REG_IsoRecvIntEventClear)); 359 if (intmask & OHCI_Int_IsochTx) 360 printf(" IsochTx(0x%08x)", 361 OHCI_CSR_READ(sc, 362 OHCI_REG_IsoXmitIntEventClear)); 363 if (intmask & OHCI_Int_RQPkt) 364 printf(" RQPkt(0x%04x)", 365 OHCI_ASYNC_DMA_READ(sc, 366 OHCI_CTX_ASYNC_RX_REQUEST, 367 OHCI_SUBREG_ContextControlClear)); 368 if (intmask & OHCI_Int_RSPkt) 369 printf(" RSPkt(0x%04x)", 370 OHCI_ASYNC_DMA_READ(sc, 371 OHCI_CTX_ASYNC_RX_RESPONSE, 372 OHCI_SUBREG_ContextControlClear)); 373 printf("\n"); 374 } 375 #endif /* FW_DEBUG */ 376 if (intmask & OHCI_Int_BusReset) { 377 /* 378 * According to OHCI spec 6.1.1 "busReset", 379 * All asynchronous transmit must be stopped before 380 * clearing BusReset. Moreover, the BusReset 381 * interrupt bit should not be cleared during the 382 * SelfID phase. Thus we turned off interrupt mask 383 * bit of BusReset instead until SelfID completion 384 * or SelfID timeout. 385 */ 386 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 387 OHCI_Int_BusReset); 388 intmask &= OHCI_Int_SelfIDComplete; 389 fwohci_buf_stop(sc); 390 fwohci_buf_init(sc); 391 if (sc->sc_uidtbl != NULL) { 392 free(sc->sc_uidtbl, M_DEVBUF); 393 sc->sc_uidtbl = NULL; 394 } 395 callout_reset(&sc->sc_selfid_callout, 396 OHCI_SELFID_TIMEOUT, 397 (void (*)(void *))fwohci_phy_busreset, sc); 398 sc->sc_nodeid = 0xffff; /* indicate invalid */ 399 sc->sc_rootid = 0; 400 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 401 } 402 403 if (intmask & OHCI_Int_SelfIDComplete) { 404 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 405 OHCI_Int_BusReset); 406 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 407 OHCI_Int_BusReset); 408 callout_stop(&sc->sc_selfid_callout); 409 if (fwohci_selfid_input(sc) == 0) { 410 fwohci_buf_start(sc); 411 fwohci_uid_collect(sc); 412 } 413 } 414 415 if (intmask & OHCI_Int_ReqTxComplete) 416 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 417 if (intmask & OHCI_Int_RespTxComplete) 418 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 419 if (intmask & OHCI_Int_RQPkt) 420 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 421 if (intmask & OHCI_Int_RSPkt) 422 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 423 424 if (intmask & OHCI_Int_IsochTx) { 425 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 426 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 427 } 428 if (intmask & OHCI_Int_IsochRx) { 429 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 430 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 431 for (i = 0; i < sc->sc_isoctx; i++) { 432 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) 433 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 434 } 435 } 436 437 if (!progress) { 438 sc->sc_intrcnt.ev_count++; 439 progress = 1; 440 } 441 } 442 } 443 444 #if 0 445 static int 446 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 447 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 448 { 449 bus_dma_segment_t segs[1]; 450 int error, nsegs, steps; 451 452 steps = 0; 453 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 454 segs, 1, &nsegs, flags); 455 if (error) 456 goto cleanup; 457 458 steps = 1; 459 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 460 kvap, flags); 461 if (error) 462 goto cleanup; 463 464 if (error == 0) 465 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 466 size, flags, mapp); 467 if (error) 468 goto cleanup; 469 if (error == 0) 470 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 471 if (error) 472 goto cleanup; 473 474 cleanup: 475 switch (steps) { 476 case 1: 477 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 478 } 479 480 return error; 481 } 482 #endif 483 484 int 485 fwohci_print(void *aux, const char *pnp) 486 { 487 char *name = aux; 488 489 if (pnp) 490 printf("%s at %s", name, pnp); 491 492 return UNCONF; 493 } 494 495 static void 496 fwohci_hw_init(struct fwohci_softc *sc) 497 { 498 int i; 499 u_int32_t val; 500 501 /* 502 * Software Reset. 503 */ 504 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 505 for (i = 0; i < OHCI_LOOP; i++) { 506 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 507 if ((val & OHCI_HCControl_SoftReset) == 0) 508 break; 509 } 510 511 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 512 513 /* 514 * First, initilize CSRs with undefined value to default settings. 515 */ 516 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 517 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 518 #if 0 519 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 520 #else 521 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 522 #endif 523 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 524 for (i = 0; i < sc->sc_isoctx; i++) { 525 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 526 ~0); 527 } 528 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 529 530 fwohci_configrom_init(sc); 531 fwohci_selfid_init(sc); 532 fwohci_buf_init(sc); 533 fwohci_csr_init(sc); 534 535 /* 536 * Final CSR settings. 537 */ 538 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 539 OHCI_LinkControl_CycleTimerEnable | 540 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 541 542 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 543 544 /* clear receive filter */ 545 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 546 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 547 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 548 549 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 550 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 551 552 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 553 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 554 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 555 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 556 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 557 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 558 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 559 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 560 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 561 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 562 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 563 564 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 565 566 /* 567 * Start the receivers 568 */ 569 fwohci_buf_start(sc); 570 } 571 572 static void 573 fwohci_power(int why, void *arg) 574 { 575 struct fwohci_softc *sc = arg; 576 int s; 577 578 s = splimp(); 579 switch (why) { 580 case PWR_SUSPEND: 581 case PWR_STANDBY: 582 fwohci_shutdown(sc); 583 break; 584 case PWR_RESUME: 585 fwohci_hw_init(sc); 586 fwohci_phy_busreset(sc); 587 break; 588 case PWR_SOFTSUSPEND: 589 case PWR_SOFTSTANDBY: 590 case PWR_SOFTRESUME: 591 break; 592 } 593 splx(s); 594 } 595 596 static void 597 fwohci_shutdown(void *arg) 598 { 599 struct fwohci_softc *sc = arg; 600 u_int32_t val; 601 602 callout_stop(&sc->sc_selfid_callout); 603 /* disable all interrupt */ 604 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 605 fwohci_buf_stop(sc); 606 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 607 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 608 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 609 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 610 fwohci_phy_busreset(sc); 611 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 612 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 613 } 614 615 /* 616 * COMMON FUNCTIONS 617 */ 618 619 /* 620 * read the PHY Register. 621 */ 622 static u_int8_t 623 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 624 { 625 int i; 626 u_int32_t val; 627 628 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 629 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 630 for (i = 0; i < OHCI_LOOP; i++) { 631 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 632 OHCI_PhyControl_RdDone) 633 break; 634 } 635 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 636 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 637 } 638 639 /* 640 * write the PHY Register. 641 */ 642 static void 643 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 644 { 645 int i; 646 647 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 648 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 649 (val << OHCI_PhyControl_WrData_BITPOS)); 650 for (i = 0; i < OHCI_LOOP; i++) { 651 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 652 OHCI_PhyControl_WrReg)) 653 break; 654 } 655 } 656 657 /* 658 * Initiate Bus Reset 659 */ 660 static void 661 fwohci_phy_busreset(struct fwohci_softc *sc) 662 { 663 int s; 664 u_int8_t val; 665 666 s = splimp(); 667 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 668 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 669 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 670 callout_stop(&sc->sc_selfid_callout); 671 val = fwohci_phy_read(sc, 1); 672 val = (val & 0x80) | /* preserve RHB (force root) */ 673 0x40 | /* Initiate Bus Reset */ 674 0x3f; /* default GAP count */ 675 fwohci_phy_write(sc, 1, val); 676 splx(s); 677 } 678 679 /* 680 * PHY Packet 681 */ 682 static void 683 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 684 { 685 u_int32_t val; 686 u_int8_t key, phyid; 687 688 val = pkt->fp_hdr[1]; 689 if (val != ~pkt->fp_hdr[2]) { 690 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 691 OHCI_CTXCTL_EVENT_BUS_RESET) { 692 #ifdef FW_DEBUG 693 if (fw_verbose) 694 printf("fwohci_phy_input: BusReset: 0x%08x\n", 695 pkt->fp_hdr[2]); 696 #endif 697 } else { 698 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 699 sc->sc_sc1394.sc1394_dev.dv_xname, val, 700 pkt->fp_hdr[2]); 701 } 702 return; 703 } 704 key = (val & 0xc0000000) >> 30; 705 phyid = (val & 0x3f000000) >> 24; 706 switch (key) { 707 case 0: 708 #ifdef FW_DEBUG 709 if (fw_verbose) { 710 printf("fwohci_phy_input: PHY Config from %d:", phyid); 711 if (val & 0x00800000) 712 printf(" ForceRoot"); 713 if (val & 0x00400000) 714 printf(" Gap=%x", (val & 0x003f0000) >> 16); 715 printf("\n"); 716 } 717 #endif 718 break; 719 case 1: 720 #ifdef FW_DEBUG 721 if (fw_verbose) 722 printf("fwohci_phy_input: Link-on from %d\n", phyid); 723 #endif 724 break; 725 case 2: 726 #ifdef FW_DEBUG 727 if (fw_verbose) { 728 printf("fwohci_phy_input: SelfID from %d:", phyid); 729 if (val & 0x00800000) { 730 printf(" #%d", (val & 0x00700000) >> 20); 731 } else { 732 if (val & 0x00400000) 733 printf(" LinkActive"); 734 printf(" Gap=%x", (val & 0x003f0000) >> 16); 735 printf(" Spd=S%d", 736 100 << ((val & 0x0000c000) >> 14)); 737 if (val & 0x00000800) 738 printf(" Cont"); 739 if (val & 0x00000002) 740 printf(" InitiateBusReset"); 741 } 742 if (val & 0x00000001) 743 printf(" +"); 744 printf("\n"); 745 } 746 #endif 747 break; 748 default: 749 printf("%s: unknown PHY packet: 0x%08x\n", 750 sc->sc_sc1394.sc1394_dev.dv_xname, val); 751 break; 752 } 753 } 754 755 /* 756 * Descriptor for context DMA. 757 */ 758 static int 759 fwohci_desc_alloc(struct fwohci_softc *sc) 760 { 761 int error, mapsize, dsize; 762 763 /* 764 * allocate descriptor buffer 765 */ 766 767 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 768 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 769 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 770 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 771 mapsize = howmany(sc->sc_descsize, NBBY); 772 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 773 memset(sc->sc_descmap, 0, mapsize); 774 775 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 776 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 777 printf("%s: unable to allocate descriptor buffer, error = %d\n", 778 sc->sc_sc1394.sc1394_dev.dv_xname, error); 779 goto fail_0; 780 } 781 782 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 783 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 784 != 0) { 785 printf("%s: unable to map descriptor buffer, error = %d\n", 786 sc->sc_sc1394.sc1394_dev.dv_xname, error); 787 goto fail_1; 788 } 789 790 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 791 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 792 printf("%s: unable to create descriptor buffer DMA map, " 793 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 794 goto fail_2; 795 } 796 797 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 798 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 799 printf("%s: unable to load descriptor buffer DMA map, " 800 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 801 goto fail_3; 802 } 803 804 return 0; 805 806 fail_3: 807 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 808 fail_2: 809 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 810 fail_1: 811 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 812 fail_0: 813 return error; 814 } 815 816 static struct fwohci_desc * 817 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 818 { 819 int i, n; 820 821 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 822 for (i = 0; ; i++) { 823 if (i == ndesc) { 824 for (i = 0; i < ndesc; i++) 825 setbit(sc->sc_descmap, n + i); 826 return sc->sc_desc + n; 827 } 828 if (isset(sc->sc_descmap, n + i)) 829 break; 830 } 831 } 832 return NULL; 833 } 834 835 static void 836 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 837 { 838 int i, n; 839 840 n = fd - sc->sc_desc; 841 for (i = 0; i < ndesc; i++, n++) { 842 #ifdef DIAGNOSTICS 843 if (isclr(sc->sc_descmap, n)) 844 panic("fwohci_desc_put: duplicated free"); 845 #endif 846 clrbit(sc->sc_descmap, n); 847 } 848 } 849 850 /* 851 * Asyncronous/Isochronous Transmit/Receive Context 852 */ 853 static int 854 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 855 int bufcnt, int ctx) 856 { 857 int i, error; 858 struct fwohci_ctx *fc; 859 struct fwohci_buf *fb; 860 struct fwohci_desc *fd; 861 862 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 863 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 864 LIST_INIT(&fc->fc_handler); 865 TAILQ_INIT(&fc->fc_buf); 866 fc->fc_ctx = ctx; 867 fc->fc_bufcnt = bufcnt; 868 fb = (struct fwohci_buf *)&fc[1]; 869 for (i = 0; i < bufcnt; i++, fb++) { 870 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 871 goto fail; 872 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 873 error = ENOBUFS; 874 goto fail; 875 } 876 fb->fb_desc = fd; 877 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 878 ((caddr_t)fd - (caddr_t)sc->sc_desc); 879 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 880 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 881 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 882 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 883 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 884 } 885 *fcp = fc; 886 return 0; 887 888 fail: 889 while (i-- > 0) 890 fwohci_buf_free(sc, --fb); 891 free(fc, M_DEVBUF); 892 return error; 893 } 894 895 static void 896 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 897 { 898 struct fwohci_buf *fb; 899 struct fwohci_handler *fh; 900 901 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 902 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 903 NULL, NULL); 904 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 905 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 906 fwohci_buf_free(sc, fb); 907 } 908 free(fc, M_DEVBUF); 909 } 910 911 static void 912 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 913 { 914 struct fwohci_buf *fb, *nfb; 915 struct fwohci_desc *fd; 916 int n; 917 918 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 919 nfb = TAILQ_NEXT(fb, fb_list); 920 fb->fb_off = 0; 921 fd = fb->fb_desc; 922 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 923 fd->fd_rescount = fd->fd_reqcount; 924 } 925 926 n = fc->fc_ctx; 927 fb = TAILQ_FIRST(&fc->fc_buf); 928 if (fc->fc_isoch) { 929 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 930 fb->fb_daddr | 1); 931 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 932 OHCI_CTXCTL_RX_BUFFER_FILL | 933 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 934 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 935 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 936 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 937 OHCI_CTXCTL_RX_ISOCH_HEADER); 938 } else { 939 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 940 fb->fb_daddr | 1); 941 } 942 } 943 944 /* 945 * DMA data buffer 946 */ 947 static int 948 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 949 { 950 int error; 951 952 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 953 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 954 printf("%s: unable to allocate buffer, error = %d\n", 955 sc->sc_sc1394.sc1394_dev.dv_xname, error); 956 goto fail_0; 957 } 958 959 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 960 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 961 printf("%s: unable to map buffer, error = %d\n", 962 sc->sc_sc1394.sc1394_dev.dv_xname, error); 963 goto fail_1; 964 } 965 966 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 967 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 968 printf("%s: unable to create buffer DMA map, " 969 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 970 error); 971 goto fail_2; 972 } 973 974 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 975 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 976 printf("%s: unable to load buffer DMA map, " 977 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 978 error); 979 goto fail_3; 980 } 981 982 return 0; 983 984 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 985 fail_3: 986 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 987 fail_2: 988 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 989 fail_1: 990 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 991 fail_0: 992 return error; 993 } 994 995 static void 996 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 997 { 998 999 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1000 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1001 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1002 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1003 } 1004 1005 static void 1006 fwohci_buf_init(struct fwohci_softc *sc) 1007 { 1008 int i; 1009 1010 /* 1011 * Initialize for Asynchronous Transmit Queue. 1012 */ 1013 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1014 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1015 1016 /* 1017 * Initialize for Asynchronous Receive Queue. 1018 */ 1019 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1020 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1021 1022 /* 1023 * Initialize for Isochronous Receive Queue. 1024 */ 1025 for (i = 0; i < sc->sc_isoctx; i++) { 1026 if (sc->sc_ctx_ir[i] != NULL) 1027 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1028 } 1029 } 1030 1031 static void 1032 fwohci_buf_start(struct fwohci_softc *sc) 1033 { 1034 int i; 1035 1036 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1037 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1038 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1039 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1040 for (i = 0; i < sc->sc_isoctx; i++) { 1041 if (sc->sc_ctx_ir[i] != NULL && 1042 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1043 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1044 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1045 } 1046 } 1047 } 1048 1049 static void 1050 fwohci_buf_stop(struct fwohci_softc *sc) 1051 { 1052 int i, j; 1053 1054 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1055 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1056 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1057 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1058 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1059 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1060 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1061 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1062 for (i = 0; i < sc->sc_isoctx; i++) { 1063 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1064 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1065 } 1066 1067 /* 1068 * Make sure the transmitter is stopped. 1069 */ 1070 for (j = 0; j < OHCI_LOOP; j++) { 1071 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1072 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1073 continue; 1074 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1075 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1076 continue; 1077 break; 1078 } 1079 } 1080 1081 static void 1082 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1083 { 1084 struct fwohci_buf *fb, *tfb; 1085 1086 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1087 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1088 fb->fb_desc->fd_rescount != 0) 1089 break; 1090 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1091 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1092 fb->fb_off = 0; 1093 fb->fb_desc->fd_branch = 0; 1094 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1095 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1096 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1097 } 1098 } 1099 1100 static int 1101 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1102 int len) 1103 { 1104 struct fwohci_buf *fb; 1105 struct fwohci_desc *fd; 1106 int bufend; 1107 1108 fb = TAILQ_FIRST(&fc->fc_buf); 1109 again: 1110 fd = fb->fb_desc; 1111 #ifdef FW_DEBUG 1112 if (fw_verbose) 1113 printf("fwohci_buf_pktget: desc %d, off %d, req %d, res %d," 1114 " len %d, avail %d\n", 1115 fd - sc->sc_desc, fb->fb_off, fd->fd_reqcount, 1116 fd->fd_rescount, len, 1117 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1118 #endif 1119 bufend = fd->fd_reqcount - fd->fd_rescount; 1120 if (fb->fb_off >= bufend) { 1121 if (fc->fc_isoch && fb->fb_off > 0) { 1122 fb->fb_off = fd->fd_reqcount; 1123 fd->fd_rescount = 0; 1124 } 1125 if (fd->fd_rescount == 0) { 1126 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1127 goto again; 1128 } 1129 return 0; 1130 } 1131 if (fb->fb_off + len > bufend) 1132 len = bufend - fb->fb_off; 1133 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1134 BUS_DMASYNC_POSTREAD); 1135 *pp = fb->fb_buf + fb->fb_off; 1136 fb->fb_off += roundup(len, 4); 1137 return len; 1138 } 1139 1140 static int 1141 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1142 struct fwohci_pkt *pkt) 1143 { 1144 caddr_t p; 1145 int len, count, i; 1146 1147 memset(pkt, 0, sizeof(*pkt)); 1148 pkt->fp_uio.uio_iov = pkt->fp_iov; 1149 pkt->fp_uio.uio_rw = UIO_WRITE; 1150 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1151 1152 /* get first quadlet */ 1153 count = 4; 1154 if (fc->fc_isoch) { 1155 /* 1156 * get trailer first, may be bogus data unless status update 1157 * in descriptor is set. 1158 */ 1159 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1160 sizeof(pkt->fp_trail)); 1161 if (len <= 0) { 1162 #ifdef FW_DEBUG 1163 if (fw_verbose) 1164 printf("fwohci_buf_input: no input for is#%d\n", 1165 fc->fc_ctx); 1166 #endif 1167 return 0; 1168 } 1169 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1170 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1171 } 1172 len = fwohci_buf_pktget(sc, fc, &p, count); 1173 if (len <= 0) { 1174 #ifdef FW_DEBUG 1175 if (fw_verbose) 1176 printf("fwohci_buf_input: no input for %d\n", 1177 fc->fc_ctx); 1178 #endif 1179 return 0; 1180 } 1181 pkt->fp_hdr[0] = *(u_int32_t *)p; 1182 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1183 switch (pkt->fp_tcode) { 1184 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1185 case IEEE1394_TCODE_READ_RESP_QUAD: 1186 pkt->fp_hlen = 12; 1187 pkt->fp_dlen = 4; 1188 break; 1189 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1190 case IEEE1394_TCODE_READ_RESP_BLOCK: 1191 case IEEE1394_TCODE_LOCK_REQ: 1192 case IEEE1394_TCODE_LOCK_RESP: 1193 pkt->fp_hlen = 16; 1194 break; 1195 case IEEE1394_TCODE_STREAM_DATA: 1196 pkt->fp_hlen = 4; 1197 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1198 break; 1199 default: 1200 pkt->fp_hlen = 12; 1201 pkt->fp_dlen = 0; 1202 break; 1203 } 1204 1205 /* get header */ 1206 while (count < pkt->fp_hlen) { 1207 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1208 if (len == 0) { 1209 printf("fwohci_buf_input: malformed input 1: %d\n", 1210 pkt->fp_hlen - count); 1211 return 0; 1212 } 1213 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1214 count += len; 1215 } 1216 if (pkt->fp_hlen == 16) 1217 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1218 #ifdef FW_DEBUG 1219 if (fw_verbose) 1220 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1221 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1222 #endif 1223 1224 /* get data */ 1225 count = 0; 1226 i = 0; 1227 while (count < pkt->fp_dlen) { 1228 len = fwohci_buf_pktget(sc, fc, 1229 (caddr_t *)&pkt->fp_iov[i].iov_base, 1230 pkt->fp_dlen - count); 1231 if (len == 0) { 1232 printf("fwohci_buf_input: malformed input 2: %d\n", 1233 pkt->fp_hlen - count); 1234 return 0; 1235 } 1236 pkt->fp_iov[i++].iov_len = len; 1237 count += len; 1238 } 1239 pkt->fp_uio.uio_iovcnt = i; 1240 pkt->fp_uio.uio_resid = count; 1241 1242 if (!fc->fc_isoch) { 1243 /* get trailer */ 1244 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1245 sizeof(pkt->fp_trail)); 1246 if (len <= 0) { 1247 printf("fwohci_buf_input: malformed input 3: %d\n", 1248 pkt->fp_hlen - count); 1249 return 0; 1250 } 1251 } 1252 return 1; 1253 } 1254 1255 static int 1256 fwohci_handler_set(struct fwohci_softc *sc, 1257 int tcode, u_int32_t key1, u_int32_t key2, 1258 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1259 void *arg) 1260 { 1261 struct fwohci_ctx *fc; 1262 struct fwohci_handler *fh; 1263 int i, j; 1264 1265 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1266 j = sc->sc_isoctx; 1267 fh = NULL; 1268 for (i = 0; i < sc->sc_isoctx; i++) { 1269 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1270 if (j == sc->sc_isoctx) 1271 j = i; 1272 continue; 1273 } 1274 fh = LIST_FIRST(&fc->fc_handler); 1275 if (fh == NULL) { 1276 j = i; 1277 break; 1278 } 1279 if (fh->fh_tcode == tcode && 1280 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1281 break; 1282 fh = NULL; 1283 } 1284 if (fh == NULL) { 1285 if (handler == NULL) 1286 return 0; 1287 if (j == sc->sc_isoctx) { 1288 #ifdef FW_DEBUG 1289 if (fw_verbose) 1290 printf("fwohci_handler_set: " 1291 "no more free context\n"); 1292 #endif 1293 return ENOMEM; 1294 } 1295 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1296 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1297 fc->fc_isoch = 1; 1298 sc->sc_ctx_ir[j] = fc; 1299 } 1300 } 1301 } else { 1302 switch (tcode) { 1303 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1304 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1305 case IEEE1394_TCODE_READ_REQ_QUAD: 1306 case IEEE1394_TCODE_READ_REQ_BLOCK: 1307 case IEEE1394_TCODE_LOCK_REQ: 1308 fc = sc->sc_ctx_arrq; 1309 break; 1310 case IEEE1394_TCODE_WRITE_RESP: 1311 case IEEE1394_TCODE_READ_RESP_QUAD: 1312 case IEEE1394_TCODE_READ_RESP_BLOCK: 1313 case IEEE1394_TCODE_LOCK_RESP: 1314 fc = sc->sc_ctx_arrs; 1315 break; 1316 default: 1317 return EIO; 1318 } 1319 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1320 fh = LIST_NEXT(fh, fh_list)) { 1321 if (fh->fh_tcode == tcode && 1322 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1323 break; 1324 } 1325 } 1326 if (handler == NULL) { 1327 if (fh != NULL) { 1328 LIST_REMOVE(fh, fh_list); 1329 free(fh, M_DEVBUF); 1330 } 1331 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1332 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1333 fwohci_ctx_free(sc, fc); 1334 } 1335 return 0; 1336 } 1337 if (fh == NULL) { 1338 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 1339 if (fh == NULL) 1340 return ENOMEM; 1341 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1342 } 1343 fh->fh_tcode = tcode; 1344 fh->fh_key1 = key1; 1345 fh->fh_key2 = key2; 1346 fh->fh_handler = handler; 1347 fh->fh_handarg = arg; 1348 #ifdef FW_DEBUG 1349 if (fw_verbose) 1350 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1351 fc->fc_ctx, tcode, key1, key2); 1352 #endif 1353 1354 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1355 fwohci_ctx_init(sc, fc); 1356 #ifdef FW_DEBUG 1357 if (fw_verbose) 1358 printf("fwohci_handler_set: SYNC desc %d\n", 1359 TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc); 1360 #endif 1361 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextMatch, 1362 (OHCI_CTXMATCH_TAG0 << key2) | key1); 1363 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1364 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1365 } 1366 return 0; 1367 } 1368 1369 /* 1370 * Asyncronous Receive Requests input frontend. 1371 */ 1372 static void 1373 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1374 { 1375 int rcode; 1376 u_int32_t key1, key2; 1377 struct fwohci_handler *fh; 1378 struct fwohci_pkt pkt, res; 1379 1380 while (fwohci_buf_input(sc, fc, &pkt)) { 1381 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1382 fwohci_phy_input(sc, &pkt); 1383 continue; 1384 } 1385 key1 = pkt.fp_hdr[1] & 0xffff; 1386 key2 = pkt.fp_hdr[2]; 1387 memset(&res, 0, sizeof(res)); 1388 res.fp_uio.uio_rw = UIO_WRITE; 1389 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1390 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1391 fh = LIST_NEXT(fh, fh_list)) { 1392 if (pkt.fp_tcode == fh->fh_tcode && 1393 key1 == fh->fh_key1 && 1394 key2 == fh->fh_key2) { 1395 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1396 &pkt); 1397 break; 1398 } 1399 } 1400 if (fh == NULL) { 1401 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1402 #ifdef FW_DEBUG 1403 if (fw_verbose) 1404 printf("fwohci_arrq_input: no listener:" 1405 " tcode 0x%x, addr=0x%04x %08x\n", 1406 pkt.fp_tcode, key1, key2); 1407 #endif 1408 } 1409 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1410 OHCI_CTXCTL_EVENT_ACK_PENDING) 1411 continue; 1412 if (rcode != -1) 1413 fwohci_atrs_output(sc, rcode, &pkt, &res); 1414 } 1415 fwohci_buf_next(sc, fc); 1416 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1417 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1418 } 1419 1420 /* 1421 * Asynchronous Receive Response input frontend. 1422 */ 1423 static void 1424 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1425 { 1426 struct fwohci_pkt pkt; 1427 struct fwohci_handler *fh; 1428 u_int16_t srcid; 1429 int rcode, tlabel; 1430 1431 while (fwohci_buf_input(sc, fc, &pkt)) { 1432 srcid = pkt.fp_hdr[1] >> 16; 1433 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1434 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1435 #ifdef FW_DEBUG 1436 if (fw_verbose) 1437 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1438 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1439 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1440 pkt.fp_dlen); 1441 #endif 1442 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1443 fh = LIST_NEXT(fh, fh_list)) { 1444 if (pkt.fp_tcode == fh->fh_tcode && 1445 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1446 tlabel == fh->fh_key2) { 1447 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1448 LIST_REMOVE(fh, fh_list); 1449 free(fh, M_DEVBUF); 1450 break; 1451 } 1452 } 1453 #ifdef FW_DEBUG 1454 if (fw_verbose) 1455 if (fh == NULL) 1456 printf("fwohci_arrs_input: no lister\n"); 1457 #endif 1458 } 1459 fwohci_buf_next(sc, fc); 1460 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1461 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1462 } 1463 1464 /* 1465 * Isochronous Receive input frontend. 1466 */ 1467 static void 1468 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1469 { 1470 int rcode, chan, tag; 1471 struct iovec *iov; 1472 struct fwohci_handler *fh; 1473 struct fwohci_pkt pkt; 1474 1475 while (fwohci_buf_input(sc, fc, &pkt)) { 1476 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1477 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1478 #ifdef FW_DEBUG 1479 if (fw_verbose) 1480 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1481 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1482 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1483 #endif 1484 if (tag == IEEE1394_TAG_GASP) { 1485 /* 1486 * The pkt with tag=3 is GASP format. 1487 * Move GASP header to header part. 1488 */ 1489 if (pkt.fp_dlen < 8) 1490 continue; 1491 iov = pkt.fp_iov; 1492 /* assuming pkt per buffer mode */ 1493 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1494 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1495 iov->iov_base = (caddr_t)iov->iov_base + 8; 1496 iov->iov_len -= 8; 1497 pkt.fp_hlen += 8; 1498 pkt.fp_dlen -= 8; 1499 } 1500 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1501 fh = LIST_NEXT(fh, fh_list)) { 1502 if (pkt.fp_tcode == fh->fh_tcode && 1503 chan == fh->fh_key1 && tag == fh->fh_key2) { 1504 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1505 &pkt); 1506 break; 1507 } 1508 } 1509 #ifdef FW_DEBUG 1510 if (fw_verbose) { 1511 if (fh == NULL) 1512 printf("fwohci_ir_input: no handler\n"); 1513 else 1514 printf("fwohci_ir_input: rcode %d\n", rcode); 1515 } 1516 #endif 1517 } 1518 fwohci_buf_next(sc, fc); 1519 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1520 OHCI_CTXCTL_WAKE); 1521 } 1522 1523 /* 1524 * Asynchronous Transmit common routine. 1525 */ 1526 static int 1527 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1528 struct fwohci_pkt *pkt) 1529 { 1530 struct fwohci_buf *fb; 1531 struct fwohci_desc *fd; 1532 struct mbuf *m, *m0; 1533 int i, ndesc, error, off, len; 1534 u_int32_t val; 1535 1536 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) { 1537 /* We can't send anything during selfid duration */ 1538 return EAGAIN; 1539 } 1540 #ifdef FW_DEBUG 1541 if (fw_verbose) { 1542 struct iovec *iov; 1543 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1544 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1545 if (fw_dump) { 1546 for (i = 0; i < pkt->fp_hlen/4; i++) 1547 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1548 printf("$"); 1549 for (ndesc = 0, iov = pkt->fp_iov; 1550 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1551 for (i = 0; i < iov->iov_len; i++) 1552 printf("%s%02x", 1553 (i%32)?((i%4)?"":" "):"\n\t", 1554 ((u_int8_t *)iov->iov_base)[i]); 1555 printf("$"); 1556 } 1557 } 1558 printf("\n"); 1559 } 1560 #endif 1561 1562 if ((m = pkt->fp_m) != NULL) { 1563 for (ndesc = 2; m != NULL; m = m->m_next) 1564 ndesc++; 1565 if (ndesc > OHCI_DESC_MAX) { 1566 m0 = NULL; 1567 ndesc = 2; 1568 for (off = 0; off < pkt->fp_dlen; off += len) { 1569 if (m0 == NULL) { 1570 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1571 if (m0 != NULL) 1572 M_COPY_PKTHDR(m0, pkt->fp_m); 1573 m = m0; 1574 } else { 1575 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1576 m = m->m_next; 1577 } 1578 if (m != NULL) 1579 MCLGET(m, M_DONTWAIT); 1580 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1581 m_freem(m0); 1582 return ENOMEM; 1583 } 1584 len = pkt->fp_dlen - off; 1585 if (len > m->m_ext.ext_size) 1586 len = m->m_ext.ext_size; 1587 m_copydata(pkt->fp_m, off, len, 1588 mtod(m, caddr_t)); 1589 ndesc++; 1590 } 1591 m_freem(pkt->fp_m); 1592 pkt->fp_m = m0; 1593 } 1594 } else 1595 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1596 1597 if (ndesc > OHCI_DESC_MAX) 1598 return ENOBUFS; 1599 1600 if (fc->fc_bufcnt > 50) /*XXX*/ 1601 return ENOBUFS; 1602 if ((fb = malloc(sizeof(*fb), M_DEVBUF, M_NOWAIT)) == NULL) 1603 return ENOBUFS; 1604 fb->fb_nseg = ndesc; 1605 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1606 if (fb->fb_desc == NULL) { 1607 free(fb, M_DEVBUF); 1608 return ENOBUFS; 1609 } 1610 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1611 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1612 fb->fb_m = pkt->fp_m; 1613 fb->fb_callback = pkt->fp_callback; 1614 1615 if (ndesc > 2) { 1616 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1617 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &fb->fb_dmamap)) != 0) { 1618 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1619 free(fb, M_DEVBUF); 1620 return error; 1621 } 1622 1623 if (pkt->fp_m != NULL) 1624 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1625 pkt->fp_m, BUS_DMA_NOWAIT); 1626 else 1627 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1628 &pkt->fp_uio, BUS_DMA_NOWAIT); 1629 if (error != 0) { 1630 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1631 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1632 free(fb, M_DEVBUF); 1633 return error; 1634 } 1635 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1636 BUS_DMASYNC_PREWRITE); 1637 } 1638 1639 fd = fb->fb_desc; 1640 fd->fd_flags = OHCI_DESC_IMMED; 1641 fd->fd_reqcount = pkt->fp_hlen; 1642 fd->fd_data = 0; 1643 fd->fd_branch = 0; 1644 fd->fd_status = 0; 1645 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1646 i = 3; /* XXX: 3 sec */ 1647 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1648 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1649 ((((val >> 25) + i) & 0x7) << 13); 1650 } else 1651 fd->fd_timestamp = 0; 1652 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1653 for (i = 0; i < ndesc - 2; i++) { 1654 fd = fb->fb_desc + 2 + i; 1655 fd->fd_flags = 0; 1656 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1657 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1658 fd->fd_branch = 0; 1659 fd->fd_status = 0; 1660 fd->fd_timestamp = 0; 1661 } 1662 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1663 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1664 1665 #ifdef FW_DEBUG 1666 if (fw_verbose) { 1667 printf("fwohci_at_output: desc %d", fb->fb_desc - sc->sc_desc); 1668 for (i = 0; i < ndesc * 4; i++) 1669 printf("%s%08x", i&7?" ":"\n\t", 1670 ((u_int32_t *)fb->fb_desc)[i]); 1671 printf("\n"); 1672 } 1673 #endif 1674 1675 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1676 OHCI_SUBREG_ContextControlClear); 1677 1678 if (val & OHCI_CTXCTL_RUN) { 1679 if (fc->fc_branch == NULL) { 1680 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1681 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1682 goto run; 1683 } 1684 *fc->fc_branch = fb->fb_daddr | ndesc; 1685 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1686 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1687 } else { 1688 run: 1689 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1690 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1691 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1692 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1693 } 1694 fc->fc_branch = &fd->fd_branch; 1695 1696 fc->fc_bufcnt++; 1697 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1698 return 0; 1699 } 1700 1701 static void 1702 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1703 { 1704 struct fwohci_buf *fb; 1705 struct fwohci_desc *fd; 1706 int i; 1707 1708 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1709 fd = fb->fb_desc; 1710 #ifdef FW_DEBUG 1711 if (fw_verbose) { 1712 printf("fwohci_at_done: %sdesc %d (%d)", 1713 force ? "force " : "", 1714 fd - sc->sc_desc, fb->fb_nseg); 1715 for (i = 0; i < fb->fb_nseg * 4; i++) 1716 printf("%s%08x", i&7?" ":"\n ", 1717 ((u_int32_t *)fd)[i]); 1718 printf("\n"); 1719 } 1720 #endif 1721 if (fb->fb_nseg > 2) 1722 fd += fb->fb_nseg - 1; 1723 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1724 break; 1725 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1726 if (fc->fc_branch == &fd->fd_branch) { 1727 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1728 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1729 fc->fc_branch = NULL; 1730 for (i = 0; i < OHCI_LOOP; i++) { 1731 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1732 OHCI_SUBREG_ContextControlClear) & 1733 OHCI_CTXCTL_ACTIVE)) 1734 break; 1735 } 1736 } 1737 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1738 if (fb->fb_nseg > 2) 1739 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1740 fc->fc_bufcnt--; 1741 if (fb->fb_callback != NULL) { 1742 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1743 fb->fb_callback = NULL; 1744 } else if (fb->fb_m != NULL) 1745 m_freem(fb->fb_m); 1746 free(fb, M_DEVBUF); 1747 } 1748 } 1749 1750 /* 1751 * Asynchronous Transmit Reponse -- in response of request packet. 1752 */ 1753 static void 1754 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1755 struct fwohci_pkt *res) 1756 { 1757 1758 if (((*req->fp_trail & 0x001f0000) >> 16) != 1759 OHCI_CTXCTL_EVENT_ACK_PENDING) 1760 return; 1761 1762 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1763 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1764 switch (req->fp_tcode) { 1765 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1766 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1767 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1768 res->fp_hlen = 12; 1769 break; 1770 case IEEE1394_TCODE_READ_REQ_QUAD: 1771 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1772 res->fp_hlen = 16; 1773 res->fp_dlen = 0; 1774 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1775 res->fp_hdr[3] = 1776 *(u_int32_t *)res->fp_iov[0].iov_base; 1777 res->fp_uio.uio_iovcnt = 0; 1778 break; 1779 case IEEE1394_TCODE_READ_REQ_BLOCK: 1780 case IEEE1394_TCODE_LOCK_REQ: 1781 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1782 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1783 else 1784 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1785 res->fp_hlen = 16; 1786 res->fp_dlen = res->fp_uio.uio_resid; 1787 res->fp_hdr[3] = res->fp_dlen << 16; 1788 break; 1789 } 1790 res->fp_hdr[0] |= (res->fp_tcode << 4); 1791 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1792 } 1793 1794 /* 1795 * APPLICATION LAYER SERVICES 1796 */ 1797 1798 /* 1799 * Initialization for Configuration ROM (no DMA context) 1800 */ 1801 1802 #define CFR_MAXUNIT 20 1803 1804 struct configromctx { 1805 u_int32_t *ptr; 1806 int curunit; 1807 struct { 1808 u_int32_t *start; 1809 int length; 1810 u_int32_t *refer; 1811 int refunit; 1812 } unit[CFR_MAXUNIT]; 1813 }; 1814 1815 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1816 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1817 1818 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1819 1820 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1821 1822 #define CFR_PUT_CRC(cfr, n) \ 1823 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1824 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1825 1826 #define CFR_START_UNIT(cfr, n) \ 1827 do { \ 1828 if ((cfr)->unit[n].refer != NULL) { \ 1829 *(cfr)->unit[n].refer |= \ 1830 (cfr)->ptr - (cfr)->unit[n].refer; \ 1831 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1832 } \ 1833 (cfr)->curunit = (n); \ 1834 (cfr)->unit[n].start = (cfr)->ptr++; \ 1835 } while (0 /* CONSTCOND */) 1836 1837 #define CFR_PUT_REFER(cfr, key, n) \ 1838 do { \ 1839 (cfr)->unit[n].refer = (cfr)->ptr; \ 1840 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1841 *(cfr)->ptr++ = (key) << 24; \ 1842 } while (0 /* CONSTCOND */) 1843 1844 #define CFR_END_UNIT(cfr) \ 1845 do { \ 1846 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1847 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1848 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1849 } while (0 /* CONSTCOND */) 1850 1851 static u_int16_t 1852 fwohci_crc16(u_int32_t *ptr, int len) 1853 { 1854 int shift; 1855 u_int32_t crc, sum, data; 1856 1857 crc = 0; 1858 while (len-- > 0) { 1859 data = *ptr++; 1860 for (shift = 28; shift >= 0; shift -= 4) { 1861 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1862 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1863 } 1864 crc &= 0xffff; 1865 } 1866 return crc; 1867 } 1868 1869 static void 1870 fwohci_configrom_init(struct fwohci_softc *sc) 1871 { 1872 int i; 1873 struct fwohci_buf *fb; 1874 u_int32_t *hdr; 1875 struct configromctx cfr; 1876 1877 fb = &sc->sc_buf_cnfrom; 1878 memset(&cfr, 0, sizeof(cfr)); 1879 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1880 1881 /* headers */ 1882 CFR_START_UNIT(&cfr, 0); 1883 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1884 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1885 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1886 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1887 CFR_END_UNIT(&cfr); 1888 /* copy info_length from crc_length */ 1889 *hdr |= (*hdr & 0x00ff0000) << 8; 1890 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1891 1892 /* root directory */ 1893 CFR_START_UNIT(&cfr, 1); 1894 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1895 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1896 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1897 /* spt,64,fix,lst,drq */ 1898 #ifdef INET 1899 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1900 #endif /* INET */ 1901 #ifdef INET6 1902 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1903 #endif /* INET6 */ 1904 CFR_END_UNIT(&cfr); 1905 1906 CFR_START_UNIT(&cfr, 2); 1907 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1908 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1909 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1910 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1911 CFR_END_UNIT(&cfr); 1912 1913 #ifdef INET 1914 /* IPv4 unit directory */ 1915 CFR_START_UNIT(&cfr, 3); 1916 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1917 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1918 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1919 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1920 CFR_END_UNIT(&cfr); 1921 1922 CFR_START_UNIT(&cfr, 6); 1923 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1924 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1925 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1926 CFR_END_UNIT(&cfr); 1927 1928 CFR_START_UNIT(&cfr, 7); 1929 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1930 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1931 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1932 CFR_END_UNIT(&cfr); 1933 #endif /* INET */ 1934 1935 #ifdef INET6 1936 /* IPv6 unit directory */ 1937 CFR_START_UNIT(&cfr, 4); 1938 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1939 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1940 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 1941 /* XXX: TBA by IANA */ 1942 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1943 CFR_END_UNIT(&cfr); 1944 1945 CFR_START_UNIT(&cfr, 8); 1946 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1947 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1948 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1949 CFR_END_UNIT(&cfr); 1950 1951 CFR_START_UNIT(&cfr, 9); 1952 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1953 CFR_PUT_DATA1(&cfr, 0); 1954 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1955 CFR_END_UNIT(&cfr); 1956 #endif /* INET6 */ 1957 1958 #ifdef FW_DEBUG 1959 if (fw_dump) { 1960 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 1961 for (i = 0; i < cfr.ptr - hdr; i++) 1962 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 1963 printf("\n"); 1964 } 1965 #endif /* FW_DEBUG */ 1966 1967 /* 1968 * Make network byte order for DMA 1969 */ 1970 for (i = 0; i < cfr.ptr - hdr; i++) 1971 HTONL(hdr[i]); 1972 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 1973 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 1974 1975 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 1976 fb->fb_dmamap->dm_segs[0].ds_addr); 1977 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 1978 } 1979 1980 /* 1981 * SelfID buffer (no DMA context) 1982 */ 1983 static void 1984 fwohci_selfid_init(struct fwohci_softc *sc) 1985 { 1986 struct fwohci_buf *fb; 1987 u_int32_t val; 1988 1989 fb = &sc->sc_buf_selfid; 1990 #ifdef DIAGNOSTICS 1991 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 1992 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 1993 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 1994 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 1995 #endif 1996 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 1997 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 1998 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 1999 2000 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2001 fb->fb_dmamap->dm_segs[0].ds_addr); 2002 2003 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2004 } 2005 2006 static int 2007 fwohci_selfid_input(struct fwohci_softc *sc) 2008 { 2009 int i; 2010 u_int32_t count, val, gen; 2011 u_int32_t *buf; 2012 2013 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2014 if (val & OHCI_SelfID_Error) { 2015 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2016 return -1; 2017 } 2018 count = (val & OHCI_SelfID_Size_MASK) >> OHCI_SelfID_Size_BITPOS; 2019 gen = (val & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS; 2020 2021 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2022 0, count << 2, BUS_DMASYNC_POSTREAD); 2023 2024 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2025 if ((val & OHCI_SelfID_Gen_MASK) != (buf[0] & OHCI_SelfID_Gen_MASK)) { 2026 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2027 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2028 (buf[0] & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS); 2029 return -1; 2030 } 2031 2032 #ifdef FW_DEBUG 2033 if (fw_verbose) { 2034 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2035 val); 2036 for (i = 0; i < count; i++) 2037 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2038 printf("\n"); 2039 } 2040 #endif /* FW_DEBUG */ 2041 2042 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2043 if ((val & OHCI_NodeId_IDValid) == 0) { 2044 sc->sc_nodeid = 0xffff; /* invalid */ 2045 printf("%s: nodeid is invalid\n", 2046 sc->sc_sc1394.sc1394_dev.dv_xname); 2047 return -1; 2048 } 2049 sc->sc_nodeid = val & 0xffff; 2050 2051 for (i = 1; i < count; i += 2) { 2052 if (buf[i] != ~buf[i + 1]) { 2053 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2054 sc->sc_sc1394.sc1394_dev.dv_xname, i, 2055 buf[i], buf[i + 1]); 2056 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2057 /* 2058 * XXX: CXD3222 sometimes fails to DMA 2059 * selfid packet?? 2060 */ 2061 sc->sc_rootid = (count - 1) / 2 - 1; 2062 sc->sc_irmid = sc->sc_rootid; 2063 break; 2064 } 2065 return -1; 2066 } 2067 if (buf[i] & 0x00000001) 2068 continue; /* more pkt */ 2069 if (buf[i] & 0x00800000) 2070 continue; /* external id */ 2071 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2072 if ((buf[i] & 0x00400800) == 0x00400800) 2073 sc->sc_irmid = sc->sc_rootid; 2074 } 2075 #ifdef FW_DEBUG 2076 if (fw_verbose) 2077 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2078 sc->sc_sc1394.sc1394_dev.dv_xname, 2079 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2080 sc->sc_rootid, sc->sc_irmid); 2081 #endif 2082 2083 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2084 return -1; 2085 2086 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2087 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2088 OHCI_LinkControl_CycleMaster); 2089 else 2090 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2091 OHCI_LinkControl_CycleMaster); 2092 return 0; 2093 } 2094 2095 /* 2096 * some CSRs are handled by driver. 2097 */ 2098 static void 2099 fwohci_csr_init(struct fwohci_softc *sc) 2100 { 2101 int i; 2102 static u_int32_t csr[] = { 2103 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2104 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2105 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2106 CSR_SB_BROADCAST_CHANNEL 2107 }; 2108 2109 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2110 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2111 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2112 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2113 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2114 } 2115 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2116 } 2117 2118 static int 2119 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2120 { 2121 struct fwohci_pkt res; 2122 u_int32_t reg; 2123 2124 /* 2125 * XXX need to do special functionality other than just r/w... 2126 */ 2127 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2128 2129 if ((reg & 0x03) != 0) { 2130 /* alignment error */ 2131 return IEEE1394_RCODE_ADDRESS_ERROR; 2132 } 2133 #ifdef FW_DEBUG 2134 if (fw_verbose) 2135 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2136 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2137 #endif 2138 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2139 #ifdef FW_DEBUG 2140 if (fw_verbose) 2141 printf(" -> 0x%08x\n", 2142 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2143 #endif 2144 *(u_int32_t *)&sc->sc_csr[reg] = 2145 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2146 } else { 2147 #ifdef FW_DEBUG 2148 if (fw_verbose) 2149 printf("\n"); 2150 #endif 2151 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2152 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2153 res.fp_iov[0].iov_len = 4; 2154 res.fp_uio.uio_resid = 4; 2155 res.fp_uio.uio_iovcnt = 1; 2156 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2157 return -1; 2158 } 2159 return IEEE1394_RCODE_COMPLETE; 2160 } 2161 2162 /* 2163 * Mapping between nodeid and unique ID (EUI-64). 2164 */ 2165 static void 2166 fwohci_uid_collect(struct fwohci_softc *sc) 2167 { 2168 int i; 2169 struct fwohci_uidtbl *fu; 2170 struct fwohci_pkt pkt; 2171 2172 if (sc->sc_uidtbl != NULL) 2173 free(sc->sc_uidtbl, M_DEVBUF); 2174 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 2175 M_DEVBUF, M_NOWAIT); 2176 if (sc->sc_uidtbl == NULL) 2177 return; 2178 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2179 2180 memset(&pkt, 0, sizeof(pkt)); 2181 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2182 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2183 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2184 fu->fu_valid = 3; 2185 continue; 2186 } 2187 fu->fu_valid = 0; 2188 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2189 pkt.fp_hlen = 12; 2190 pkt.fp_dlen = 0; 2191 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2192 (pkt.fp_tcode << 4); 2193 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2194 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2195 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2196 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2197 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2198 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2199 2200 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2201 (pkt.fp_tcode << 4); 2202 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2203 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2204 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2205 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2206 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2207 } 2208 } 2209 2210 static int 2211 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2212 { 2213 int n, rcode; 2214 struct fwohci_uidtbl *fu; 2215 2216 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2217 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2218 if (rcode != IEEE1394_RCODE_COMPLETE || 2219 sc->sc_uidtbl == NULL || 2220 n > sc->sc_rootid) 2221 return 0; 2222 fu = &sc->sc_uidtbl[n]; 2223 if (arg == 0) { 2224 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2225 fu->fu_valid |= 0x1; 2226 } else { 2227 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2228 fu->fu_valid |= 0x2; 2229 } 2230 #ifdef FW_DEBUG 2231 if (fw_verbose && fu->fu_valid == 0x3) 2232 printf("fwohci_uid_input: " 2233 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2234 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2235 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2236 #endif 2237 return 0; 2238 } 2239 2240 static int 2241 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2242 { 2243 struct fwohci_uidtbl *fu; 2244 int n; 2245 static const u_int8_t bcast[] = 2246 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2247 2248 fu = sc->sc_uidtbl; 2249 if (fu == NULL) { 2250 notfound: 2251 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2252 return IEEE1394_BCAST_PHY_ID; 2253 fwohci_uid_collect(sc); /* try to get */ 2254 return -1; 2255 } 2256 for (n = 0; ; n++, fu++) { 2257 if (n > sc->sc_rootid) 2258 goto notfound; 2259 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2260 break; 2261 } 2262 return n; 2263 } 2264 2265 /* 2266 * functions to support network interface 2267 */ 2268 static int 2269 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2270 void (*handler)(struct device *, struct mbuf *)) 2271 { 2272 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2273 int s; 2274 2275 s = splimp(); 2276 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2277 fwohci_if_input, handler); 2278 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2279 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2280 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2281 splx(s); 2282 return 0; 2283 } 2284 2285 static int 2286 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2287 { 2288 int n, len; 2289 struct mbuf *m; 2290 struct iovec *iov; 2291 void (*handler)(struct device *, struct mbuf *) = arg; 2292 2293 #ifdef FW_DEBUG 2294 if (fw_verbose) { 2295 int i; 2296 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2297 pkt->fp_tcode, pkt->fp_dlen); 2298 if (fw_dump) { 2299 for (i = 0; i < pkt->fp_hlen/4; i++) 2300 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2301 printf("$"); 2302 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2303 iov = &pkt->fp_iov[n]; 2304 for (i = 0; i < iov->iov_len; i++) 2305 printf("%s%02x", 2306 (i%32)?((i%4)?"":" "):"\n\t", 2307 ((u_int8_t *)iov->iov_base)[i]); 2308 printf("$"); 2309 } 2310 } 2311 printf("\n"); 2312 } 2313 #endif /* FW_DEBUG */ 2314 len = pkt->fp_dlen; 2315 MGETHDR(m, M_DONTWAIT, MT_DATA); 2316 if (m == NULL) 2317 return IEEE1394_RCODE_COMPLETE; 2318 if (len + m->m_len > MHLEN) { 2319 MCLGET(m, M_DONTWAIT); 2320 if ((m->m_flags & M_EXT) == 0) { 2321 m_freem(m); 2322 return IEEE1394_RCODE_COMPLETE; 2323 } 2324 } 2325 m->m_len = 16; 2326 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2327 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2328 sc->sc_uidtbl[n].fu_valid != 0x3) { 2329 printf("%s: packet from unknown node: phy id %d\n", 2330 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2331 m_freem(m); 2332 return IEEE1394_RCODE_COMPLETE; 2333 } 2334 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2335 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2336 m->m_flags |= M_BCAST; 2337 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2338 } else { 2339 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2340 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2341 } 2342 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2343 mtod(m, u_int8_t *)[9] = 2344 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2345 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2346 2347 m->m_pkthdr.rcvif = NULL; /* set in child */ 2348 m->m_pkthdr.len = len + m->m_len; 2349 /* 2350 * We may use receive buffer by external mbuf instead of copy here. 2351 * But asynchronous receive buffer must be operate in buffer fill 2352 * mode, so that each receive buffer will shared by multiple mbufs. 2353 * If upper layer doesn't free mbuf soon, e.g. application program 2354 * is suspended, buffer must be reallocated. 2355 * Isochronous buffer must be operate in packet buffer mode, and 2356 * it is easy to map receive buffer to external mbuf. But it is 2357 * used for broadcast/multicast only, and is expected not so 2358 * performance sensitive for now. 2359 * XXX: The performance may be important for multicast case, 2360 * so we should revisit here later. 2361 * -- onoe 2362 */ 2363 n = 0; 2364 iov = pkt->fp_uio.uio_iov; 2365 while (len > 0) { 2366 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2367 iov->iov_len); 2368 m->m_len += iov->iov_len; 2369 len -= iov->iov_len; 2370 iov++; 2371 } 2372 (*handler)(sc->sc_sc1394.sc1394_if, m); 2373 return IEEE1394_RCODE_COMPLETE; 2374 } 2375 2376 static int 2377 fwohci_if_output(struct device *self, struct mbuf *m0, 2378 void (*callback)(struct device *, struct mbuf *)) 2379 { 2380 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2381 struct fwohci_pkt pkt; 2382 u_int8_t *p; 2383 int s, n, error, spd, hdrlen, maxrec; 2384 2385 p = mtod(m0, u_int8_t *); 2386 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2387 spd = IEEE1394_SPD_S100; /*XXX*/ 2388 maxrec = 512; /*XXX*/ 2389 hdrlen = 8; 2390 } else { 2391 n = fwohci_uid_lookup(sc, p); 2392 if (n < 0) { 2393 printf("%s: nodeid unknown:" 2394 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2395 sc->sc_sc1394.sc1394_dev.dv_xname, 2396 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2397 error = EHOSTUNREACH; 2398 goto end; 2399 } 2400 if (n == IEEE1394_BCAST_PHY_ID) { 2401 printf("%s: broadcast with !M_MCAST\n", 2402 sc->sc_sc1394.sc1394_dev.dv_xname); 2403 #ifdef FW_DEBUG 2404 if (fw_dump) { 2405 struct mbuf *m; 2406 printf("packet:"); 2407 for (m = m0; m != NULL; m = m->m_next) { 2408 for (n = 0; n < m->m_len; n++) 2409 printf("%s%02x", (n%32)? 2410 ((n%4)?"":" "):"\n\t", 2411 mtod(m, u_int8_t *)[n]); 2412 printf("$"); 2413 } 2414 printf("\n"); 2415 } 2416 #endif 2417 error = EHOSTUNREACH; 2418 goto end; 2419 } 2420 maxrec = 2 << p[8]; 2421 spd = p[9]; 2422 hdrlen = 0; 2423 } 2424 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2425 #ifdef FW_DEBUG 2426 if (fw_verbose) 2427 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2428 spd, sc->sc_sc1394.sc1394_link_speed); 2429 #endif 2430 spd = sc->sc_sc1394.sc1394_link_speed; 2431 } 2432 if (maxrec > (512 << spd)) { 2433 #ifdef FW_DEBUG 2434 if (fw_verbose) 2435 printf("fwohci_if_output: maxrec (%d) is larger for" 2436 " spd (%d)\n", maxrec, spd); 2437 #endif 2438 maxrec = 512 << spd; 2439 } 2440 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2441 #ifdef FW_DEBUG 2442 if (fw_verbose) 2443 printf("fwohci_if_output: maxrec (%d) is larger than" 2444 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2445 #endif 2446 maxrec >>= 1; 2447 } 2448 if (maxrec < 512) { 2449 #ifdef FW_DEBUG 2450 if (fw_verbose) 2451 printf("fwohci_if_output: maxrec (%d) is smaller" 2452 " than minimum\n", maxrec); 2453 #endif 2454 maxrec = 512; 2455 } 2456 2457 m_adj(m0, 16 - hdrlen); 2458 if (m0->m_pkthdr.len > maxrec) { 2459 #ifdef FW_DEBUG 2460 if (fw_verbose) 2461 printf("fwohci_if_output: packet too big:" 2462 " hdr %d, pktlen %d, maxrec %d\n", 2463 hdrlen, m0->m_pkthdr.len, maxrec); 2464 #endif 2465 error = E2BIG; /*XXX*/ 2466 goto end; 2467 } 2468 2469 memset(&pkt, 0, sizeof(pkt)); 2470 pkt.fp_uio.uio_iov = pkt.fp_iov; 2471 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2472 pkt.fp_uio.uio_rw = UIO_WRITE; 2473 s = splimp(); 2474 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2475 /* construct GASP header */ 2476 p = mtod(m0, u_int8_t *); 2477 p[0] = sc->sc_nodeid >> 8; 2478 p[1] = sc->sc_nodeid & 0xff; 2479 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2480 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2481 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2482 pkt.fp_hlen = 8; 2483 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2484 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2485 OHCI_NodeId_NodeNumber) << 8); 2486 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2487 } else { 2488 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2489 pkt.fp_hlen = 16; 2490 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2491 (spd << 16); 2492 pkt.fp_hdr[1] = 2493 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2494 (p[10] << 8) | p[11]; 2495 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2496 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2497 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2498 } 2499 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2500 pkt.fp_dlen = m0->m_pkthdr.len; 2501 pkt.fp_m = m0; 2502 pkt.fp_callback = callback; 2503 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2504 splx(s); 2505 m0 = pkt.fp_m; 2506 end: 2507 if (error) { 2508 if (callback) 2509 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2510 else 2511 m_freem(m0); 2512 } 2513 return error; 2514 } 2515
Indexes created Wed Sep 24 15:09:51 GMT 2025