fwohci.c revision 1.110
1 /* $NetBSD: fwohci.c,v 1.110 2007/11/05 19:08:56 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.93 2007/06/08 09:04:30 simokawa Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/kdb.h> 59 60 <<<<<<< fwohci.c 61 #include <machine/bus.h> 62 ======= 63 #include <sys/cdefs.h> 64 <<<<<<< fwohci.c 65 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.110 2007/11/05 19:08:56 kiyohara Exp $"); 66 >>>>>>> 1.108 67 ======= 68 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.110 2007/11/05 19:08:56 kiyohara Exp $"); 69 >>>>>>> 1.109 70 71 #if defined(__DragonFly__) || __FreeBSD_version < 500000 72 #include <machine/clock.h> /* for DELAY() */ 73 #endif 74 75 #ifdef __DragonFly__ 76 #include "fw_port.h" 77 #include "firewire.h" 78 #include "firewirereg.h" 79 #include "fwdma.h" 80 #include "fwohcireg.h" 81 #include "fwohcivar.h" 82 #include "firewire_phy.h" 83 #else 84 #include <dev/firewire/fw_port.h> 85 #include <dev/firewire/firewire.h> 86 #include <dev/firewire/firewirereg.h> 87 #include <dev/firewire/fwdma.h> 88 #include <dev/firewire/fwohcireg.h> 89 #include <dev/firewire/fwohcivar.h> 90 #include <dev/firewire/firewire_phy.h> 91 #endif 92 #elif defined(__NetBSD__) 93 #include <sys/param.h> 94 #include <sys/device.h> 95 #include <sys/errno.h> 96 #include <sys/conf.h> 97 #include <sys/kernel.h> 98 #include <sys/malloc.h> 99 #include <sys/mbuf.h> 100 #include <sys/proc.h> 101 #include <sys/reboot.h> 102 #include <sys/sysctl.h> 103 #include <sys/systm.h> 104 105 #include <sys/bus.h> 106 107 #include <dev/ieee1394/fw_port.h> 108 #include <dev/ieee1394/firewire.h> 109 #include <dev/ieee1394/firewirereg.h> 110 #include <dev/ieee1394/fwdma.h> 111 #include <dev/ieee1394/fwohcireg.h> 112 #include <dev/ieee1394/fwohcivar.h> 113 #include <dev/ieee1394/firewire_phy.h> 114 115 #include "ioconf.h" 116 #endif 117 118 #undef OHCI_DEBUG 119 120 static int nocyclemaster = 0; 121 int firewire_phydma_enable = 1; 122 #if defined(__FreeBSD__) 123 SYSCTL_DECL(_hw_firewire); 124 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 125 "Do not send cycle start packets"); 126 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW, 127 &firewire_phydma_enable, 1, "Allow physical request DMA from firewire"); 128 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable); 129 #elif defined(__NetBSD__) 130 /* 131 * Setup sysctl(3) MIB, hw.fwohci.* 132 * 133 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 134 */ 135 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 136 { 137 int rc, fwohci_node_num; 138 const struct sysctlnode *node; 139 140 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 141 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 142 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 143 goto err; 144 } 145 146 if ((rc = sysctl_createv(clog, 0, NULL, &node, 147 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 148 SYSCTL_DESCR("fwohci controls"), 149 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 150 goto err; 151 } 152 fwohci_node_num = node->sysctl_num; 153 154 /* fwohci no cyclemaster flag */ 155 if ((rc = sysctl_createv(clog, 0, NULL, &node, 156 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 157 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 158 NULL, 0, &nocyclemaster, 159 0, CTL_HW, fwohci_node_num, CTL_CREATE, CTL_EOL)) != 0) { 160 goto err; 161 } 162 163 /* fwohci physical request DMA enable */ 164 if ((rc = sysctl_createv(clog, 0, NULL, &node, 165 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, "phydma_enable", 166 SYSCTL_DESCR("Allow physical request DMA from firewire"), 167 NULL, 0, &firewire_phydma_enable, 168 0, CTL_HW, fwohci_node_num, CTL_CREATE, CTL_EOL)) != 0) { 169 goto err; 170 } 171 return; 172 173 err: 174 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 175 } 176 #endif 177 178 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 179 "STOR","LOAD","NOP ","STOP", 180 "", "", "", "", "", "", "", ""}; 181 182 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 183 "UNDEF","REG","SYS","DEV"}; 184 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 185 static const char * const fwohcicode[32] = { 186 "No stat","Undef","long","miss Ack err", 187 "FIFO underrun","FIFO overrun","desc err", "data read err", 188 "data write err","bus reset","timeout","tcode err", 189 "Undef","Undef","unknown event","flushed", 190 "Undef","ack complete","ack pend","Undef", 191 "ack busy_X","ack busy_A","ack busy_B","Undef", 192 "Undef","Undef","Undef","ack tardy", 193 "Undef","ack data_err","ack type_err",""}; 194 195 #define MAX_SPEED 3 196 extern const char *fw_linkspeed[]; 197 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 198 199 static const struct tcode_info tinfo[] = { 200 /* hdr_len block flag valid_response*/ 201 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES}, 202 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES}, 203 /* 2 WRES */ {12, FWTI_RES, 0xff}, 204 /* 3 XXX */ { 0, 0, 0xff}, 205 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ}, 206 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB}, 207 /* 6 RRESQ */ {16, FWTI_RES, 0xff}, 208 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 209 /* 8 CYCS */ { 0, 0, 0xff}, 210 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES}, 211 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff}, 212 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 213 /* c XXX */ { 0, 0, 0xff}, 214 /* d XXX */ { 0, 0, 0xff}, 215 /* e PHY */ {12, FWTI_REQ, 0xff}, 216 /* f XXX */ { 0, 0, 0xff} 217 }; 218 219 #define OHCI_WRITE_SIGMASK 0xffff0000 220 #define OHCI_READ_SIGMASK 0xffff0000 221 222 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 223 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 224 225 static void fwohci_ibr (struct firewire_comm *); 226 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 227 static void fwohci_db_free (struct fwohci_dbch *); 228 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 229 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 230 static void fwohci_start_atq (struct firewire_comm *); 231 static void fwohci_start_ats (struct firewire_comm *); 232 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 233 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 234 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 235 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 236 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 237 static int fwohci_irx_enable (struct firewire_comm *, int); 238 static int fwohci_irx_disable (struct firewire_comm *, int); 239 #if BYTE_ORDER == BIG_ENDIAN 240 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 241 #endif 242 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 243 static int fwohci_itx_disable (struct firewire_comm *, int); 244 static void fwohci_timeout (void *); 245 static void fwohci_set_intr (struct firewire_comm *, int); 246 247 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 248 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 249 static void dump_db (struct fwohci_softc *, uint32_t); 250 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 251 static void dump_dma (struct fwohci_softc *, uint32_t); 252 static uint32_t fwohci_cyctimer (struct firewire_comm *); 253 static void fwohci_rbuf_update (struct fwohci_softc *, int); 254 static void fwohci_tbuf_update (struct fwohci_softc *, int); 255 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 256 static void fwohci_task_busreset(void *, int); 257 static void fwohci_task_sid(void *, int); 258 static void fwohci_task_dma(void *, int); 259 #if defined(__NetBSD__) 260 int fwohci_print(void *, const char *); 261 #endif 262 263 /* 264 * memory allocated for DMA programs 265 */ 266 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 267 268 #define NDB FWMAXQUEUE 269 270 #define OHCI_VERSION 0x00 271 #define OHCI_ATRETRY 0x08 272 #define OHCI_CROMHDR 0x18 273 #define OHCI_BUS_OPT 0x20 274 #define OHCI_BUSIRMC (1 << 31) 275 #define OHCI_BUSCMC (1 << 30) 276 #define OHCI_BUSISC (1 << 29) 277 #define OHCI_BUSBMC (1 << 28) 278 #define OHCI_BUSPMC (1 << 27) 279 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 280 OHCI_BUSBMC | OHCI_BUSPMC 281 282 #define OHCI_EUID_HI 0x24 283 #define OHCI_EUID_LO 0x28 284 285 #define OHCI_CROMPTR 0x34 286 #define OHCI_HCCCTL 0x50 287 #define OHCI_HCCCTLCLR 0x54 288 #define OHCI_AREQHI 0x100 289 #define OHCI_AREQHICLR 0x104 290 #define OHCI_AREQLO 0x108 291 #define OHCI_AREQLOCLR 0x10c 292 #define OHCI_PREQHI 0x110 293 #define OHCI_PREQHICLR 0x114 294 #define OHCI_PREQLO 0x118 295 #define OHCI_PREQLOCLR 0x11c 296 #define OHCI_PREQUPPER 0x120 297 298 #define OHCI_SID_BUF 0x64 299 #define OHCI_SID_CNT 0x68 300 #define OHCI_SID_ERR (1 << 31) 301 #define OHCI_SID_CNT_MASK 0xffc 302 303 #define OHCI_IT_STAT 0x90 304 #define OHCI_IT_STATCLR 0x94 305 #define OHCI_IT_MASK 0x98 306 #define OHCI_IT_MASKCLR 0x9c 307 308 #define OHCI_IR_STAT 0xa0 309 #define OHCI_IR_STATCLR 0xa4 310 #define OHCI_IR_MASK 0xa8 311 #define OHCI_IR_MASKCLR 0xac 312 313 #define OHCI_LNKCTL 0xe0 314 #define OHCI_LNKCTLCLR 0xe4 315 316 #define OHCI_PHYACCESS 0xec 317 #define OHCI_CYCLETIMER 0xf0 318 319 #define OHCI_DMACTL(off) (off) 320 #define OHCI_DMACTLCLR(off) (off + 4) 321 #define OHCI_DMACMD(off) (off + 0xc) 322 #define OHCI_DMAMATCH(off) (off + 0x10) 323 324 #define OHCI_ATQOFF 0x180 325 #define OHCI_ATQCTL OHCI_ATQOFF 326 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 327 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 328 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 329 330 #define OHCI_ATSOFF 0x1a0 331 #define OHCI_ATSCTL OHCI_ATSOFF 332 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 333 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 334 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 335 336 #define OHCI_ARQOFF 0x1c0 337 #define OHCI_ARQCTL OHCI_ARQOFF 338 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 339 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 340 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 341 342 #define OHCI_ARSOFF 0x1e0 343 #define OHCI_ARSCTL OHCI_ARSOFF 344 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 345 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 346 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 347 348 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 349 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 350 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 351 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 352 353 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 354 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 355 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 356 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 357 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 358 359 #if defined(__FreeBSD__) 360 d_ioctl_t fwohci_ioctl; 361 #elif defined(__NetBSD__) 362 dev_type_ioctl(fwohci_ioctl); 363 #endif 364 365 /* 366 * Communication with PHY device 367 */ 368 /* XXX need lock for phy access */ 369 static uint32_t 370 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 371 { 372 uint32_t fun; 373 374 addr &= 0xf; 375 data &= 0xff; 376 377 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 378 OWRITE(sc, OHCI_PHYACCESS, fun); 379 DELAY(100); 380 381 return(fwphy_rddata( sc, addr)); 382 } 383 384 static uint32_t 385 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 386 { 387 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 388 int i; 389 uint32_t bm; 390 391 #define OHCI_CSR_DATA 0x0c 392 #define OHCI_CSR_COMP 0x10 393 #define OHCI_CSR_CONT 0x14 394 #define OHCI_BUS_MANAGER_ID 0 395 396 OWRITE(sc, OHCI_CSR_DATA, node); 397 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 398 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 399 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 400 DELAY(10); 401 bm = OREAD(sc, OHCI_CSR_DATA); 402 if((bm & 0x3f) == 0x3f) 403 bm = node; 404 if (firewire_debug) 405 fw_printf(sc->fc.dev, 406 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 407 408 return(bm); 409 } 410 411 static uint32_t 412 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 413 { 414 uint32_t fun, stat; 415 u_int i, retry = 0; 416 417 addr &= 0xf; 418 #define MAX_RETRY 100 419 again: 420 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 421 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 422 OWRITE(sc, OHCI_PHYACCESS, fun); 423 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 424 fun = OREAD(sc, OHCI_PHYACCESS); 425 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 426 break; 427 DELAY(100); 428 } 429 if(i >= MAX_RETRY) { 430 if (firewire_debug) 431 fw_printf(sc->fc.dev, "phy read failed(1).\n"); 432 if (++retry < MAX_RETRY) { 433 DELAY(100); 434 goto again; 435 } 436 } 437 /* Make sure that SCLK is started */ 438 stat = OREAD(sc, FWOHCI_INTSTAT); 439 if ((stat & OHCI_INT_REG_FAIL) != 0 || 440 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 441 if (firewire_debug) 442 fw_printf(sc->fc.dev, "phy read failed(2).\n"); 443 if (++retry < MAX_RETRY) { 444 DELAY(100); 445 goto again; 446 } 447 } 448 if (firewire_debug || retry >= MAX_RETRY) 449 fw_printf(sc->fc.dev, 450 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 451 #undef MAX_RETRY 452 return((fun >> PHYDEV_RDDATA )& 0xff); 453 } 454 /* Device specific ioctl. */ 455 FW_IOCTL(fwohci) 456 { 457 FW_IOCTL_START; 458 struct fwohci_softc *fc; 459 int err = 0; 460 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 461 uint32_t *dmach = (uint32_t *) data; 462 463 if(sc == NULL){ 464 return(EINVAL); 465 } 466 fc = (struct fwohci_softc *)sc->fc; 467 468 if (!data) 469 return(EINVAL); 470 471 switch (cmd) { 472 case FWOHCI_WRREG: 473 #define OHCI_MAX_REG 0x800 474 if(reg->addr <= OHCI_MAX_REG){ 475 OWRITE(fc, reg->addr, reg->data); 476 reg->data = OREAD(fc, reg->addr); 477 }else{ 478 err = EINVAL; 479 } 480 break; 481 case FWOHCI_RDREG: 482 if(reg->addr <= OHCI_MAX_REG){ 483 reg->data = OREAD(fc, reg->addr); 484 }else{ 485 err = EINVAL; 486 } 487 break; 488 /* Read DMA descriptors for debug */ 489 case DUMPDMA: 490 if(*dmach <= OHCI_MAX_DMA_CH ){ 491 dump_dma(fc, *dmach); 492 dump_db(fc, *dmach); 493 }else{ 494 err = EINVAL; 495 } 496 break; 497 /* Read/Write Phy registers */ 498 #define OHCI_MAX_PHY_REG 0xf 499 case FWOHCI_RDPHYREG: 500 if (reg->addr <= OHCI_MAX_PHY_REG) 501 reg->data = fwphy_rddata(fc, reg->addr); 502 else 503 err = EINVAL; 504 break; 505 case FWOHCI_WRPHYREG: 506 if (reg->addr <= OHCI_MAX_PHY_REG) 507 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 508 else 509 err = EINVAL; 510 break; 511 default: 512 err = EINVAL; 513 break; 514 } 515 return err; 516 } 517 518 static int 519 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 520 { 521 uint32_t reg, reg2; 522 int e1394a = 1; 523 /* 524 * probe PHY parameters 525 * 0. to prove PHY version, whether compliance of 1394a. 526 * 1. to probe maximum speed supported by the PHY and 527 * number of port supported by core-logic. 528 * It is not actually available port on your PC . 529 */ 530 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 531 DELAY(500); 532 533 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 534 535 if((reg >> 5) != 7 ){ 536 sc->fc.mode &= ~FWPHYASYST; 537 sc->fc.nport = reg & FW_PHY_NP; 538 sc->fc.speed = reg & FW_PHY_SPD >> 6; 539 if (sc->fc.speed > MAX_SPEED) { 540 fw_printf(dev, "invalid speed %d (fixed to %d).\n", 541 sc->fc.speed, MAX_SPEED); 542 sc->fc.speed = MAX_SPEED; 543 } 544 fw_printf(dev, "Phy 1394 only %s, %d ports.\n", 545 fw_linkspeed[sc->fc.speed], sc->fc.nport); 546 }else{ 547 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 548 sc->fc.mode |= FWPHYASYST; 549 sc->fc.nport = reg & FW_PHY_NP; 550 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 551 if (sc->fc.speed > MAX_SPEED) { 552 fw_printf(dev, "invalid speed %d (fixed to %d).\n", 553 sc->fc.speed, MAX_SPEED); 554 sc->fc.speed = MAX_SPEED; 555 } 556 fw_printf(dev, "Phy 1394a available %s, %d ports.\n", 557 fw_linkspeed[sc->fc.speed], sc->fc.nport); 558 559 /* check programPhyEnable */ 560 reg2 = fwphy_rddata(sc, 5); 561 #if 0 562 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 563 #else /* XXX force to enable 1394a */ 564 if (e1394a) { 565 #endif 566 if (firewire_debug) 567 fw_printf(dev, "Enable 1394a Enhancements\n"); 568 /* enable EAA EMC */ 569 reg2 |= 0x03; 570 /* set aPhyEnhanceEnable */ 571 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 572 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 573 } 574 #if 0 575 else { 576 /* for safe */ 577 reg2 &= ~0x83; 578 } 579 #endif 580 reg2 = fwphy_wrdata(sc, 5, reg2); 581 } 582 583 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 584 if((reg >> 5) == 7 ){ 585 reg = fwphy_rddata(sc, 4); 586 reg |= 1 << 6; 587 fwphy_wrdata(sc, 4, reg); 588 reg = fwphy_rddata(sc, 4); 589 } 590 return 0; 591 } 592 593 594 void 595 fwohci_reset(struct fwohci_softc *sc, device_t dev) 596 { 597 int i, max_rec, speed; 598 uint32_t reg, reg2; 599 struct fwohcidb_tr *db_tr; 600 601 /* Disable interrupts */ 602 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 603 604 /* Now stopping all DMA channels */ 605 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 606 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 607 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 608 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 609 610 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 611 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 612 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 613 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 614 } 615 616 /* FLUSH FIFO and reset Transmitter/Reciever */ 617 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 618 if (firewire_debug) 619 fw_printf(dev, "resetting OHCI..."); 620 i = 0; 621 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 622 if (i++ > 100) break; 623 DELAY(1000); 624 } 625 if (firewire_debug) 626 printf("done (loop=%d)\n", i); 627 628 /* Probe phy */ 629 fwohci_probe_phy(sc, dev); 630 631 /* Probe link */ 632 reg = OREAD(sc, OHCI_BUS_OPT); 633 reg2 = reg | OHCI_BUSFNC; 634 max_rec = (reg & 0x0000f000) >> 12; 635 speed = (reg & 0x00000007); 636 fw_printf(dev, "Link %s, max_rec %d bytes.\n", 637 fw_linkspeed[speed], MAXREC(max_rec)); 638 /* XXX fix max_rec */ 639 sc->fc.maxrec = sc->fc.speed + 8; 640 if (max_rec != sc->fc.maxrec) { 641 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 642 fw_printf(dev, "max_rec %d -> %d\n", 643 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 644 } 645 if (firewire_debug) 646 fw_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 647 OWRITE(sc, OHCI_BUS_OPT, reg2); 648 649 /* Initialize registers */ 650 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 651 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 652 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 653 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 654 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 655 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 656 657 /* Enable link */ 658 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 659 660 /* Force to start async RX DMA */ 661 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 662 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 663 fwohci_rx_enable(sc, &sc->arrq); 664 fwohci_rx_enable(sc, &sc->arrs); 665 666 /* Initialize async TX */ 667 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 668 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 669 670 /* AT Retries */ 671 OWRITE(sc, FWOHCI_RETRY, 672 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 673 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 674 675 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 676 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 677 sc->atrq.bottom = sc->atrq.top; 678 sc->atrs.bottom = sc->atrs.top; 679 680 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 681 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 682 db_tr->xfer = NULL; 683 } 684 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 685 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 686 db_tr->xfer = NULL; 687 } 688 689 690 /* Enable interrupts */ 691 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID 692 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 693 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 694 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 695 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT; 696 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT; 697 OWRITE(sc, FWOHCI_INTMASK, sc->intmask); 698 fwohci_set_intr(&sc->fc, 1); 699 } 700 701 int 702 fwohci_init(struct fwohci_softc *sc, device_t dev) 703 { 704 int i, mver; 705 uint32_t reg; 706 uint8_t ui[8]; 707 708 /* OHCI version */ 709 reg = OREAD(sc, OHCI_VERSION); 710 mver = (reg >> 16) & 0xff; 711 fw_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 712 mver, reg & 0xff, (reg>>24) & 1); 713 if (mver < 1 || mver > 9) { 714 fw_printf(dev, "invalid OHCI version\n"); 715 return (ENXIO); 716 } 717 718 /* Available Isochronous DMA channel probe */ 719 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 720 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 721 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 722 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 723 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 724 for (i = 0; i < 0x20; i++) 725 if ((reg & (1 << i)) == 0) 726 break; 727 sc->fc.nisodma = i; 728 fw_printf(dev, "No. of Isochronous channels is %d.\n", i); 729 if (i == 0) 730 return (ENXIO); 731 732 sc->fc.arq = &sc->arrq.xferq; 733 sc->fc.ars = &sc->arrs.xferq; 734 sc->fc.atq = &sc->atrq.xferq; 735 sc->fc.ats = &sc->atrs.xferq; 736 737 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 738 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 739 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 740 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 741 742 sc->arrq.xferq.start = NULL; 743 sc->arrs.xferq.start = NULL; 744 sc->atrq.xferq.start = fwohci_start_atq; 745 sc->atrs.xferq.start = fwohci_start_ats; 746 747 sc->arrq.xferq.buf = NULL; 748 sc->arrs.xferq.buf = NULL; 749 sc->atrq.xferq.buf = NULL; 750 sc->atrs.xferq.buf = NULL; 751 752 sc->arrq.xferq.dmach = -1; 753 sc->arrs.xferq.dmach = -1; 754 sc->atrq.xferq.dmach = -1; 755 sc->atrs.xferq.dmach = -1; 756 757 sc->arrq.ndesc = 1; 758 sc->arrs.ndesc = 1; 759 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 760 sc->atrs.ndesc = 2; 761 762 sc->arrq.ndb = NDB; 763 sc->arrs.ndb = NDB / 2; 764 sc->atrq.ndb = NDB; 765 sc->atrs.ndb = NDB / 2; 766 767 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 768 sc->fc.it[i] = &sc->it[i].xferq; 769 sc->fc.ir[i] = &sc->ir[i].xferq; 770 sc->it[i].xferq.dmach = i; 771 sc->ir[i].xferq.dmach = i; 772 sc->it[i].ndb = 0; 773 sc->ir[i].ndb = 0; 774 } 775 776 sc->fc.tcode = tinfo; 777 sc->fc.dev = dev; 778 779 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 780 &sc->crom_dma, BUS_DMA_WAITOK); 781 if(sc->fc.config_rom == NULL){ 782 fw_printf(dev, "config_rom alloc failed."); 783 return ENOMEM; 784 } 785 786 #if 0 787 bzero(&sc->fc.config_rom[0], CROMSIZE); 788 sc->fc.config_rom[1] = 0x31333934; 789 sc->fc.config_rom[2] = 0xf000a002; 790 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 791 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 792 sc->fc.config_rom[5] = 0; 793 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 794 795 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 796 #endif 797 798 /* SID recieve buffer must align 2^11 */ 799 #define OHCI_SIDSIZE (1 << 11) 800 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 801 &sc->sid_dma, BUS_DMA_WAITOK); 802 if (sc->sid_buf == NULL) { 803 fw_printf(dev, "sid_buf alloc failed."); 804 return ENOMEM; 805 } 806 807 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 808 &sc->dummy_dma, BUS_DMA_WAITOK); 809 810 if (sc->dummy_dma.v_addr == NULL) { 811 fw_printf(dev, "dummy_dma alloc failed."); 812 return ENOMEM; 813 } 814 815 fwohci_db_init(sc, &sc->arrq); 816 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 817 return ENOMEM; 818 819 fwohci_db_init(sc, &sc->arrs); 820 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 821 return ENOMEM; 822 823 fwohci_db_init(sc, &sc->atrq); 824 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 825 return ENOMEM; 826 827 fwohci_db_init(sc, &sc->atrs); 828 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 829 return ENOMEM; 830 831 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 832 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 833 for( i = 0 ; i < 8 ; i ++) 834 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 835 fw_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 836 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 837 838 sc->fc.ioctl = fwohci_ioctl; 839 sc->fc.cyctimer = fwohci_cyctimer; 840 sc->fc.set_bmr = fwohci_set_bus_manager; 841 sc->fc.ibr = fwohci_ibr; 842 sc->fc.irx_enable = fwohci_irx_enable; 843 sc->fc.irx_disable = fwohci_irx_disable; 844 845 sc->fc.itx_enable = fwohci_itxbuf_enable; 846 sc->fc.itx_disable = fwohci_itx_disable; 847 #if BYTE_ORDER == BIG_ENDIAN 848 sc->fc.irx_post = fwohci_irx_post; 849 #else 850 sc->fc.irx_post = NULL; 851 #endif 852 sc->fc.itx_post = NULL; 853 sc->fc.timeout = fwohci_timeout; 854 sc->fc.poll = fwohci_poll; 855 sc->fc.set_intr = fwohci_set_intr; 856 857 sc->intmask = sc->irstat = sc->itstat = 0; 858 859 /* Init task queue */ 860 sc->fc.taskqueue = fw_taskqueue_create_fast("fw_taskq", M_WAITOK, 861 fw_taskqueue_thread_enqueue, &sc->fc.taskqueue); 862 fw_taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq", 863 fw_get_unit(dev)); 864 FW_TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc); 865 FW_TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc); 866 FW_TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc); 867 868 fw_init(&sc->fc); 869 fwohci_reset(sc, dev); 870 FWOHCI_INIT_END; 871 872 return 0; 873 } 874 875 void 876 fwohci_timeout(void *arg) 877 { 878 struct fwohci_softc *sc; 879 880 sc = (struct fwohci_softc *)arg; 881 } 882 883 uint32_t 884 fwohci_cyctimer(struct firewire_comm *fc) 885 { 886 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 887 return(OREAD(sc, OHCI_CYCLETIMER)); 888 } 889 890 FWOHCI_DETACH() 891 { 892 int i; 893 894 FWOHCI_DETACH_START; 895 if (sc->sid_buf != NULL) 896 fwdma_free(&sc->fc, &sc->sid_dma); 897 if (sc->fc.config_rom != NULL) 898 fwdma_free(&sc->fc, &sc->crom_dma); 899 900 fwohci_db_free(&sc->arrq); 901 fwohci_db_free(&sc->arrs); 902 903 fwohci_db_free(&sc->atrq); 904 fwohci_db_free(&sc->atrs); 905 906 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 907 fwohci_db_free(&sc->it[i]); 908 fwohci_db_free(&sc->ir[i]); 909 } 910 FWOHCI_DETACH_END; 911 912 return 0; 913 } 914 915 #define LAST_DB(dbtr, db) do { \ 916 struct fwohcidb_tr *_dbtr = (dbtr); \ 917 int _cnt = _dbtr->dbcnt; \ 918 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 919 } while (0) 920 921 static void 922 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 923 { 924 struct fwohcidb_tr *db_tr; 925 struct fwohcidb *db; 926 bus_dma_segment_t *s; 927 int i; 928 929 db_tr = (struct fwohcidb_tr *)arg; 930 db = &db_tr->db[db_tr->dbcnt]; 931 if (error) { 932 if (firewire_debug || error != EFBIG) 933 printf("fwohci_execute_db: error=%d\n", error); 934 return; 935 } 936 for (i = 0; i < nseg; i++) { 937 s = &segs[i]; 938 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 939 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 940 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 941 db++; 942 db_tr->dbcnt++; 943 } 944 } 945 946 static void 947 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 948 bus_size_t size, int error) 949 { 950 fwohci_execute_db(arg, segs, nseg, error); 951 } 952 953 static void 954 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 955 { 956 int i, s; 957 int tcode, hdr_len, pl_off; 958 int fsegment = -1; 959 uint32_t off; 960 struct fw_xfer *xfer; 961 struct fw_pkt *fp; 962 struct fwohci_txpkthdr *ohcifp; 963 struct fwohcidb_tr *db_tr; 964 struct fwohcidb *db; 965 uint32_t *ld; 966 const struct tcode_info *info; 967 static int maxdesc=0; 968 969 FW_GLOCK_ASSERT(&sc->fc); 970 971 if(&sc->atrq == dbch){ 972 off = OHCI_ATQOFF; 973 }else if(&sc->atrs == dbch){ 974 off = OHCI_ATSOFF; 975 }else{ 976 return; 977 } 978 979 if (dbch->flags & FWOHCI_DBCH_FULL) 980 return; 981 982 s = splfw(); 983 fwdma_sync_multiseg_all(dbch->am, 984 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 985 db_tr = dbch->top; 986 txloop: 987 xfer = STAILQ_FIRST(&dbch->xferq.q); 988 if(xfer == NULL){ 989 goto kick; 990 } 991 #if 0 992 if(dbch->xferq.queued == 0 ){ 993 fw_printf(sc->fc.dev, "TX queue empty\n"); 994 } 995 #endif 996 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 997 db_tr->xfer = xfer; 998 xfer->flag = FWXF_START; 999 1000 fp = &xfer->send.hdr; 1001 tcode = fp->mode.common.tcode; 1002 1003 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 1004 info = &tinfo[tcode]; 1005 hdr_len = pl_off = info->hdr_len; 1006 1007 ld = &ohcifp->mode.ld[0]; 1008 ld[0] = ld[1] = ld[2] = ld[3] = 0; 1009 for( i = 0 ; i < pl_off ; i+= 4) 1010 ld[i/4] = fp->mode.ld[i/4]; 1011 1012 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 1013 if (tcode == FWTCODE_STREAM ){ 1014 hdr_len = 8; 1015 ohcifp->mode.stream.len = fp->mode.stream.len; 1016 } else if (tcode == FWTCODE_PHY) { 1017 hdr_len = 12; 1018 ld[1] = fp->mode.ld[1]; 1019 ld[2] = fp->mode.ld[2]; 1020 ohcifp->mode.common.spd = 0; 1021 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 1022 } else { 1023 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 1024 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 1025 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 1026 } 1027 db = &db_tr->db[0]; 1028 FWOHCI_DMA_WRITE(db->db.desc.cmd, 1029 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 1030 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1031 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1032 /* Specify bound timer of asy. responce */ 1033 if(&sc->atrs == dbch){ 1034 FWOHCI_DMA_WRITE(db->db.desc.res, 1035 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1036 } 1037 #if BYTE_ORDER == BIG_ENDIAN 1038 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1039 hdr_len = 12; 1040 for (i = 0; i < hdr_len/4; i ++) 1041 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1042 #endif 1043 1044 again: 1045 db_tr->dbcnt = 2; 1046 db = &db_tr->db[db_tr->dbcnt]; 1047 if (xfer->send.pay_len > 0) { 1048 int err; 1049 /* handle payload */ 1050 if (xfer->mbuf == NULL) { 1051 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1052 &xfer->send.payload[0], xfer->send.pay_len, 1053 fwohci_execute_db, db_tr, 1054 BUS_DMA_WAITOK); 1055 } else { 1056 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1057 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1058 db_tr->dma_map, xfer->mbuf, 1059 fwohci_execute_db2, db_tr, 1060 BUS_DMA_WAITOK); 1061 if (err == EFBIG) { 1062 struct mbuf *m0; 1063 1064 if (firewire_debug) 1065 fw_printf(sc->fc.dev, "EFBIG.\n"); 1066 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1067 if (m0 != NULL) { 1068 m_copydata(xfer->mbuf, 0, 1069 xfer->mbuf->m_pkthdr.len, 1070 mtod(m0, void *)); 1071 m0->m_len = m0->m_pkthdr.len = 1072 xfer->mbuf->m_pkthdr.len; 1073 m_freem(xfer->mbuf); 1074 xfer->mbuf = m0; 1075 goto again; 1076 } 1077 fw_printf(sc->fc.dev, "m_getcl failed.\n"); 1078 } 1079 } 1080 if (err) 1081 printf("dmamap_load: err=%d\n", err); 1082 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1083 BUS_DMASYNC_PREWRITE); 1084 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1085 for (i = 2; i < db_tr->dbcnt; i++) 1086 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1087 OHCI_OUTPUT_MORE); 1088 #endif 1089 } 1090 if (maxdesc < db_tr->dbcnt) { 1091 maxdesc = db_tr->dbcnt; 1092 if (firewire_debug) 1093 fw_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1094 } 1095 /* last db */ 1096 LAST_DB(db_tr, db); 1097 FWOHCI_DMA_SET(db->db.desc.cmd, 1098 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1099 FWOHCI_DMA_WRITE(db->db.desc.depend, 1100 STAILQ_NEXT(db_tr, link)->bus_addr); 1101 1102 if(fsegment == -1 ) 1103 fsegment = db_tr->dbcnt; 1104 if (dbch->pdb_tr != NULL) { 1105 LAST_DB(dbch->pdb_tr, db); 1106 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1107 } 1108 dbch->xferq.queued ++; 1109 dbch->pdb_tr = db_tr; 1110 db_tr = STAILQ_NEXT(db_tr, link); 1111 if(db_tr != dbch->bottom){ 1112 goto txloop; 1113 } else { 1114 fw_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1115 dbch->flags |= FWOHCI_DBCH_FULL; 1116 } 1117 kick: 1118 /* kick asy q */ 1119 fwdma_sync_multiseg_all(dbch->am, 1120 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1121 1122 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1123 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1124 } else { 1125 if (firewire_debug) 1126 fw_printf(sc->fc.dev, "start AT DMA status=%x\n", 1127 OREAD(sc, OHCI_DMACTL(off))); 1128 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1129 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1130 dbch->xferq.flag |= FWXFERQ_RUNNING; 1131 } 1132 CTR0(KTR_DEV, "start kick done"); 1133 CTR0(KTR_DEV, "start kick done2"); 1134 1135 dbch->top = db_tr; 1136 splx(s); 1137 return; 1138 } 1139 1140 static void 1141 fwohci_start_atq(struct firewire_comm *fc) 1142 { 1143 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1144 FW_GLOCK(&sc->fc); 1145 fwohci_start( sc, &(sc->atrq)); 1146 FW_GUNLOCK(&sc->fc); 1147 return; 1148 } 1149 1150 static void 1151 fwohci_start_ats(struct firewire_comm *fc) 1152 { 1153 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1154 FW_GLOCK(&sc->fc); 1155 fwohci_start( sc, &(sc->atrs)); 1156 FW_GUNLOCK(&sc->fc); 1157 return; 1158 } 1159 1160 void 1161 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1162 { 1163 int s, ch, err = 0; 1164 struct fwohcidb_tr *tr; 1165 struct fwohcidb *db; 1166 struct fw_xfer *xfer; 1167 uint32_t off; 1168 u_int stat, status; 1169 int packets; 1170 struct firewire_comm *fc = (struct firewire_comm *)sc; 1171 1172 if(&sc->atrq == dbch){ 1173 off = OHCI_ATQOFF; 1174 ch = ATRQ_CH; 1175 }else if(&sc->atrs == dbch){ 1176 off = OHCI_ATSOFF; 1177 ch = ATRS_CH; 1178 }else{ 1179 return; 1180 } 1181 s = splfw(); 1182 tr = dbch->bottom; 1183 packets = 0; 1184 fwdma_sync_multiseg_all(dbch->am, 1185 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1186 while(dbch->xferq.queued > 0){ 1187 LAST_DB(tr, db); 1188 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1189 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1190 if (fc->status != FWBUSINIT) 1191 /* maybe out of order?? */ 1192 goto out; 1193 } 1194 if (tr->xfer->send.pay_len > 0) { 1195 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1196 BUS_DMASYNC_POSTWRITE); 1197 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1198 } 1199 #if 1 1200 if (firewire_debug > 1) 1201 dump_db(sc, ch); 1202 #endif 1203 if(status & OHCI_CNTL_DMA_DEAD) { 1204 /* Stop DMA */ 1205 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1206 fw_printf(sc->fc.dev, "force reset AT FIFO\n"); 1207 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1208 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1209 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1210 } 1211 stat = status & FWOHCIEV_MASK; 1212 switch(stat){ 1213 case FWOHCIEV_ACKPEND: 1214 CTR0(KTR_DEV, "txd: ack pending"); 1215 /* fall through */ 1216 case FWOHCIEV_ACKCOMPL: 1217 err = 0; 1218 break; 1219 case FWOHCIEV_ACKBSA: 1220 case FWOHCIEV_ACKBSB: 1221 case FWOHCIEV_ACKBSX: 1222 fw_printf(sc->fc.dev, "txd err=%2x %s\n", stat, 1223 fwohcicode[stat]); 1224 err = EBUSY; 1225 break; 1226 case FWOHCIEV_FLUSHED: 1227 case FWOHCIEV_ACKTARD: 1228 fw_printf(sc->fc.dev, "txd err=%2x %s\n", stat, 1229 fwohcicode[stat]); 1230 err = EAGAIN; 1231 break; 1232 case FWOHCIEV_MISSACK: 1233 case FWOHCIEV_UNDRRUN: 1234 case FWOHCIEV_OVRRUN: 1235 case FWOHCIEV_DESCERR: 1236 case FWOHCIEV_DTRDERR: 1237 case FWOHCIEV_TIMEOUT: 1238 case FWOHCIEV_TCODERR: 1239 case FWOHCIEV_UNKNOWN: 1240 case FWOHCIEV_ACKDERR: 1241 case FWOHCIEV_ACKTERR: 1242 default: 1243 fw_printf(sc->fc.dev, "txd err=%2x %s\n", 1244 stat, fwohcicode[stat]); 1245 err = EINVAL; 1246 break; 1247 } 1248 if (tr->xfer != NULL) { 1249 xfer = tr->xfer; 1250 CTR0(KTR_DEV, "txd"); 1251 if (xfer->flag & FWXF_RCVD) { 1252 #if 0 1253 if (firewire_debug) 1254 printf("already rcvd\n"); 1255 #endif 1256 fw_xfer_done(xfer); 1257 } else { 1258 microtime(&xfer->tv); 1259 xfer->flag = FWXF_SENT; 1260 if (err == EBUSY) { 1261 xfer->flag = FWXF_BUSY; 1262 xfer->resp = err; 1263 xfer->recv.pay_len = 0; 1264 fw_xfer_done(xfer); 1265 } else if (stat != FWOHCIEV_ACKPEND) { 1266 if (stat != FWOHCIEV_ACKCOMPL) 1267 xfer->flag = FWXF_SENTERR; 1268 xfer->resp = err; 1269 xfer->recv.pay_len = 0; 1270 fw_xfer_done(xfer); 1271 } 1272 } 1273 /* 1274 * The watchdog timer takes care of split 1275 * transcation timeout for ACKPEND case. 1276 */ 1277 } else { 1278 printf("this shouldn't happen\n"); 1279 } 1280 FW_GLOCK(fc); 1281 dbch->xferq.queued --; 1282 FW_GUNLOCK(fc); 1283 tr->xfer = NULL; 1284 1285 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1286 packets ++; 1287 tr = STAILQ_NEXT(tr, link); 1288 dbch->bottom = tr; 1289 if (dbch->bottom == dbch->top) { 1290 /* we reaches the end of context program */ 1291 if (firewire_debug && dbch->xferq.queued > 0) 1292 printf("queued > 0\n"); 1293 break; 1294 } 1295 } 1296 out: 1297 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1298 printf("make free slot\n"); 1299 dbch->flags &= ~FWOHCI_DBCH_FULL; 1300 FW_GLOCK(fc); 1301 fwohci_start(sc, dbch); 1302 FW_GUNLOCK(fc); 1303 } 1304 fwdma_sync_multiseg_all( 1305 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1306 splx(s); 1307 } 1308 1309 static void 1310 fwohci_db_free(struct fwohci_dbch *dbch) 1311 { 1312 struct fwohcidb_tr *db_tr; 1313 int idb; 1314 1315 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1316 return; 1317 1318 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1319 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1320 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1321 db_tr->buf != NULL) { 1322 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1323 db_tr->buf, dbch->xferq.psize); 1324 db_tr->buf = NULL; 1325 } else if (db_tr->dma_map != NULL) 1326 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1327 } 1328 dbch->ndb = 0; 1329 db_tr = STAILQ_FIRST(&dbch->db_trq); 1330 fwdma_free_multiseg(dbch->am); 1331 free(db_tr, M_FW); 1332 STAILQ_INIT(&dbch->db_trq); 1333 dbch->flags &= ~FWOHCI_DBCH_INIT; 1334 seldestroy(&dbch->xferq.rsel); 1335 } 1336 1337 static void 1338 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1339 { 1340 int idb; 1341 struct fwohcidb_tr *db_tr; 1342 1343 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1344 goto out; 1345 1346 /* create dma_tag for buffers */ 1347 #define MAX_REQCOUNT 0xffff 1348 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1349 /*alignment*/ 1, /*boundary*/ 0, 1350 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1351 /*highaddr*/ BUS_SPACE_MAXADDR, 1352 /*filter*/NULL, /*filterarg*/NULL, 1353 /*maxsize*/ dbch->xferq.psize, 1354 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1355 /*maxsegsz*/ MAX_REQCOUNT, 1356 /*flags*/ 0, 1357 /*lockfunc*/busdma_lock_mutex, 1358 /*lockarg*/FW_GMTX(&sc->fc), 1359 &dbch->dmat)) 1360 return; 1361 1362 /* allocate DB entries and attach one to each DMA channels */ 1363 /* DB entry must start at 16 bytes bounary. */ 1364 STAILQ_INIT(&dbch->db_trq); 1365 db_tr = (struct fwohcidb_tr *) 1366 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1367 M_FW, M_WAITOK | M_ZERO); 1368 if(db_tr == NULL){ 1369 printf("fwohci_db_init: malloc(1) failed\n"); 1370 return; 1371 } 1372 1373 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1374 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1375 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1376 if (dbch->am == NULL) { 1377 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1378 free(db_tr, M_FW); 1379 return; 1380 } 1381 /* Attach DB to DMA ch. */ 1382 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1383 db_tr->dbcnt = 0; 1384 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1385 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1386 /* create dmamap for buffers */ 1387 /* XXX do we need 4bytes alignment tag? */ 1388 /* XXX don't alloc dma_map for AR */ 1389 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1390 printf("fw_bus_dmamap_create failed\n"); 1391 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1392 fwohci_db_free(dbch); 1393 return; 1394 } 1395 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1396 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1397 if (idb % dbch->xferq.bnpacket == 0) 1398 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1399 ].start = (void *)db_tr; 1400 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1401 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1402 ].end = (void *)db_tr; 1403 } 1404 db_tr++; 1405 } 1406 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1407 = STAILQ_FIRST(&dbch->db_trq); 1408 out: 1409 dbch->xferq.queued = 0; 1410 dbch->pdb_tr = NULL; 1411 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1412 dbch->bottom = dbch->top; 1413 dbch->flags = FWOHCI_DBCH_INIT; 1414 selinit(&dbch->xferq.rsel); 1415 } 1416 1417 static int 1418 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1419 { 1420 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1421 int sleepch; 1422 1423 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1424 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1425 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1426 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1427 /* XXX we cannot free buffers until the DMA really stops */ 1428 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1429 fwohci_db_free(&sc->it[dmach]); 1430 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1431 return 0; 1432 } 1433 1434 static int 1435 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1436 { 1437 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1438 int sleepch; 1439 1440 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1441 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1442 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1443 /* XXX we cannot free buffers until the DMA really stops */ 1444 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1445 fwohci_db_free(&sc->ir[dmach]); 1446 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1447 return 0; 1448 } 1449 1450 #if BYTE_ORDER == BIG_ENDIAN 1451 static void 1452 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1453 { 1454 qld[0] = FWOHCI_DMA_READ(qld[0]); 1455 return; 1456 } 1457 #endif 1458 1459 static int 1460 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1461 { 1462 int err = 0; 1463 int idb, z, i, dmach = 0, ldesc; 1464 uint32_t off = 0; 1465 struct fwohcidb_tr *db_tr; 1466 struct fwohcidb *db; 1467 1468 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1469 err = EINVAL; 1470 return err; 1471 } 1472 z = dbch->ndesc; 1473 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1474 if( &sc->it[dmach] == dbch){ 1475 off = OHCI_ITOFF(dmach); 1476 break; 1477 } 1478 } 1479 if(off == 0){ 1480 err = EINVAL; 1481 return err; 1482 } 1483 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1484 return err; 1485 dbch->xferq.flag |= FWXFERQ_RUNNING; 1486 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1487 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1488 } 1489 db_tr = dbch->top; 1490 for (idb = 0; idb < dbch->ndb; idb ++) { 1491 fwohci_add_tx_buf(dbch, db_tr, idb); 1492 if(STAILQ_NEXT(db_tr, link) == NULL){ 1493 break; 1494 } 1495 db = db_tr->db; 1496 ldesc = db_tr->dbcnt - 1; 1497 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1498 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1499 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1500 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1501 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1502 FWOHCI_DMA_SET( 1503 db[ldesc].db.desc.cmd, 1504 OHCI_INTERRUPT_ALWAYS); 1505 /* OHCI 1.1 and above */ 1506 FWOHCI_DMA_SET( 1507 db[0].db.desc.cmd, 1508 OHCI_INTERRUPT_ALWAYS); 1509 } 1510 } 1511 db_tr = STAILQ_NEXT(db_tr, link); 1512 } 1513 FWOHCI_DMA_CLEAR( 1514 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1515 return err; 1516 } 1517 1518 static int 1519 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1520 { 1521 int err = 0; 1522 int idb, z, i, dmach = 0, ldesc; 1523 uint32_t off = 0; 1524 struct fwohcidb_tr *db_tr; 1525 struct fwohcidb *db; 1526 1527 z = dbch->ndesc; 1528 if(&sc->arrq == dbch){ 1529 off = OHCI_ARQOFF; 1530 }else if(&sc->arrs == dbch){ 1531 off = OHCI_ARSOFF; 1532 }else{ 1533 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1534 if( &sc->ir[dmach] == dbch){ 1535 off = OHCI_IROFF(dmach); 1536 break; 1537 } 1538 } 1539 } 1540 if(off == 0){ 1541 err = EINVAL; 1542 return err; 1543 } 1544 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1545 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1546 return err; 1547 }else{ 1548 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1549 err = EBUSY; 1550 return err; 1551 } 1552 } 1553 dbch->xferq.flag |= FWXFERQ_RUNNING; 1554 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1555 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1556 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1557 } 1558 db_tr = dbch->top; 1559 if (db_tr->dbcnt != 0) 1560 goto run; 1561 for (idb = 0; idb < dbch->ndb; idb ++) { 1562 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1563 if (STAILQ_NEXT(db_tr, link) == NULL) 1564 break; 1565 db = db_tr->db; 1566 ldesc = db_tr->dbcnt - 1; 1567 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1568 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1569 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1570 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1571 FWOHCI_DMA_SET( 1572 db[ldesc].db.desc.cmd, 1573 OHCI_INTERRUPT_ALWAYS); 1574 FWOHCI_DMA_CLEAR( 1575 db[ldesc].db.desc.depend, 1576 0xf); 1577 } 1578 } 1579 db_tr = STAILQ_NEXT(db_tr, link); 1580 } 1581 FWOHCI_DMA_CLEAR( 1582 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1583 dbch->buf_offset = 0; 1584 run: 1585 fwdma_sync_multiseg_all(dbch->am, 1586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1587 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1588 return err; 1589 }else{ 1590 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1591 } 1592 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1593 return err; 1594 } 1595 1596 static int 1597 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1598 { 1599 int sec, cycle, cycle_match; 1600 1601 cycle = cycle_now & 0x1fff; 1602 sec = cycle_now >> 13; 1603 #define CYCLE_MOD 0x10 1604 #if 1 1605 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1606 #else 1607 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1608 #endif 1609 cycle = cycle + CYCLE_DELAY; 1610 if (cycle >= 8000) { 1611 sec ++; 1612 cycle -= 8000; 1613 } 1614 cycle = roundup2(cycle, CYCLE_MOD); 1615 if (cycle >= 8000) { 1616 sec ++; 1617 if (cycle == 8000) 1618 cycle = 0; 1619 else 1620 cycle = CYCLE_MOD; 1621 } 1622 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1623 1624 return(cycle_match); 1625 } 1626 1627 static int 1628 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1629 { 1630 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1631 int err = 0; 1632 unsigned short tag, ich; 1633 struct fwohci_dbch *dbch; 1634 int cycle_match, cycle_now, s, ldesc; 1635 uint32_t stat; 1636 struct fw_bulkxfer *first, *chunk, *prev; 1637 struct fw_xferq *it; 1638 1639 dbch = &sc->it[dmach]; 1640 it = &dbch->xferq; 1641 1642 tag = (it->flag >> 6) & 3; 1643 ich = it->flag & 0x3f; 1644 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1645 dbch->ndb = it->bnpacket * it->bnchunk; 1646 dbch->ndesc = 3; 1647 fwohci_db_init(sc, dbch); 1648 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1649 return ENOMEM; 1650 1651 err = fwohci_tx_enable(sc, dbch); 1652 } 1653 if(err) 1654 return err; 1655 1656 ldesc = dbch->ndesc - 1; 1657 s = splfw(); 1658 FW_GLOCK(fc); 1659 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1660 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1661 struct fwohcidb *db; 1662 1663 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1664 BUS_DMASYNC_PREWRITE); 1665 fwohci_txbufdb(sc, dmach, chunk); 1666 if (prev != NULL) { 1667 db = ((struct fwohcidb_tr *)(prev->end))->db; 1668 #if 0 /* XXX necessary? */ 1669 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1670 OHCI_BRANCH_ALWAYS); 1671 #endif 1672 #if 0 /* if bulkxfer->npacket changes */ 1673 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1674 ((struct fwohcidb_tr *) 1675 (chunk->start))->bus_addr | dbch->ndesc; 1676 #else 1677 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1678 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1679 #endif 1680 } 1681 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1682 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1683 prev = chunk; 1684 } 1685 FW_GUNLOCK(fc); 1686 fwdma_sync_multiseg_all(dbch->am, 1687 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1688 splx(s); 1689 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1690 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1691 printf("stat 0x%x\n", stat); 1692 1693 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1694 return 0; 1695 1696 #if 0 1697 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1698 #endif 1699 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1700 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1701 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1702 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1703 1704 first = STAILQ_FIRST(&it->stdma); 1705 OWRITE(sc, OHCI_ITCMD(dmach), 1706 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1707 if (firewire_debug > 1) { 1708 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1709 #if 1 1710 dump_dma(sc, ITX_CH + dmach); 1711 #endif 1712 } 1713 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1714 #if 1 1715 /* Don't start until all chunks are buffered */ 1716 if (STAILQ_FIRST(&it->stfree) != NULL) 1717 goto out; 1718 #endif 1719 #if 1 1720 /* Clear cycle match counter bits */ 1721 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1722 1723 /* 2bit second + 13bit cycle */ 1724 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1725 cycle_match = fwohci_next_cycle(fc, cycle_now); 1726 1727 OWRITE(sc, OHCI_ITCTL(dmach), 1728 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1729 | OHCI_CNTL_DMA_RUN); 1730 #else 1731 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1732 #endif 1733 if (firewire_debug > 1) { 1734 printf("cycle_match: 0x%04x->0x%04x\n", 1735 cycle_now, cycle_match); 1736 dump_dma(sc, ITX_CH + dmach); 1737 dump_db(sc, ITX_CH + dmach); 1738 } 1739 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1740 fw_printf(sc->fc.dev, "IT DMA underrun (0x%08x)\n", stat); 1741 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1742 } 1743 out: 1744 return err; 1745 } 1746 1747 static int 1748 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1749 { 1750 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1751 int err = 0, s, ldesc; 1752 unsigned short tag, ich; 1753 uint32_t stat; 1754 struct fwohci_dbch *dbch; 1755 struct fwohcidb_tr *db_tr; 1756 struct fw_bulkxfer *first, *prev, *chunk; 1757 struct fw_xferq *ir; 1758 1759 dbch = &sc->ir[dmach]; 1760 ir = &dbch->xferq; 1761 1762 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1763 tag = (ir->flag >> 6) & 3; 1764 ich = ir->flag & 0x3f; 1765 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1766 1767 ir->queued = 0; 1768 dbch->ndb = ir->bnpacket * ir->bnchunk; 1769 dbch->ndesc = 2; 1770 fwohci_db_init(sc, dbch); 1771 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1772 return ENOMEM; 1773 err = fwohci_rx_enable(sc, dbch); 1774 } 1775 if(err) 1776 return err; 1777 1778 first = STAILQ_FIRST(&ir->stfree); 1779 if (first == NULL) { 1780 fw_printf(fc->dev, "IR DMA no free chunk\n"); 1781 return 0; 1782 } 1783 1784 ldesc = dbch->ndesc - 1; 1785 s = splfw(); 1786 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1787 FW_GLOCK(fc); 1788 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1789 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1790 struct fwohcidb *db; 1791 1792 #if 1 /* XXX for if_fwe */ 1793 if (chunk->mbuf != NULL) { 1794 db_tr = (struct fwohcidb_tr *)(chunk->start); 1795 db_tr->dbcnt = 1; 1796 err = fw_bus_dmamap_load_mbuf( 1797 dbch->dmat, db_tr->dma_map, 1798 chunk->mbuf, fwohci_execute_db2, db_tr, 1799 BUS_DMA_WAITOK); 1800 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1801 OHCI_UPDATE | OHCI_INPUT_LAST | 1802 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1803 } 1804 #endif 1805 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1806 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1807 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1808 if (prev != NULL) { 1809 db = ((struct fwohcidb_tr *)(prev->end))->db; 1810 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1811 } 1812 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1813 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1814 prev = chunk; 1815 } 1816 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1817 FW_GUNLOCK(fc); 1818 fwdma_sync_multiseg_all(dbch->am, 1819 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1820 splx(s); 1821 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1822 if (stat & OHCI_CNTL_DMA_ACTIVE) 1823 return 0; 1824 if (stat & OHCI_CNTL_DMA_RUN) { 1825 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1826 fw_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1827 } 1828 1829 if (firewire_debug) 1830 printf("start IR DMA 0x%x\n", stat); 1831 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1832 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1833 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1834 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1835 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1836 OWRITE(sc, OHCI_IRCMD(dmach), 1837 ((struct fwohcidb_tr *)(first->start))->bus_addr 1838 | dbch->ndesc); 1839 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1840 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1841 #if 0 1842 dump_db(sc, IRX_CH + dmach); 1843 #endif 1844 return err; 1845 } 1846 1847 int 1848 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1849 { 1850 u_int i; 1851 1852 /* Now stopping all DMA channel */ 1853 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1854 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1855 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1856 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1857 1858 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1859 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1860 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1861 } 1862 1863 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1864 fw_drain_txq(&sc->fc); 1865 1866 #if 0 /* Let dcons(4) be accessed */ 1867 /* Stop interrupt */ 1868 OWRITE(sc, FWOHCI_INTMASKCLR, 1869 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1870 | OHCI_INT_PHY_INT 1871 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1872 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1873 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1874 | OHCI_INT_PHY_BUS_R); 1875 1876 /* FLUSH FIFO and reset Transmitter/Reciever */ 1877 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1878 #endif 1879 1880 /* XXX Link down? Bus reset? */ 1881 return 0; 1882 } 1883 1884 int 1885 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1886 { 1887 int i; 1888 struct fw_xferq *ir; 1889 struct fw_bulkxfer *chunk; 1890 1891 fwohci_reset(sc, dev); 1892 /* XXX resume isochronous receive automatically. (how about TX?) */ 1893 for(i = 0; i < sc->fc.nisodma; i ++) { 1894 ir = &sc->ir[i].xferq; 1895 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1896 fw_printf(sc->fc.dev, 1897 "resume iso receive ch: %d\n", i); 1898 ir->flag &= ~FWXFERQ_RUNNING; 1899 /* requeue stdma to stfree */ 1900 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1901 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1902 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1903 } 1904 sc->fc.irx_enable(&sc->fc, i); 1905 } 1906 } 1907 1908 #if defined(__FreeBSD__) 1909 bus_generic_resume(dev); 1910 #elif defined(__NetBSD__) 1911 { 1912 extern int firewire_resume(struct firewire_comm *); 1913 firewire_resume(&sc->fc); 1914 } 1915 #endif 1916 sc->fc.ibr(&sc->fc); 1917 return 0; 1918 } 1919 1920 #ifdef OHCI_DEBUG 1921 static void 1922 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat) 1923 { 1924 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1925 fw_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1926 stat & OHCI_INT_EN ? "DMA_EN ":"", 1927 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1928 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1929 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1930 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1931 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1932 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1933 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1934 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1935 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1936 stat & OHCI_INT_PHY_SID ? "SID ":"", 1937 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1938 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1939 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1940 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1941 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1942 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1943 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1944 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1945 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1946 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1947 stat, OREAD(sc, FWOHCI_INTMASK) 1948 ); 1949 } 1950 #endif 1951 static void 1952 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count) 1953 { 1954 struct firewire_comm *fc = (struct firewire_comm *)sc; 1955 uint32_t node_id, plen; 1956 1957 CTR0(KTR_DEV, "fwohci_intr_core"); 1958 1959 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) { 1960 fc->status = FWBUSRESET; 1961 /* Disable bus reset interrupt until sid recv. */ 1962 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1963 1964 fw_printf(fc->dev, "BUS reset\n"); 1965 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1966 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1967 1968 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1969 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1970 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1971 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1972 1973 if (!kdb_active) 1974 fw_taskqueue_enqueue(sc->fc.taskqueue, 1975 &sc->fwohci_task_busreset); 1976 } 1977 if (stat & OHCI_INT_PHY_SID) { 1978 /* Enable bus reset interrupt */ 1979 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1980 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1981 1982 /* Allow async. request to us */ 1983 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1984 if (firewire_phydma_enable) { 1985 /* allow from all nodes */ 1986 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1987 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1988 /* 0 to 4GB regison */ 1989 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1990 } 1991 /* Set ATRetries register */ 1992 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1993 1994 /* 1995 * Checking whether the node is root or not. If root, turn on 1996 * cycle master. 1997 */ 1998 node_id = OREAD(sc, FWOHCI_NODEID); 1999 plen = OREAD(sc, OHCI_SID_CNT); 2000 2001 fc->nodeid = node_id & 0x3f; 2002 fw_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2003 node_id, (plen >> 16) & 0xff); 2004 if (!(node_id & OHCI_NODE_VALID)) { 2005 printf("Bus reset failure\n"); 2006 goto sidout; 2007 } 2008 2009 /* cycle timer */ 2010 sc->cycle_lost = 0; 2011 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2012 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2013 printf("CYCLEMASTER mode\n"); 2014 OWRITE(sc, OHCI_LNKCTL, 2015 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2016 } else { 2017 printf("non CYCLEMASTER mode\n"); 2018 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2019 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2020 } 2021 2022 fc->status = FWBUSINIT; 2023 2024 if (!kdb_active) 2025 fw_taskqueue_enqueue(sc->fc.taskqueue, 2026 &sc->fwohci_task_sid); 2027 } 2028 sidout: 2029 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active)) 2030 fw_taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma); 2031 2032 CTR0(KTR_DEV, "fwohci_intr_core done"); 2033 } 2034 2035 static void 2036 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count) 2037 { 2038 uint32_t irstat, itstat; 2039 u_int i; 2040 struct firewire_comm *fc = (struct firewire_comm *)sc; 2041 2042 CTR0(KTR_DEV, "fwohci_intr_dma"); 2043 if (stat & OHCI_INT_DMA_IR) { 2044 irstat = fw_atomic_readandclear_int(&sc->irstat); 2045 for(i = 0; i < fc->nisodma ; i++){ 2046 struct fwohci_dbch *dbch; 2047 2048 if((irstat & (1 << i)) != 0){ 2049 dbch = &sc->ir[i]; 2050 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 2051 fw_printf(sc->fc.dev, 2052 "dma(%d) not active\n", i); 2053 continue; 2054 } 2055 fwohci_rbuf_update(sc, i); 2056 } 2057 } 2058 } 2059 if (stat & OHCI_INT_DMA_IT) { 2060 itstat = fw_atomic_readandclear_int(&sc->itstat); 2061 for(i = 0; i < fc->nisodma ; i++){ 2062 if((itstat & (1 << i)) != 0){ 2063 fwohci_tbuf_update(sc, i); 2064 } 2065 } 2066 } 2067 if (stat & OHCI_INT_DMA_PRRS) { 2068 #if 0 2069 dump_dma(sc, ARRS_CH); 2070 dump_db(sc, ARRS_CH); 2071 #endif 2072 fwohci_arcv(sc, &sc->arrs, count); 2073 } 2074 if (stat & OHCI_INT_DMA_PRRQ) { 2075 #if 0 2076 dump_dma(sc, ARRQ_CH); 2077 dump_db(sc, ARRQ_CH); 2078 #endif 2079 fwohci_arcv(sc, &sc->arrq, count); 2080 } 2081 if (stat & OHCI_INT_CYC_LOST) { 2082 if (sc->cycle_lost >= 0) 2083 sc->cycle_lost ++; 2084 if (sc->cycle_lost > 10) { 2085 sc->cycle_lost = -1; 2086 #if 0 2087 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2088 #endif 2089 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2090 fw_printf(fc->dev, "too many cycle lost, " 2091 "no cycle master presents?\n"); 2092 } 2093 } 2094 if (stat & OHCI_INT_DMA_ATRQ) { 2095 fwohci_txd(sc, &(sc->atrq)); 2096 } 2097 if (stat & OHCI_INT_DMA_ATRS) { 2098 fwohci_txd(sc, &(sc->atrs)); 2099 } 2100 if (stat & OHCI_INT_PW_ERR) { 2101 fw_printf(fc->dev, "posted write error\n"); 2102 } 2103 if (stat & OHCI_INT_ERR) { 2104 fw_printf(fc->dev, "unrecoverable error\n"); 2105 } 2106 if (stat & OHCI_INT_PHY_INT) { 2107 fw_printf(fc->dev, "phy int\n"); 2108 } 2109 2110 CTR0(KTR_DEV, "fwohci_intr_dma done"); 2111 return; 2112 } 2113 2114 static void 2115 fwohci_task_busreset(void *arg, int pending) 2116 { 2117 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2118 2119 fw_busreset(&sc->fc, FWBUSRESET); 2120 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2121 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2122 } 2123 2124 static void 2125 fwohci_task_sid(void *arg, int pending) 2126 { 2127 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2128 struct firewire_comm *fc = &sc->fc; 2129 uint32_t *buf; 2130 int i, plen; 2131 2132 plen = OREAD(sc, OHCI_SID_CNT); 2133 2134 if (plen & OHCI_SID_ERR) { 2135 fw_printf(fc->dev, "SID Error\n"); 2136 return; 2137 } 2138 plen &= OHCI_SID_CNT_MASK; 2139 if (plen < 4 || plen > OHCI_SIDSIZE) { 2140 fw_printf(fc->dev, "invalid SID len = %d\n", plen); 2141 return; 2142 } 2143 plen -= 4; /* chop control info */ 2144 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2145 if (buf == NULL) { 2146 fw_printf(fc->dev, "malloc failed\n"); 2147 return; 2148 } 2149 for (i = 0; i < plen / 4; i ++) 2150 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2151 #if 1 /* XXX needed?? */ 2152 /* pending all pre-bus_reset packets */ 2153 fwohci_txd(sc, &sc->atrq); 2154 fwohci_txd(sc, &sc->atrs); 2155 fwohci_arcv(sc, &sc->arrs, -1); 2156 fwohci_arcv(sc, &sc->arrq, -1); 2157 fw_drain_txq(fc); 2158 #endif 2159 fw_sidrcv(fc, buf, plen); 2160 free(buf, M_FW); 2161 } 2162 2163 static void 2164 fwohci_task_dma(void *arg, int pending) 2165 { 2166 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2167 uint32_t stat; 2168 2169 again: 2170 stat = fw_atomic_readandclear_int(&sc->intstat); 2171 if (stat) 2172 fwohci_intr_dma(sc, stat, -1); 2173 else 2174 return; 2175 goto again; 2176 } 2177 2178 static int 2179 fwohci_check_stat(struct fwohci_softc *sc) 2180 { 2181 uint32_t stat, irstat, itstat; 2182 2183 stat = OREAD(sc, FWOHCI_INTSTAT); 2184 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2185 if (stat == 0xffffffff) { 2186 fw_printf(sc->fc.dev, 2187 "device physically ejected?\n"); 2188 return (FILTER_STRAY); 2189 } 2190 if (stat) 2191 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R); 2192 2193 stat &= sc->intmask; 2194 if (stat == 0) 2195 return (FILTER_STRAY); 2196 2197 fw_atomic_set_int(&sc->intstat, stat); 2198 if (stat & OHCI_INT_DMA_IR) { 2199 irstat = OREAD(sc, OHCI_IR_STAT); 2200 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2201 fw_atomic_set_int(&sc->irstat, irstat); 2202 } 2203 if (stat & OHCI_INT_DMA_IT) { 2204 itstat = OREAD(sc, OHCI_IT_STAT); 2205 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2206 fw_atomic_set_int(&sc->itstat, itstat); 2207 } 2208 2209 fwohci_intr_core(sc, stat, -1); 2210 return (FILTER_HANDLED); 2211 } 2212 2213 int 2214 fwohci_filt(void *arg) 2215 { 2216 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2217 2218 if (!(sc->intmask & OHCI_INT_EN)) { 2219 /* polling mode */ 2220 return (FILTER_STRAY); 2221 } 2222 return (fwohci_check_stat(sc)); 2223 } 2224 2225 void 2226 fwohci_intr(void *arg) 2227 { 2228 2229 fwohci_filt(arg); 2230 CTR0(KTR_DEV, "fwohci_intr end"); 2231 } 2232 2233 void 2234 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2235 { 2236 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2237 2238 fwohci_check_stat(sc); 2239 } 2240 2241 static void 2242 fwohci_set_intr(struct firewire_comm *fc, int enable) 2243 { 2244 struct fwohci_softc *sc; 2245 2246 sc = (struct fwohci_softc *)fc; 2247 if (firewire_debug) 2248 fw_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2249 if (enable) { 2250 sc->intmask |= OHCI_INT_EN; 2251 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2252 } else { 2253 sc->intmask &= ~OHCI_INT_EN; 2254 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2255 } 2256 } 2257 2258 static void 2259 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2260 { 2261 struct firewire_comm *fc = &sc->fc; 2262 struct fwohcidb *db; 2263 struct fw_bulkxfer *chunk; 2264 struct fw_xferq *it; 2265 uint32_t stat, count; 2266 int s, w=0, ldesc; 2267 2268 it = fc->it[dmach]; 2269 ldesc = sc->it[dmach].ndesc - 1; 2270 s = splfw(); /* unnecessary ? */ 2271 FW_GLOCK(fc); 2272 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2273 if (firewire_debug) 2274 dump_db(sc, ITX_CH + dmach); 2275 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2276 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2277 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2278 >> OHCI_STATUS_SHIFT; 2279 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2280 /* timestamp */ 2281 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2282 & OHCI_COUNT_MASK; 2283 if (stat == 0) 2284 break; 2285 STAILQ_REMOVE_HEAD(&it->stdma, link); 2286 switch (stat & FWOHCIEV_MASK){ 2287 case FWOHCIEV_ACKCOMPL: 2288 #if 0 2289 fw_printf(fc->dev, "0x%08x\n", count); 2290 #endif 2291 break; 2292 default: 2293 fw_printf(fc->dev, 2294 "Isochronous transmit err %02x(%s)\n", 2295 stat, fwohcicode[stat & 0x1f]); 2296 } 2297 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2298 w++; 2299 } 2300 FW_GUNLOCK(fc); 2301 splx(s); 2302 if (w) 2303 wakeup(it); 2304 } 2305 2306 static void 2307 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2308 { 2309 struct firewire_comm *fc = &sc->fc; 2310 struct fwohcidb_tr *db_tr; 2311 struct fw_bulkxfer *chunk; 2312 struct fw_xferq *ir; 2313 uint32_t stat; 2314 int s, w = 0, ldesc; 2315 2316 ir = fc->ir[dmach]; 2317 ldesc = sc->ir[dmach].ndesc - 1; 2318 2319 #if 0 2320 dump_db(sc, dmach); 2321 #endif 2322 s = splfw(); 2323 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2324 FW_GLOCK(fc); 2325 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2326 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2327 db_tr = (struct fwohcidb_tr *)chunk->end; 2328 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2329 >> OHCI_STATUS_SHIFT; 2330 if (stat == 0) 2331 break; 2332 2333 if (chunk->mbuf != NULL) { 2334 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2335 BUS_DMASYNC_POSTREAD); 2336 fw_bus_dmamap_unload( 2337 sc->ir[dmach].dmat, db_tr->dma_map); 2338 } else if (ir->buf != NULL) { 2339 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2340 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2341 } else { 2342 /* XXX */ 2343 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2344 } 2345 2346 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2347 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2348 switch (stat & FWOHCIEV_MASK) { 2349 case FWOHCIEV_ACKCOMPL: 2350 chunk->resp = 0; 2351 break; 2352 default: 2353 chunk->resp = EINVAL; 2354 fw_printf(fc->dev, "Isochronous receive err %02x(%s)\n", 2355 stat, fwohcicode[stat & 0x1f]); 2356 } 2357 w++; 2358 } 2359 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2360 FW_GUNLOCK(fc); 2361 splx(s); 2362 if (w == 0) 2363 return; 2364 if (ir->flag & FWXFERQ_HANDLER) 2365 ir->hand(ir); 2366 else 2367 wakeup(ir); 2368 } 2369 2370 void 2371 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2372 { 2373 uint32_t off, cntl, stat, cmd, match; 2374 2375 if(ch == 0){ 2376 off = OHCI_ATQOFF; 2377 }else if(ch == 1){ 2378 off = OHCI_ATSOFF; 2379 }else if(ch == 2){ 2380 off = OHCI_ARQOFF; 2381 }else if(ch == 3){ 2382 off = OHCI_ARSOFF; 2383 }else if(ch < IRX_CH){ 2384 off = OHCI_ITCTL(ch - ITX_CH); 2385 }else{ 2386 off = OHCI_IRCTL(ch - IRX_CH); 2387 } 2388 cntl = stat = OREAD(sc, off); 2389 cmd = OREAD(sc, off + 0xc); 2390 match = OREAD(sc, off + 0x10); 2391 2392 fw_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2393 ch, 2394 cntl, 2395 cmd, 2396 match); 2397 stat &= 0xffff ; 2398 if (stat) { 2399 fw_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2400 ch, 2401 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2402 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2403 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2404 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2405 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2406 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2407 fwohcicode[stat & 0x1f], 2408 stat & 0x1f 2409 ); 2410 }else{ 2411 fw_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2412 } 2413 } 2414 2415 void 2416 dump_db(struct fwohci_softc *sc, uint32_t ch) 2417 { 2418 struct fwohci_dbch *dbch; 2419 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2420 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2421 int idb, jdb; 2422 uint32_t cmd, off; 2423 if(ch == 0){ 2424 off = OHCI_ATQOFF; 2425 dbch = &sc->atrq; 2426 }else if(ch == 1){ 2427 off = OHCI_ATSOFF; 2428 dbch = &sc->atrs; 2429 }else if(ch == 2){ 2430 off = OHCI_ARQOFF; 2431 dbch = &sc->arrq; 2432 }else if(ch == 3){ 2433 off = OHCI_ARSOFF; 2434 dbch = &sc->arrs; 2435 }else if(ch < IRX_CH){ 2436 off = OHCI_ITCTL(ch - ITX_CH); 2437 dbch = &sc->it[ch - ITX_CH]; 2438 }else { 2439 off = OHCI_IRCTL(ch - IRX_CH); 2440 dbch = &sc->ir[ch - IRX_CH]; 2441 } 2442 cmd = OREAD(sc, off + 0xc); 2443 2444 if( dbch->ndb == 0 ){ 2445 fw_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2446 return; 2447 } 2448 pp = dbch->top; 2449 prev = pp->db; 2450 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2451 cp = STAILQ_NEXT(pp, link); 2452 if(cp == NULL){ 2453 curr = NULL; 2454 goto outdb; 2455 } 2456 np = STAILQ_NEXT(cp, link); 2457 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2458 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2459 curr = cp->db; 2460 if(np != NULL){ 2461 next = np->db; 2462 }else{ 2463 next = NULL; 2464 } 2465 goto outdb; 2466 } 2467 } 2468 pp = STAILQ_NEXT(pp, link); 2469 if(pp == NULL){ 2470 curr = NULL; 2471 goto outdb; 2472 } 2473 prev = pp->db; 2474 } 2475 outdb: 2476 if( curr != NULL){ 2477 #if 0 2478 printf("Prev DB %d\n", ch); 2479 print_db(pp, prev, ch, dbch->ndesc); 2480 #endif 2481 printf("Current DB %d\n", ch); 2482 print_db(cp, curr, ch, dbch->ndesc); 2483 #if 0 2484 printf("Next DB %d\n", ch); 2485 print_db(np, next, ch, dbch->ndesc); 2486 #endif 2487 }else{ 2488 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2489 } 2490 return; 2491 } 2492 2493 void 2494 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2495 uint32_t ch, uint32_t hogemax) 2496 { 2497 fwohcireg_t stat; 2498 int i, key; 2499 uint32_t cmd, res; 2500 2501 if(db == NULL){ 2502 printf("No Descriptor is found\n"); 2503 return; 2504 } 2505 2506 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2507 ch, 2508 "Current", 2509 "OP ", 2510 "KEY", 2511 "INT", 2512 "BR ", 2513 "len", 2514 "Addr", 2515 "Depend", 2516 "Stat", 2517 "Cnt"); 2518 for( i = 0 ; i <= hogemax ; i ++){ 2519 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2520 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2521 key = cmd & OHCI_KEY_MASK; 2522 stat = res >> OHCI_STATUS_SHIFT; 2523 #if defined(__DragonFly__) || \ 2524 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2525 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2526 db_tr->bus_addr, 2527 #else 2528 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2529 (uintmax_t)db_tr->bus_addr, 2530 #endif 2531 dbcode[(cmd >> 28) & 0xf], 2532 dbkey[(cmd >> 24) & 0x7], 2533 dbcond[(cmd >> 20) & 0x3], 2534 dbcond[(cmd >> 18) & 0x3], 2535 cmd & OHCI_COUNT_MASK, 2536 FWOHCI_DMA_READ(db[i].db.desc.addr), 2537 FWOHCI_DMA_READ(db[i].db.desc.depend), 2538 stat, 2539 res & OHCI_COUNT_MASK); 2540 if(stat & 0xff00){ 2541 printf(" %s%s%s%s%s%s %s(%x)\n", 2542 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2543 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2544 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2545 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2546 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2547 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2548 fwohcicode[stat & 0x1f], 2549 stat & 0x1f 2550 ); 2551 }else{ 2552 printf(" Nostat\n"); 2553 } 2554 if(key == OHCI_KEY_ST2 ){ 2555 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2556 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2557 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2558 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2559 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2560 } 2561 if(key == OHCI_KEY_DEVICE){ 2562 return; 2563 } 2564 if((cmd & OHCI_BRANCH_MASK) 2565 == OHCI_BRANCH_ALWAYS){ 2566 return; 2567 } 2568 if((cmd & OHCI_CMD_MASK) 2569 == OHCI_OUTPUT_LAST){ 2570 return; 2571 } 2572 if((cmd & OHCI_CMD_MASK) 2573 == OHCI_INPUT_LAST){ 2574 return; 2575 } 2576 if(key == OHCI_KEY_ST2 ){ 2577 i++; 2578 } 2579 } 2580 return; 2581 } 2582 2583 void 2584 fwohci_ibr(struct firewire_comm *fc) 2585 { 2586 struct fwohci_softc *sc; 2587 uint32_t fun; 2588 2589 fw_printf(fc->dev, "Initiate bus reset\n"); 2590 sc = (struct fwohci_softc *)fc; 2591 2592 /* 2593 * Make sure our cached values from the config rom are 2594 * initialised. 2595 */ 2596 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2597 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2598 2599 /* 2600 * Set root hold-off bit so that non cyclemaster capable node 2601 * shouldn't became the root node. 2602 */ 2603 #if 1 2604 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2605 fun |= FW_PHY_IBR | FW_PHY_RHB; 2606 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2607 #else /* Short bus reset */ 2608 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2609 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2610 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2611 #endif 2612 } 2613 2614 void 2615 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2616 { 2617 struct fwohcidb_tr *db_tr, *fdb_tr; 2618 struct fwohci_dbch *dbch; 2619 struct fwohcidb *db; 2620 struct fw_pkt *fp; 2621 struct fwohci_txpkthdr *ohcifp; 2622 unsigned short chtag; 2623 int idb; 2624 2625 FW_GLOCK_ASSERT(&sc->fc); 2626 2627 dbch = &sc->it[dmach]; 2628 chtag = sc->it[dmach].xferq.flag & 0xff; 2629 2630 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2631 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2632 /* 2633 fw_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2634 */ 2635 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2636 db = db_tr->db; 2637 fp = (struct fw_pkt *)db_tr->buf; 2638 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2639 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2640 ohcifp->mode.common.spd = 0 & 0x7; 2641 ohcifp->mode.stream.len = fp->mode.stream.len; 2642 ohcifp->mode.stream.chtag = chtag; 2643 ohcifp->mode.stream.tcode = 0xa; 2644 #if BYTE_ORDER == BIG_ENDIAN 2645 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2646 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2647 #endif 2648 2649 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2650 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2651 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2652 #if 0 /* if bulkxfer->npackets changes */ 2653 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2654 | OHCI_UPDATE 2655 | OHCI_BRANCH_ALWAYS; 2656 db[0].db.desc.depend = 2657 = db[dbch->ndesc - 1].db.desc.depend 2658 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2659 #else 2660 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2661 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2662 #endif 2663 bulkxfer->end = (void *)db_tr; 2664 db_tr = STAILQ_NEXT(db_tr, link); 2665 } 2666 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2667 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2668 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2669 #if 0 /* if bulkxfer->npackets changes */ 2670 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2671 /* OHCI 1.1 and above */ 2672 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2673 #endif 2674 /* 2675 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2676 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2677 fw_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2678 */ 2679 return; 2680 } 2681 2682 static int 2683 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2684 int poffset) 2685 { 2686 struct fwohcidb *db = db_tr->db; 2687 struct fw_xferq *it; 2688 int err = 0; 2689 2690 it = &dbch->xferq; 2691 if(it->buf == 0){ 2692 err = EINVAL; 2693 return err; 2694 } 2695 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2696 db_tr->dbcnt = 3; 2697 2698 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2699 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2700 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2701 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2702 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2703 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2704 2705 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2706 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2707 #if 1 2708 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2709 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2710 #endif 2711 return 0; 2712 } 2713 2714 int 2715 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2716 int poffset, struct fwdma_alloc *dummy_dma) 2717 { 2718 struct fwohcidb *db = db_tr->db; 2719 struct fw_xferq *ir; 2720 int i, ldesc; 2721 bus_addr_t dbuf[2]; 2722 int dsiz[2]; 2723 2724 ir = &dbch->xferq; 2725 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2726 if (db_tr->buf == NULL) 2727 db_tr->buf = fwdma_malloc_size( 2728 dbch->dmat, &db_tr->dma_map, 2729 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2730 if (db_tr->buf == NULL) 2731 return(ENOMEM); 2732 db_tr->dbcnt = 1; 2733 dsiz[0] = ir->psize; 2734 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2735 BUS_DMASYNC_PREREAD); 2736 } else { 2737 db_tr->dbcnt = 0; 2738 if (dummy_dma != NULL) { 2739 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2740 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2741 } 2742 dsiz[db_tr->dbcnt] = ir->psize; 2743 if (ir->buf != NULL) { 2744 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2745 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2746 } 2747 db_tr->dbcnt++; 2748 } 2749 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2750 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2751 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2752 if (ir->flag & FWXFERQ_STREAM) { 2753 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2754 } 2755 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2756 } 2757 ldesc = db_tr->dbcnt - 1; 2758 if (ir->flag & FWXFERQ_STREAM) { 2759 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2760 } 2761 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2762 return 0; 2763 } 2764 2765 2766 static int 2767 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2768 { 2769 struct fw_pkt *fp0; 2770 uint32_t ld0; 2771 int slen, hlen; 2772 #if BYTE_ORDER == BIG_ENDIAN 2773 int i; 2774 #endif 2775 2776 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2777 #if 0 2778 printf("ld0: x%08x\n", ld0); 2779 #endif 2780 fp0 = (struct fw_pkt *)&ld0; 2781 /* determine length to swap */ 2782 switch (fp0->mode.common.tcode) { 2783 case FWTCODE_WRES: 2784 CTR0(KTR_DEV, "WRES"); 2785 case FWTCODE_RREQQ: 2786 case FWTCODE_WREQQ: 2787 case FWTCODE_RRESQ: 2788 case FWOHCITCODE_PHY: 2789 slen = 12; 2790 break; 2791 case FWTCODE_RREQB: 2792 case FWTCODE_WREQB: 2793 case FWTCODE_LREQ: 2794 case FWTCODE_RRESB: 2795 case FWTCODE_LRES: 2796 slen = 16; 2797 break; 2798 default: 2799 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2800 return(0); 2801 } 2802 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2803 if (hlen > len) { 2804 if (firewire_debug) 2805 printf("splitted header\n"); 2806 return(-hlen); 2807 } 2808 #if BYTE_ORDER == BIG_ENDIAN 2809 for(i = 0; i < slen/4; i ++) 2810 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2811 #endif 2812 return(hlen); 2813 } 2814 2815 static int 2816 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2817 { 2818 const struct tcode_info *info; 2819 int r; 2820 2821 info = &tinfo[fp->mode.common.tcode]; 2822 r = info->hdr_len + sizeof(uint32_t); 2823 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2824 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2825 2826 if (r == sizeof(uint32_t)) { 2827 /* XXX */ 2828 fw_printf(sc->fc.dev, "Unknown tcode %d\n", 2829 fp->mode.common.tcode); 2830 return (-1); 2831 } 2832 2833 if (r > dbch->xferq.psize) { 2834 fw_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2835 return (-1); 2836 /* panic ? */ 2837 } 2838 2839 return r; 2840 } 2841 2842 static void 2843 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2844 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2845 { 2846 struct fwohcidb *db = &db_tr->db[0]; 2847 2848 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2849 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2850 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2851 fwdma_sync_multiseg_all(dbch->am, 2852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2853 dbch->bottom = db_tr; 2854 2855 if (wake) 2856 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2857 } 2858 2859 static void 2860 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2861 { 2862 struct fwohcidb_tr *db_tr; 2863 struct iovec vec[2]; 2864 struct fw_pkt pktbuf; 2865 int nvec; 2866 struct fw_pkt *fp; 2867 uint8_t *ld; 2868 uint32_t stat, off, status, event; 2869 u_int spd; 2870 int len, plen, hlen, pcnt, offset; 2871 int s; 2872 void *buf; 2873 int resCount; 2874 2875 CTR0(KTR_DEV, "fwohci_arv"); 2876 2877 if(&sc->arrq == dbch){ 2878 off = OHCI_ARQOFF; 2879 }else if(&sc->arrs == dbch){ 2880 off = OHCI_ARSOFF; 2881 }else{ 2882 return; 2883 } 2884 2885 s = splfw(); 2886 db_tr = dbch->top; 2887 pcnt = 0; 2888 /* XXX we cannot handle a packet which lies in more than two buf */ 2889 fwdma_sync_multiseg_all(dbch->am, 2890 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2891 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2892 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2893 while (status & OHCI_CNTL_DMA_ACTIVE) { 2894 #if 0 2895 2896 if (off == OHCI_ARQOFF) 2897 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2898 db_tr->bus_addr, status, resCount); 2899 #endif 2900 len = dbch->xferq.psize - resCount; 2901 ld = (uint8_t *)db_tr->buf; 2902 if (dbch->pdb_tr == NULL) { 2903 len -= dbch->buf_offset; 2904 ld += dbch->buf_offset; 2905 } 2906 if (len > 0) 2907 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2908 BUS_DMASYNC_POSTREAD); 2909 while (len > 0 ) { 2910 if (count >= 0 && count-- == 0) 2911 goto out; 2912 if(dbch->pdb_tr != NULL){ 2913 /* we have a fragment in previous buffer */ 2914 int rlen; 2915 2916 offset = dbch->buf_offset; 2917 if (offset < 0) 2918 offset = - offset; 2919 buf = (char *)dbch->pdb_tr->buf + offset; 2920 rlen = dbch->xferq.psize - offset; 2921 if (firewire_debug) 2922 printf("rlen=%d, offset=%d\n", 2923 rlen, dbch->buf_offset); 2924 if (dbch->buf_offset < 0) { 2925 /* splitted in header, pull up */ 2926 char *p; 2927 2928 p = (char *)&pktbuf; 2929 bcopy(buf, p, rlen); 2930 p += rlen; 2931 /* this must be too long but harmless */ 2932 rlen = sizeof(pktbuf) - rlen; 2933 if (rlen < 0) 2934 printf("why rlen < 0\n"); 2935 bcopy(db_tr->buf, p, rlen); 2936 ld += rlen; 2937 len -= rlen; 2938 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2939 if (hlen <= 0) { 2940 printf("hlen should be positive."); 2941 goto err; 2942 } 2943 offset = sizeof(pktbuf); 2944 vec[0].iov_base = (char *)&pktbuf; 2945 vec[0].iov_len = offset; 2946 } else { 2947 /* splitted in payload */ 2948 offset = rlen; 2949 vec[0].iov_base = buf; 2950 vec[0].iov_len = rlen; 2951 } 2952 fp=(struct fw_pkt *)vec[0].iov_base; 2953 nvec = 1; 2954 } else { 2955 /* no fragment in previous buffer */ 2956 fp=(struct fw_pkt *)ld; 2957 hlen = fwohci_arcv_swap(fp, len); 2958 if (hlen == 0) 2959 goto err; 2960 if (hlen < 0) { 2961 dbch->pdb_tr = db_tr; 2962 dbch->buf_offset = - dbch->buf_offset; 2963 /* sanity check */ 2964 if (resCount != 0) { 2965 printf("resCount=%d hlen=%d\n", 2966 resCount, hlen); 2967 goto err; 2968 } 2969 goto out; 2970 } 2971 offset = 0; 2972 nvec = 0; 2973 } 2974 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2975 if (plen < 0) { 2976 /* minimum header size + trailer 2977 = sizeof(fw_pkt) so this shouldn't happens */ 2978 printf("plen(%d) is negative! offset=%d\n", 2979 plen, offset); 2980 goto err; 2981 } 2982 if (plen > 0) { 2983 len -= plen; 2984 if (len < 0) { 2985 dbch->pdb_tr = db_tr; 2986 if (firewire_debug) 2987 printf("splitted payload\n"); 2988 /* sanity check */ 2989 if (resCount != 0) { 2990 printf("resCount=%d plen=%d" 2991 " len=%d\n", 2992 resCount, plen, len); 2993 goto err; 2994 } 2995 goto out; 2996 } 2997 vec[nvec].iov_base = ld; 2998 vec[nvec].iov_len = plen; 2999 nvec ++; 3000 ld += plen; 3001 } 3002 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3003 if (nvec == 0) 3004 printf("nvec == 0\n"); 3005 3006 /* DMA result-code will be written at the tail of packet */ 3007 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3008 #if 0 3009 printf("plen: %d, stat %x\n", 3010 plen ,stat); 3011 #endif 3012 spd = (stat >> 21) & 0x3; 3013 event = (stat >> 16) & 0x1f; 3014 switch (event) { 3015 case FWOHCIEV_ACKPEND: 3016 #if 0 3017 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3018 #endif 3019 /* fall through */ 3020 case FWOHCIEV_ACKCOMPL: 3021 { 3022 struct fw_rcv_buf rb; 3023 3024 if ((vec[nvec-1].iov_len -= 3025 sizeof(struct fwohci_trailer)) == 0) 3026 nvec--; 3027 rb.fc = &sc->fc; 3028 rb.vec = vec; 3029 rb.nvec = nvec; 3030 rb.spd = spd; 3031 fw_rcv(&rb); 3032 break; 3033 } 3034 case FWOHCIEV_BUSRST: 3035 if ((sc->fc.status != FWBUSRESET) && 3036 (sc->fc.status != FWBUSINIT)) 3037 printf("got BUSRST packet!?\n"); 3038 break; 3039 default: 3040 fw_printf(sc->fc.dev, 3041 "Async DMA Receive error err=%02x %s" 3042 " plen=%d offset=%d len=%d status=0x%08x" 3043 " tcode=0x%x, stat=0x%08x\n", 3044 event, fwohcicode[event], plen, 3045 dbch->buf_offset, len, 3046 OREAD(sc, OHCI_DMACTL(off)), 3047 fp->mode.common.tcode, stat); 3048 #if 1 /* XXX */ 3049 goto err; 3050 #endif 3051 break; 3052 } 3053 pcnt ++; 3054 if (dbch->pdb_tr != NULL) { 3055 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3056 off, 1); 3057 dbch->pdb_tr = NULL; 3058 } 3059 3060 } 3061 out: 3062 if (resCount == 0) { 3063 /* done on this buffer */ 3064 if (dbch->pdb_tr == NULL) { 3065 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3066 dbch->buf_offset = 0; 3067 } else 3068 if (dbch->pdb_tr != db_tr) 3069 printf("pdb_tr != db_tr\n"); 3070 db_tr = STAILQ_NEXT(db_tr, link); 3071 fwdma_sync_multiseg_all(dbch->am, 3072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3073 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3074 >> OHCI_STATUS_SHIFT; 3075 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3076 & OHCI_COUNT_MASK; 3077 /* XXX check buffer overrun */ 3078 dbch->top = db_tr; 3079 } else { 3080 dbch->buf_offset = dbch->xferq.psize - resCount; 3081 fw_bus_dmamap_sync( 3082 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3083 break; 3084 } 3085 /* XXX make sure DMA is not dead */ 3086 } 3087 #if 0 3088 if (pcnt < 1) 3089 printf("fwohci_arcv: no packets\n"); 3090 #endif 3091 fwdma_sync_multiseg_all(dbch->am, 3092 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3093 splx(s); 3094 return; 3095 3096 err: 3097 fw_printf(sc->fc.dev, "AR DMA status=%x, ", 3098 OREAD(sc, OHCI_DMACTL(off))); 3099 dbch->pdb_tr = NULL; 3100 /* skip until resCount != 0 */ 3101 printf(" skip buffer"); 3102 while (resCount == 0) { 3103 printf(" #"); 3104 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3105 db_tr = STAILQ_NEXT(db_tr, link); 3106 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3107 & OHCI_COUNT_MASK; 3108 } 3109 printf(" done\n"); 3110 dbch->top = db_tr; 3111 dbch->buf_offset = dbch->xferq.psize - resCount; 3112 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3113 fwdma_sync_multiseg_all( 3114 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3115 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3116 splx(s); 3117 } 3118 #if defined(__NetBSD__) 3119 3120 int 3121 fwohci_print(void *aux, const char *pnp) 3122 { 3123 struct fw_attach_args *fwa = (struct fw_attach_args *)aux; 3124 3125 if (pnp) 3126 aprint_normal("%s at %s", fwa->name, pnp); 3127 3128 return UNCONF; 3129 } 3130 #endif 3131
Indexes created Tue Sep 30 07:10:03 GMT 2025