fwohci.c revision 1.111
1 /* $NetBSD: fwohci.c,v 1.111 2007/11/06 12:32:12 dogcow Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.93 2007/06/08 09:04:30 simokawa Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/kdb.h> 59 60 #include <sys/bus.h> 61 #include <sys/cdefs.h> 62 63 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.111 2007/11/06 12:32:12 dogcow Exp $"); 64 65 #if defined(__DragonFly__) || __FreeBSD_version < 500000 66 #include <machine/clock.h> /* for DELAY() */ 67 #endif 68 69 #ifdef __DragonFly__ 70 #include "fw_port.h" 71 #include "firewire.h" 72 #include "firewirereg.h" 73 #include "fwdma.h" 74 #include "fwohcireg.h" 75 #include "fwohcivar.h" 76 #include "firewire_phy.h" 77 #else 78 #include <dev/firewire/fw_port.h> 79 #include <dev/firewire/firewire.h> 80 #include <dev/firewire/firewirereg.h> 81 #include <dev/firewire/fwdma.h> 82 #include <dev/firewire/fwohcireg.h> 83 #include <dev/firewire/fwohcivar.h> 84 #include <dev/firewire/firewire_phy.h> 85 #endif 86 #elif defined(__NetBSD__) 87 #include <sys/param.h> 88 #include <sys/device.h> 89 #include <sys/errno.h> 90 #include <sys/conf.h> 91 #include <sys/kernel.h> 92 #include <sys/malloc.h> 93 #include <sys/mbuf.h> 94 #include <sys/proc.h> 95 #include <sys/reboot.h> 96 #include <sys/sysctl.h> 97 #include <sys/systm.h> 98 99 #include <sys/bus.h> 100 101 #include <dev/ieee1394/fw_port.h> 102 #include <dev/ieee1394/firewire.h> 103 #include <dev/ieee1394/firewirereg.h> 104 #include <dev/ieee1394/fwdma.h> 105 #include <dev/ieee1394/fwohcireg.h> 106 #include <dev/ieee1394/fwohcivar.h> 107 #include <dev/ieee1394/firewire_phy.h> 108 109 #include "ioconf.h" 110 #endif 111 112 #undef OHCI_DEBUG 113 114 static int nocyclemaster = 0; 115 int firewire_phydma_enable = 1; 116 #if defined(__FreeBSD__) 117 SYSCTL_DECL(_hw_firewire); 118 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 119 "Do not send cycle start packets"); 120 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW, 121 &firewire_phydma_enable, 1, "Allow physical request DMA from firewire"); 122 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable); 123 #elif defined(__NetBSD__) 124 /* 125 * Setup sysctl(3) MIB, hw.fwohci.* 126 * 127 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 128 */ 129 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 130 { 131 int rc, fwohci_node_num; 132 const struct sysctlnode *node; 133 134 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 135 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 136 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 137 goto err; 138 } 139 140 if ((rc = sysctl_createv(clog, 0, NULL, &node, 141 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 142 SYSCTL_DESCR("fwohci controls"), 143 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 144 goto err; 145 } 146 fwohci_node_num = node->sysctl_num; 147 148 /* fwohci no cyclemaster flag */ 149 if ((rc = sysctl_createv(clog, 0, NULL, &node, 150 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 151 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 152 NULL, 0, &nocyclemaster, 153 0, CTL_HW, fwohci_node_num, CTL_CREATE, CTL_EOL)) != 0) { 154 goto err; 155 } 156 157 /* fwohci physical request DMA enable */ 158 if ((rc = sysctl_createv(clog, 0, NULL, &node, 159 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, "phydma_enable", 160 SYSCTL_DESCR("Allow physical request DMA from firewire"), 161 NULL, 0, &firewire_phydma_enable, 162 0, CTL_HW, fwohci_node_num, CTL_CREATE, CTL_EOL)) != 0) { 163 goto err; 164 } 165 return; 166 167 err: 168 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 169 } 170 #endif 171 172 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 173 "STOR","LOAD","NOP ","STOP", 174 "", "", "", "", "", "", "", ""}; 175 176 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 177 "UNDEF","REG","SYS","DEV"}; 178 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 179 static const char * const fwohcicode[32] = { 180 "No stat","Undef","long","miss Ack err", 181 "FIFO underrun","FIFO overrun","desc err", "data read err", 182 "data write err","bus reset","timeout","tcode err", 183 "Undef","Undef","unknown event","flushed", 184 "Undef","ack complete","ack pend","Undef", 185 "ack busy_X","ack busy_A","ack busy_B","Undef", 186 "Undef","Undef","Undef","ack tardy", 187 "Undef","ack data_err","ack type_err",""}; 188 189 #define MAX_SPEED 3 190 extern const char *fw_linkspeed[]; 191 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 192 193 static const struct tcode_info tinfo[] = { 194 /* hdr_len block flag valid_response*/ 195 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES}, 196 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES}, 197 /* 2 WRES */ {12, FWTI_RES, 0xff}, 198 /* 3 XXX */ { 0, 0, 0xff}, 199 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ}, 200 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB}, 201 /* 6 RRESQ */ {16, FWTI_RES, 0xff}, 202 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 203 /* 8 CYCS */ { 0, 0, 0xff}, 204 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES}, 205 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff}, 206 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 207 /* c XXX */ { 0, 0, 0xff}, 208 /* d XXX */ { 0, 0, 0xff}, 209 /* e PHY */ {12, FWTI_REQ, 0xff}, 210 /* f XXX */ { 0, 0, 0xff} 211 }; 212 213 #define OHCI_WRITE_SIGMASK 0xffff0000 214 #define OHCI_READ_SIGMASK 0xffff0000 215 216 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 217 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 218 219 static void fwohci_ibr (struct firewire_comm *); 220 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 221 static void fwohci_db_free (struct fwohci_dbch *); 222 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 223 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 224 static void fwohci_start_atq (struct firewire_comm *); 225 static void fwohci_start_ats (struct firewire_comm *); 226 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 227 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 228 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 229 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 230 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 231 static int fwohci_irx_enable (struct firewire_comm *, int); 232 static int fwohci_irx_disable (struct firewire_comm *, int); 233 #if BYTE_ORDER == BIG_ENDIAN 234 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 235 #endif 236 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 237 static int fwohci_itx_disable (struct firewire_comm *, int); 238 static void fwohci_timeout (void *); 239 static void fwohci_set_intr (struct firewire_comm *, int); 240 241 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 242 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 243 static void dump_db (struct fwohci_softc *, uint32_t); 244 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 245 static void dump_dma (struct fwohci_softc *, uint32_t); 246 static uint32_t fwohci_cyctimer (struct firewire_comm *); 247 static void fwohci_rbuf_update (struct fwohci_softc *, int); 248 static void fwohci_tbuf_update (struct fwohci_softc *, int); 249 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 250 static void fwohci_task_busreset(void *, int); 251 static void fwohci_task_sid(void *, int); 252 static void fwohci_task_dma(void *, int); 253 #if defined(__NetBSD__) 254 int fwohci_print(void *, const char *); 255 #endif 256 257 /* 258 * memory allocated for DMA programs 259 */ 260 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 261 262 #define NDB FWMAXQUEUE 263 264 #define OHCI_VERSION 0x00 265 #define OHCI_ATRETRY 0x08 266 #define OHCI_CROMHDR 0x18 267 #define OHCI_BUS_OPT 0x20 268 #define OHCI_BUSIRMC (1 << 31) 269 #define OHCI_BUSCMC (1 << 30) 270 #define OHCI_BUSISC (1 << 29) 271 #define OHCI_BUSBMC (1 << 28) 272 #define OHCI_BUSPMC (1 << 27) 273 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 274 OHCI_BUSBMC | OHCI_BUSPMC 275 276 #define OHCI_EUID_HI 0x24 277 #define OHCI_EUID_LO 0x28 278 279 #define OHCI_CROMPTR 0x34 280 #define OHCI_HCCCTL 0x50 281 #define OHCI_HCCCTLCLR 0x54 282 #define OHCI_AREQHI 0x100 283 #define OHCI_AREQHICLR 0x104 284 #define OHCI_AREQLO 0x108 285 #define OHCI_AREQLOCLR 0x10c 286 #define OHCI_PREQHI 0x110 287 #define OHCI_PREQHICLR 0x114 288 #define OHCI_PREQLO 0x118 289 #define OHCI_PREQLOCLR 0x11c 290 #define OHCI_PREQUPPER 0x120 291 292 #define OHCI_SID_BUF 0x64 293 #define OHCI_SID_CNT 0x68 294 #define OHCI_SID_ERR (1 << 31) 295 #define OHCI_SID_CNT_MASK 0xffc 296 297 #define OHCI_IT_STAT 0x90 298 #define OHCI_IT_STATCLR 0x94 299 #define OHCI_IT_MASK 0x98 300 #define OHCI_IT_MASKCLR 0x9c 301 302 #define OHCI_IR_STAT 0xa0 303 #define OHCI_IR_STATCLR 0xa4 304 #define OHCI_IR_MASK 0xa8 305 #define OHCI_IR_MASKCLR 0xac 306 307 #define OHCI_LNKCTL 0xe0 308 #define OHCI_LNKCTLCLR 0xe4 309 310 #define OHCI_PHYACCESS 0xec 311 #define OHCI_CYCLETIMER 0xf0 312 313 #define OHCI_DMACTL(off) (off) 314 #define OHCI_DMACTLCLR(off) (off + 4) 315 #define OHCI_DMACMD(off) (off + 0xc) 316 #define OHCI_DMAMATCH(off) (off + 0x10) 317 318 #define OHCI_ATQOFF 0x180 319 #define OHCI_ATQCTL OHCI_ATQOFF 320 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 321 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 322 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 323 324 #define OHCI_ATSOFF 0x1a0 325 #define OHCI_ATSCTL OHCI_ATSOFF 326 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 327 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 328 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 329 330 #define OHCI_ARQOFF 0x1c0 331 #define OHCI_ARQCTL OHCI_ARQOFF 332 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 333 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 334 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 335 336 #define OHCI_ARSOFF 0x1e0 337 #define OHCI_ARSCTL OHCI_ARSOFF 338 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 339 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 340 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 341 342 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 343 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 344 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 345 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 346 347 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 348 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 349 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 350 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 351 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 352 353 #if defined(__FreeBSD__) 354 d_ioctl_t fwohci_ioctl; 355 #elif defined(__NetBSD__) 356 dev_type_ioctl(fwohci_ioctl); 357 #endif 358 359 /* 360 * Communication with PHY device 361 */ 362 /* XXX need lock for phy access */ 363 static uint32_t 364 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 365 { 366 uint32_t fun; 367 368 addr &= 0xf; 369 data &= 0xff; 370 371 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 372 OWRITE(sc, OHCI_PHYACCESS, fun); 373 DELAY(100); 374 375 return(fwphy_rddata( sc, addr)); 376 } 377 378 static uint32_t 379 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 380 { 381 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 382 int i; 383 uint32_t bm; 384 385 #define OHCI_CSR_DATA 0x0c 386 #define OHCI_CSR_COMP 0x10 387 #define OHCI_CSR_CONT 0x14 388 #define OHCI_BUS_MANAGER_ID 0 389 390 OWRITE(sc, OHCI_CSR_DATA, node); 391 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 392 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 393 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 394 DELAY(10); 395 bm = OREAD(sc, OHCI_CSR_DATA); 396 if((bm & 0x3f) == 0x3f) 397 bm = node; 398 if (firewire_debug) 399 fw_printf(sc->fc.dev, 400 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 401 402 return(bm); 403 } 404 405 static uint32_t 406 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 407 { 408 uint32_t fun, stat; 409 u_int i, retry = 0; 410 411 addr &= 0xf; 412 #define MAX_RETRY 100 413 again: 414 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 415 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 416 OWRITE(sc, OHCI_PHYACCESS, fun); 417 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 418 fun = OREAD(sc, OHCI_PHYACCESS); 419 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 420 break; 421 DELAY(100); 422 } 423 if(i >= MAX_RETRY) { 424 if (firewire_debug) 425 fw_printf(sc->fc.dev, "phy read failed(1).\n"); 426 if (++retry < MAX_RETRY) { 427 DELAY(100); 428 goto again; 429 } 430 } 431 /* Make sure that SCLK is started */ 432 stat = OREAD(sc, FWOHCI_INTSTAT); 433 if ((stat & OHCI_INT_REG_FAIL) != 0 || 434 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 435 if (firewire_debug) 436 fw_printf(sc->fc.dev, "phy read failed(2).\n"); 437 if (++retry < MAX_RETRY) { 438 DELAY(100); 439 goto again; 440 } 441 } 442 if (firewire_debug || retry >= MAX_RETRY) 443 fw_printf(sc->fc.dev, 444 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 445 #undef MAX_RETRY 446 return((fun >> PHYDEV_RDDATA )& 0xff); 447 } 448 /* Device specific ioctl. */ 449 FW_IOCTL(fwohci) 450 { 451 FW_IOCTL_START; 452 struct fwohci_softc *fc; 453 int err = 0; 454 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 455 uint32_t *dmach = (uint32_t *) data; 456 457 if(sc == NULL){ 458 return(EINVAL); 459 } 460 fc = (struct fwohci_softc *)sc->fc; 461 462 if (!data) 463 return(EINVAL); 464 465 switch (cmd) { 466 case FWOHCI_WRREG: 467 #define OHCI_MAX_REG 0x800 468 if(reg->addr <= OHCI_MAX_REG){ 469 OWRITE(fc, reg->addr, reg->data); 470 reg->data = OREAD(fc, reg->addr); 471 }else{ 472 err = EINVAL; 473 } 474 break; 475 case FWOHCI_RDREG: 476 if(reg->addr <= OHCI_MAX_REG){ 477 reg->data = OREAD(fc, reg->addr); 478 }else{ 479 err = EINVAL; 480 } 481 break; 482 /* Read DMA descriptors for debug */ 483 case DUMPDMA: 484 if(*dmach <= OHCI_MAX_DMA_CH ){ 485 dump_dma(fc, *dmach); 486 dump_db(fc, *dmach); 487 }else{ 488 err = EINVAL; 489 } 490 break; 491 /* Read/Write Phy registers */ 492 #define OHCI_MAX_PHY_REG 0xf 493 case FWOHCI_RDPHYREG: 494 if (reg->addr <= OHCI_MAX_PHY_REG) 495 reg->data = fwphy_rddata(fc, reg->addr); 496 else 497 err = EINVAL; 498 break; 499 case FWOHCI_WRPHYREG: 500 if (reg->addr <= OHCI_MAX_PHY_REG) 501 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 502 else 503 err = EINVAL; 504 break; 505 default: 506 err = EINVAL; 507 break; 508 } 509 return err; 510 } 511 512 static int 513 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 514 { 515 uint32_t reg, reg2; 516 int e1394a = 1; 517 /* 518 * probe PHY parameters 519 * 0. to prove PHY version, whether compliance of 1394a. 520 * 1. to probe maximum speed supported by the PHY and 521 * number of port supported by core-logic. 522 * It is not actually available port on your PC . 523 */ 524 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 525 DELAY(500); 526 527 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 528 529 if((reg >> 5) != 7 ){ 530 sc->fc.mode &= ~FWPHYASYST; 531 sc->fc.nport = reg & FW_PHY_NP; 532 sc->fc.speed = reg & FW_PHY_SPD >> 6; 533 if (sc->fc.speed > MAX_SPEED) { 534 fw_printf(dev, "invalid speed %d (fixed to %d).\n", 535 sc->fc.speed, MAX_SPEED); 536 sc->fc.speed = MAX_SPEED; 537 } 538 fw_printf(dev, "Phy 1394 only %s, %d ports.\n", 539 fw_linkspeed[sc->fc.speed], sc->fc.nport); 540 }else{ 541 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 542 sc->fc.mode |= FWPHYASYST; 543 sc->fc.nport = reg & FW_PHY_NP; 544 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 545 if (sc->fc.speed > MAX_SPEED) { 546 fw_printf(dev, "invalid speed %d (fixed to %d).\n", 547 sc->fc.speed, MAX_SPEED); 548 sc->fc.speed = MAX_SPEED; 549 } 550 fw_printf(dev, "Phy 1394a available %s, %d ports.\n", 551 fw_linkspeed[sc->fc.speed], sc->fc.nport); 552 553 /* check programPhyEnable */ 554 reg2 = fwphy_rddata(sc, 5); 555 #if 0 556 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 557 #else /* XXX force to enable 1394a */ 558 if (e1394a) { 559 #endif 560 if (firewire_debug) 561 fw_printf(dev, "Enable 1394a Enhancements\n"); 562 /* enable EAA EMC */ 563 reg2 |= 0x03; 564 /* set aPhyEnhanceEnable */ 565 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 566 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 567 } 568 #if 0 569 else { 570 /* for safe */ 571 reg2 &= ~0x83; 572 } 573 #endif 574 reg2 = fwphy_wrdata(sc, 5, reg2); 575 } 576 577 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 578 if((reg >> 5) == 7 ){ 579 reg = fwphy_rddata(sc, 4); 580 reg |= 1 << 6; 581 fwphy_wrdata(sc, 4, reg); 582 reg = fwphy_rddata(sc, 4); 583 } 584 return 0; 585 } 586 587 588 void 589 fwohci_reset(struct fwohci_softc *sc, device_t dev) 590 { 591 int i, max_rec, speed; 592 uint32_t reg, reg2; 593 struct fwohcidb_tr *db_tr; 594 595 /* Disable interrupts */ 596 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 597 598 /* Now stopping all DMA channels */ 599 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 600 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 601 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 602 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 603 604 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 605 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 606 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 607 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 608 } 609 610 /* FLUSH FIFO and reset Transmitter/Reciever */ 611 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 612 if (firewire_debug) 613 fw_printf(dev, "resetting OHCI..."); 614 i = 0; 615 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 616 if (i++ > 100) break; 617 DELAY(1000); 618 } 619 if (firewire_debug) 620 printf("done (loop=%d)\n", i); 621 622 /* Probe phy */ 623 fwohci_probe_phy(sc, dev); 624 625 /* Probe link */ 626 reg = OREAD(sc, OHCI_BUS_OPT); 627 reg2 = reg | OHCI_BUSFNC; 628 max_rec = (reg & 0x0000f000) >> 12; 629 speed = (reg & 0x00000007); 630 fw_printf(dev, "Link %s, max_rec %d bytes.\n", 631 fw_linkspeed[speed], MAXREC(max_rec)); 632 /* XXX fix max_rec */ 633 sc->fc.maxrec = sc->fc.speed + 8; 634 if (max_rec != sc->fc.maxrec) { 635 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 636 fw_printf(dev, "max_rec %d -> %d\n", 637 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 638 } 639 if (firewire_debug) 640 fw_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 641 OWRITE(sc, OHCI_BUS_OPT, reg2); 642 643 /* Initialize registers */ 644 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 645 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 646 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 647 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 648 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 649 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 650 651 /* Enable link */ 652 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 653 654 /* Force to start async RX DMA */ 655 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 656 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 657 fwohci_rx_enable(sc, &sc->arrq); 658 fwohci_rx_enable(sc, &sc->arrs); 659 660 /* Initialize async TX */ 661 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 662 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 663 664 /* AT Retries */ 665 OWRITE(sc, FWOHCI_RETRY, 666 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 667 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 668 669 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 670 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 671 sc->atrq.bottom = sc->atrq.top; 672 sc->atrs.bottom = sc->atrs.top; 673 674 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 675 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 676 db_tr->xfer = NULL; 677 } 678 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 679 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 680 db_tr->xfer = NULL; 681 } 682 683 684 /* Enable interrupts */ 685 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID 686 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 687 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 688 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 689 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT; 690 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT; 691 OWRITE(sc, FWOHCI_INTMASK, sc->intmask); 692 fwohci_set_intr(&sc->fc, 1); 693 } 694 695 int 696 fwohci_init(struct fwohci_softc *sc, device_t dev) 697 { 698 int i, mver; 699 uint32_t reg; 700 uint8_t ui[8]; 701 702 /* OHCI version */ 703 reg = OREAD(sc, OHCI_VERSION); 704 mver = (reg >> 16) & 0xff; 705 fw_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 706 mver, reg & 0xff, (reg>>24) & 1); 707 if (mver < 1 || mver > 9) { 708 fw_printf(dev, "invalid OHCI version\n"); 709 return (ENXIO); 710 } 711 712 /* Available Isochronous DMA channel probe */ 713 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 714 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 715 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 716 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 717 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 718 for (i = 0; i < 0x20; i++) 719 if ((reg & (1 << i)) == 0) 720 break; 721 sc->fc.nisodma = i; 722 fw_printf(dev, "No. of Isochronous channels is %d.\n", i); 723 if (i == 0) 724 return (ENXIO); 725 726 sc->fc.arq = &sc->arrq.xferq; 727 sc->fc.ars = &sc->arrs.xferq; 728 sc->fc.atq = &sc->atrq.xferq; 729 sc->fc.ats = &sc->atrs.xferq; 730 731 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 732 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 733 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 734 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 735 736 sc->arrq.xferq.start = NULL; 737 sc->arrs.xferq.start = NULL; 738 sc->atrq.xferq.start = fwohci_start_atq; 739 sc->atrs.xferq.start = fwohci_start_ats; 740 741 sc->arrq.xferq.buf = NULL; 742 sc->arrs.xferq.buf = NULL; 743 sc->atrq.xferq.buf = NULL; 744 sc->atrs.xferq.buf = NULL; 745 746 sc->arrq.xferq.dmach = -1; 747 sc->arrs.xferq.dmach = -1; 748 sc->atrq.xferq.dmach = -1; 749 sc->atrs.xferq.dmach = -1; 750 751 sc->arrq.ndesc = 1; 752 sc->arrs.ndesc = 1; 753 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 754 sc->atrs.ndesc = 2; 755 756 sc->arrq.ndb = NDB; 757 sc->arrs.ndb = NDB / 2; 758 sc->atrq.ndb = NDB; 759 sc->atrs.ndb = NDB / 2; 760 761 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 762 sc->fc.it[i] = &sc->it[i].xferq; 763 sc->fc.ir[i] = &sc->ir[i].xferq; 764 sc->it[i].xferq.dmach = i; 765 sc->ir[i].xferq.dmach = i; 766 sc->it[i].ndb = 0; 767 sc->ir[i].ndb = 0; 768 } 769 770 sc->fc.tcode = tinfo; 771 sc->fc.dev = dev; 772 773 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 774 &sc->crom_dma, BUS_DMA_WAITOK); 775 if(sc->fc.config_rom == NULL){ 776 fw_printf(dev, "config_rom alloc failed."); 777 return ENOMEM; 778 } 779 780 #if 0 781 bzero(&sc->fc.config_rom[0], CROMSIZE); 782 sc->fc.config_rom[1] = 0x31333934; 783 sc->fc.config_rom[2] = 0xf000a002; 784 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 785 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 786 sc->fc.config_rom[5] = 0; 787 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 788 789 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 790 #endif 791 792 /* SID recieve buffer must align 2^11 */ 793 #define OHCI_SIDSIZE (1 << 11) 794 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 795 &sc->sid_dma, BUS_DMA_WAITOK); 796 if (sc->sid_buf == NULL) { 797 fw_printf(dev, "sid_buf alloc failed."); 798 return ENOMEM; 799 } 800 801 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 802 &sc->dummy_dma, BUS_DMA_WAITOK); 803 804 if (sc->dummy_dma.v_addr == NULL) { 805 fw_printf(dev, "dummy_dma alloc failed."); 806 return ENOMEM; 807 } 808 809 fwohci_db_init(sc, &sc->arrq); 810 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 811 return ENOMEM; 812 813 fwohci_db_init(sc, &sc->arrs); 814 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 815 return ENOMEM; 816 817 fwohci_db_init(sc, &sc->atrq); 818 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 819 return ENOMEM; 820 821 fwohci_db_init(sc, &sc->atrs); 822 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 823 return ENOMEM; 824 825 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 826 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 827 for( i = 0 ; i < 8 ; i ++) 828 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 829 fw_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 830 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 831 832 sc->fc.ioctl = fwohci_ioctl; 833 sc->fc.cyctimer = fwohci_cyctimer; 834 sc->fc.set_bmr = fwohci_set_bus_manager; 835 sc->fc.ibr = fwohci_ibr; 836 sc->fc.irx_enable = fwohci_irx_enable; 837 sc->fc.irx_disable = fwohci_irx_disable; 838 839 sc->fc.itx_enable = fwohci_itxbuf_enable; 840 sc->fc.itx_disable = fwohci_itx_disable; 841 #if BYTE_ORDER == BIG_ENDIAN 842 sc->fc.irx_post = fwohci_irx_post; 843 #else 844 sc->fc.irx_post = NULL; 845 #endif 846 sc->fc.itx_post = NULL; 847 sc->fc.timeout = fwohci_timeout; 848 sc->fc.poll = fwohci_poll; 849 sc->fc.set_intr = fwohci_set_intr; 850 851 sc->intmask = sc->irstat = sc->itstat = 0; 852 853 /* Init task queue */ 854 sc->fc.taskqueue = fw_taskqueue_create_fast("fw_taskq", M_WAITOK, 855 fw_taskqueue_thread_enqueue, &sc->fc.taskqueue); 856 fw_taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq", 857 fw_get_unit(dev)); 858 FW_TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc); 859 FW_TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc); 860 FW_TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc); 861 862 fw_init(&sc->fc); 863 fwohci_reset(sc, dev); 864 FWOHCI_INIT_END; 865 866 return 0; 867 } 868 869 void 870 fwohci_timeout(void *arg) 871 { 872 struct fwohci_softc *sc; 873 874 sc = (struct fwohci_softc *)arg; 875 } 876 877 uint32_t 878 fwohci_cyctimer(struct firewire_comm *fc) 879 { 880 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 881 return(OREAD(sc, OHCI_CYCLETIMER)); 882 } 883 884 FWOHCI_DETACH() 885 { 886 int i; 887 888 FWOHCI_DETACH_START; 889 if (sc->sid_buf != NULL) 890 fwdma_free(&sc->fc, &sc->sid_dma); 891 if (sc->fc.config_rom != NULL) 892 fwdma_free(&sc->fc, &sc->crom_dma); 893 894 fwohci_db_free(&sc->arrq); 895 fwohci_db_free(&sc->arrs); 896 897 fwohci_db_free(&sc->atrq); 898 fwohci_db_free(&sc->atrs); 899 900 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 901 fwohci_db_free(&sc->it[i]); 902 fwohci_db_free(&sc->ir[i]); 903 } 904 FWOHCI_DETACH_END; 905 906 return 0; 907 } 908 909 #define LAST_DB(dbtr, db) do { \ 910 struct fwohcidb_tr *_dbtr = (dbtr); \ 911 int _cnt = _dbtr->dbcnt; \ 912 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 913 } while (0) 914 915 static void 916 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 917 { 918 struct fwohcidb_tr *db_tr; 919 struct fwohcidb *db; 920 bus_dma_segment_t *s; 921 int i; 922 923 db_tr = (struct fwohcidb_tr *)arg; 924 db = &db_tr->db[db_tr->dbcnt]; 925 if (error) { 926 if (firewire_debug || error != EFBIG) 927 printf("fwohci_execute_db: error=%d\n", error); 928 return; 929 } 930 for (i = 0; i < nseg; i++) { 931 s = &segs[i]; 932 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 933 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 934 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 935 db++; 936 db_tr->dbcnt++; 937 } 938 } 939 940 static void 941 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 942 bus_size_t size, int error) 943 { 944 fwohci_execute_db(arg, segs, nseg, error); 945 } 946 947 static void 948 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 949 { 950 int i, s; 951 int tcode, hdr_len, pl_off; 952 int fsegment = -1; 953 uint32_t off; 954 struct fw_xfer *xfer; 955 struct fw_pkt *fp; 956 struct fwohci_txpkthdr *ohcifp; 957 struct fwohcidb_tr *db_tr; 958 struct fwohcidb *db; 959 uint32_t *ld; 960 const struct tcode_info *info; 961 static int maxdesc=0; 962 963 FW_GLOCK_ASSERT(&sc->fc); 964 965 if(&sc->atrq == dbch){ 966 off = OHCI_ATQOFF; 967 }else if(&sc->atrs == dbch){ 968 off = OHCI_ATSOFF; 969 }else{ 970 return; 971 } 972 973 if (dbch->flags & FWOHCI_DBCH_FULL) 974 return; 975 976 s = splfw(); 977 fwdma_sync_multiseg_all(dbch->am, 978 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 979 db_tr = dbch->top; 980 txloop: 981 xfer = STAILQ_FIRST(&dbch->xferq.q); 982 if(xfer == NULL){ 983 goto kick; 984 } 985 #if 0 986 if(dbch->xferq.queued == 0 ){ 987 fw_printf(sc->fc.dev, "TX queue empty\n"); 988 } 989 #endif 990 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 991 db_tr->xfer = xfer; 992 xfer->flag = FWXF_START; 993 994 fp = &xfer->send.hdr; 995 tcode = fp->mode.common.tcode; 996 997 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 998 info = &tinfo[tcode]; 999 hdr_len = pl_off = info->hdr_len; 1000 1001 ld = &ohcifp->mode.ld[0]; 1002 ld[0] = ld[1] = ld[2] = ld[3] = 0; 1003 for( i = 0 ; i < pl_off ; i+= 4) 1004 ld[i/4] = fp->mode.ld[i/4]; 1005 1006 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 1007 if (tcode == FWTCODE_STREAM ){ 1008 hdr_len = 8; 1009 ohcifp->mode.stream.len = fp->mode.stream.len; 1010 } else if (tcode == FWTCODE_PHY) { 1011 hdr_len = 12; 1012 ld[1] = fp->mode.ld[1]; 1013 ld[2] = fp->mode.ld[2]; 1014 ohcifp->mode.common.spd = 0; 1015 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 1016 } else { 1017 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 1018 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 1019 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 1020 } 1021 db = &db_tr->db[0]; 1022 FWOHCI_DMA_WRITE(db->db.desc.cmd, 1023 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 1024 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1025 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1026 /* Specify bound timer of asy. responce */ 1027 if(&sc->atrs == dbch){ 1028 FWOHCI_DMA_WRITE(db->db.desc.res, 1029 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1030 } 1031 #if BYTE_ORDER == BIG_ENDIAN 1032 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1033 hdr_len = 12; 1034 for (i = 0; i < hdr_len/4; i ++) 1035 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1036 #endif 1037 1038 again: 1039 db_tr->dbcnt = 2; 1040 db = &db_tr->db[db_tr->dbcnt]; 1041 if (xfer->send.pay_len > 0) { 1042 int err; 1043 /* handle payload */ 1044 if (xfer->mbuf == NULL) { 1045 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1046 &xfer->send.payload[0], xfer->send.pay_len, 1047 fwohci_execute_db, db_tr, 1048 BUS_DMA_WAITOK); 1049 } else { 1050 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1051 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1052 db_tr->dma_map, xfer->mbuf, 1053 fwohci_execute_db2, db_tr, 1054 BUS_DMA_WAITOK); 1055 if (err == EFBIG) { 1056 struct mbuf *m0; 1057 1058 if (firewire_debug) 1059 fw_printf(sc->fc.dev, "EFBIG.\n"); 1060 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1061 if (m0 != NULL) { 1062 m_copydata(xfer->mbuf, 0, 1063 xfer->mbuf->m_pkthdr.len, 1064 mtod(m0, void *)); 1065 m0->m_len = m0->m_pkthdr.len = 1066 xfer->mbuf->m_pkthdr.len; 1067 m_freem(xfer->mbuf); 1068 xfer->mbuf = m0; 1069 goto again; 1070 } 1071 fw_printf(sc->fc.dev, "m_getcl failed.\n"); 1072 } 1073 } 1074 if (err) 1075 printf("dmamap_load: err=%d\n", err); 1076 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1077 BUS_DMASYNC_PREWRITE); 1078 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1079 for (i = 2; i < db_tr->dbcnt; i++) 1080 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1081 OHCI_OUTPUT_MORE); 1082 #endif 1083 } 1084 if (maxdesc < db_tr->dbcnt) { 1085 maxdesc = db_tr->dbcnt; 1086 if (firewire_debug) 1087 fw_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1088 } 1089 /* last db */ 1090 LAST_DB(db_tr, db); 1091 FWOHCI_DMA_SET(db->db.desc.cmd, 1092 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1093 FWOHCI_DMA_WRITE(db->db.desc.depend, 1094 STAILQ_NEXT(db_tr, link)->bus_addr); 1095 1096 if(fsegment == -1 ) 1097 fsegment = db_tr->dbcnt; 1098 if (dbch->pdb_tr != NULL) { 1099 LAST_DB(dbch->pdb_tr, db); 1100 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1101 } 1102 dbch->xferq.queued ++; 1103 dbch->pdb_tr = db_tr; 1104 db_tr = STAILQ_NEXT(db_tr, link); 1105 if(db_tr != dbch->bottom){ 1106 goto txloop; 1107 } else { 1108 fw_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1109 dbch->flags |= FWOHCI_DBCH_FULL; 1110 } 1111 kick: 1112 /* kick asy q */ 1113 fwdma_sync_multiseg_all(dbch->am, 1114 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1115 1116 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1117 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1118 } else { 1119 if (firewire_debug) 1120 fw_printf(sc->fc.dev, "start AT DMA status=%x\n", 1121 OREAD(sc, OHCI_DMACTL(off))); 1122 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1123 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1124 dbch->xferq.flag |= FWXFERQ_RUNNING; 1125 } 1126 CTR0(KTR_DEV, "start kick done"); 1127 CTR0(KTR_DEV, "start kick done2"); 1128 1129 dbch->top = db_tr; 1130 splx(s); 1131 return; 1132 } 1133 1134 static void 1135 fwohci_start_atq(struct firewire_comm *fc) 1136 { 1137 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1138 FW_GLOCK(&sc->fc); 1139 fwohci_start( sc, &(sc->atrq)); 1140 FW_GUNLOCK(&sc->fc); 1141 return; 1142 } 1143 1144 static void 1145 fwohci_start_ats(struct firewire_comm *fc) 1146 { 1147 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1148 FW_GLOCK(&sc->fc); 1149 fwohci_start( sc, &(sc->atrs)); 1150 FW_GUNLOCK(&sc->fc); 1151 return; 1152 } 1153 1154 void 1155 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1156 { 1157 int s, ch, err = 0; 1158 struct fwohcidb_tr *tr; 1159 struct fwohcidb *db; 1160 struct fw_xfer *xfer; 1161 uint32_t off; 1162 u_int stat, status; 1163 int packets; 1164 struct firewire_comm *fc = (struct firewire_comm *)sc; 1165 1166 if(&sc->atrq == dbch){ 1167 off = OHCI_ATQOFF; 1168 ch = ATRQ_CH; 1169 }else if(&sc->atrs == dbch){ 1170 off = OHCI_ATSOFF; 1171 ch = ATRS_CH; 1172 }else{ 1173 return; 1174 } 1175 s = splfw(); 1176 tr = dbch->bottom; 1177 packets = 0; 1178 fwdma_sync_multiseg_all(dbch->am, 1179 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1180 while(dbch->xferq.queued > 0){ 1181 LAST_DB(tr, db); 1182 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1183 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1184 if (fc->status != FWBUSINIT) 1185 /* maybe out of order?? */ 1186 goto out; 1187 } 1188 if (tr->xfer->send.pay_len > 0) { 1189 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1190 BUS_DMASYNC_POSTWRITE); 1191 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1192 } 1193 #if 1 1194 if (firewire_debug > 1) 1195 dump_db(sc, ch); 1196 #endif 1197 if(status & OHCI_CNTL_DMA_DEAD) { 1198 /* Stop DMA */ 1199 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1200 fw_printf(sc->fc.dev, "force reset AT FIFO\n"); 1201 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1202 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1203 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1204 } 1205 stat = status & FWOHCIEV_MASK; 1206 switch(stat){ 1207 case FWOHCIEV_ACKPEND: 1208 CTR0(KTR_DEV, "txd: ack pending"); 1209 /* fall through */ 1210 case FWOHCIEV_ACKCOMPL: 1211 err = 0; 1212 break; 1213 case FWOHCIEV_ACKBSA: 1214 case FWOHCIEV_ACKBSB: 1215 case FWOHCIEV_ACKBSX: 1216 fw_printf(sc->fc.dev, "txd err=%2x %s\n", stat, 1217 fwohcicode[stat]); 1218 err = EBUSY; 1219 break; 1220 case FWOHCIEV_FLUSHED: 1221 case FWOHCIEV_ACKTARD: 1222 fw_printf(sc->fc.dev, "txd err=%2x %s\n", stat, 1223 fwohcicode[stat]); 1224 err = EAGAIN; 1225 break; 1226 case FWOHCIEV_MISSACK: 1227 case FWOHCIEV_UNDRRUN: 1228 case FWOHCIEV_OVRRUN: 1229 case FWOHCIEV_DESCERR: 1230 case FWOHCIEV_DTRDERR: 1231 case FWOHCIEV_TIMEOUT: 1232 case FWOHCIEV_TCODERR: 1233 case FWOHCIEV_UNKNOWN: 1234 case FWOHCIEV_ACKDERR: 1235 case FWOHCIEV_ACKTERR: 1236 default: 1237 fw_printf(sc->fc.dev, "txd err=%2x %s\n", 1238 stat, fwohcicode[stat]); 1239 err = EINVAL; 1240 break; 1241 } 1242 if (tr->xfer != NULL) { 1243 xfer = tr->xfer; 1244 CTR0(KTR_DEV, "txd"); 1245 if (xfer->flag & FWXF_RCVD) { 1246 #if 0 1247 if (firewire_debug) 1248 printf("already rcvd\n"); 1249 #endif 1250 fw_xfer_done(xfer); 1251 } else { 1252 microtime(&xfer->tv); 1253 xfer->flag = FWXF_SENT; 1254 if (err == EBUSY) { 1255 xfer->flag = FWXF_BUSY; 1256 xfer->resp = err; 1257 xfer->recv.pay_len = 0; 1258 fw_xfer_done(xfer); 1259 } else if (stat != FWOHCIEV_ACKPEND) { 1260 if (stat != FWOHCIEV_ACKCOMPL) 1261 xfer->flag = FWXF_SENTERR; 1262 xfer->resp = err; 1263 xfer->recv.pay_len = 0; 1264 fw_xfer_done(xfer); 1265 } 1266 } 1267 /* 1268 * The watchdog timer takes care of split 1269 * transcation timeout for ACKPEND case. 1270 */ 1271 } else { 1272 printf("this shouldn't happen\n"); 1273 } 1274 FW_GLOCK(fc); 1275 dbch->xferq.queued --; 1276 FW_GUNLOCK(fc); 1277 tr->xfer = NULL; 1278 1279 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1280 packets ++; 1281 tr = STAILQ_NEXT(tr, link); 1282 dbch->bottom = tr; 1283 if (dbch->bottom == dbch->top) { 1284 /* we reaches the end of context program */ 1285 if (firewire_debug && dbch->xferq.queued > 0) 1286 printf("queued > 0\n"); 1287 break; 1288 } 1289 } 1290 out: 1291 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1292 printf("make free slot\n"); 1293 dbch->flags &= ~FWOHCI_DBCH_FULL; 1294 FW_GLOCK(fc); 1295 fwohci_start(sc, dbch); 1296 FW_GUNLOCK(fc); 1297 } 1298 fwdma_sync_multiseg_all( 1299 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1300 splx(s); 1301 } 1302 1303 static void 1304 fwohci_db_free(struct fwohci_dbch *dbch) 1305 { 1306 struct fwohcidb_tr *db_tr; 1307 int idb; 1308 1309 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1310 return; 1311 1312 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1313 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1314 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1315 db_tr->buf != NULL) { 1316 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1317 db_tr->buf, dbch->xferq.psize); 1318 db_tr->buf = NULL; 1319 } else if (db_tr->dma_map != NULL) 1320 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1321 } 1322 dbch->ndb = 0; 1323 db_tr = STAILQ_FIRST(&dbch->db_trq); 1324 fwdma_free_multiseg(dbch->am); 1325 free(db_tr, M_FW); 1326 STAILQ_INIT(&dbch->db_trq); 1327 dbch->flags &= ~FWOHCI_DBCH_INIT; 1328 seldestroy(&dbch->xferq.rsel); 1329 } 1330 1331 static void 1332 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1333 { 1334 int idb; 1335 struct fwohcidb_tr *db_tr; 1336 1337 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1338 goto out; 1339 1340 /* create dma_tag for buffers */ 1341 #define MAX_REQCOUNT 0xffff 1342 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1343 /*alignment*/ 1, /*boundary*/ 0, 1344 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1345 /*highaddr*/ BUS_SPACE_MAXADDR, 1346 /*filter*/NULL, /*filterarg*/NULL, 1347 /*maxsize*/ dbch->xferq.psize, 1348 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1349 /*maxsegsz*/ MAX_REQCOUNT, 1350 /*flags*/ 0, 1351 /*lockfunc*/busdma_lock_mutex, 1352 /*lockarg*/FW_GMTX(&sc->fc), 1353 &dbch->dmat)) 1354 return; 1355 1356 /* allocate DB entries and attach one to each DMA channels */ 1357 /* DB entry must start at 16 bytes bounary. */ 1358 STAILQ_INIT(&dbch->db_trq); 1359 db_tr = (struct fwohcidb_tr *) 1360 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1361 M_FW, M_WAITOK | M_ZERO); 1362 if(db_tr == NULL){ 1363 printf("fwohci_db_init: malloc(1) failed\n"); 1364 return; 1365 } 1366 1367 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1368 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1369 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1370 if (dbch->am == NULL) { 1371 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1372 free(db_tr, M_FW); 1373 return; 1374 } 1375 /* Attach DB to DMA ch. */ 1376 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1377 db_tr->dbcnt = 0; 1378 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1379 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1380 /* create dmamap for buffers */ 1381 /* XXX do we need 4bytes alignment tag? */ 1382 /* XXX don't alloc dma_map for AR */ 1383 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1384 printf("fw_bus_dmamap_create failed\n"); 1385 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1386 fwohci_db_free(dbch); 1387 return; 1388 } 1389 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1390 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1391 if (idb % dbch->xferq.bnpacket == 0) 1392 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1393 ].start = (void *)db_tr; 1394 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1395 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1396 ].end = (void *)db_tr; 1397 } 1398 db_tr++; 1399 } 1400 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1401 = STAILQ_FIRST(&dbch->db_trq); 1402 out: 1403 dbch->xferq.queued = 0; 1404 dbch->pdb_tr = NULL; 1405 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1406 dbch->bottom = dbch->top; 1407 dbch->flags = FWOHCI_DBCH_INIT; 1408 selinit(&dbch->xferq.rsel); 1409 } 1410 1411 static int 1412 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1413 { 1414 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1415 int sleepch; 1416 1417 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1418 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1419 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1420 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1421 /* XXX we cannot free buffers until the DMA really stops */ 1422 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1423 fwohci_db_free(&sc->it[dmach]); 1424 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1425 return 0; 1426 } 1427 1428 static int 1429 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1430 { 1431 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1432 int sleepch; 1433 1434 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1435 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1436 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1437 /* XXX we cannot free buffers until the DMA really stops */ 1438 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1439 fwohci_db_free(&sc->ir[dmach]); 1440 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1441 return 0; 1442 } 1443 1444 #if BYTE_ORDER == BIG_ENDIAN 1445 static void 1446 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1447 { 1448 qld[0] = FWOHCI_DMA_READ(qld[0]); 1449 return; 1450 } 1451 #endif 1452 1453 static int 1454 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1455 { 1456 int err = 0; 1457 int idb, z, i, dmach = 0, ldesc; 1458 uint32_t off = 0; 1459 struct fwohcidb_tr *db_tr; 1460 struct fwohcidb *db; 1461 1462 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1463 err = EINVAL; 1464 return err; 1465 } 1466 z = dbch->ndesc; 1467 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1468 if( &sc->it[dmach] == dbch){ 1469 off = OHCI_ITOFF(dmach); 1470 break; 1471 } 1472 } 1473 if(off == 0){ 1474 err = EINVAL; 1475 return err; 1476 } 1477 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1478 return err; 1479 dbch->xferq.flag |= FWXFERQ_RUNNING; 1480 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1481 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1482 } 1483 db_tr = dbch->top; 1484 for (idb = 0; idb < dbch->ndb; idb ++) { 1485 fwohci_add_tx_buf(dbch, db_tr, idb); 1486 if(STAILQ_NEXT(db_tr, link) == NULL){ 1487 break; 1488 } 1489 db = db_tr->db; 1490 ldesc = db_tr->dbcnt - 1; 1491 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1492 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1493 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1494 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1495 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1496 FWOHCI_DMA_SET( 1497 db[ldesc].db.desc.cmd, 1498 OHCI_INTERRUPT_ALWAYS); 1499 /* OHCI 1.1 and above */ 1500 FWOHCI_DMA_SET( 1501 db[0].db.desc.cmd, 1502 OHCI_INTERRUPT_ALWAYS); 1503 } 1504 } 1505 db_tr = STAILQ_NEXT(db_tr, link); 1506 } 1507 FWOHCI_DMA_CLEAR( 1508 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1509 return err; 1510 } 1511 1512 static int 1513 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1514 { 1515 int err = 0; 1516 int idb, z, i, dmach = 0, ldesc; 1517 uint32_t off = 0; 1518 struct fwohcidb_tr *db_tr; 1519 struct fwohcidb *db; 1520 1521 z = dbch->ndesc; 1522 if(&sc->arrq == dbch){ 1523 off = OHCI_ARQOFF; 1524 }else if(&sc->arrs == dbch){ 1525 off = OHCI_ARSOFF; 1526 }else{ 1527 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1528 if( &sc->ir[dmach] == dbch){ 1529 off = OHCI_IROFF(dmach); 1530 break; 1531 } 1532 } 1533 } 1534 if(off == 0){ 1535 err = EINVAL; 1536 return err; 1537 } 1538 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1539 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1540 return err; 1541 }else{ 1542 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1543 err = EBUSY; 1544 return err; 1545 } 1546 } 1547 dbch->xferq.flag |= FWXFERQ_RUNNING; 1548 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1549 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1550 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1551 } 1552 db_tr = dbch->top; 1553 if (db_tr->dbcnt != 0) 1554 goto run; 1555 for (idb = 0; idb < dbch->ndb; idb ++) { 1556 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1557 if (STAILQ_NEXT(db_tr, link) == NULL) 1558 break; 1559 db = db_tr->db; 1560 ldesc = db_tr->dbcnt - 1; 1561 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1562 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1563 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1564 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1565 FWOHCI_DMA_SET( 1566 db[ldesc].db.desc.cmd, 1567 OHCI_INTERRUPT_ALWAYS); 1568 FWOHCI_DMA_CLEAR( 1569 db[ldesc].db.desc.depend, 1570 0xf); 1571 } 1572 } 1573 db_tr = STAILQ_NEXT(db_tr, link); 1574 } 1575 FWOHCI_DMA_CLEAR( 1576 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1577 dbch->buf_offset = 0; 1578 run: 1579 fwdma_sync_multiseg_all(dbch->am, 1580 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1581 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1582 return err; 1583 }else{ 1584 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1585 } 1586 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1587 return err; 1588 } 1589 1590 static int 1591 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1592 { 1593 int sec, cycle, cycle_match; 1594 1595 cycle = cycle_now & 0x1fff; 1596 sec = cycle_now >> 13; 1597 #define CYCLE_MOD 0x10 1598 #if 1 1599 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1600 #else 1601 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1602 #endif 1603 cycle = cycle + CYCLE_DELAY; 1604 if (cycle >= 8000) { 1605 sec ++; 1606 cycle -= 8000; 1607 } 1608 cycle = roundup2(cycle, CYCLE_MOD); 1609 if (cycle >= 8000) { 1610 sec ++; 1611 if (cycle == 8000) 1612 cycle = 0; 1613 else 1614 cycle = CYCLE_MOD; 1615 } 1616 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1617 1618 return(cycle_match); 1619 } 1620 1621 static int 1622 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1623 { 1624 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1625 int err = 0; 1626 unsigned short tag, ich; 1627 struct fwohci_dbch *dbch; 1628 int cycle_match, cycle_now, s, ldesc; 1629 uint32_t stat; 1630 struct fw_bulkxfer *first, *chunk, *prev; 1631 struct fw_xferq *it; 1632 1633 dbch = &sc->it[dmach]; 1634 it = &dbch->xferq; 1635 1636 tag = (it->flag >> 6) & 3; 1637 ich = it->flag & 0x3f; 1638 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1639 dbch->ndb = it->bnpacket * it->bnchunk; 1640 dbch->ndesc = 3; 1641 fwohci_db_init(sc, dbch); 1642 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1643 return ENOMEM; 1644 1645 err = fwohci_tx_enable(sc, dbch); 1646 } 1647 if(err) 1648 return err; 1649 1650 ldesc = dbch->ndesc - 1; 1651 s = splfw(); 1652 FW_GLOCK(fc); 1653 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1654 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1655 struct fwohcidb *db; 1656 1657 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1658 BUS_DMASYNC_PREWRITE); 1659 fwohci_txbufdb(sc, dmach, chunk); 1660 if (prev != NULL) { 1661 db = ((struct fwohcidb_tr *)(prev->end))->db; 1662 #if 0 /* XXX necessary? */ 1663 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1664 OHCI_BRANCH_ALWAYS); 1665 #endif 1666 #if 0 /* if bulkxfer->npacket changes */ 1667 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1668 ((struct fwohcidb_tr *) 1669 (chunk->start))->bus_addr | dbch->ndesc; 1670 #else 1671 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1672 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1673 #endif 1674 } 1675 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1676 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1677 prev = chunk; 1678 } 1679 FW_GUNLOCK(fc); 1680 fwdma_sync_multiseg_all(dbch->am, 1681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1682 splx(s); 1683 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1684 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1685 printf("stat 0x%x\n", stat); 1686 1687 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1688 return 0; 1689 1690 #if 0 1691 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1692 #endif 1693 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1694 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1695 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1696 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1697 1698 first = STAILQ_FIRST(&it->stdma); 1699 OWRITE(sc, OHCI_ITCMD(dmach), 1700 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1701 if (firewire_debug > 1) { 1702 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1703 #if 1 1704 dump_dma(sc, ITX_CH + dmach); 1705 #endif 1706 } 1707 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1708 #if 1 1709 /* Don't start until all chunks are buffered */ 1710 if (STAILQ_FIRST(&it->stfree) != NULL) 1711 goto out; 1712 #endif 1713 #if 1 1714 /* Clear cycle match counter bits */ 1715 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1716 1717 /* 2bit second + 13bit cycle */ 1718 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1719 cycle_match = fwohci_next_cycle(fc, cycle_now); 1720 1721 OWRITE(sc, OHCI_ITCTL(dmach), 1722 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1723 | OHCI_CNTL_DMA_RUN); 1724 #else 1725 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1726 #endif 1727 if (firewire_debug > 1) { 1728 printf("cycle_match: 0x%04x->0x%04x\n", 1729 cycle_now, cycle_match); 1730 dump_dma(sc, ITX_CH + dmach); 1731 dump_db(sc, ITX_CH + dmach); 1732 } 1733 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1734 fw_printf(sc->fc.dev, "IT DMA underrun (0x%08x)\n", stat); 1735 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1736 } 1737 out: 1738 return err; 1739 } 1740 1741 static int 1742 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1743 { 1744 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1745 int err = 0, s, ldesc; 1746 unsigned short tag, ich; 1747 uint32_t stat; 1748 struct fwohci_dbch *dbch; 1749 struct fwohcidb_tr *db_tr; 1750 struct fw_bulkxfer *first, *prev, *chunk; 1751 struct fw_xferq *ir; 1752 1753 dbch = &sc->ir[dmach]; 1754 ir = &dbch->xferq; 1755 1756 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1757 tag = (ir->flag >> 6) & 3; 1758 ich = ir->flag & 0x3f; 1759 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1760 1761 ir->queued = 0; 1762 dbch->ndb = ir->bnpacket * ir->bnchunk; 1763 dbch->ndesc = 2; 1764 fwohci_db_init(sc, dbch); 1765 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1766 return ENOMEM; 1767 err = fwohci_rx_enable(sc, dbch); 1768 } 1769 if(err) 1770 return err; 1771 1772 first = STAILQ_FIRST(&ir->stfree); 1773 if (first == NULL) { 1774 fw_printf(fc->dev, "IR DMA no free chunk\n"); 1775 return 0; 1776 } 1777 1778 ldesc = dbch->ndesc - 1; 1779 s = splfw(); 1780 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1781 FW_GLOCK(fc); 1782 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1783 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1784 struct fwohcidb *db; 1785 1786 #if 1 /* XXX for if_fwe */ 1787 if (chunk->mbuf != NULL) { 1788 db_tr = (struct fwohcidb_tr *)(chunk->start); 1789 db_tr->dbcnt = 1; 1790 err = fw_bus_dmamap_load_mbuf( 1791 dbch->dmat, db_tr->dma_map, 1792 chunk->mbuf, fwohci_execute_db2, db_tr, 1793 BUS_DMA_WAITOK); 1794 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1795 OHCI_UPDATE | OHCI_INPUT_LAST | 1796 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1797 } 1798 #endif 1799 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1800 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1801 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1802 if (prev != NULL) { 1803 db = ((struct fwohcidb_tr *)(prev->end))->db; 1804 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1805 } 1806 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1807 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1808 prev = chunk; 1809 } 1810 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1811 FW_GUNLOCK(fc); 1812 fwdma_sync_multiseg_all(dbch->am, 1813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1814 splx(s); 1815 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1816 if (stat & OHCI_CNTL_DMA_ACTIVE) 1817 return 0; 1818 if (stat & OHCI_CNTL_DMA_RUN) { 1819 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1820 fw_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1821 } 1822 1823 if (firewire_debug) 1824 printf("start IR DMA 0x%x\n", stat); 1825 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1826 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1827 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1828 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1829 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1830 OWRITE(sc, OHCI_IRCMD(dmach), 1831 ((struct fwohcidb_tr *)(first->start))->bus_addr 1832 | dbch->ndesc); 1833 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1834 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1835 #if 0 1836 dump_db(sc, IRX_CH + dmach); 1837 #endif 1838 return err; 1839 } 1840 1841 int 1842 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1843 { 1844 u_int i; 1845 1846 /* Now stopping all DMA channel */ 1847 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1848 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1849 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1850 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1851 1852 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1853 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1854 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1855 } 1856 1857 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1858 fw_drain_txq(&sc->fc); 1859 1860 #if 0 /* Let dcons(4) be accessed */ 1861 /* Stop interrupt */ 1862 OWRITE(sc, FWOHCI_INTMASKCLR, 1863 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1864 | OHCI_INT_PHY_INT 1865 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1866 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1867 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1868 | OHCI_INT_PHY_BUS_R); 1869 1870 /* FLUSH FIFO and reset Transmitter/Reciever */ 1871 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1872 #endif 1873 1874 /* XXX Link down? Bus reset? */ 1875 return 0; 1876 } 1877 1878 int 1879 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1880 { 1881 int i; 1882 struct fw_xferq *ir; 1883 struct fw_bulkxfer *chunk; 1884 1885 fwohci_reset(sc, dev); 1886 /* XXX resume isochronous receive automatically. (how about TX?) */ 1887 for(i = 0; i < sc->fc.nisodma; i ++) { 1888 ir = &sc->ir[i].xferq; 1889 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1890 fw_printf(sc->fc.dev, 1891 "resume iso receive ch: %d\n", i); 1892 ir->flag &= ~FWXFERQ_RUNNING; 1893 /* requeue stdma to stfree */ 1894 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1895 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1896 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1897 } 1898 sc->fc.irx_enable(&sc->fc, i); 1899 } 1900 } 1901 1902 #if defined(__FreeBSD__) 1903 bus_generic_resume(dev); 1904 #elif defined(__NetBSD__) 1905 { 1906 extern int firewire_resume(struct firewire_comm *); 1907 firewire_resume(&sc->fc); 1908 } 1909 #endif 1910 sc->fc.ibr(&sc->fc); 1911 return 0; 1912 } 1913 1914 #ifdef OHCI_DEBUG 1915 static void 1916 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat) 1917 { 1918 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1919 fw_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1920 stat & OHCI_INT_EN ? "DMA_EN ":"", 1921 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1922 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1923 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1924 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1925 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1926 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1927 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1928 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1929 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1930 stat & OHCI_INT_PHY_SID ? "SID ":"", 1931 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1932 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1933 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1934 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1935 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1936 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1937 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1938 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1939 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1940 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1941 stat, OREAD(sc, FWOHCI_INTMASK) 1942 ); 1943 } 1944 #endif 1945 static void 1946 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count) 1947 { 1948 struct firewire_comm *fc = (struct firewire_comm *)sc; 1949 uint32_t node_id, plen; 1950 1951 CTR0(KTR_DEV, "fwohci_intr_core"); 1952 1953 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) { 1954 fc->status = FWBUSRESET; 1955 /* Disable bus reset interrupt until sid recv. */ 1956 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1957 1958 fw_printf(fc->dev, "BUS reset\n"); 1959 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1960 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1961 1962 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1963 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1964 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1965 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1966 1967 if (!kdb_active) 1968 fw_taskqueue_enqueue(sc->fc.taskqueue, 1969 &sc->fwohci_task_busreset); 1970 } 1971 if (stat & OHCI_INT_PHY_SID) { 1972 /* Enable bus reset interrupt */ 1973 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1974 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1975 1976 /* Allow async. request to us */ 1977 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1978 if (firewire_phydma_enable) { 1979 /* allow from all nodes */ 1980 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1981 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1982 /* 0 to 4GB regison */ 1983 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1984 } 1985 /* Set ATRetries register */ 1986 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1987 1988 /* 1989 * Checking whether the node is root or not. If root, turn on 1990 * cycle master. 1991 */ 1992 node_id = OREAD(sc, FWOHCI_NODEID); 1993 plen = OREAD(sc, OHCI_SID_CNT); 1994 1995 fc->nodeid = node_id & 0x3f; 1996 fw_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1997 node_id, (plen >> 16) & 0xff); 1998 if (!(node_id & OHCI_NODE_VALID)) { 1999 printf("Bus reset failure\n"); 2000 goto sidout; 2001 } 2002 2003 /* cycle timer */ 2004 sc->cycle_lost = 0; 2005 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2006 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2007 printf("CYCLEMASTER mode\n"); 2008 OWRITE(sc, OHCI_LNKCTL, 2009 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2010 } else { 2011 printf("non CYCLEMASTER mode\n"); 2012 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2013 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2014 } 2015 2016 fc->status = FWBUSINIT; 2017 2018 if (!kdb_active) 2019 fw_taskqueue_enqueue(sc->fc.taskqueue, 2020 &sc->fwohci_task_sid); 2021 } 2022 sidout: 2023 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active)) 2024 fw_taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma); 2025 2026 CTR0(KTR_DEV, "fwohci_intr_core done"); 2027 } 2028 2029 static void 2030 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count) 2031 { 2032 uint32_t irstat, itstat; 2033 u_int i; 2034 struct firewire_comm *fc = (struct firewire_comm *)sc; 2035 2036 CTR0(KTR_DEV, "fwohci_intr_dma"); 2037 if (stat & OHCI_INT_DMA_IR) { 2038 irstat = fw_atomic_readandclear_int(&sc->irstat); 2039 for(i = 0; i < fc->nisodma ; i++){ 2040 struct fwohci_dbch *dbch; 2041 2042 if((irstat & (1 << i)) != 0){ 2043 dbch = &sc->ir[i]; 2044 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 2045 fw_printf(sc->fc.dev, 2046 "dma(%d) not active\n", i); 2047 continue; 2048 } 2049 fwohci_rbuf_update(sc, i); 2050 } 2051 } 2052 } 2053 if (stat & OHCI_INT_DMA_IT) { 2054 itstat = fw_atomic_readandclear_int(&sc->itstat); 2055 for(i = 0; i < fc->nisodma ; i++){ 2056 if((itstat & (1 << i)) != 0){ 2057 fwohci_tbuf_update(sc, i); 2058 } 2059 } 2060 } 2061 if (stat & OHCI_INT_DMA_PRRS) { 2062 #if 0 2063 dump_dma(sc, ARRS_CH); 2064 dump_db(sc, ARRS_CH); 2065 #endif 2066 fwohci_arcv(sc, &sc->arrs, count); 2067 } 2068 if (stat & OHCI_INT_DMA_PRRQ) { 2069 #if 0 2070 dump_dma(sc, ARRQ_CH); 2071 dump_db(sc, ARRQ_CH); 2072 #endif 2073 fwohci_arcv(sc, &sc->arrq, count); 2074 } 2075 if (stat & OHCI_INT_CYC_LOST) { 2076 if (sc->cycle_lost >= 0) 2077 sc->cycle_lost ++; 2078 if (sc->cycle_lost > 10) { 2079 sc->cycle_lost = -1; 2080 #if 0 2081 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2082 #endif 2083 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2084 fw_printf(fc->dev, "too many cycle lost, " 2085 "no cycle master presents?\n"); 2086 } 2087 } 2088 if (stat & OHCI_INT_DMA_ATRQ) { 2089 fwohci_txd(sc, &(sc->atrq)); 2090 } 2091 if (stat & OHCI_INT_DMA_ATRS) { 2092 fwohci_txd(sc, &(sc->atrs)); 2093 } 2094 if (stat & OHCI_INT_PW_ERR) { 2095 fw_printf(fc->dev, "posted write error\n"); 2096 } 2097 if (stat & OHCI_INT_ERR) { 2098 fw_printf(fc->dev, "unrecoverable error\n"); 2099 } 2100 if (stat & OHCI_INT_PHY_INT) { 2101 fw_printf(fc->dev, "phy int\n"); 2102 } 2103 2104 CTR0(KTR_DEV, "fwohci_intr_dma done"); 2105 return; 2106 } 2107 2108 static void 2109 fwohci_task_busreset(void *arg, int pending) 2110 { 2111 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2112 2113 fw_busreset(&sc->fc, FWBUSRESET); 2114 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2115 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2116 } 2117 2118 static void 2119 fwohci_task_sid(void *arg, int pending) 2120 { 2121 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2122 struct firewire_comm *fc = &sc->fc; 2123 uint32_t *buf; 2124 int i, plen; 2125 2126 plen = OREAD(sc, OHCI_SID_CNT); 2127 2128 if (plen & OHCI_SID_ERR) { 2129 fw_printf(fc->dev, "SID Error\n"); 2130 return; 2131 } 2132 plen &= OHCI_SID_CNT_MASK; 2133 if (plen < 4 || plen > OHCI_SIDSIZE) { 2134 fw_printf(fc->dev, "invalid SID len = %d\n", plen); 2135 return; 2136 } 2137 plen -= 4; /* chop control info */ 2138 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2139 if (buf == NULL) { 2140 fw_printf(fc->dev, "malloc failed\n"); 2141 return; 2142 } 2143 for (i = 0; i < plen / 4; i ++) 2144 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2145 #if 1 /* XXX needed?? */ 2146 /* pending all pre-bus_reset packets */ 2147 fwohci_txd(sc, &sc->atrq); 2148 fwohci_txd(sc, &sc->atrs); 2149 fwohci_arcv(sc, &sc->arrs, -1); 2150 fwohci_arcv(sc, &sc->arrq, -1); 2151 fw_drain_txq(fc); 2152 #endif 2153 fw_sidrcv(fc, buf, plen); 2154 free(buf, M_FW); 2155 } 2156 2157 static void 2158 fwohci_task_dma(void *arg, int pending) 2159 { 2160 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2161 uint32_t stat; 2162 2163 again: 2164 stat = fw_atomic_readandclear_int(&sc->intstat); 2165 if (stat) 2166 fwohci_intr_dma(sc, stat, -1); 2167 else 2168 return; 2169 goto again; 2170 } 2171 2172 static int 2173 fwohci_check_stat(struct fwohci_softc *sc) 2174 { 2175 uint32_t stat, irstat, itstat; 2176 2177 stat = OREAD(sc, FWOHCI_INTSTAT); 2178 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2179 if (stat == 0xffffffff) { 2180 fw_printf(sc->fc.dev, 2181 "device physically ejected?\n"); 2182 return (FILTER_STRAY); 2183 } 2184 if (stat) 2185 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R); 2186 2187 stat &= sc->intmask; 2188 if (stat == 0) 2189 return (FILTER_STRAY); 2190 2191 fw_atomic_set_int(&sc->intstat, stat); 2192 if (stat & OHCI_INT_DMA_IR) { 2193 irstat = OREAD(sc, OHCI_IR_STAT); 2194 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2195 fw_atomic_set_int(&sc->irstat, irstat); 2196 } 2197 if (stat & OHCI_INT_DMA_IT) { 2198 itstat = OREAD(sc, OHCI_IT_STAT); 2199 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2200 fw_atomic_set_int(&sc->itstat, itstat); 2201 } 2202 2203 fwohci_intr_core(sc, stat, -1); 2204 return (FILTER_HANDLED); 2205 } 2206 2207 int 2208 fwohci_filt(void *arg) 2209 { 2210 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2211 2212 if (!(sc->intmask & OHCI_INT_EN)) { 2213 /* polling mode */ 2214 return (FILTER_STRAY); 2215 } 2216 return (fwohci_check_stat(sc)); 2217 } 2218 2219 int 2220 fwohci_intr(void *arg) 2221 { 2222 2223 fwohci_filt(arg); 2224 CTR0(KTR_DEV, "fwohci_intr end"); 2225 return 0; 2226 } 2227 2228 void 2229 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2230 { 2231 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2232 2233 fwohci_check_stat(sc); 2234 } 2235 2236 static void 2237 fwohci_set_intr(struct firewire_comm *fc, int enable) 2238 { 2239 struct fwohci_softc *sc; 2240 2241 sc = (struct fwohci_softc *)fc; 2242 if (firewire_debug) 2243 fw_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2244 if (enable) { 2245 sc->intmask |= OHCI_INT_EN; 2246 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2247 } else { 2248 sc->intmask &= ~OHCI_INT_EN; 2249 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2250 } 2251 } 2252 2253 static void 2254 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2255 { 2256 struct firewire_comm *fc = &sc->fc; 2257 struct fwohcidb *db; 2258 struct fw_bulkxfer *chunk; 2259 struct fw_xferq *it; 2260 uint32_t stat, count; 2261 int s, w=0, ldesc; 2262 2263 it = fc->it[dmach]; 2264 ldesc = sc->it[dmach].ndesc - 1; 2265 s = splfw(); /* unnecessary ? */ 2266 FW_GLOCK(fc); 2267 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2268 if (firewire_debug) 2269 dump_db(sc, ITX_CH + dmach); 2270 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2271 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2272 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2273 >> OHCI_STATUS_SHIFT; 2274 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2275 /* timestamp */ 2276 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2277 & OHCI_COUNT_MASK; 2278 if (stat == 0) 2279 break; 2280 STAILQ_REMOVE_HEAD(&it->stdma, link); 2281 switch (stat & FWOHCIEV_MASK){ 2282 case FWOHCIEV_ACKCOMPL: 2283 #if 0 2284 fw_printf(fc->dev, "0x%08x\n", count); 2285 #endif 2286 break; 2287 default: 2288 fw_printf(fc->dev, 2289 "Isochronous transmit err %02x(%s)\n", 2290 stat, fwohcicode[stat & 0x1f]); 2291 } 2292 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2293 w++; 2294 } 2295 FW_GUNLOCK(fc); 2296 splx(s); 2297 if (w) 2298 wakeup(it); 2299 } 2300 2301 static void 2302 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2303 { 2304 struct firewire_comm *fc = &sc->fc; 2305 struct fwohcidb_tr *db_tr; 2306 struct fw_bulkxfer *chunk; 2307 struct fw_xferq *ir; 2308 uint32_t stat; 2309 int s, w = 0, ldesc; 2310 2311 ir = fc->ir[dmach]; 2312 ldesc = sc->ir[dmach].ndesc - 1; 2313 2314 #if 0 2315 dump_db(sc, dmach); 2316 #endif 2317 s = splfw(); 2318 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2319 FW_GLOCK(fc); 2320 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2321 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2322 db_tr = (struct fwohcidb_tr *)chunk->end; 2323 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2324 >> OHCI_STATUS_SHIFT; 2325 if (stat == 0) 2326 break; 2327 2328 if (chunk->mbuf != NULL) { 2329 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2330 BUS_DMASYNC_POSTREAD); 2331 fw_bus_dmamap_unload( 2332 sc->ir[dmach].dmat, db_tr->dma_map); 2333 } else if (ir->buf != NULL) { 2334 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2335 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2336 } else { 2337 /* XXX */ 2338 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2339 } 2340 2341 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2342 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2343 switch (stat & FWOHCIEV_MASK) { 2344 case FWOHCIEV_ACKCOMPL: 2345 chunk->resp = 0; 2346 break; 2347 default: 2348 chunk->resp = EINVAL; 2349 fw_printf(fc->dev, "Isochronous receive err %02x(%s)\n", 2350 stat, fwohcicode[stat & 0x1f]); 2351 } 2352 w++; 2353 } 2354 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2355 FW_GUNLOCK(fc); 2356 splx(s); 2357 if (w == 0) 2358 return; 2359 if (ir->flag & FWXFERQ_HANDLER) 2360 ir->hand(ir); 2361 else 2362 wakeup(ir); 2363 } 2364 2365 void 2366 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2367 { 2368 uint32_t off, cntl, stat, cmd, match; 2369 2370 if(ch == 0){ 2371 off = OHCI_ATQOFF; 2372 }else if(ch == 1){ 2373 off = OHCI_ATSOFF; 2374 }else if(ch == 2){ 2375 off = OHCI_ARQOFF; 2376 }else if(ch == 3){ 2377 off = OHCI_ARSOFF; 2378 }else if(ch < IRX_CH){ 2379 off = OHCI_ITCTL(ch - ITX_CH); 2380 }else{ 2381 off = OHCI_IRCTL(ch - IRX_CH); 2382 } 2383 cntl = stat = OREAD(sc, off); 2384 cmd = OREAD(sc, off + 0xc); 2385 match = OREAD(sc, off + 0x10); 2386 2387 fw_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2388 ch, 2389 cntl, 2390 cmd, 2391 match); 2392 stat &= 0xffff ; 2393 if (stat) { 2394 fw_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2395 ch, 2396 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2397 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2398 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2399 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2400 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2401 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2402 fwohcicode[stat & 0x1f], 2403 stat & 0x1f 2404 ); 2405 }else{ 2406 fw_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2407 } 2408 } 2409 2410 void 2411 dump_db(struct fwohci_softc *sc, uint32_t ch) 2412 { 2413 struct fwohci_dbch *dbch; 2414 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2415 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2416 int idb, jdb; 2417 uint32_t cmd, off; 2418 if(ch == 0){ 2419 off = OHCI_ATQOFF; 2420 dbch = &sc->atrq; 2421 }else if(ch == 1){ 2422 off = OHCI_ATSOFF; 2423 dbch = &sc->atrs; 2424 }else if(ch == 2){ 2425 off = OHCI_ARQOFF; 2426 dbch = &sc->arrq; 2427 }else if(ch == 3){ 2428 off = OHCI_ARSOFF; 2429 dbch = &sc->arrs; 2430 }else if(ch < IRX_CH){ 2431 off = OHCI_ITCTL(ch - ITX_CH); 2432 dbch = &sc->it[ch - ITX_CH]; 2433 }else { 2434 off = OHCI_IRCTL(ch - IRX_CH); 2435 dbch = &sc->ir[ch - IRX_CH]; 2436 } 2437 cmd = OREAD(sc, off + 0xc); 2438 2439 if( dbch->ndb == 0 ){ 2440 fw_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2441 return; 2442 } 2443 pp = dbch->top; 2444 prev = pp->db; 2445 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2446 cp = STAILQ_NEXT(pp, link); 2447 if(cp == NULL){ 2448 curr = NULL; 2449 goto outdb; 2450 } 2451 np = STAILQ_NEXT(cp, link); 2452 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2453 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2454 curr = cp->db; 2455 if(np != NULL){ 2456 next = np->db; 2457 }else{ 2458 next = NULL; 2459 } 2460 goto outdb; 2461 } 2462 } 2463 pp = STAILQ_NEXT(pp, link); 2464 if(pp == NULL){ 2465 curr = NULL; 2466 goto outdb; 2467 } 2468 prev = pp->db; 2469 } 2470 outdb: 2471 if( curr != NULL){ 2472 #if 0 2473 printf("Prev DB %d\n", ch); 2474 print_db(pp, prev, ch, dbch->ndesc); 2475 #endif 2476 printf("Current DB %d\n", ch); 2477 print_db(cp, curr, ch, dbch->ndesc); 2478 #if 0 2479 printf("Next DB %d\n", ch); 2480 print_db(np, next, ch, dbch->ndesc); 2481 #endif 2482 }else{ 2483 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2484 } 2485 return; 2486 } 2487 2488 void 2489 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2490 uint32_t ch, uint32_t hogemax) 2491 { 2492 fwohcireg_t stat; 2493 int i, key; 2494 uint32_t cmd, res; 2495 2496 if(db == NULL){ 2497 printf("No Descriptor is found\n"); 2498 return; 2499 } 2500 2501 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2502 ch, 2503 "Current", 2504 "OP ", 2505 "KEY", 2506 "INT", 2507 "BR ", 2508 "len", 2509 "Addr", 2510 "Depend", 2511 "Stat", 2512 "Cnt"); 2513 for( i = 0 ; i <= hogemax ; i ++){ 2514 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2515 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2516 key = cmd & OHCI_KEY_MASK; 2517 stat = res >> OHCI_STATUS_SHIFT; 2518 #if defined(__DragonFly__) || \ 2519 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2520 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2521 db_tr->bus_addr, 2522 #else 2523 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2524 (uintmax_t)db_tr->bus_addr, 2525 #endif 2526 dbcode[(cmd >> 28) & 0xf], 2527 dbkey[(cmd >> 24) & 0x7], 2528 dbcond[(cmd >> 20) & 0x3], 2529 dbcond[(cmd >> 18) & 0x3], 2530 cmd & OHCI_COUNT_MASK, 2531 FWOHCI_DMA_READ(db[i].db.desc.addr), 2532 FWOHCI_DMA_READ(db[i].db.desc.depend), 2533 stat, 2534 res & OHCI_COUNT_MASK); 2535 if(stat & 0xff00){ 2536 printf(" %s%s%s%s%s%s %s(%x)\n", 2537 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2538 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2539 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2540 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2541 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2542 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2543 fwohcicode[stat & 0x1f], 2544 stat & 0x1f 2545 ); 2546 }else{ 2547 printf(" Nostat\n"); 2548 } 2549 if(key == OHCI_KEY_ST2 ){ 2550 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2551 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2552 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2553 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2554 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2555 } 2556 if(key == OHCI_KEY_DEVICE){ 2557 return; 2558 } 2559 if((cmd & OHCI_BRANCH_MASK) 2560 == OHCI_BRANCH_ALWAYS){ 2561 return; 2562 } 2563 if((cmd & OHCI_CMD_MASK) 2564 == OHCI_OUTPUT_LAST){ 2565 return; 2566 } 2567 if((cmd & OHCI_CMD_MASK) 2568 == OHCI_INPUT_LAST){ 2569 return; 2570 } 2571 if(key == OHCI_KEY_ST2 ){ 2572 i++; 2573 } 2574 } 2575 return; 2576 } 2577 2578 void 2579 fwohci_ibr(struct firewire_comm *fc) 2580 { 2581 struct fwohci_softc *sc; 2582 uint32_t fun; 2583 2584 fw_printf(fc->dev, "Initiate bus reset\n"); 2585 sc = (struct fwohci_softc *)fc; 2586 2587 /* 2588 * Make sure our cached values from the config rom are 2589 * initialised. 2590 */ 2591 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2592 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2593 2594 /* 2595 * Set root hold-off bit so that non cyclemaster capable node 2596 * shouldn't became the root node. 2597 */ 2598 #if 1 2599 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2600 fun |= FW_PHY_IBR | FW_PHY_RHB; 2601 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2602 #else /* Short bus reset */ 2603 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2604 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2605 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2606 #endif 2607 } 2608 2609 void 2610 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2611 { 2612 struct fwohcidb_tr *db_tr, *fdb_tr; 2613 struct fwohci_dbch *dbch; 2614 struct fwohcidb *db; 2615 struct fw_pkt *fp; 2616 struct fwohci_txpkthdr *ohcifp; 2617 unsigned short chtag; 2618 int idb; 2619 2620 FW_GLOCK_ASSERT(&sc->fc); 2621 2622 dbch = &sc->it[dmach]; 2623 chtag = sc->it[dmach].xferq.flag & 0xff; 2624 2625 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2626 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2627 /* 2628 fw_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2629 */ 2630 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2631 db = db_tr->db; 2632 fp = (struct fw_pkt *)db_tr->buf; 2633 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2634 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2635 ohcifp->mode.common.spd = 0 & 0x7; 2636 ohcifp->mode.stream.len = fp->mode.stream.len; 2637 ohcifp->mode.stream.chtag = chtag; 2638 ohcifp->mode.stream.tcode = 0xa; 2639 #if BYTE_ORDER == BIG_ENDIAN 2640 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2641 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2642 #endif 2643 2644 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2645 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2646 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2647 #if 0 /* if bulkxfer->npackets changes */ 2648 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2649 | OHCI_UPDATE 2650 | OHCI_BRANCH_ALWAYS; 2651 db[0].db.desc.depend = 2652 = db[dbch->ndesc - 1].db.desc.depend 2653 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2654 #else 2655 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2656 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2657 #endif 2658 bulkxfer->end = (void *)db_tr; 2659 db_tr = STAILQ_NEXT(db_tr, link); 2660 } 2661 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2662 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2663 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2664 #if 0 /* if bulkxfer->npackets changes */ 2665 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2666 /* OHCI 1.1 and above */ 2667 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2668 #endif 2669 /* 2670 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2671 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2672 fw_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2673 */ 2674 return; 2675 } 2676 2677 static int 2678 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2679 int poffset) 2680 { 2681 struct fwohcidb *db = db_tr->db; 2682 struct fw_xferq *it; 2683 int err = 0; 2684 2685 it = &dbch->xferq; 2686 if(it->buf == 0){ 2687 err = EINVAL; 2688 return err; 2689 } 2690 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2691 db_tr->dbcnt = 3; 2692 2693 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2694 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2695 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2696 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2697 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2698 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2699 2700 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2701 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2702 #if 1 2703 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2704 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2705 #endif 2706 return 0; 2707 } 2708 2709 int 2710 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2711 int poffset, struct fwdma_alloc *dummy_dma) 2712 { 2713 struct fwohcidb *db = db_tr->db; 2714 struct fw_xferq *ir; 2715 int i, ldesc; 2716 bus_addr_t dbuf[2]; 2717 int dsiz[2]; 2718 2719 ir = &dbch->xferq; 2720 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2721 if (db_tr->buf == NULL) 2722 db_tr->buf = fwdma_malloc_size( 2723 dbch->dmat, &db_tr->dma_map, 2724 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2725 if (db_tr->buf == NULL) 2726 return(ENOMEM); 2727 db_tr->dbcnt = 1; 2728 dsiz[0] = ir->psize; 2729 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2730 BUS_DMASYNC_PREREAD); 2731 } else { 2732 db_tr->dbcnt = 0; 2733 if (dummy_dma != NULL) { 2734 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2735 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2736 } 2737 dsiz[db_tr->dbcnt] = ir->psize; 2738 if (ir->buf != NULL) { 2739 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2740 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2741 } 2742 db_tr->dbcnt++; 2743 } 2744 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2745 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2746 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2747 if (ir->flag & FWXFERQ_STREAM) { 2748 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2749 } 2750 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2751 } 2752 ldesc = db_tr->dbcnt - 1; 2753 if (ir->flag & FWXFERQ_STREAM) { 2754 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2755 } 2756 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2757 return 0; 2758 } 2759 2760 2761 static int 2762 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2763 { 2764 struct fw_pkt *fp0; 2765 uint32_t ld0; 2766 int slen, hlen; 2767 #if BYTE_ORDER == BIG_ENDIAN 2768 int i; 2769 #endif 2770 2771 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2772 #if 0 2773 printf("ld0: x%08x\n", ld0); 2774 #endif 2775 fp0 = (struct fw_pkt *)&ld0; 2776 /* determine length to swap */ 2777 switch (fp0->mode.common.tcode) { 2778 case FWTCODE_WRES: 2779 CTR0(KTR_DEV, "WRES"); 2780 case FWTCODE_RREQQ: 2781 case FWTCODE_WREQQ: 2782 case FWTCODE_RRESQ: 2783 case FWOHCITCODE_PHY: 2784 slen = 12; 2785 break; 2786 case FWTCODE_RREQB: 2787 case FWTCODE_WREQB: 2788 case FWTCODE_LREQ: 2789 case FWTCODE_RRESB: 2790 case FWTCODE_LRES: 2791 slen = 16; 2792 break; 2793 default: 2794 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2795 return(0); 2796 } 2797 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2798 if (hlen > len) { 2799 if (firewire_debug) 2800 printf("splitted header\n"); 2801 return(-hlen); 2802 } 2803 #if BYTE_ORDER == BIG_ENDIAN 2804 for(i = 0; i < slen/4; i ++) 2805 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2806 #endif 2807 return(hlen); 2808 } 2809 2810 static int 2811 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2812 { 2813 const struct tcode_info *info; 2814 int r; 2815 2816 info = &tinfo[fp->mode.common.tcode]; 2817 r = info->hdr_len + sizeof(uint32_t); 2818 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2819 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2820 2821 if (r == sizeof(uint32_t)) { 2822 /* XXX */ 2823 fw_printf(sc->fc.dev, "Unknown tcode %d\n", 2824 fp->mode.common.tcode); 2825 return (-1); 2826 } 2827 2828 if (r > dbch->xferq.psize) { 2829 fw_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2830 return (-1); 2831 /* panic ? */ 2832 } 2833 2834 return r; 2835 } 2836 2837 static void 2838 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2839 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2840 { 2841 struct fwohcidb *db = &db_tr->db[0]; 2842 2843 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2844 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2845 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2846 fwdma_sync_multiseg_all(dbch->am, 2847 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2848 dbch->bottom = db_tr; 2849 2850 if (wake) 2851 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2852 } 2853 2854 static void 2855 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2856 { 2857 struct fwohcidb_tr *db_tr; 2858 struct iovec vec[2]; 2859 struct fw_pkt pktbuf; 2860 int nvec; 2861 struct fw_pkt *fp; 2862 uint8_t *ld; 2863 uint32_t stat, off, status, event; 2864 u_int spd; 2865 int len, plen, hlen, pcnt, offset; 2866 int s; 2867 void *buf; 2868 int resCount; 2869 2870 CTR0(KTR_DEV, "fwohci_arv"); 2871 2872 if(&sc->arrq == dbch){ 2873 off = OHCI_ARQOFF; 2874 }else if(&sc->arrs == dbch){ 2875 off = OHCI_ARSOFF; 2876 }else{ 2877 return; 2878 } 2879 2880 s = splfw(); 2881 db_tr = dbch->top; 2882 pcnt = 0; 2883 /* XXX we cannot handle a packet which lies in more than two buf */ 2884 fwdma_sync_multiseg_all(dbch->am, 2885 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2886 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2887 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2888 while (status & OHCI_CNTL_DMA_ACTIVE) { 2889 #if 0 2890 2891 if (off == OHCI_ARQOFF) 2892 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2893 db_tr->bus_addr, status, resCount); 2894 #endif 2895 len = dbch->xferq.psize - resCount; 2896 ld = (uint8_t *)db_tr->buf; 2897 if (dbch->pdb_tr == NULL) { 2898 len -= dbch->buf_offset; 2899 ld += dbch->buf_offset; 2900 } 2901 if (len > 0) 2902 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2903 BUS_DMASYNC_POSTREAD); 2904 while (len > 0 ) { 2905 if (count >= 0 && count-- == 0) 2906 goto out; 2907 if(dbch->pdb_tr != NULL){ 2908 /* we have a fragment in previous buffer */ 2909 int rlen; 2910 2911 offset = dbch->buf_offset; 2912 if (offset < 0) 2913 offset = - offset; 2914 buf = (char *)dbch->pdb_tr->buf + offset; 2915 rlen = dbch->xferq.psize - offset; 2916 if (firewire_debug) 2917 printf("rlen=%d, offset=%d\n", 2918 rlen, dbch->buf_offset); 2919 if (dbch->buf_offset < 0) { 2920 /* splitted in header, pull up */ 2921 char *p; 2922 2923 p = (char *)&pktbuf; 2924 bcopy(buf, p, rlen); 2925 p += rlen; 2926 /* this must be too long but harmless */ 2927 rlen = sizeof(pktbuf) - rlen; 2928 if (rlen < 0) 2929 printf("why rlen < 0\n"); 2930 bcopy(db_tr->buf, p, rlen); 2931 ld += rlen; 2932 len -= rlen; 2933 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2934 if (hlen <= 0) { 2935 printf("hlen should be positive."); 2936 goto err; 2937 } 2938 offset = sizeof(pktbuf); 2939 vec[0].iov_base = (char *)&pktbuf; 2940 vec[0].iov_len = offset; 2941 } else { 2942 /* splitted in payload */ 2943 offset = rlen; 2944 vec[0].iov_base = buf; 2945 vec[0].iov_len = rlen; 2946 } 2947 fp=(struct fw_pkt *)vec[0].iov_base; 2948 nvec = 1; 2949 } else { 2950 /* no fragment in previous buffer */ 2951 fp=(struct fw_pkt *)ld; 2952 hlen = fwohci_arcv_swap(fp, len); 2953 if (hlen == 0) 2954 goto err; 2955 if (hlen < 0) { 2956 dbch->pdb_tr = db_tr; 2957 dbch->buf_offset = - dbch->buf_offset; 2958 /* sanity check */ 2959 if (resCount != 0) { 2960 printf("resCount=%d hlen=%d\n", 2961 resCount, hlen); 2962 goto err; 2963 } 2964 goto out; 2965 } 2966 offset = 0; 2967 nvec = 0; 2968 } 2969 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2970 if (plen < 0) { 2971 /* minimum header size + trailer 2972 = sizeof(fw_pkt) so this shouldn't happens */ 2973 printf("plen(%d) is negative! offset=%d\n", 2974 plen, offset); 2975 goto err; 2976 } 2977 if (plen > 0) { 2978 len -= plen; 2979 if (len < 0) { 2980 dbch->pdb_tr = db_tr; 2981 if (firewire_debug) 2982 printf("splitted payload\n"); 2983 /* sanity check */ 2984 if (resCount != 0) { 2985 printf("resCount=%d plen=%d" 2986 " len=%d\n", 2987 resCount, plen, len); 2988 goto err; 2989 } 2990 goto out; 2991 } 2992 vec[nvec].iov_base = ld; 2993 vec[nvec].iov_len = plen; 2994 nvec ++; 2995 ld += plen; 2996 } 2997 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2998 if (nvec == 0) 2999 printf("nvec == 0\n"); 3000 3001 /* DMA result-code will be written at the tail of packet */ 3002 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3003 #if 0 3004 printf("plen: %d, stat %x\n", 3005 plen ,stat); 3006 #endif 3007 spd = (stat >> 21) & 0x3; 3008 event = (stat >> 16) & 0x1f; 3009 switch (event) { 3010 case FWOHCIEV_ACKPEND: 3011 #if 0 3012 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3013 #endif 3014 /* fall through */ 3015 case FWOHCIEV_ACKCOMPL: 3016 { 3017 struct fw_rcv_buf rb; 3018 3019 if ((vec[nvec-1].iov_len -= 3020 sizeof(struct fwohci_trailer)) == 0) 3021 nvec--; 3022 rb.fc = &sc->fc; 3023 rb.vec = vec; 3024 rb.nvec = nvec; 3025 rb.spd = spd; 3026 fw_rcv(&rb); 3027 break; 3028 } 3029 case FWOHCIEV_BUSRST: 3030 if ((sc->fc.status != FWBUSRESET) && 3031 (sc->fc.status != FWBUSINIT)) 3032 printf("got BUSRST packet!?\n"); 3033 break; 3034 default: 3035 fw_printf(sc->fc.dev, 3036 "Async DMA Receive error err=%02x %s" 3037 " plen=%d offset=%d len=%d status=0x%08x" 3038 " tcode=0x%x, stat=0x%08x\n", 3039 event, fwohcicode[event], plen, 3040 dbch->buf_offset, len, 3041 OREAD(sc, OHCI_DMACTL(off)), 3042 fp->mode.common.tcode, stat); 3043 #if 1 /* XXX */ 3044 goto err; 3045 #endif 3046 break; 3047 } 3048 pcnt ++; 3049 if (dbch->pdb_tr != NULL) { 3050 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3051 off, 1); 3052 dbch->pdb_tr = NULL; 3053 } 3054 3055 } 3056 out: 3057 if (resCount == 0) { 3058 /* done on this buffer */ 3059 if (dbch->pdb_tr == NULL) { 3060 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3061 dbch->buf_offset = 0; 3062 } else 3063 if (dbch->pdb_tr != db_tr) 3064 printf("pdb_tr != db_tr\n"); 3065 db_tr = STAILQ_NEXT(db_tr, link); 3066 fwdma_sync_multiseg_all(dbch->am, 3067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3068 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3069 >> OHCI_STATUS_SHIFT; 3070 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3071 & OHCI_COUNT_MASK; 3072 /* XXX check buffer overrun */ 3073 dbch->top = db_tr; 3074 } else { 3075 dbch->buf_offset = dbch->xferq.psize - resCount; 3076 fw_bus_dmamap_sync( 3077 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3078 break; 3079 } 3080 /* XXX make sure DMA is not dead */ 3081 } 3082 #if 0 3083 if (pcnt < 1) 3084 printf("fwohci_arcv: no packets\n"); 3085 #endif 3086 fwdma_sync_multiseg_all(dbch->am, 3087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3088 splx(s); 3089 return; 3090 3091 err: 3092 fw_printf(sc->fc.dev, "AR DMA status=%x, ", 3093 OREAD(sc, OHCI_DMACTL(off))); 3094 dbch->pdb_tr = NULL; 3095 /* skip until resCount != 0 */ 3096 printf(" skip buffer"); 3097 while (resCount == 0) { 3098 printf(" #"); 3099 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3100 db_tr = STAILQ_NEXT(db_tr, link); 3101 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3102 & OHCI_COUNT_MASK; 3103 } 3104 printf(" done\n"); 3105 dbch->top = db_tr; 3106 dbch->buf_offset = dbch->xferq.psize - resCount; 3107 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3108 fwdma_sync_multiseg_all( 3109 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3110 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3111 splx(s); 3112 } 3113 #if defined(__NetBSD__) 3114 3115 int 3116 fwohci_print(void *aux, const char *pnp) 3117 { 3118 struct fw_attach_args *fwa = (struct fw_attach_args *)aux; 3119 3120 if (pnp) 3121 aprint_normal("%s at %s", fwa->name, pnp); 3122 3123 return UNCONF; 3124 } 3125 #endif 3126
Indexes created Sat Sep 27 22:09:54 GMT 2025