fwohci.c revision 1.112
1 /* $NetBSD: fwohci.c,v 1.112 2007/11/06 15:24:11 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.93 2007/06/08 09:04:30 simokawa Exp $ 37 * 38 */ 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.112 2007/11/06 15:24:11 kiyohara Exp $"); 41 42 #define ATRQ_CH 0 43 #define ATRS_CH 1 44 #define ARRQ_CH 2 45 #define ARRS_CH 3 46 #define ITX_CH 4 47 #define IRX_CH 0x24 48 49 #if defined(__FreeBSD__) 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 #include <sys/bus.h> 57 #include <sys/kernel.h> 58 #include <sys/conf.h> 59 #include <sys/endian.h> 60 #include <sys/kdb.h> 61 62 #include <machine/bus.h> 63 64 #if defined(__DragonFly__) || __FreeBSD_version < 500000 65 #include <machine/clock.h> /* for DELAY() */ 66 #endif 67 68 #ifdef __DragonFly__ 69 #include "fw_port.h" 70 #include "firewire.h" 71 #include "firewirereg.h" 72 #include "fwdma.h" 73 #include "fwohcireg.h" 74 #include "fwohcivar.h" 75 #include "firewire_phy.h" 76 #else 77 #include <dev/firewire/fw_port.h> 78 #include <dev/firewire/firewire.h> 79 #include <dev/firewire/firewirereg.h> 80 #include <dev/firewire/fwdma.h> 81 #include <dev/firewire/fwohcireg.h> 82 #include <dev/firewire/fwohcivar.h> 83 #include <dev/firewire/firewire_phy.h> 84 #endif 85 #elif defined(__NetBSD__) 86 #include <sys/param.h> 87 #include <sys/device.h> 88 #include <sys/errno.h> 89 #include <sys/conf.h> 90 #include <sys/kernel.h> 91 #include <sys/malloc.h> 92 #include <sys/mbuf.h> 93 #include <sys/proc.h> 94 #include <sys/reboot.h> 95 #include <sys/sysctl.h> 96 #include <sys/systm.h> 97 98 #include <sys/bus.h> 99 100 #include <dev/ieee1394/fw_port.h> 101 #include <dev/ieee1394/firewire.h> 102 #include <dev/ieee1394/firewirereg.h> 103 #include <dev/ieee1394/fwdma.h> 104 #include <dev/ieee1394/fwohcireg.h> 105 #include <dev/ieee1394/fwohcivar.h> 106 #include <dev/ieee1394/firewire_phy.h> 107 108 #include "ioconf.h" 109 #endif 110 111 #undef OHCI_DEBUG 112 113 static int nocyclemaster = 0; 114 int firewire_phydma_enable = 1; 115 #if defined(__FreeBSD__) 116 SYSCTL_DECL(_hw_firewire); 117 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 118 "Do not send cycle start packets"); 119 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW, 120 &firewire_phydma_enable, 1, "Allow physical request DMA from firewire"); 121 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable); 122 #elif defined(__NetBSD__) 123 /* 124 * Setup sysctl(3) MIB, hw.fwohci.* 125 * 126 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 127 */ 128 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 129 { 130 int rc, fwohci_node_num; 131 const struct sysctlnode *node; 132 133 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 134 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 135 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 136 goto err; 137 } 138 139 if ((rc = sysctl_createv(clog, 0, NULL, &node, 140 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 141 SYSCTL_DESCR("fwohci controls"), 142 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 143 goto err; 144 } 145 fwohci_node_num = node->sysctl_num; 146 147 /* fwohci no cyclemaster flag */ 148 if ((rc = sysctl_createv(clog, 0, NULL, &node, 149 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 150 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 151 NULL, 0, &nocyclemaster, 152 0, CTL_HW, fwohci_node_num, CTL_CREATE, CTL_EOL)) != 0) { 153 goto err; 154 } 155 156 /* fwohci physical request DMA enable */ 157 if ((rc = sysctl_createv(clog, 0, NULL, &node, 158 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, "phydma_enable", 159 SYSCTL_DESCR("Allow physical request DMA from firewire"), 160 NULL, 0, &firewire_phydma_enable, 161 0, CTL_HW, fwohci_node_num, CTL_CREATE, CTL_EOL)) != 0) { 162 goto err; 163 } 164 return; 165 166 err: 167 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 168 } 169 #endif 170 171 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 172 "STOR","LOAD","NOP ","STOP", 173 "", "", "", "", "", "", "", ""}; 174 175 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 176 "UNDEF","REG","SYS","DEV"}; 177 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 178 static const char * const fwohcicode[32] = { 179 "No stat","Undef","long","miss Ack err", 180 "FIFO underrun","FIFO overrun","desc err", "data read err", 181 "data write err","bus reset","timeout","tcode err", 182 "Undef","Undef","unknown event","flushed", 183 "Undef","ack complete","ack pend","Undef", 184 "ack busy_X","ack busy_A","ack busy_B","Undef", 185 "Undef","Undef","Undef","ack tardy", 186 "Undef","ack data_err","ack type_err",""}; 187 188 #define MAX_SPEED 3 189 extern const char *fw_linkspeed[]; 190 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 191 192 static const struct tcode_info tinfo[] = { 193 /* hdr_len block flag valid_response*/ 194 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES}, 195 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES}, 196 /* 2 WRES */ {12, FWTI_RES, 0xff}, 197 /* 3 XXX */ { 0, 0, 0xff}, 198 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ}, 199 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB}, 200 /* 6 RRESQ */ {16, FWTI_RES, 0xff}, 201 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 202 /* 8 CYCS */ { 0, 0, 0xff}, 203 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES}, 204 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff}, 205 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 206 /* c XXX */ { 0, 0, 0xff}, 207 /* d XXX */ { 0, 0, 0xff}, 208 /* e PHY */ {12, FWTI_REQ, 0xff}, 209 /* f XXX */ { 0, 0, 0xff} 210 }; 211 212 #define OHCI_WRITE_SIGMASK 0xffff0000 213 #define OHCI_READ_SIGMASK 0xffff0000 214 215 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 216 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 217 218 static void fwohci_ibr (struct firewire_comm *); 219 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 220 static void fwohci_db_free (struct fwohci_dbch *); 221 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 222 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 223 static void fwohci_start_atq (struct firewire_comm *); 224 static void fwohci_start_ats (struct firewire_comm *); 225 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 226 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 227 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 228 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 229 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 230 static int fwohci_irx_enable (struct firewire_comm *, int); 231 static int fwohci_irx_disable (struct firewire_comm *, int); 232 #if BYTE_ORDER == BIG_ENDIAN 233 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 234 #endif 235 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 236 static int fwohci_itx_disable (struct firewire_comm *, int); 237 static void fwohci_timeout (void *); 238 static void fwohci_set_intr (struct firewire_comm *, int); 239 240 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 241 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 242 static void dump_db (struct fwohci_softc *, uint32_t); 243 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 244 static void dump_dma (struct fwohci_softc *, uint32_t); 245 static uint32_t fwohci_cyctimer (struct firewire_comm *); 246 static void fwohci_rbuf_update (struct fwohci_softc *, int); 247 static void fwohci_tbuf_update (struct fwohci_softc *, int); 248 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 249 static void fwohci_task_busreset(void *, int); 250 static void fwohci_task_sid(void *, int); 251 static void fwohci_task_dma(void *, int); 252 #if defined(__NetBSD__) 253 int fwohci_print(void *, const char *); 254 #endif 255 256 /* 257 * memory allocated for DMA programs 258 */ 259 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 260 261 #define NDB FWMAXQUEUE 262 263 #define OHCI_VERSION 0x00 264 #define OHCI_ATRETRY 0x08 265 #define OHCI_CROMHDR 0x18 266 #define OHCI_BUS_OPT 0x20 267 #define OHCI_BUSIRMC (1 << 31) 268 #define OHCI_BUSCMC (1 << 30) 269 #define OHCI_BUSISC (1 << 29) 270 #define OHCI_BUSBMC (1 << 28) 271 #define OHCI_BUSPMC (1 << 27) 272 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 273 OHCI_BUSBMC | OHCI_BUSPMC 274 275 #define OHCI_EUID_HI 0x24 276 #define OHCI_EUID_LO 0x28 277 278 #define OHCI_CROMPTR 0x34 279 #define OHCI_HCCCTL 0x50 280 #define OHCI_HCCCTLCLR 0x54 281 #define OHCI_AREQHI 0x100 282 #define OHCI_AREQHICLR 0x104 283 #define OHCI_AREQLO 0x108 284 #define OHCI_AREQLOCLR 0x10c 285 #define OHCI_PREQHI 0x110 286 #define OHCI_PREQHICLR 0x114 287 #define OHCI_PREQLO 0x118 288 #define OHCI_PREQLOCLR 0x11c 289 #define OHCI_PREQUPPER 0x120 290 291 #define OHCI_SID_BUF 0x64 292 #define OHCI_SID_CNT 0x68 293 #define OHCI_SID_ERR (1 << 31) 294 #define OHCI_SID_CNT_MASK 0xffc 295 296 #define OHCI_IT_STAT 0x90 297 #define OHCI_IT_STATCLR 0x94 298 #define OHCI_IT_MASK 0x98 299 #define OHCI_IT_MASKCLR 0x9c 300 301 #define OHCI_IR_STAT 0xa0 302 #define OHCI_IR_STATCLR 0xa4 303 #define OHCI_IR_MASK 0xa8 304 #define OHCI_IR_MASKCLR 0xac 305 306 #define OHCI_LNKCTL 0xe0 307 #define OHCI_LNKCTLCLR 0xe4 308 309 #define OHCI_PHYACCESS 0xec 310 #define OHCI_CYCLETIMER 0xf0 311 312 #define OHCI_DMACTL(off) (off) 313 #define OHCI_DMACTLCLR(off) (off + 4) 314 #define OHCI_DMACMD(off) (off + 0xc) 315 #define OHCI_DMAMATCH(off) (off + 0x10) 316 317 #define OHCI_ATQOFF 0x180 318 #define OHCI_ATQCTL OHCI_ATQOFF 319 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 320 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 321 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 322 323 #define OHCI_ATSOFF 0x1a0 324 #define OHCI_ATSCTL OHCI_ATSOFF 325 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 326 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 327 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 328 329 #define OHCI_ARQOFF 0x1c0 330 #define OHCI_ARQCTL OHCI_ARQOFF 331 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 332 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 333 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 334 335 #define OHCI_ARSOFF 0x1e0 336 #define OHCI_ARSCTL OHCI_ARSOFF 337 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 338 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 339 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 340 341 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 342 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 343 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 344 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 345 346 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 347 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 348 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 349 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 350 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 351 352 #if defined(__FreeBSD__) 353 d_ioctl_t fwohci_ioctl; 354 #elif defined(__NetBSD__) 355 dev_type_ioctl(fwohci_ioctl); 356 #endif 357 358 /* 359 * Communication with PHY device 360 */ 361 /* XXX need lock for phy access */ 362 static uint32_t 363 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 364 { 365 uint32_t fun; 366 367 addr &= 0xf; 368 data &= 0xff; 369 370 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 371 OWRITE(sc, OHCI_PHYACCESS, fun); 372 DELAY(100); 373 374 return(fwphy_rddata( sc, addr)); 375 } 376 377 static uint32_t 378 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 379 { 380 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 381 int i; 382 uint32_t bm; 383 384 #define OHCI_CSR_DATA 0x0c 385 #define OHCI_CSR_COMP 0x10 386 #define OHCI_CSR_CONT 0x14 387 #define OHCI_BUS_MANAGER_ID 0 388 389 OWRITE(sc, OHCI_CSR_DATA, node); 390 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 391 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 392 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 393 DELAY(10); 394 bm = OREAD(sc, OHCI_CSR_DATA); 395 if((bm & 0x3f) == 0x3f) 396 bm = node; 397 if (firewire_debug) 398 fw_printf(sc->fc.dev, 399 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 400 401 return(bm); 402 } 403 404 static uint32_t 405 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 406 { 407 uint32_t fun, stat; 408 u_int i, retry = 0; 409 410 addr &= 0xf; 411 #define MAX_RETRY 100 412 again: 413 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 414 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 415 OWRITE(sc, OHCI_PHYACCESS, fun); 416 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 417 fun = OREAD(sc, OHCI_PHYACCESS); 418 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 419 break; 420 DELAY(100); 421 } 422 if(i >= MAX_RETRY) { 423 if (firewire_debug) 424 fw_printf(sc->fc.dev, "phy read failed(1).\n"); 425 if (++retry < MAX_RETRY) { 426 DELAY(100); 427 goto again; 428 } 429 } 430 /* Make sure that SCLK is started */ 431 stat = OREAD(sc, FWOHCI_INTSTAT); 432 if ((stat & OHCI_INT_REG_FAIL) != 0 || 433 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 434 if (firewire_debug) 435 fw_printf(sc->fc.dev, "phy read failed(2).\n"); 436 if (++retry < MAX_RETRY) { 437 DELAY(100); 438 goto again; 439 } 440 } 441 if (firewire_debug || retry >= MAX_RETRY) 442 fw_printf(sc->fc.dev, 443 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 444 #undef MAX_RETRY 445 return((fun >> PHYDEV_RDDATA )& 0xff); 446 } 447 /* Device specific ioctl. */ 448 FW_IOCTL(fwohci) 449 { 450 FW_IOCTL_START; 451 struct fwohci_softc *fc; 452 int err = 0; 453 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 454 uint32_t *dmach = (uint32_t *) data; 455 456 if(sc == NULL){ 457 return(EINVAL); 458 } 459 fc = (struct fwohci_softc *)sc->fc; 460 461 if (!data) 462 return(EINVAL); 463 464 switch (cmd) { 465 case FWOHCI_WRREG: 466 #define OHCI_MAX_REG 0x800 467 if(reg->addr <= OHCI_MAX_REG){ 468 OWRITE(fc, reg->addr, reg->data); 469 reg->data = OREAD(fc, reg->addr); 470 }else{ 471 err = EINVAL; 472 } 473 break; 474 case FWOHCI_RDREG: 475 if(reg->addr <= OHCI_MAX_REG){ 476 reg->data = OREAD(fc, reg->addr); 477 }else{ 478 err = EINVAL; 479 } 480 break; 481 /* Read DMA descriptors for debug */ 482 case DUMPDMA: 483 if(*dmach <= OHCI_MAX_DMA_CH ){ 484 dump_dma(fc, *dmach); 485 dump_db(fc, *dmach); 486 }else{ 487 err = EINVAL; 488 } 489 break; 490 /* Read/Write Phy registers */ 491 #define OHCI_MAX_PHY_REG 0xf 492 case FWOHCI_RDPHYREG: 493 if (reg->addr <= OHCI_MAX_PHY_REG) 494 reg->data = fwphy_rddata(fc, reg->addr); 495 else 496 err = EINVAL; 497 break; 498 case FWOHCI_WRPHYREG: 499 if (reg->addr <= OHCI_MAX_PHY_REG) 500 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 501 else 502 err = EINVAL; 503 break; 504 default: 505 err = EINVAL; 506 break; 507 } 508 return err; 509 } 510 511 static int 512 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 513 { 514 uint32_t reg, reg2; 515 int e1394a = 1; 516 /* 517 * probe PHY parameters 518 * 0. to prove PHY version, whether compliance of 1394a. 519 * 1. to probe maximum speed supported by the PHY and 520 * number of port supported by core-logic. 521 * It is not actually available port on your PC . 522 */ 523 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 524 DELAY(500); 525 526 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 527 528 if((reg >> 5) != 7 ){ 529 sc->fc.mode &= ~FWPHYASYST; 530 sc->fc.nport = reg & FW_PHY_NP; 531 sc->fc.speed = reg & FW_PHY_SPD >> 6; 532 if (sc->fc.speed > MAX_SPEED) { 533 fw_printf(dev, "invalid speed %d (fixed to %d).\n", 534 sc->fc.speed, MAX_SPEED); 535 sc->fc.speed = MAX_SPEED; 536 } 537 fw_printf(dev, "Phy 1394 only %s, %d ports.\n", 538 fw_linkspeed[sc->fc.speed], sc->fc.nport); 539 }else{ 540 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 541 sc->fc.mode |= FWPHYASYST; 542 sc->fc.nport = reg & FW_PHY_NP; 543 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 544 if (sc->fc.speed > MAX_SPEED) { 545 fw_printf(dev, "invalid speed %d (fixed to %d).\n", 546 sc->fc.speed, MAX_SPEED); 547 sc->fc.speed = MAX_SPEED; 548 } 549 fw_printf(dev, "Phy 1394a available %s, %d ports.\n", 550 fw_linkspeed[sc->fc.speed], sc->fc.nport); 551 552 /* check programPhyEnable */ 553 reg2 = fwphy_rddata(sc, 5); 554 #if 0 555 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 556 #else /* XXX force to enable 1394a */ 557 if (e1394a) { 558 #endif 559 if (firewire_debug) 560 fw_printf(dev, "Enable 1394a Enhancements\n"); 561 /* enable EAA EMC */ 562 reg2 |= 0x03; 563 /* set aPhyEnhanceEnable */ 564 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 565 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 566 } 567 #if 0 568 else { 569 /* for safe */ 570 reg2 &= ~0x83; 571 } 572 #endif 573 reg2 = fwphy_wrdata(sc, 5, reg2); 574 } 575 576 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 577 if((reg >> 5) == 7 ){ 578 reg = fwphy_rddata(sc, 4); 579 reg |= 1 << 6; 580 fwphy_wrdata(sc, 4, reg); 581 reg = fwphy_rddata(sc, 4); 582 } 583 return 0; 584 } 585 586 587 void 588 fwohci_reset(struct fwohci_softc *sc, device_t dev) 589 { 590 int i, max_rec, speed; 591 uint32_t reg, reg2; 592 struct fwohcidb_tr *db_tr; 593 594 /* Disable interrupts */ 595 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 596 597 /* Now stopping all DMA channels */ 598 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 599 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 600 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 601 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 602 603 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 604 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 605 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 606 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 607 } 608 609 /* FLUSH FIFO and reset Transmitter/Reciever */ 610 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 611 if (firewire_debug) 612 fw_printf(dev, "resetting OHCI..."); 613 i = 0; 614 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 615 if (i++ > 100) break; 616 DELAY(1000); 617 } 618 if (firewire_debug) 619 printf("done (loop=%d)\n", i); 620 621 /* Probe phy */ 622 fwohci_probe_phy(sc, dev); 623 624 /* Probe link */ 625 reg = OREAD(sc, OHCI_BUS_OPT); 626 reg2 = reg | OHCI_BUSFNC; 627 max_rec = (reg & 0x0000f000) >> 12; 628 speed = (reg & 0x00000007); 629 fw_printf(dev, "Link %s, max_rec %d bytes.\n", 630 fw_linkspeed[speed], MAXREC(max_rec)); 631 /* XXX fix max_rec */ 632 sc->fc.maxrec = sc->fc.speed + 8; 633 if (max_rec != sc->fc.maxrec) { 634 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 635 fw_printf(dev, "max_rec %d -> %d\n", 636 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 637 } 638 if (firewire_debug) 639 fw_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 640 OWRITE(sc, OHCI_BUS_OPT, reg2); 641 642 /* Initialize registers */ 643 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 644 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 645 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 646 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 647 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 648 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 649 650 /* Enable link */ 651 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 652 653 /* Force to start async RX DMA */ 654 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 655 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 656 fwohci_rx_enable(sc, &sc->arrq); 657 fwohci_rx_enable(sc, &sc->arrs); 658 659 /* Initialize async TX */ 660 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 661 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 662 663 /* AT Retries */ 664 OWRITE(sc, FWOHCI_RETRY, 665 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 666 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 667 668 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 669 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 670 sc->atrq.bottom = sc->atrq.top; 671 sc->atrs.bottom = sc->atrs.top; 672 673 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 674 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 675 db_tr->xfer = NULL; 676 } 677 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 678 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 679 db_tr->xfer = NULL; 680 } 681 682 683 /* Enable interrupts */ 684 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID 685 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 686 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 687 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 688 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT; 689 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT; 690 OWRITE(sc, FWOHCI_INTMASK, sc->intmask); 691 fwohci_set_intr(&sc->fc, 1); 692 } 693 694 int 695 fwohci_init(struct fwohci_softc *sc, device_t dev) 696 { 697 int i, mver; 698 uint32_t reg; 699 uint8_t ui[8]; 700 701 /* OHCI version */ 702 reg = OREAD(sc, OHCI_VERSION); 703 mver = (reg >> 16) & 0xff; 704 fw_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 705 mver, reg & 0xff, (reg>>24) & 1); 706 if (mver < 1 || mver > 9) { 707 fw_printf(dev, "invalid OHCI version\n"); 708 return (ENXIO); 709 } 710 711 /* Available Isochronous DMA channel probe */ 712 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 713 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 714 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 715 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 716 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 717 for (i = 0; i < 0x20; i++) 718 if ((reg & (1 << i)) == 0) 719 break; 720 sc->fc.nisodma = i; 721 fw_printf(dev, "No. of Isochronous channels is %d.\n", i); 722 if (i == 0) 723 return (ENXIO); 724 725 sc->fc.arq = &sc->arrq.xferq; 726 sc->fc.ars = &sc->arrs.xferq; 727 sc->fc.atq = &sc->atrq.xferq; 728 sc->fc.ats = &sc->atrs.xferq; 729 730 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 731 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 732 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 733 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 734 735 sc->arrq.xferq.start = NULL; 736 sc->arrs.xferq.start = NULL; 737 sc->atrq.xferq.start = fwohci_start_atq; 738 sc->atrs.xferq.start = fwohci_start_ats; 739 740 sc->arrq.xferq.buf = NULL; 741 sc->arrs.xferq.buf = NULL; 742 sc->atrq.xferq.buf = NULL; 743 sc->atrs.xferq.buf = NULL; 744 745 sc->arrq.xferq.dmach = -1; 746 sc->arrs.xferq.dmach = -1; 747 sc->atrq.xferq.dmach = -1; 748 sc->atrs.xferq.dmach = -1; 749 750 sc->arrq.ndesc = 1; 751 sc->arrs.ndesc = 1; 752 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 753 sc->atrs.ndesc = 2; 754 755 sc->arrq.ndb = NDB; 756 sc->arrs.ndb = NDB / 2; 757 sc->atrq.ndb = NDB; 758 sc->atrs.ndb = NDB / 2; 759 760 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 761 sc->fc.it[i] = &sc->it[i].xferq; 762 sc->fc.ir[i] = &sc->ir[i].xferq; 763 sc->it[i].xferq.dmach = i; 764 sc->ir[i].xferq.dmach = i; 765 sc->it[i].ndb = 0; 766 sc->ir[i].ndb = 0; 767 } 768 769 sc->fc.tcode = tinfo; 770 sc->fc.dev = dev; 771 772 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 773 &sc->crom_dma, BUS_DMA_WAITOK); 774 if(sc->fc.config_rom == NULL){ 775 fw_printf(dev, "config_rom alloc failed."); 776 return ENOMEM; 777 } 778 779 #if 0 780 bzero(&sc->fc.config_rom[0], CROMSIZE); 781 sc->fc.config_rom[1] = 0x31333934; 782 sc->fc.config_rom[2] = 0xf000a002; 783 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 784 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 785 sc->fc.config_rom[5] = 0; 786 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 787 788 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 789 #endif 790 791 /* SID recieve buffer must align 2^11 */ 792 #define OHCI_SIDSIZE (1 << 11) 793 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 794 &sc->sid_dma, BUS_DMA_WAITOK); 795 if (sc->sid_buf == NULL) { 796 fw_printf(dev, "sid_buf alloc failed."); 797 return ENOMEM; 798 } 799 800 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 801 &sc->dummy_dma, BUS_DMA_WAITOK); 802 803 if (sc->dummy_dma.v_addr == NULL) { 804 fw_printf(dev, "dummy_dma alloc failed."); 805 return ENOMEM; 806 } 807 808 fwohci_db_init(sc, &sc->arrq); 809 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 810 return ENOMEM; 811 812 fwohci_db_init(sc, &sc->arrs); 813 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 814 return ENOMEM; 815 816 fwohci_db_init(sc, &sc->atrq); 817 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 818 return ENOMEM; 819 820 fwohci_db_init(sc, &sc->atrs); 821 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 822 return ENOMEM; 823 824 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 825 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 826 for( i = 0 ; i < 8 ; i ++) 827 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 828 fw_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 829 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 830 831 sc->fc.ioctl = fwohci_ioctl; 832 sc->fc.cyctimer = fwohci_cyctimer; 833 sc->fc.set_bmr = fwohci_set_bus_manager; 834 sc->fc.ibr = fwohci_ibr; 835 sc->fc.irx_enable = fwohci_irx_enable; 836 sc->fc.irx_disable = fwohci_irx_disable; 837 838 sc->fc.itx_enable = fwohci_itxbuf_enable; 839 sc->fc.itx_disable = fwohci_itx_disable; 840 #if BYTE_ORDER == BIG_ENDIAN 841 sc->fc.irx_post = fwohci_irx_post; 842 #else 843 sc->fc.irx_post = NULL; 844 #endif 845 sc->fc.itx_post = NULL; 846 sc->fc.timeout = fwohci_timeout; 847 sc->fc.poll = fwohci_poll; 848 sc->fc.set_intr = fwohci_set_intr; 849 850 sc->intmask = sc->irstat = sc->itstat = 0; 851 852 /* Init task queue */ 853 sc->fc.taskqueue = fw_taskqueue_create_fast("fw_taskq", M_WAITOK, 854 fw_taskqueue_thread_enqueue, &sc->fc.taskqueue); 855 fw_taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq", 856 fw_get_unit(dev)); 857 FW_TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc); 858 FW_TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc); 859 FW_TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc); 860 861 fw_init(&sc->fc); 862 fwohci_reset(sc, dev); 863 FWOHCI_INIT_END; 864 865 return 0; 866 } 867 868 void 869 fwohci_timeout(void *arg) 870 { 871 struct fwohci_softc *sc; 872 873 sc = (struct fwohci_softc *)arg; 874 } 875 876 uint32_t 877 fwohci_cyctimer(struct firewire_comm *fc) 878 { 879 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 880 return(OREAD(sc, OHCI_CYCLETIMER)); 881 } 882 883 FWOHCI_DETACH() 884 { 885 int i; 886 887 FWOHCI_DETACH_START; 888 if (sc->sid_buf != NULL) 889 fwdma_free(&sc->fc, &sc->sid_dma); 890 if (sc->fc.config_rom != NULL) 891 fwdma_free(&sc->fc, &sc->crom_dma); 892 893 fwohci_db_free(&sc->arrq); 894 fwohci_db_free(&sc->arrs); 895 896 fwohci_db_free(&sc->atrq); 897 fwohci_db_free(&sc->atrs); 898 899 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 900 fwohci_db_free(&sc->it[i]); 901 fwohci_db_free(&sc->ir[i]); 902 } 903 FWOHCI_DETACH_END; 904 905 return 0; 906 } 907 908 #define LAST_DB(dbtr, db) do { \ 909 struct fwohcidb_tr *_dbtr = (dbtr); \ 910 int _cnt = _dbtr->dbcnt; \ 911 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 912 } while (0) 913 914 static void 915 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 916 { 917 struct fwohcidb_tr *db_tr; 918 struct fwohcidb *db; 919 bus_dma_segment_t *s; 920 int i; 921 922 db_tr = (struct fwohcidb_tr *)arg; 923 db = &db_tr->db[db_tr->dbcnt]; 924 if (error) { 925 if (firewire_debug || error != EFBIG) 926 printf("fwohci_execute_db: error=%d\n", error); 927 return; 928 } 929 for (i = 0; i < nseg; i++) { 930 s = &segs[i]; 931 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 932 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 933 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 934 db++; 935 db_tr->dbcnt++; 936 } 937 } 938 939 static void 940 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 941 bus_size_t size, int error) 942 { 943 fwohci_execute_db(arg, segs, nseg, error); 944 } 945 946 static void 947 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 948 { 949 int i, s; 950 int tcode, hdr_len, pl_off; 951 int fsegment = -1; 952 uint32_t off; 953 struct fw_xfer *xfer; 954 struct fw_pkt *fp; 955 struct fwohci_txpkthdr *ohcifp; 956 struct fwohcidb_tr *db_tr; 957 struct fwohcidb *db; 958 uint32_t *ld; 959 const struct tcode_info *info; 960 static int maxdesc=0; 961 962 FW_GLOCK_ASSERT(&sc->fc); 963 964 if(&sc->atrq == dbch){ 965 off = OHCI_ATQOFF; 966 }else if(&sc->atrs == dbch){ 967 off = OHCI_ATSOFF; 968 }else{ 969 return; 970 } 971 972 if (dbch->flags & FWOHCI_DBCH_FULL) 973 return; 974 975 s = splfw(); 976 fwdma_sync_multiseg_all(dbch->am, 977 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 978 db_tr = dbch->top; 979 txloop: 980 xfer = STAILQ_FIRST(&dbch->xferq.q); 981 if(xfer == NULL){ 982 goto kick; 983 } 984 #if 0 985 if(dbch->xferq.queued == 0 ){ 986 fw_printf(sc->fc.dev, "TX queue empty\n"); 987 } 988 #endif 989 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 990 db_tr->xfer = xfer; 991 xfer->flag = FWXF_START; 992 993 fp = &xfer->send.hdr; 994 tcode = fp->mode.common.tcode; 995 996 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 997 info = &tinfo[tcode]; 998 hdr_len = pl_off = info->hdr_len; 999 1000 ld = &ohcifp->mode.ld[0]; 1001 ld[0] = ld[1] = ld[2] = ld[3] = 0; 1002 for( i = 0 ; i < pl_off ; i+= 4) 1003 ld[i/4] = fp->mode.ld[i/4]; 1004 1005 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 1006 if (tcode == FWTCODE_STREAM ){ 1007 hdr_len = 8; 1008 ohcifp->mode.stream.len = fp->mode.stream.len; 1009 } else if (tcode == FWTCODE_PHY) { 1010 hdr_len = 12; 1011 ld[1] = fp->mode.ld[1]; 1012 ld[2] = fp->mode.ld[2]; 1013 ohcifp->mode.common.spd = 0; 1014 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 1015 } else { 1016 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 1017 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 1018 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 1019 } 1020 db = &db_tr->db[0]; 1021 FWOHCI_DMA_WRITE(db->db.desc.cmd, 1022 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 1023 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1024 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1025 /* Specify bound timer of asy. responce */ 1026 if(&sc->atrs == dbch){ 1027 FWOHCI_DMA_WRITE(db->db.desc.res, 1028 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1029 } 1030 #if BYTE_ORDER == BIG_ENDIAN 1031 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1032 hdr_len = 12; 1033 for (i = 0; i < hdr_len/4; i ++) 1034 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1035 #endif 1036 1037 again: 1038 db_tr->dbcnt = 2; 1039 db = &db_tr->db[db_tr->dbcnt]; 1040 if (xfer->send.pay_len > 0) { 1041 int err; 1042 /* handle payload */ 1043 if (xfer->mbuf == NULL) { 1044 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1045 &xfer->send.payload[0], xfer->send.pay_len, 1046 fwohci_execute_db, db_tr, 1047 BUS_DMA_WAITOK); 1048 } else { 1049 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1050 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1051 db_tr->dma_map, xfer->mbuf, 1052 fwohci_execute_db2, db_tr, 1053 BUS_DMA_WAITOK); 1054 if (err == EFBIG) { 1055 struct mbuf *m0; 1056 1057 if (firewire_debug) 1058 fw_printf(sc->fc.dev, "EFBIG.\n"); 1059 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1060 if (m0 != NULL) { 1061 m_copydata(xfer->mbuf, 0, 1062 xfer->mbuf->m_pkthdr.len, 1063 mtod(m0, void *)); 1064 m0->m_len = m0->m_pkthdr.len = 1065 xfer->mbuf->m_pkthdr.len; 1066 m_freem(xfer->mbuf); 1067 xfer->mbuf = m0; 1068 goto again; 1069 } 1070 fw_printf(sc->fc.dev, "m_getcl failed.\n"); 1071 } 1072 } 1073 if (err) 1074 printf("dmamap_load: err=%d\n", err); 1075 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1076 BUS_DMASYNC_PREWRITE); 1077 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1078 for (i = 2; i < db_tr->dbcnt; i++) 1079 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1080 OHCI_OUTPUT_MORE); 1081 #endif 1082 } 1083 if (maxdesc < db_tr->dbcnt) { 1084 maxdesc = db_tr->dbcnt; 1085 if (firewire_debug) 1086 fw_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1087 } 1088 /* last db */ 1089 LAST_DB(db_tr, db); 1090 FWOHCI_DMA_SET(db->db.desc.cmd, 1091 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1092 FWOHCI_DMA_WRITE(db->db.desc.depend, 1093 STAILQ_NEXT(db_tr, link)->bus_addr); 1094 1095 if(fsegment == -1 ) 1096 fsegment = db_tr->dbcnt; 1097 if (dbch->pdb_tr != NULL) { 1098 LAST_DB(dbch->pdb_tr, db); 1099 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1100 } 1101 dbch->xferq.queued ++; 1102 dbch->pdb_tr = db_tr; 1103 db_tr = STAILQ_NEXT(db_tr, link); 1104 if(db_tr != dbch->bottom){ 1105 goto txloop; 1106 } else { 1107 fw_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1108 dbch->flags |= FWOHCI_DBCH_FULL; 1109 } 1110 kick: 1111 /* kick asy q */ 1112 fwdma_sync_multiseg_all(dbch->am, 1113 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1114 1115 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1116 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1117 } else { 1118 if (firewire_debug) 1119 fw_printf(sc->fc.dev, "start AT DMA status=%x\n", 1120 OREAD(sc, OHCI_DMACTL(off))); 1121 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1122 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1123 dbch->xferq.flag |= FWXFERQ_RUNNING; 1124 } 1125 CTR0(KTR_DEV, "start kick done"); 1126 CTR0(KTR_DEV, "start kick done2"); 1127 1128 dbch->top = db_tr; 1129 splx(s); 1130 return; 1131 } 1132 1133 static void 1134 fwohci_start_atq(struct firewire_comm *fc) 1135 { 1136 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1137 FW_GLOCK(&sc->fc); 1138 fwohci_start( sc, &(sc->atrq)); 1139 FW_GUNLOCK(&sc->fc); 1140 return; 1141 } 1142 1143 static void 1144 fwohci_start_ats(struct firewire_comm *fc) 1145 { 1146 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1147 FW_GLOCK(&sc->fc); 1148 fwohci_start( sc, &(sc->atrs)); 1149 FW_GUNLOCK(&sc->fc); 1150 return; 1151 } 1152 1153 void 1154 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1155 { 1156 int s, ch, err = 0; 1157 struct fwohcidb_tr *tr; 1158 struct fwohcidb *db; 1159 struct fw_xfer *xfer; 1160 uint32_t off; 1161 u_int stat, status; 1162 int packets; 1163 struct firewire_comm *fc = (struct firewire_comm *)sc; 1164 1165 if(&sc->atrq == dbch){ 1166 off = OHCI_ATQOFF; 1167 ch = ATRQ_CH; 1168 }else if(&sc->atrs == dbch){ 1169 off = OHCI_ATSOFF; 1170 ch = ATRS_CH; 1171 }else{ 1172 return; 1173 } 1174 s = splfw(); 1175 tr = dbch->bottom; 1176 packets = 0; 1177 fwdma_sync_multiseg_all(dbch->am, 1178 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1179 while(dbch->xferq.queued > 0){ 1180 LAST_DB(tr, db); 1181 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1182 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1183 if (fc->status != FWBUSINIT) 1184 /* maybe out of order?? */ 1185 goto out; 1186 } 1187 if (tr->xfer->send.pay_len > 0) { 1188 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1189 BUS_DMASYNC_POSTWRITE); 1190 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1191 } 1192 #if 1 1193 if (firewire_debug > 1) 1194 dump_db(sc, ch); 1195 #endif 1196 if(status & OHCI_CNTL_DMA_DEAD) { 1197 /* Stop DMA */ 1198 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1199 fw_printf(sc->fc.dev, "force reset AT FIFO\n"); 1200 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1201 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1202 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1203 } 1204 stat = status & FWOHCIEV_MASK; 1205 switch(stat){ 1206 case FWOHCIEV_ACKPEND: 1207 CTR0(KTR_DEV, "txd: ack pending"); 1208 /* fall through */ 1209 case FWOHCIEV_ACKCOMPL: 1210 err = 0; 1211 break; 1212 case FWOHCIEV_ACKBSA: 1213 case FWOHCIEV_ACKBSB: 1214 case FWOHCIEV_ACKBSX: 1215 fw_printf(sc->fc.dev, "txd err=%2x %s\n", stat, 1216 fwohcicode[stat]); 1217 err = EBUSY; 1218 break; 1219 case FWOHCIEV_FLUSHED: 1220 case FWOHCIEV_ACKTARD: 1221 fw_printf(sc->fc.dev, "txd err=%2x %s\n", stat, 1222 fwohcicode[stat]); 1223 err = EAGAIN; 1224 break; 1225 case FWOHCIEV_MISSACK: 1226 case FWOHCIEV_UNDRRUN: 1227 case FWOHCIEV_OVRRUN: 1228 case FWOHCIEV_DESCERR: 1229 case FWOHCIEV_DTRDERR: 1230 case FWOHCIEV_TIMEOUT: 1231 case FWOHCIEV_TCODERR: 1232 case FWOHCIEV_UNKNOWN: 1233 case FWOHCIEV_ACKDERR: 1234 case FWOHCIEV_ACKTERR: 1235 default: 1236 fw_printf(sc->fc.dev, "txd err=%2x %s\n", 1237 stat, fwohcicode[stat]); 1238 err = EINVAL; 1239 break; 1240 } 1241 if (tr->xfer != NULL) { 1242 xfer = tr->xfer; 1243 CTR0(KTR_DEV, "txd"); 1244 if (xfer->flag & FWXF_RCVD) { 1245 #if 0 1246 if (firewire_debug) 1247 printf("already rcvd\n"); 1248 #endif 1249 fw_xfer_done(xfer); 1250 } else { 1251 microtime(&xfer->tv); 1252 xfer->flag = FWXF_SENT; 1253 if (err == EBUSY) { 1254 xfer->flag = FWXF_BUSY; 1255 xfer->resp = err; 1256 xfer->recv.pay_len = 0; 1257 fw_xfer_done(xfer); 1258 } else if (stat != FWOHCIEV_ACKPEND) { 1259 if (stat != FWOHCIEV_ACKCOMPL) 1260 xfer->flag = FWXF_SENTERR; 1261 xfer->resp = err; 1262 xfer->recv.pay_len = 0; 1263 fw_xfer_done(xfer); 1264 } 1265 } 1266 /* 1267 * The watchdog timer takes care of split 1268 * transcation timeout for ACKPEND case. 1269 */ 1270 } else { 1271 printf("this shouldn't happen\n"); 1272 } 1273 FW_GLOCK(fc); 1274 dbch->xferq.queued --; 1275 FW_GUNLOCK(fc); 1276 tr->xfer = NULL; 1277 1278 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1279 packets ++; 1280 tr = STAILQ_NEXT(tr, link); 1281 dbch->bottom = tr; 1282 if (dbch->bottom == dbch->top) { 1283 /* we reaches the end of context program */ 1284 if (firewire_debug && dbch->xferq.queued > 0) 1285 printf("queued > 0\n"); 1286 break; 1287 } 1288 } 1289 out: 1290 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1291 printf("make free slot\n"); 1292 dbch->flags &= ~FWOHCI_DBCH_FULL; 1293 FW_GLOCK(fc); 1294 fwohci_start(sc, dbch); 1295 FW_GUNLOCK(fc); 1296 } 1297 fwdma_sync_multiseg_all( 1298 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1299 splx(s); 1300 } 1301 1302 static void 1303 fwohci_db_free(struct fwohci_dbch *dbch) 1304 { 1305 struct fwohcidb_tr *db_tr; 1306 int idb; 1307 1308 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1309 return; 1310 1311 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1312 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1313 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1314 db_tr->buf != NULL) { 1315 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1316 db_tr->buf, dbch->xferq.psize); 1317 db_tr->buf = NULL; 1318 } else if (db_tr->dma_map != NULL) 1319 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1320 } 1321 dbch->ndb = 0; 1322 db_tr = STAILQ_FIRST(&dbch->db_trq); 1323 fwdma_free_multiseg(dbch->am); 1324 free(db_tr, M_FW); 1325 STAILQ_INIT(&dbch->db_trq); 1326 dbch->flags &= ~FWOHCI_DBCH_INIT; 1327 seldestroy(&dbch->xferq.rsel); 1328 } 1329 1330 static void 1331 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1332 { 1333 int idb; 1334 struct fwohcidb_tr *db_tr; 1335 1336 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1337 goto out; 1338 1339 /* create dma_tag for buffers */ 1340 #define MAX_REQCOUNT 0xffff 1341 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1342 /*alignment*/ 1, /*boundary*/ 0, 1343 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1344 /*highaddr*/ BUS_SPACE_MAXADDR, 1345 /*filter*/NULL, /*filterarg*/NULL, 1346 /*maxsize*/ dbch->xferq.psize, 1347 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1348 /*maxsegsz*/ MAX_REQCOUNT, 1349 /*flags*/ 0, 1350 /*lockfunc*/busdma_lock_mutex, 1351 /*lockarg*/FW_GMTX(&sc->fc), 1352 &dbch->dmat)) 1353 return; 1354 1355 /* allocate DB entries and attach one to each DMA channels */ 1356 /* DB entry must start at 16 bytes bounary. */ 1357 STAILQ_INIT(&dbch->db_trq); 1358 db_tr = (struct fwohcidb_tr *) 1359 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1360 M_FW, M_WAITOK | M_ZERO); 1361 if(db_tr == NULL){ 1362 printf("fwohci_db_init: malloc(1) failed\n"); 1363 return; 1364 } 1365 1366 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1367 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1368 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1369 if (dbch->am == NULL) { 1370 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1371 free(db_tr, M_FW); 1372 return; 1373 } 1374 /* Attach DB to DMA ch. */ 1375 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1376 db_tr->dbcnt = 0; 1377 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1378 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1379 /* create dmamap for buffers */ 1380 /* XXX do we need 4bytes alignment tag? */ 1381 /* XXX don't alloc dma_map for AR */ 1382 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1383 printf("fw_bus_dmamap_create failed\n"); 1384 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1385 fwohci_db_free(dbch); 1386 return; 1387 } 1388 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1389 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1390 if (idb % dbch->xferq.bnpacket == 0) 1391 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1392 ].start = (void *)db_tr; 1393 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1394 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1395 ].end = (void *)db_tr; 1396 } 1397 db_tr++; 1398 } 1399 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1400 = STAILQ_FIRST(&dbch->db_trq); 1401 out: 1402 dbch->xferq.queued = 0; 1403 dbch->pdb_tr = NULL; 1404 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1405 dbch->bottom = dbch->top; 1406 dbch->flags = FWOHCI_DBCH_INIT; 1407 selinit(&dbch->xferq.rsel); 1408 } 1409 1410 static int 1411 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1412 { 1413 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1414 int sleepch; 1415 1416 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1417 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1418 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1419 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1420 /* XXX we cannot free buffers until the DMA really stops */ 1421 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1422 fwohci_db_free(&sc->it[dmach]); 1423 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1424 return 0; 1425 } 1426 1427 static int 1428 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1429 { 1430 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1431 int sleepch; 1432 1433 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1434 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1435 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1436 /* XXX we cannot free buffers until the DMA really stops */ 1437 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1438 fwohci_db_free(&sc->ir[dmach]); 1439 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1440 return 0; 1441 } 1442 1443 #if BYTE_ORDER == BIG_ENDIAN 1444 static void 1445 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1446 { 1447 qld[0] = FWOHCI_DMA_READ(qld[0]); 1448 return; 1449 } 1450 #endif 1451 1452 static int 1453 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1454 { 1455 int err = 0; 1456 int idb, z, i, dmach = 0, ldesc; 1457 uint32_t off = 0; 1458 struct fwohcidb_tr *db_tr; 1459 struct fwohcidb *db; 1460 1461 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1462 err = EINVAL; 1463 return err; 1464 } 1465 z = dbch->ndesc; 1466 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1467 if( &sc->it[dmach] == dbch){ 1468 off = OHCI_ITOFF(dmach); 1469 break; 1470 } 1471 } 1472 if(off == 0){ 1473 err = EINVAL; 1474 return err; 1475 } 1476 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1477 return err; 1478 dbch->xferq.flag |= FWXFERQ_RUNNING; 1479 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1480 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1481 } 1482 db_tr = dbch->top; 1483 for (idb = 0; idb < dbch->ndb; idb ++) { 1484 fwohci_add_tx_buf(dbch, db_tr, idb); 1485 if(STAILQ_NEXT(db_tr, link) == NULL){ 1486 break; 1487 } 1488 db = db_tr->db; 1489 ldesc = db_tr->dbcnt - 1; 1490 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1491 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1492 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1493 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1494 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1495 FWOHCI_DMA_SET( 1496 db[ldesc].db.desc.cmd, 1497 OHCI_INTERRUPT_ALWAYS); 1498 /* OHCI 1.1 and above */ 1499 FWOHCI_DMA_SET( 1500 db[0].db.desc.cmd, 1501 OHCI_INTERRUPT_ALWAYS); 1502 } 1503 } 1504 db_tr = STAILQ_NEXT(db_tr, link); 1505 } 1506 FWOHCI_DMA_CLEAR( 1507 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1508 return err; 1509 } 1510 1511 static int 1512 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1513 { 1514 int err = 0; 1515 int idb, z, i, dmach = 0, ldesc; 1516 uint32_t off = 0; 1517 struct fwohcidb_tr *db_tr; 1518 struct fwohcidb *db; 1519 1520 z = dbch->ndesc; 1521 if(&sc->arrq == dbch){ 1522 off = OHCI_ARQOFF; 1523 }else if(&sc->arrs == dbch){ 1524 off = OHCI_ARSOFF; 1525 }else{ 1526 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1527 if( &sc->ir[dmach] == dbch){ 1528 off = OHCI_IROFF(dmach); 1529 break; 1530 } 1531 } 1532 } 1533 if(off == 0){ 1534 err = EINVAL; 1535 return err; 1536 } 1537 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1538 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1539 return err; 1540 }else{ 1541 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1542 err = EBUSY; 1543 return err; 1544 } 1545 } 1546 dbch->xferq.flag |= FWXFERQ_RUNNING; 1547 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1548 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1549 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1550 } 1551 db_tr = dbch->top; 1552 if (db_tr->dbcnt != 0) 1553 goto run; 1554 for (idb = 0; idb < dbch->ndb; idb ++) { 1555 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1556 if (STAILQ_NEXT(db_tr, link) == NULL) 1557 break; 1558 db = db_tr->db; 1559 ldesc = db_tr->dbcnt - 1; 1560 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1561 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1562 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1563 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1564 FWOHCI_DMA_SET( 1565 db[ldesc].db.desc.cmd, 1566 OHCI_INTERRUPT_ALWAYS); 1567 FWOHCI_DMA_CLEAR( 1568 db[ldesc].db.desc.depend, 1569 0xf); 1570 } 1571 } 1572 db_tr = STAILQ_NEXT(db_tr, link); 1573 } 1574 FWOHCI_DMA_CLEAR( 1575 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1576 dbch->buf_offset = 0; 1577 run: 1578 fwdma_sync_multiseg_all(dbch->am, 1579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1580 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1581 return err; 1582 }else{ 1583 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1584 } 1585 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1586 return err; 1587 } 1588 1589 static int 1590 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1591 { 1592 int sec, cycle, cycle_match; 1593 1594 cycle = cycle_now & 0x1fff; 1595 sec = cycle_now >> 13; 1596 #define CYCLE_MOD 0x10 1597 #if 1 1598 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1599 #else 1600 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1601 #endif 1602 cycle = cycle + CYCLE_DELAY; 1603 if (cycle >= 8000) { 1604 sec ++; 1605 cycle -= 8000; 1606 } 1607 cycle = roundup2(cycle, CYCLE_MOD); 1608 if (cycle >= 8000) { 1609 sec ++; 1610 if (cycle == 8000) 1611 cycle = 0; 1612 else 1613 cycle = CYCLE_MOD; 1614 } 1615 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1616 1617 return(cycle_match); 1618 } 1619 1620 static int 1621 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1622 { 1623 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1624 int err = 0; 1625 unsigned short tag, ich; 1626 struct fwohci_dbch *dbch; 1627 int cycle_match, cycle_now, s, ldesc; 1628 uint32_t stat; 1629 struct fw_bulkxfer *first, *chunk, *prev; 1630 struct fw_xferq *it; 1631 1632 dbch = &sc->it[dmach]; 1633 it = &dbch->xferq; 1634 1635 tag = (it->flag >> 6) & 3; 1636 ich = it->flag & 0x3f; 1637 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1638 dbch->ndb = it->bnpacket * it->bnchunk; 1639 dbch->ndesc = 3; 1640 fwohci_db_init(sc, dbch); 1641 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1642 return ENOMEM; 1643 1644 err = fwohci_tx_enable(sc, dbch); 1645 } 1646 if(err) 1647 return err; 1648 1649 ldesc = dbch->ndesc - 1; 1650 s = splfw(); 1651 FW_GLOCK(fc); 1652 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1653 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1654 struct fwohcidb *db; 1655 1656 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1657 BUS_DMASYNC_PREWRITE); 1658 fwohci_txbufdb(sc, dmach, chunk); 1659 if (prev != NULL) { 1660 db = ((struct fwohcidb_tr *)(prev->end))->db; 1661 #if 0 /* XXX necessary? */ 1662 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1663 OHCI_BRANCH_ALWAYS); 1664 #endif 1665 #if 0 /* if bulkxfer->npacket changes */ 1666 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1667 ((struct fwohcidb_tr *) 1668 (chunk->start))->bus_addr | dbch->ndesc; 1669 #else 1670 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1671 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1672 #endif 1673 } 1674 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1675 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1676 prev = chunk; 1677 } 1678 FW_GUNLOCK(fc); 1679 fwdma_sync_multiseg_all(dbch->am, 1680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1681 splx(s); 1682 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1683 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1684 printf("stat 0x%x\n", stat); 1685 1686 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1687 return 0; 1688 1689 #if 0 1690 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1691 #endif 1692 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1693 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1694 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1695 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1696 1697 first = STAILQ_FIRST(&it->stdma); 1698 OWRITE(sc, OHCI_ITCMD(dmach), 1699 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1700 if (firewire_debug > 1) { 1701 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1702 #if 1 1703 dump_dma(sc, ITX_CH + dmach); 1704 #endif 1705 } 1706 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1707 #if 1 1708 /* Don't start until all chunks are buffered */ 1709 if (STAILQ_FIRST(&it->stfree) != NULL) 1710 goto out; 1711 #endif 1712 #if 1 1713 /* Clear cycle match counter bits */ 1714 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1715 1716 /* 2bit second + 13bit cycle */ 1717 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1718 cycle_match = fwohci_next_cycle(fc, cycle_now); 1719 1720 OWRITE(sc, OHCI_ITCTL(dmach), 1721 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1722 | OHCI_CNTL_DMA_RUN); 1723 #else 1724 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1725 #endif 1726 if (firewire_debug > 1) { 1727 printf("cycle_match: 0x%04x->0x%04x\n", 1728 cycle_now, cycle_match); 1729 dump_dma(sc, ITX_CH + dmach); 1730 dump_db(sc, ITX_CH + dmach); 1731 } 1732 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1733 fw_printf(sc->fc.dev, "IT DMA underrun (0x%08x)\n", stat); 1734 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1735 } 1736 out: 1737 return err; 1738 } 1739 1740 static int 1741 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1742 { 1743 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1744 int err = 0, s, ldesc; 1745 unsigned short tag, ich; 1746 uint32_t stat; 1747 struct fwohci_dbch *dbch; 1748 struct fwohcidb_tr *db_tr; 1749 struct fw_bulkxfer *first, *prev, *chunk; 1750 struct fw_xferq *ir; 1751 1752 dbch = &sc->ir[dmach]; 1753 ir = &dbch->xferq; 1754 1755 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1756 tag = (ir->flag >> 6) & 3; 1757 ich = ir->flag & 0x3f; 1758 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1759 1760 ir->queued = 0; 1761 dbch->ndb = ir->bnpacket * ir->bnchunk; 1762 dbch->ndesc = 2; 1763 fwohci_db_init(sc, dbch); 1764 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1765 return ENOMEM; 1766 err = fwohci_rx_enable(sc, dbch); 1767 } 1768 if(err) 1769 return err; 1770 1771 first = STAILQ_FIRST(&ir->stfree); 1772 if (first == NULL) { 1773 fw_printf(fc->dev, "IR DMA no free chunk\n"); 1774 return 0; 1775 } 1776 1777 ldesc = dbch->ndesc - 1; 1778 s = splfw(); 1779 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1780 FW_GLOCK(fc); 1781 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1782 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1783 struct fwohcidb *db; 1784 1785 #if 1 /* XXX for if_fwe */ 1786 if (chunk->mbuf != NULL) { 1787 db_tr = (struct fwohcidb_tr *)(chunk->start); 1788 db_tr->dbcnt = 1; 1789 err = fw_bus_dmamap_load_mbuf( 1790 dbch->dmat, db_tr->dma_map, 1791 chunk->mbuf, fwohci_execute_db2, db_tr, 1792 BUS_DMA_WAITOK); 1793 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1794 OHCI_UPDATE | OHCI_INPUT_LAST | 1795 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1796 } 1797 #endif 1798 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1799 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1800 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1801 if (prev != NULL) { 1802 db = ((struct fwohcidb_tr *)(prev->end))->db; 1803 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1804 } 1805 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1806 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1807 prev = chunk; 1808 } 1809 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1810 FW_GUNLOCK(fc); 1811 fwdma_sync_multiseg_all(dbch->am, 1812 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1813 splx(s); 1814 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1815 if (stat & OHCI_CNTL_DMA_ACTIVE) 1816 return 0; 1817 if (stat & OHCI_CNTL_DMA_RUN) { 1818 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1819 fw_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1820 } 1821 1822 if (firewire_debug) 1823 printf("start IR DMA 0x%x\n", stat); 1824 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1825 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1826 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1827 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1828 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1829 OWRITE(sc, OHCI_IRCMD(dmach), 1830 ((struct fwohcidb_tr *)(first->start))->bus_addr 1831 | dbch->ndesc); 1832 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1833 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1834 #if 0 1835 dump_db(sc, IRX_CH + dmach); 1836 #endif 1837 return err; 1838 } 1839 1840 int 1841 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1842 { 1843 u_int i; 1844 1845 /* Now stopping all DMA channel */ 1846 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1847 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1848 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1849 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1850 1851 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1852 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1853 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1854 } 1855 1856 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1857 fw_drain_txq(&sc->fc); 1858 1859 #if 0 /* Let dcons(4) be accessed */ 1860 /* Stop interrupt */ 1861 OWRITE(sc, FWOHCI_INTMASKCLR, 1862 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1863 | OHCI_INT_PHY_INT 1864 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1865 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1866 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1867 | OHCI_INT_PHY_BUS_R); 1868 1869 /* FLUSH FIFO and reset Transmitter/Reciever */ 1870 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1871 #endif 1872 1873 /* XXX Link down? Bus reset? */ 1874 return 0; 1875 } 1876 1877 int 1878 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1879 { 1880 int i; 1881 struct fw_xferq *ir; 1882 struct fw_bulkxfer *chunk; 1883 1884 fwohci_reset(sc, dev); 1885 /* XXX resume isochronous receive automatically. (how about TX?) */ 1886 for(i = 0; i < sc->fc.nisodma; i ++) { 1887 ir = &sc->ir[i].xferq; 1888 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1889 fw_printf(sc->fc.dev, 1890 "resume iso receive ch: %d\n", i); 1891 ir->flag &= ~FWXFERQ_RUNNING; 1892 /* requeue stdma to stfree */ 1893 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1894 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1895 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1896 } 1897 sc->fc.irx_enable(&sc->fc, i); 1898 } 1899 } 1900 1901 #if defined(__FreeBSD__) 1902 bus_generic_resume(dev); 1903 #elif defined(__NetBSD__) 1904 { 1905 extern int firewire_resume(struct firewire_comm *); 1906 firewire_resume(&sc->fc); 1907 } 1908 #endif 1909 sc->fc.ibr(&sc->fc); 1910 return 0; 1911 } 1912 1913 #ifdef OHCI_DEBUG 1914 static void 1915 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat) 1916 { 1917 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1918 fw_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1919 stat & OHCI_INT_EN ? "DMA_EN ":"", 1920 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1921 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1922 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1923 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1924 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1925 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1926 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1927 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1928 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1929 stat & OHCI_INT_PHY_SID ? "SID ":"", 1930 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1931 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1932 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1933 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1934 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1935 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1936 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1937 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1938 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1939 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1940 stat, OREAD(sc, FWOHCI_INTMASK) 1941 ); 1942 } 1943 #endif 1944 static void 1945 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count) 1946 { 1947 struct firewire_comm *fc = (struct firewire_comm *)sc; 1948 uint32_t node_id, plen; 1949 1950 CTR0(KTR_DEV, "fwohci_intr_core"); 1951 1952 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) { 1953 fc->status = FWBUSRESET; 1954 /* Disable bus reset interrupt until sid recv. */ 1955 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1956 1957 fw_printf(fc->dev, "BUS reset\n"); 1958 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1959 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1960 1961 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1962 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1963 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1964 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1965 1966 if (!kdb_active) 1967 fw_taskqueue_enqueue(sc->fc.taskqueue, 1968 &sc->fwohci_task_busreset); 1969 } 1970 if (stat & OHCI_INT_PHY_SID) { 1971 /* Enable bus reset interrupt */ 1972 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1973 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1974 1975 /* Allow async. request to us */ 1976 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1977 if (firewire_phydma_enable) { 1978 /* allow from all nodes */ 1979 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1980 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1981 /* 0 to 4GB regison */ 1982 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1983 } 1984 /* Set ATRetries register */ 1985 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1986 1987 /* 1988 * Checking whether the node is root or not. If root, turn on 1989 * cycle master. 1990 */ 1991 node_id = OREAD(sc, FWOHCI_NODEID); 1992 plen = OREAD(sc, OHCI_SID_CNT); 1993 1994 fc->nodeid = node_id & 0x3f; 1995 fw_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1996 node_id, (plen >> 16) & 0xff); 1997 if (!(node_id & OHCI_NODE_VALID)) { 1998 printf("Bus reset failure\n"); 1999 goto sidout; 2000 } 2001 2002 /* cycle timer */ 2003 sc->cycle_lost = 0; 2004 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2005 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2006 printf("CYCLEMASTER mode\n"); 2007 OWRITE(sc, OHCI_LNKCTL, 2008 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2009 } else { 2010 printf("non CYCLEMASTER mode\n"); 2011 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2012 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2013 } 2014 2015 fc->status = FWBUSINIT; 2016 2017 if (!kdb_active) 2018 fw_taskqueue_enqueue(sc->fc.taskqueue, 2019 &sc->fwohci_task_sid); 2020 } 2021 sidout: 2022 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active)) 2023 fw_taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma); 2024 2025 CTR0(KTR_DEV, "fwohci_intr_core done"); 2026 } 2027 2028 static void 2029 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count) 2030 { 2031 uint32_t irstat, itstat; 2032 u_int i; 2033 struct firewire_comm *fc = (struct firewire_comm *)sc; 2034 2035 CTR0(KTR_DEV, "fwohci_intr_dma"); 2036 if (stat & OHCI_INT_DMA_IR) { 2037 irstat = fw_atomic_readandclear_int(&sc->irstat); 2038 for(i = 0; i < fc->nisodma ; i++){ 2039 struct fwohci_dbch *dbch; 2040 2041 if((irstat & (1 << i)) != 0){ 2042 dbch = &sc->ir[i]; 2043 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 2044 fw_printf(sc->fc.dev, 2045 "dma(%d) not active\n", i); 2046 continue; 2047 } 2048 fwohci_rbuf_update(sc, i); 2049 } 2050 } 2051 } 2052 if (stat & OHCI_INT_DMA_IT) { 2053 itstat = fw_atomic_readandclear_int(&sc->itstat); 2054 for(i = 0; i < fc->nisodma ; i++){ 2055 if((itstat & (1 << i)) != 0){ 2056 fwohci_tbuf_update(sc, i); 2057 } 2058 } 2059 } 2060 if (stat & OHCI_INT_DMA_PRRS) { 2061 #if 0 2062 dump_dma(sc, ARRS_CH); 2063 dump_db(sc, ARRS_CH); 2064 #endif 2065 fwohci_arcv(sc, &sc->arrs, count); 2066 } 2067 if (stat & OHCI_INT_DMA_PRRQ) { 2068 #if 0 2069 dump_dma(sc, ARRQ_CH); 2070 dump_db(sc, ARRQ_CH); 2071 #endif 2072 fwohci_arcv(sc, &sc->arrq, count); 2073 } 2074 if (stat & OHCI_INT_CYC_LOST) { 2075 if (sc->cycle_lost >= 0) 2076 sc->cycle_lost ++; 2077 if (sc->cycle_lost > 10) { 2078 sc->cycle_lost = -1; 2079 #if 0 2080 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2081 #endif 2082 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2083 fw_printf(fc->dev, "too many cycle lost, " 2084 "no cycle master presents?\n"); 2085 } 2086 } 2087 if (stat & OHCI_INT_DMA_ATRQ) { 2088 fwohci_txd(sc, &(sc->atrq)); 2089 } 2090 if (stat & OHCI_INT_DMA_ATRS) { 2091 fwohci_txd(sc, &(sc->atrs)); 2092 } 2093 if (stat & OHCI_INT_PW_ERR) { 2094 fw_printf(fc->dev, "posted write error\n"); 2095 } 2096 if (stat & OHCI_INT_ERR) { 2097 fw_printf(fc->dev, "unrecoverable error\n"); 2098 } 2099 if (stat & OHCI_INT_PHY_INT) { 2100 fw_printf(fc->dev, "phy int\n"); 2101 } 2102 2103 CTR0(KTR_DEV, "fwohci_intr_dma done"); 2104 return; 2105 } 2106 2107 static void 2108 fwohci_task_busreset(void *arg, int pending) 2109 { 2110 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2111 2112 fw_busreset(&sc->fc, FWBUSRESET); 2113 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2114 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2115 } 2116 2117 static void 2118 fwohci_task_sid(void *arg, int pending) 2119 { 2120 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2121 struct firewire_comm *fc = &sc->fc; 2122 uint32_t *buf; 2123 int i, plen; 2124 2125 plen = OREAD(sc, OHCI_SID_CNT); 2126 2127 if (plen & OHCI_SID_ERR) { 2128 fw_printf(fc->dev, "SID Error\n"); 2129 return; 2130 } 2131 plen &= OHCI_SID_CNT_MASK; 2132 if (plen < 4 || plen > OHCI_SIDSIZE) { 2133 fw_printf(fc->dev, "invalid SID len = %d\n", plen); 2134 return; 2135 } 2136 plen -= 4; /* chop control info */ 2137 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2138 if (buf == NULL) { 2139 fw_printf(fc->dev, "malloc failed\n"); 2140 return; 2141 } 2142 for (i = 0; i < plen / 4; i ++) 2143 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2144 #if 1 /* XXX needed?? */ 2145 /* pending all pre-bus_reset packets */ 2146 fwohci_txd(sc, &sc->atrq); 2147 fwohci_txd(sc, &sc->atrs); 2148 fwohci_arcv(sc, &sc->arrs, -1); 2149 fwohci_arcv(sc, &sc->arrq, -1); 2150 fw_drain_txq(fc); 2151 #endif 2152 fw_sidrcv(fc, buf, plen); 2153 free(buf, M_FW); 2154 } 2155 2156 static void 2157 fwohci_task_dma(void *arg, int pending) 2158 { 2159 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2160 uint32_t stat; 2161 2162 again: 2163 stat = fw_atomic_readandclear_int(&sc->intstat); 2164 if (stat) 2165 fwohci_intr_dma(sc, stat, -1); 2166 else 2167 return; 2168 goto again; 2169 } 2170 2171 static int 2172 fwohci_check_stat(struct fwohci_softc *sc) 2173 { 2174 uint32_t stat, irstat, itstat; 2175 2176 stat = OREAD(sc, FWOHCI_INTSTAT); 2177 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2178 if (stat == 0xffffffff) { 2179 fw_printf(sc->fc.dev, 2180 "device physically ejected?\n"); 2181 return (FILTER_STRAY); 2182 } 2183 if (stat) 2184 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R); 2185 2186 stat &= sc->intmask; 2187 if (stat == 0) 2188 return (FILTER_STRAY); 2189 2190 fw_atomic_set_int(&sc->intstat, stat); 2191 if (stat & OHCI_INT_DMA_IR) { 2192 irstat = OREAD(sc, OHCI_IR_STAT); 2193 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2194 fw_atomic_set_int(&sc->irstat, irstat); 2195 } 2196 if (stat & OHCI_INT_DMA_IT) { 2197 itstat = OREAD(sc, OHCI_IT_STAT); 2198 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2199 fw_atomic_set_int(&sc->itstat, itstat); 2200 } 2201 2202 fwohci_intr_core(sc, stat, -1); 2203 return (FILTER_HANDLED); 2204 } 2205 2206 int 2207 fwohci_filt(void *arg) 2208 { 2209 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2210 2211 if (!(sc->intmask & OHCI_INT_EN)) { 2212 /* polling mode */ 2213 return (FILTER_STRAY); 2214 } 2215 return (fwohci_check_stat(sc)); 2216 } 2217 2218 void 2219 fwohci_intr(void *arg) 2220 { 2221 2222 fwohci_filt(arg); 2223 CTR0(KTR_DEV, "fwohci_intr end"); 2224 } 2225 2226 void 2227 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2228 { 2229 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2230 2231 fwohci_check_stat(sc); 2232 } 2233 2234 static void 2235 fwohci_set_intr(struct firewire_comm *fc, int enable) 2236 { 2237 struct fwohci_softc *sc; 2238 2239 sc = (struct fwohci_softc *)fc; 2240 if (firewire_debug) 2241 fw_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2242 if (enable) { 2243 sc->intmask |= OHCI_INT_EN; 2244 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2245 } else { 2246 sc->intmask &= ~OHCI_INT_EN; 2247 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2248 } 2249 } 2250 2251 static void 2252 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2253 { 2254 struct firewire_comm *fc = &sc->fc; 2255 struct fwohcidb *db; 2256 struct fw_bulkxfer *chunk; 2257 struct fw_xferq *it; 2258 uint32_t stat, count; 2259 int s, w=0, ldesc; 2260 2261 it = fc->it[dmach]; 2262 ldesc = sc->it[dmach].ndesc - 1; 2263 s = splfw(); /* unnecessary ? */ 2264 FW_GLOCK(fc); 2265 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2266 if (firewire_debug) 2267 dump_db(sc, ITX_CH + dmach); 2268 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2269 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2270 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2271 >> OHCI_STATUS_SHIFT; 2272 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2273 /* timestamp */ 2274 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2275 & OHCI_COUNT_MASK; 2276 if (stat == 0) 2277 break; 2278 STAILQ_REMOVE_HEAD(&it->stdma, link); 2279 switch (stat & FWOHCIEV_MASK){ 2280 case FWOHCIEV_ACKCOMPL: 2281 #if 0 2282 fw_printf(fc->dev, "0x%08x\n", count); 2283 #endif 2284 break; 2285 default: 2286 fw_printf(fc->dev, 2287 "Isochronous transmit err %02x(%s)\n", 2288 stat, fwohcicode[stat & 0x1f]); 2289 } 2290 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2291 w++; 2292 } 2293 FW_GUNLOCK(fc); 2294 splx(s); 2295 if (w) 2296 wakeup(it); 2297 } 2298 2299 static void 2300 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2301 { 2302 struct firewire_comm *fc = &sc->fc; 2303 struct fwohcidb_tr *db_tr; 2304 struct fw_bulkxfer *chunk; 2305 struct fw_xferq *ir; 2306 uint32_t stat; 2307 int s, w = 0, ldesc; 2308 2309 ir = fc->ir[dmach]; 2310 ldesc = sc->ir[dmach].ndesc - 1; 2311 2312 #if 0 2313 dump_db(sc, dmach); 2314 #endif 2315 s = splfw(); 2316 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2317 FW_GLOCK(fc); 2318 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2319 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2320 db_tr = (struct fwohcidb_tr *)chunk->end; 2321 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2322 >> OHCI_STATUS_SHIFT; 2323 if (stat == 0) 2324 break; 2325 2326 if (chunk->mbuf != NULL) { 2327 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2328 BUS_DMASYNC_POSTREAD); 2329 fw_bus_dmamap_unload( 2330 sc->ir[dmach].dmat, db_tr->dma_map); 2331 } else if (ir->buf != NULL) { 2332 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2333 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2334 } else { 2335 /* XXX */ 2336 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2337 } 2338 2339 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2340 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2341 switch (stat & FWOHCIEV_MASK) { 2342 case FWOHCIEV_ACKCOMPL: 2343 chunk->resp = 0; 2344 break; 2345 default: 2346 chunk->resp = EINVAL; 2347 fw_printf(fc->dev, "Isochronous receive err %02x(%s)\n", 2348 stat, fwohcicode[stat & 0x1f]); 2349 } 2350 w++; 2351 } 2352 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2353 FW_GUNLOCK(fc); 2354 splx(s); 2355 if (w == 0) 2356 return; 2357 if (ir->flag & FWXFERQ_HANDLER) 2358 ir->hand(ir); 2359 else 2360 wakeup(ir); 2361 } 2362 2363 void 2364 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2365 { 2366 uint32_t off, cntl, stat, cmd, match; 2367 2368 if(ch == 0){ 2369 off = OHCI_ATQOFF; 2370 }else if(ch == 1){ 2371 off = OHCI_ATSOFF; 2372 }else if(ch == 2){ 2373 off = OHCI_ARQOFF; 2374 }else if(ch == 3){ 2375 off = OHCI_ARSOFF; 2376 }else if(ch < IRX_CH){ 2377 off = OHCI_ITCTL(ch - ITX_CH); 2378 }else{ 2379 off = OHCI_IRCTL(ch - IRX_CH); 2380 } 2381 cntl = stat = OREAD(sc, off); 2382 cmd = OREAD(sc, off + 0xc); 2383 match = OREAD(sc, off + 0x10); 2384 2385 fw_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2386 ch, 2387 cntl, 2388 cmd, 2389 match); 2390 stat &= 0xffff ; 2391 if (stat) { 2392 fw_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2393 ch, 2394 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2395 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2396 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2397 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2398 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2399 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2400 fwohcicode[stat & 0x1f], 2401 stat & 0x1f 2402 ); 2403 }else{ 2404 fw_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2405 } 2406 } 2407 2408 void 2409 dump_db(struct fwohci_softc *sc, uint32_t ch) 2410 { 2411 struct fwohci_dbch *dbch; 2412 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2413 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2414 int idb, jdb; 2415 uint32_t cmd, off; 2416 if(ch == 0){ 2417 off = OHCI_ATQOFF; 2418 dbch = &sc->atrq; 2419 }else if(ch == 1){ 2420 off = OHCI_ATSOFF; 2421 dbch = &sc->atrs; 2422 }else if(ch == 2){ 2423 off = OHCI_ARQOFF; 2424 dbch = &sc->arrq; 2425 }else if(ch == 3){ 2426 off = OHCI_ARSOFF; 2427 dbch = &sc->arrs; 2428 }else if(ch < IRX_CH){ 2429 off = OHCI_ITCTL(ch - ITX_CH); 2430 dbch = &sc->it[ch - ITX_CH]; 2431 }else { 2432 off = OHCI_IRCTL(ch - IRX_CH); 2433 dbch = &sc->ir[ch - IRX_CH]; 2434 } 2435 cmd = OREAD(sc, off + 0xc); 2436 2437 if( dbch->ndb == 0 ){ 2438 fw_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2439 return; 2440 } 2441 pp = dbch->top; 2442 prev = pp->db; 2443 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2444 cp = STAILQ_NEXT(pp, link); 2445 if(cp == NULL){ 2446 curr = NULL; 2447 goto outdb; 2448 } 2449 np = STAILQ_NEXT(cp, link); 2450 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2451 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2452 curr = cp->db; 2453 if(np != NULL){ 2454 next = np->db; 2455 }else{ 2456 next = NULL; 2457 } 2458 goto outdb; 2459 } 2460 } 2461 pp = STAILQ_NEXT(pp, link); 2462 if(pp == NULL){ 2463 curr = NULL; 2464 goto outdb; 2465 } 2466 prev = pp->db; 2467 } 2468 outdb: 2469 if( curr != NULL){ 2470 #if 0 2471 printf("Prev DB %d\n", ch); 2472 print_db(pp, prev, ch, dbch->ndesc); 2473 #endif 2474 printf("Current DB %d\n", ch); 2475 print_db(cp, curr, ch, dbch->ndesc); 2476 #if 0 2477 printf("Next DB %d\n", ch); 2478 print_db(np, next, ch, dbch->ndesc); 2479 #endif 2480 }else{ 2481 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2482 } 2483 return; 2484 } 2485 2486 void 2487 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2488 uint32_t ch, uint32_t hogemax) 2489 { 2490 fwohcireg_t stat; 2491 int i, key; 2492 uint32_t cmd, res; 2493 2494 if(db == NULL){ 2495 printf("No Descriptor is found\n"); 2496 return; 2497 } 2498 2499 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2500 ch, 2501 "Current", 2502 "OP ", 2503 "KEY", 2504 "INT", 2505 "BR ", 2506 "len", 2507 "Addr", 2508 "Depend", 2509 "Stat", 2510 "Cnt"); 2511 for( i = 0 ; i <= hogemax ; i ++){ 2512 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2513 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2514 key = cmd & OHCI_KEY_MASK; 2515 stat = res >> OHCI_STATUS_SHIFT; 2516 #if defined(__DragonFly__) || \ 2517 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2518 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2519 db_tr->bus_addr, 2520 #else 2521 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2522 (uintmax_t)db_tr->bus_addr, 2523 #endif 2524 dbcode[(cmd >> 28) & 0xf], 2525 dbkey[(cmd >> 24) & 0x7], 2526 dbcond[(cmd >> 20) & 0x3], 2527 dbcond[(cmd >> 18) & 0x3], 2528 cmd & OHCI_COUNT_MASK, 2529 FWOHCI_DMA_READ(db[i].db.desc.addr), 2530 FWOHCI_DMA_READ(db[i].db.desc.depend), 2531 stat, 2532 res & OHCI_COUNT_MASK); 2533 if(stat & 0xff00){ 2534 printf(" %s%s%s%s%s%s %s(%x)\n", 2535 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2536 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2537 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2538 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2539 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2540 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2541 fwohcicode[stat & 0x1f], 2542 stat & 0x1f 2543 ); 2544 }else{ 2545 printf(" Nostat\n"); 2546 } 2547 if(key == OHCI_KEY_ST2 ){ 2548 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2549 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2550 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2551 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2552 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2553 } 2554 if(key == OHCI_KEY_DEVICE){ 2555 return; 2556 } 2557 if((cmd & OHCI_BRANCH_MASK) 2558 == OHCI_BRANCH_ALWAYS){ 2559 return; 2560 } 2561 if((cmd & OHCI_CMD_MASK) 2562 == OHCI_OUTPUT_LAST){ 2563 return; 2564 } 2565 if((cmd & OHCI_CMD_MASK) 2566 == OHCI_INPUT_LAST){ 2567 return; 2568 } 2569 if(key == OHCI_KEY_ST2 ){ 2570 i++; 2571 } 2572 } 2573 return; 2574 } 2575 2576 void 2577 fwohci_ibr(struct firewire_comm *fc) 2578 { 2579 struct fwohci_softc *sc; 2580 uint32_t fun; 2581 2582 fw_printf(fc->dev, "Initiate bus reset\n"); 2583 sc = (struct fwohci_softc *)fc; 2584 2585 /* 2586 * Make sure our cached values from the config rom are 2587 * initialised. 2588 */ 2589 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2590 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2591 2592 /* 2593 * Set root hold-off bit so that non cyclemaster capable node 2594 * shouldn't became the root node. 2595 */ 2596 #if 1 2597 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2598 fun |= FW_PHY_IBR | FW_PHY_RHB; 2599 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2600 #else /* Short bus reset */ 2601 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2602 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2603 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2604 #endif 2605 } 2606 2607 void 2608 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2609 { 2610 struct fwohcidb_tr *db_tr, *fdb_tr; 2611 struct fwohci_dbch *dbch; 2612 struct fwohcidb *db; 2613 struct fw_pkt *fp; 2614 struct fwohci_txpkthdr *ohcifp; 2615 unsigned short chtag; 2616 int idb; 2617 2618 FW_GLOCK_ASSERT(&sc->fc); 2619 2620 dbch = &sc->it[dmach]; 2621 chtag = sc->it[dmach].xferq.flag & 0xff; 2622 2623 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2624 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2625 /* 2626 fw_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2627 */ 2628 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2629 db = db_tr->db; 2630 fp = (struct fw_pkt *)db_tr->buf; 2631 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2632 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2633 ohcifp->mode.common.spd = 0 & 0x7; 2634 ohcifp->mode.stream.len = fp->mode.stream.len; 2635 ohcifp->mode.stream.chtag = chtag; 2636 ohcifp->mode.stream.tcode = 0xa; 2637 #if BYTE_ORDER == BIG_ENDIAN 2638 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2639 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2640 #endif 2641 2642 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2643 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2644 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2645 #if 0 /* if bulkxfer->npackets changes */ 2646 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2647 | OHCI_UPDATE 2648 | OHCI_BRANCH_ALWAYS; 2649 db[0].db.desc.depend = 2650 = db[dbch->ndesc - 1].db.desc.depend 2651 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2652 #else 2653 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2654 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2655 #endif 2656 bulkxfer->end = (void *)db_tr; 2657 db_tr = STAILQ_NEXT(db_tr, link); 2658 } 2659 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2660 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2661 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2662 #if 0 /* if bulkxfer->npackets changes */ 2663 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2664 /* OHCI 1.1 and above */ 2665 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2666 #endif 2667 /* 2668 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2669 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2670 fw_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2671 */ 2672 return; 2673 } 2674 2675 static int 2676 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2677 int poffset) 2678 { 2679 struct fwohcidb *db = db_tr->db; 2680 struct fw_xferq *it; 2681 int err = 0; 2682 2683 it = &dbch->xferq; 2684 if(it->buf == 0){ 2685 err = EINVAL; 2686 return err; 2687 } 2688 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2689 db_tr->dbcnt = 3; 2690 2691 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2692 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2693 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2694 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2695 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2696 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2697 2698 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2699 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2700 #if 1 2701 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2702 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2703 #endif 2704 return 0; 2705 } 2706 2707 int 2708 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2709 int poffset, struct fwdma_alloc *dummy_dma) 2710 { 2711 struct fwohcidb *db = db_tr->db; 2712 struct fw_xferq *ir; 2713 int i, ldesc; 2714 bus_addr_t dbuf[2]; 2715 int dsiz[2]; 2716 2717 ir = &dbch->xferq; 2718 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2719 if (db_tr->buf == NULL) 2720 db_tr->buf = fwdma_malloc_size( 2721 dbch->dmat, &db_tr->dma_map, 2722 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2723 if (db_tr->buf == NULL) 2724 return(ENOMEM); 2725 db_tr->dbcnt = 1; 2726 dsiz[0] = ir->psize; 2727 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2728 BUS_DMASYNC_PREREAD); 2729 } else { 2730 db_tr->dbcnt = 0; 2731 if (dummy_dma != NULL) { 2732 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2733 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2734 } 2735 dsiz[db_tr->dbcnt] = ir->psize; 2736 if (ir->buf != NULL) { 2737 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2738 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2739 } 2740 db_tr->dbcnt++; 2741 } 2742 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2743 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2744 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2745 if (ir->flag & FWXFERQ_STREAM) { 2746 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2747 } 2748 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2749 } 2750 ldesc = db_tr->dbcnt - 1; 2751 if (ir->flag & FWXFERQ_STREAM) { 2752 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2753 } 2754 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2755 return 0; 2756 } 2757 2758 2759 static int 2760 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2761 { 2762 struct fw_pkt *fp0; 2763 uint32_t ld0; 2764 int slen, hlen; 2765 #if BYTE_ORDER == BIG_ENDIAN 2766 int i; 2767 #endif 2768 2769 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2770 #if 0 2771 printf("ld0: x%08x\n", ld0); 2772 #endif 2773 fp0 = (struct fw_pkt *)&ld0; 2774 /* determine length to swap */ 2775 switch (fp0->mode.common.tcode) { 2776 case FWTCODE_WRES: 2777 CTR0(KTR_DEV, "WRES"); 2778 case FWTCODE_RREQQ: 2779 case FWTCODE_WREQQ: 2780 case FWTCODE_RRESQ: 2781 case FWOHCITCODE_PHY: 2782 slen = 12; 2783 break; 2784 case FWTCODE_RREQB: 2785 case FWTCODE_WREQB: 2786 case FWTCODE_LREQ: 2787 case FWTCODE_RRESB: 2788 case FWTCODE_LRES: 2789 slen = 16; 2790 break; 2791 default: 2792 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2793 return(0); 2794 } 2795 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2796 if (hlen > len) { 2797 if (firewire_debug) 2798 printf("splitted header\n"); 2799 return(-hlen); 2800 } 2801 #if BYTE_ORDER == BIG_ENDIAN 2802 for(i = 0; i < slen/4; i ++) 2803 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2804 #endif 2805 return(hlen); 2806 } 2807 2808 static int 2809 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2810 { 2811 const struct tcode_info *info; 2812 int r; 2813 2814 info = &tinfo[fp->mode.common.tcode]; 2815 r = info->hdr_len + sizeof(uint32_t); 2816 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2817 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2818 2819 if (r == sizeof(uint32_t)) { 2820 /* XXX */ 2821 fw_printf(sc->fc.dev, "Unknown tcode %d\n", 2822 fp->mode.common.tcode); 2823 return (-1); 2824 } 2825 2826 if (r > dbch->xferq.psize) { 2827 fw_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2828 return (-1); 2829 /* panic ? */ 2830 } 2831 2832 return r; 2833 } 2834 2835 static void 2836 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2837 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2838 { 2839 struct fwohcidb *db = &db_tr->db[0]; 2840 2841 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2842 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2843 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2844 fwdma_sync_multiseg_all(dbch->am, 2845 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2846 dbch->bottom = db_tr; 2847 2848 if (wake) 2849 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2850 } 2851 2852 static void 2853 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2854 { 2855 struct fwohcidb_tr *db_tr; 2856 struct iovec vec[2]; 2857 struct fw_pkt pktbuf; 2858 int nvec; 2859 struct fw_pkt *fp; 2860 uint8_t *ld; 2861 uint32_t stat, off, status, event; 2862 u_int spd; 2863 int len, plen, hlen, pcnt, offset; 2864 int s; 2865 void *buf; 2866 int resCount; 2867 2868 CTR0(KTR_DEV, "fwohci_arv"); 2869 2870 if(&sc->arrq == dbch){ 2871 off = OHCI_ARQOFF; 2872 }else if(&sc->arrs == dbch){ 2873 off = OHCI_ARSOFF; 2874 }else{ 2875 return; 2876 } 2877 2878 s = splfw(); 2879 db_tr = dbch->top; 2880 pcnt = 0; 2881 /* XXX we cannot handle a packet which lies in more than two buf */ 2882 fwdma_sync_multiseg_all(dbch->am, 2883 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2884 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2885 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2886 while (status & OHCI_CNTL_DMA_ACTIVE) { 2887 #if 0 2888 2889 if (off == OHCI_ARQOFF) 2890 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2891 db_tr->bus_addr, status, resCount); 2892 #endif 2893 len = dbch->xferq.psize - resCount; 2894 ld = (uint8_t *)db_tr->buf; 2895 if (dbch->pdb_tr == NULL) { 2896 len -= dbch->buf_offset; 2897 ld += dbch->buf_offset; 2898 } 2899 if (len > 0) 2900 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2901 BUS_DMASYNC_POSTREAD); 2902 while (len > 0 ) { 2903 if (count >= 0 && count-- == 0) 2904 goto out; 2905 if(dbch->pdb_tr != NULL){ 2906 /* we have a fragment in previous buffer */ 2907 int rlen; 2908 2909 offset = dbch->buf_offset; 2910 if (offset < 0) 2911 offset = - offset; 2912 buf = (char *)dbch->pdb_tr->buf + offset; 2913 rlen = dbch->xferq.psize - offset; 2914 if (firewire_debug) 2915 printf("rlen=%d, offset=%d\n", 2916 rlen, dbch->buf_offset); 2917 if (dbch->buf_offset < 0) { 2918 /* splitted in header, pull up */ 2919 char *p; 2920 2921 p = (char *)&pktbuf; 2922 bcopy(buf, p, rlen); 2923 p += rlen; 2924 /* this must be too long but harmless */ 2925 rlen = sizeof(pktbuf) - rlen; 2926 if (rlen < 0) 2927 printf("why rlen < 0\n"); 2928 bcopy(db_tr->buf, p, rlen); 2929 ld += rlen; 2930 len -= rlen; 2931 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2932 if (hlen <= 0) { 2933 printf("hlen should be positive."); 2934 goto err; 2935 } 2936 offset = sizeof(pktbuf); 2937 vec[0].iov_base = (char *)&pktbuf; 2938 vec[0].iov_len = offset; 2939 } else { 2940 /* splitted in payload */ 2941 offset = rlen; 2942 vec[0].iov_base = buf; 2943 vec[0].iov_len = rlen; 2944 } 2945 fp=(struct fw_pkt *)vec[0].iov_base; 2946 nvec = 1; 2947 } else { 2948 /* no fragment in previous buffer */ 2949 fp=(struct fw_pkt *)ld; 2950 hlen = fwohci_arcv_swap(fp, len); 2951 if (hlen == 0) 2952 goto err; 2953 if (hlen < 0) { 2954 dbch->pdb_tr = db_tr; 2955 dbch->buf_offset = - dbch->buf_offset; 2956 /* sanity check */ 2957 if (resCount != 0) { 2958 printf("resCount=%d hlen=%d\n", 2959 resCount, hlen); 2960 goto err; 2961 } 2962 goto out; 2963 } 2964 offset = 0; 2965 nvec = 0; 2966 } 2967 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2968 if (plen < 0) { 2969 /* minimum header size + trailer 2970 = sizeof(fw_pkt) so this shouldn't happens */ 2971 printf("plen(%d) is negative! offset=%d\n", 2972 plen, offset); 2973 goto err; 2974 } 2975 if (plen > 0) { 2976 len -= plen; 2977 if (len < 0) { 2978 dbch->pdb_tr = db_tr; 2979 if (firewire_debug) 2980 printf("splitted payload\n"); 2981 /* sanity check */ 2982 if (resCount != 0) { 2983 printf("resCount=%d plen=%d" 2984 " len=%d\n", 2985 resCount, plen, len); 2986 goto err; 2987 } 2988 goto out; 2989 } 2990 vec[nvec].iov_base = ld; 2991 vec[nvec].iov_len = plen; 2992 nvec ++; 2993 ld += plen; 2994 } 2995 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2996 if (nvec == 0) 2997 printf("nvec == 0\n"); 2998 2999 /* DMA result-code will be written at the tail of packet */ 3000 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3001 #if 0 3002 printf("plen: %d, stat %x\n", 3003 plen ,stat); 3004 #endif 3005 spd = (stat >> 21) & 0x3; 3006 event = (stat >> 16) & 0x1f; 3007 switch (event) { 3008 case FWOHCIEV_ACKPEND: 3009 #if 0 3010 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3011 #endif 3012 /* fall through */ 3013 case FWOHCIEV_ACKCOMPL: 3014 { 3015 struct fw_rcv_buf rb; 3016 3017 if ((vec[nvec-1].iov_len -= 3018 sizeof(struct fwohci_trailer)) == 0) 3019 nvec--; 3020 rb.fc = &sc->fc; 3021 rb.vec = vec; 3022 rb.nvec = nvec; 3023 rb.spd = spd; 3024 fw_rcv(&rb); 3025 break; 3026 } 3027 case FWOHCIEV_BUSRST: 3028 if ((sc->fc.status != FWBUSRESET) && 3029 (sc->fc.status != FWBUSINIT)) 3030 printf("got BUSRST packet!?\n"); 3031 break; 3032 default: 3033 fw_printf(sc->fc.dev, 3034 "Async DMA Receive error err=%02x %s" 3035 " plen=%d offset=%d len=%d status=0x%08x" 3036 " tcode=0x%x, stat=0x%08x\n", 3037 event, fwohcicode[event], plen, 3038 dbch->buf_offset, len, 3039 OREAD(sc, OHCI_DMACTL(off)), 3040 fp->mode.common.tcode, stat); 3041 #if 1 /* XXX */ 3042 goto err; 3043 #endif 3044 break; 3045 } 3046 pcnt ++; 3047 if (dbch->pdb_tr != NULL) { 3048 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3049 off, 1); 3050 dbch->pdb_tr = NULL; 3051 } 3052 3053 } 3054 out: 3055 if (resCount == 0) { 3056 /* done on this buffer */ 3057 if (dbch->pdb_tr == NULL) { 3058 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3059 dbch->buf_offset = 0; 3060 } else 3061 if (dbch->pdb_tr != db_tr) 3062 printf("pdb_tr != db_tr\n"); 3063 db_tr = STAILQ_NEXT(db_tr, link); 3064 fwdma_sync_multiseg_all(dbch->am, 3065 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3066 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3067 >> OHCI_STATUS_SHIFT; 3068 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3069 & OHCI_COUNT_MASK; 3070 /* XXX check buffer overrun */ 3071 dbch->top = db_tr; 3072 } else { 3073 dbch->buf_offset = dbch->xferq.psize - resCount; 3074 fw_bus_dmamap_sync( 3075 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3076 break; 3077 } 3078 /* XXX make sure DMA is not dead */ 3079 } 3080 #if 0 3081 if (pcnt < 1) 3082 printf("fwohci_arcv: no packets\n"); 3083 #endif 3084 fwdma_sync_multiseg_all(dbch->am, 3085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3086 splx(s); 3087 return; 3088 3089 err: 3090 fw_printf(sc->fc.dev, "AR DMA status=%x, ", 3091 OREAD(sc, OHCI_DMACTL(off))); 3092 dbch->pdb_tr = NULL; 3093 /* skip until resCount != 0 */ 3094 printf(" skip buffer"); 3095 while (resCount == 0) { 3096 printf(" #"); 3097 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3098 db_tr = STAILQ_NEXT(db_tr, link); 3099 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3100 & OHCI_COUNT_MASK; 3101 } 3102 printf(" done\n"); 3103 dbch->top = db_tr; 3104 dbch->buf_offset = dbch->xferq.psize - resCount; 3105 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3106 fwdma_sync_multiseg_all( 3107 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3108 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3109 splx(s); 3110 } 3111 #if defined(__NetBSD__) 3112 3113 int 3114 fwohci_print(void *aux, const char *pnp) 3115 { 3116 struct fw_attach_args *fwa = (struct fw_attach_args *)aux; 3117 3118 if (pnp) 3119 aprint_normal("%s at %s", fwa->name, pnp); 3120 3121 return UNCONF; 3122 } 3123 #endif 3124
Indexes created Tue Sep 23 14:10:03 GMT 2025