fwohci.c revision 1.15
1 /* $NetBSD: fwohci.c,v 1.15 2001/03/03 00:52:58 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/types.h> 51 #include <sys/socket.h> 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/malloc.h> 56 #include <sys/mbuf.h> 57 58 #if __NetBSD_Version__ >= 105010000 59 #include <uvm/uvm_extern.h> 60 #else 61 #include <vm/vm.h> 62 #endif 63 64 #include <machine/bus.h> 65 66 #include <dev/ieee1394/ieee1394reg.h> 67 #include <dev/ieee1394/fwohcireg.h> 68 69 #include <dev/ieee1394/ieee1394var.h> 70 #include <dev/ieee1394/fwohcivar.h> 71 72 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 73 74 #if 0 75 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 76 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 77 #endif 78 static void fwohci_hw_init(struct fwohci_softc *); 79 static void fwohci_power(int, void *); 80 static void fwohci_shutdown(void *); 81 82 static int fwohci_desc_alloc(struct fwohci_softc *); 83 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 84 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 85 86 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 87 int, int); 88 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 89 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 90 91 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 92 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 93 static void fwohci_buf_init(struct fwohci_softc *); 94 static void fwohci_buf_start(struct fwohci_softc *); 95 static void fwohci_buf_stop(struct fwohci_softc *); 96 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 97 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 98 caddr_t *, int); 99 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 100 struct fwohci_pkt *); 101 102 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 103 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 104 static void fwohci_phy_busreset(struct fwohci_softc *); 105 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 106 107 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 108 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 109 void *); 110 111 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 112 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 113 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 114 115 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 116 struct fwohci_pkt *); 117 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 118 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 119 struct fwohci_pkt *); 120 121 static void fwohci_configrom_init(struct fwohci_softc *); 122 123 static void fwohci_selfid_init(struct fwohci_softc *); 124 static int fwohci_selfid_input(struct fwohci_softc *); 125 126 static void fwohci_csr_init(struct fwohci_softc *); 127 static int fwohci_csr_input(struct fwohci_softc *, void *, 128 struct fwohci_pkt *); 129 130 static void fwohci_uid_collect(struct fwohci_softc *); 131 static int fwohci_uid_input(struct fwohci_softc *, void *, 132 struct fwohci_pkt *); 133 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 134 135 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 136 void (*)(struct device *, struct mbuf *)); 137 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 138 static int fwohci_if_output(struct device *, struct mbuf *, 139 void (*)(struct device *, struct mbuf *)); 140 141 #ifdef FW_DEBUG 142 int fw_verbose = 0; 143 int fw_dump = 0; 144 #endif 145 146 int 147 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 148 { 149 int i; 150 u_int32_t val; 151 #if 0 152 int error; 153 #endif 154 155 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 156 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 157 158 /* 159 * Wait for reset completion 160 */ 161 for (i = 0; i < OHCI_LOOP; i++) { 162 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 163 if ((val & OHCI_HCControl_SoftReset) == 0) 164 break; 165 } 166 167 /* What dialect of OHCI is this device? 168 */ 169 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 170 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 171 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 172 173 /* Is the Global UID ROM present? 174 */ 175 if ((val & OHCI_Version_GUID_ROM) == 0) { 176 printf("\n%s: fatal: no global UID ROM\n", sc->sc_sc1394.sc1394_dev.dv_xname); 177 return -1; 178 } else { 179 180 /* Extract the Global UID 181 */ 182 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 183 sc->sc_sc1394.sc1394_guid[0] = (val >> 24) & 0xff; 184 sc->sc_sc1394.sc1394_guid[1] = (val >> 16) & 0xff; 185 sc->sc_sc1394.sc1394_guid[2] = (val >> 8) & 0xff; 186 sc->sc_sc1394.sc1394_guid[3] = (val >> 0) & 0xff; 187 188 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 189 sc->sc_sc1394.sc1394_guid[4] = (val >> 24) & 0xff; 190 sc->sc_sc1394.sc1394_guid[5] = (val >> 16) & 0xff; 191 sc->sc_sc1394.sc1394_guid[6] = (val >> 8) & 0xff; 192 sc->sc_sc1394.sc1394_guid[7] = (val >> 0) & 0xff; 193 } 194 195 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 196 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 197 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 198 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 199 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 200 201 /* Get the maximum link speed and receive size 202 */ 203 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 204 sc->sc_sc1394.sc1394_link_speed = 205 (val & OHCI_BusOptions_LinkSpd_MASK) 206 >> OHCI_BusOptions_LinkSpd_BITPOS; 207 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 208 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 209 } else { 210 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 211 } 212 213 /* MaxRec is encoded as log2(max_rec_octets)-1 214 */ 215 sc->sc_sc1394.sc1394_max_receive = 216 1 << (((val & OHCI_BusOptions_MaxRec_MASK) 217 >> OHCI_BusOptions_MaxRec_BITPOS) + 1); 218 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 219 220 /* 221 * Count how many isochronous ctx we have. 222 */ 223 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 224 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 225 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 226 for (i = 0; val != 0; val >>= 1) { 227 if (val & 0x1) 228 i++; 229 } 230 sc->sc_isoctx = i; 231 printf(", %d iso_ctx", sc->sc_isoctx); 232 233 printf("\n"); 234 235 #if 0 236 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 237 &sc->sc_configrom_map, 238 (caddr_t *) &sc->sc_configrom, 239 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 240 return error; 241 #endif 242 243 /* 244 * Enable Link Power 245 */ 246 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 247 248 /* 249 * Allocate descriptors 250 */ 251 if (fwohci_desc_alloc(sc)) 252 return -1; 253 254 /* 255 * Allocate DMA Context 256 */ 257 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 258 OHCI_CTX_ASYNC_RX_REQUEST); 259 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 260 OHCI_CTX_ASYNC_RX_RESPONSE); 261 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 262 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 263 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 264 M_DEVBUF, M_WAITOK); 265 for (i = 0; i < sc->sc_isoctx; i++) { 266 sc->sc_ctx_ir[i] = NULL; 267 #if 0 268 fwohci_ctx_alloc(sc, &sc->sc_ctx_ir[i], OHCI_BUF_IR_CNT, i); 269 sc->sc_ctx_ir[i]->fc_isoch = 1; 270 #endif 271 } 272 273 /* 274 * Allocate buffer for configuration ROM and SelfID buffer 275 */ 276 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 277 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 278 279 /* 280 * establish hooks for shutdown and suspend/resume 281 */ 282 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 283 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 284 callout_init(&sc->sc_selfid_callout); 285 286 /* 287 * Initialize hardware registers. 288 */ 289 fwohci_hw_init(sc); 290 291 /* 292 * Initiate Bus Reset 293 */ 294 config_defer(&sc->sc_sc1394.sc1394_dev, 295 (void (*)(struct device *))fwohci_phy_busreset); 296 297 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 298 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 299 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 300 "fw", fwohci_print); 301 302 return 0; 303 } 304 305 int 306 fwohci_intr(void *arg) 307 { 308 struct fwohci_softc * const sc = arg; 309 int i; 310 int progress = 0; 311 u_int32_t intmask, iso; 312 313 for (;;) { 314 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 315 if (intmask == 0) 316 return progress; 317 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 318 intmask & ~OHCI_Int_BusReset); 319 #ifdef FW_DEBUG 320 if (fw_verbose) { 321 printf("%s: intmask=0x%08x:", 322 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 323 if (intmask & OHCI_Int_CycleTooLong) 324 printf(" CycleTooLong"); 325 if (intmask & OHCI_Int_UnrecoverableError) 326 printf(" UnrecoverableError"); 327 if (intmask & OHCI_Int_CycleInconsistent) 328 printf(" CycleInconsistent"); 329 if (intmask & OHCI_Int_BusReset) 330 printf(" BusReset"); 331 if (intmask & OHCI_Int_SelfIDComplete) 332 printf(" SelfIDComplete"); 333 if (intmask & OHCI_Int_LockRespErr) 334 printf(" LockRespErr"); 335 if (intmask & OHCI_Int_PostedWriteErr) 336 printf(" PostedWriteErr"); 337 if (intmask & OHCI_Int_ReqTxComplete) 338 printf(" ReqTxComplete(0x%04x)", 339 OHCI_ASYNC_DMA_READ(sc, 340 OHCI_CTX_ASYNC_TX_REQUEST, 341 OHCI_SUBREG_ContextControlClear)); 342 if (intmask & OHCI_Int_RespTxComplete) 343 printf(" RespTxComplete(0x%04x)", 344 OHCI_ASYNC_DMA_READ(sc, 345 OHCI_CTX_ASYNC_TX_RESPONSE, 346 OHCI_SUBREG_ContextControlClear)); 347 if (intmask & OHCI_Int_ARRS) 348 printf(" ARRS(0x%04x)", 349 OHCI_ASYNC_DMA_READ(sc, 350 OHCI_CTX_ASYNC_RX_RESPONSE, 351 OHCI_SUBREG_ContextControlClear)); 352 if (intmask & OHCI_Int_ARRQ) 353 printf(" ARRQ(0x%04x)", 354 OHCI_ASYNC_DMA_READ(sc, 355 OHCI_CTX_ASYNC_RX_REQUEST, 356 OHCI_SUBREG_ContextControlClear)); 357 if (intmask & OHCI_Int_IsochRx) 358 printf(" IsochRx(0x%08x)", 359 OHCI_CSR_READ(sc, 360 OHCI_REG_IsoRecvIntEventClear)); 361 if (intmask & OHCI_Int_IsochTx) 362 printf(" IsochTx(0x%08x)", 363 OHCI_CSR_READ(sc, 364 OHCI_REG_IsoXmitIntEventClear)); 365 if (intmask & OHCI_Int_RQPkt) 366 printf(" RQPkt(0x%04x)", 367 OHCI_ASYNC_DMA_READ(sc, 368 OHCI_CTX_ASYNC_RX_REQUEST, 369 OHCI_SUBREG_ContextControlClear)); 370 if (intmask & OHCI_Int_RSPkt) 371 printf(" RSPkt(0x%04x)", 372 OHCI_ASYNC_DMA_READ(sc, 373 OHCI_CTX_ASYNC_RX_RESPONSE, 374 OHCI_SUBREG_ContextControlClear)); 375 printf("\n"); 376 } 377 #endif /* FW_DEBUG */ 378 if (intmask & OHCI_Int_BusReset) { 379 /* 380 * According to OHCI spec 6.1.1 "busReset", 381 * All asynchronous transmit must be stopped before 382 * clearing BusReset. Moreover, the BusReset 383 * interrupt bit should not be cleared during the 384 * SelfID phase. Thus we turned off interrupt mask 385 * bit of BusReset instead until SelfID completion 386 * or SelfID timeout. 387 */ 388 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 389 OHCI_Int_BusReset); 390 intmask &= OHCI_Int_SelfIDComplete; 391 fwohci_buf_stop(sc); 392 fwohci_buf_init(sc); 393 if (sc->sc_uidtbl != NULL) { 394 free(sc->sc_uidtbl, M_DEVBUF); 395 sc->sc_uidtbl = NULL; 396 } 397 callout_reset(&sc->sc_selfid_callout, 398 OHCI_SELFID_TIMEOUT, 399 (void (*)(void *))fwohci_phy_busreset, sc); 400 sc->sc_nodeid = 0xffff; /* indicate invalid */ 401 sc->sc_rootid = 0; 402 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 403 } 404 405 if (intmask & OHCI_Int_SelfIDComplete) { 406 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 407 OHCI_Int_BusReset); 408 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 409 OHCI_Int_BusReset); 410 callout_stop(&sc->sc_selfid_callout); 411 if (fwohci_selfid_input(sc) == 0) { 412 fwohci_buf_start(sc); 413 fwohci_uid_collect(sc); 414 } 415 } 416 417 if (intmask & OHCI_Int_ReqTxComplete) 418 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 419 if (intmask & OHCI_Int_RespTxComplete) 420 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 421 if (intmask & OHCI_Int_RQPkt) 422 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 423 if (intmask & OHCI_Int_RSPkt) 424 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 425 426 if (intmask & OHCI_Int_IsochTx) { 427 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 428 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 429 } 430 if (intmask & OHCI_Int_IsochRx) { 431 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 432 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 433 for (i = 0; i < sc->sc_isoctx; i++) { 434 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) 435 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 436 } 437 } 438 439 if (!progress) { 440 sc->sc_intrcnt.ev_count++; 441 progress = 1; 442 } 443 } 444 } 445 446 #if 0 447 static int 448 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 449 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 450 { 451 bus_dma_segment_t segs[1]; 452 int error, nsegs, steps; 453 454 steps = 0; 455 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 456 segs, 1, &nsegs, flags); 457 if (error) 458 goto cleanup; 459 460 steps = 1; 461 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 462 kvap, flags); 463 if (error) 464 goto cleanup; 465 466 if (error == 0) 467 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 468 size, flags, mapp); 469 if (error) 470 goto cleanup; 471 if (error == 0) 472 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 473 if (error) 474 goto cleanup; 475 476 cleanup: 477 switch (steps) { 478 case 1: 479 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 480 } 481 482 return error; 483 } 484 #endif 485 486 int 487 fwohci_print(void *aux, const char *pnp) 488 { 489 char *name = aux; 490 491 if (pnp) 492 printf("%s at %s", name, pnp); 493 494 return UNCONF; 495 } 496 497 static void 498 fwohci_hw_init(struct fwohci_softc *sc) 499 { 500 int i; 501 u_int32_t val; 502 503 /* 504 * Software Reset. 505 */ 506 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 507 for (i = 0; i < OHCI_LOOP; i++) { 508 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 509 if ((val & OHCI_HCControl_SoftReset) == 0) 510 break; 511 } 512 513 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 514 515 /* 516 * First, initilize CSRs with undefined value to default settings. 517 */ 518 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 519 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 520 #if 0 521 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 522 #else 523 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 524 #endif 525 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 526 for (i = 0; i < sc->sc_isoctx; i++) { 527 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 528 ~0); 529 } 530 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 531 532 fwohci_configrom_init(sc); 533 fwohci_selfid_init(sc); 534 fwohci_buf_init(sc); 535 fwohci_csr_init(sc); 536 537 /* 538 * Final CSR settings. 539 */ 540 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 541 OHCI_LinkControl_CycleTimerEnable | 542 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 543 544 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 545 546 /* clear receive filter */ 547 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 548 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 549 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 550 551 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 552 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 553 554 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 555 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 556 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 557 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 558 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 559 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 560 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 561 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 562 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 563 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 564 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 565 566 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 567 568 /* 569 * Start the receivers 570 */ 571 fwohci_buf_start(sc); 572 } 573 574 static void 575 fwohci_power(int why, void *arg) 576 { 577 struct fwohci_softc *sc = arg; 578 int s; 579 580 s = splimp(); 581 switch (why) { 582 case PWR_SUSPEND: 583 case PWR_STANDBY: 584 fwohci_shutdown(sc); 585 break; 586 case PWR_RESUME: 587 fwohci_hw_init(sc); 588 fwohci_phy_busreset(sc); 589 break; 590 case PWR_SOFTSUSPEND: 591 case PWR_SOFTSTANDBY: 592 case PWR_SOFTRESUME: 593 break; 594 } 595 splx(s); 596 } 597 598 static void 599 fwohci_shutdown(void *arg) 600 { 601 struct fwohci_softc *sc = arg; 602 u_int32_t val; 603 604 callout_stop(&sc->sc_selfid_callout); 605 /* disable all interrupt */ 606 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 607 fwohci_buf_stop(sc); 608 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 609 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 610 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 611 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 612 fwohci_phy_busreset(sc); 613 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 614 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 615 } 616 617 /* 618 * COMMON FUNCTIONS 619 */ 620 621 /* 622 * read the PHY Register. 623 */ 624 static u_int8_t 625 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 626 { 627 int i; 628 u_int32_t val; 629 630 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 631 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 632 for (i = 0; i < OHCI_LOOP; i++) { 633 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 634 OHCI_PhyControl_RdDone) 635 break; 636 } 637 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 638 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 639 } 640 641 /* 642 * write the PHY Register. 643 */ 644 static void 645 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 646 { 647 int i; 648 649 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 650 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 651 (val << OHCI_PhyControl_WrData_BITPOS)); 652 for (i = 0; i < OHCI_LOOP; i++) { 653 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 654 OHCI_PhyControl_WrReg)) 655 break; 656 } 657 } 658 659 /* 660 * Initiate Bus Reset 661 */ 662 static void 663 fwohci_phy_busreset(struct fwohci_softc *sc) 664 { 665 int s; 666 u_int8_t val; 667 668 s = splimp(); 669 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 670 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 671 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 672 callout_stop(&sc->sc_selfid_callout); 673 val = fwohci_phy_read(sc, 1); 674 val = (val & 0x80) | /* preserve RHB (force root) */ 675 0x40 | /* Initiate Bus Reset */ 676 0x3f; /* default GAP count */ 677 fwohci_phy_write(sc, 1, val); 678 splx(s); 679 } 680 681 /* 682 * PHY Packet 683 */ 684 static void 685 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 686 { 687 u_int32_t val; 688 u_int8_t key, phyid; 689 690 val = pkt->fp_hdr[1]; 691 if (val != ~pkt->fp_hdr[2]) { 692 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 693 OHCI_CTXCTL_EVENT_BUS_RESET) { 694 #ifdef FW_DEBUG 695 if (fw_verbose) 696 printf("fwohci_phy_input: BusReset: 0x%08x\n", 697 pkt->fp_hdr[2]); 698 #endif 699 } else { 700 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 701 sc->sc_sc1394.sc1394_dev.dv_xname, val, 702 pkt->fp_hdr[2]); 703 } 704 return; 705 } 706 key = (val & 0xc0000000) >> 30; 707 phyid = (val & 0x3f000000) >> 24; 708 switch (key) { 709 case 0: 710 #ifdef FW_DEBUG 711 if (fw_verbose) { 712 printf("fwohci_phy_input: PHY Config from %d:", phyid); 713 if (val & 0x00800000) 714 printf(" ForceRoot"); 715 if (val & 0x00400000) 716 printf(" Gap=%x", (val & 0x003f0000) >> 16); 717 printf("\n"); 718 } 719 #endif 720 break; 721 case 1: 722 #ifdef FW_DEBUG 723 if (fw_verbose) 724 printf("fwohci_phy_input: Link-on from %d\n", phyid); 725 #endif 726 break; 727 case 2: 728 #ifdef FW_DEBUG 729 if (fw_verbose) { 730 printf("fwohci_phy_input: SelfID from %d:", phyid); 731 if (val & 0x00800000) { 732 printf(" #%d", (val & 0x00700000) >> 20); 733 } else { 734 if (val & 0x00400000) 735 printf(" LinkActive"); 736 printf(" Gap=%x", (val & 0x003f0000) >> 16); 737 printf(" Spd=S%d", 738 100 << ((val & 0x0000c000) >> 14)); 739 if (val & 0x00000800) 740 printf(" Cont"); 741 if (val & 0x00000002) 742 printf(" InitiateBusReset"); 743 } 744 if (val & 0x00000001) 745 printf(" +"); 746 printf("\n"); 747 } 748 #endif 749 break; 750 default: 751 printf("%s: unknown PHY packet: 0x%08x\n", 752 sc->sc_sc1394.sc1394_dev.dv_xname, val); 753 break; 754 } 755 } 756 757 /* 758 * Descriptor for context DMA. 759 */ 760 static int 761 fwohci_desc_alloc(struct fwohci_softc *sc) 762 { 763 int error, mapsize, dsize; 764 765 /* 766 * allocate descriptor buffer 767 */ 768 769 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 770 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 771 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 772 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 773 mapsize = howmany(sc->sc_descsize, NBBY); 774 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 775 memset(sc->sc_descmap, 0, mapsize); 776 777 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 778 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 779 printf("%s: unable to allocate descriptor buffer, error = %d\n", 780 sc->sc_sc1394.sc1394_dev.dv_xname, error); 781 goto fail_0; 782 } 783 784 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 785 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 786 != 0) { 787 printf("%s: unable to map descriptor buffer, error = %d\n", 788 sc->sc_sc1394.sc1394_dev.dv_xname, error); 789 goto fail_1; 790 } 791 792 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 793 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 794 printf("%s: unable to create descriptor buffer DMA map, " 795 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 796 goto fail_2; 797 } 798 799 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 800 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 801 printf("%s: unable to load descriptor buffer DMA map, " 802 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 803 goto fail_3; 804 } 805 806 return 0; 807 808 fail_3: 809 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 810 fail_2: 811 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 812 fail_1: 813 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 814 fail_0: 815 return error; 816 } 817 818 static struct fwohci_desc * 819 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 820 { 821 int i, n; 822 823 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 824 for (i = 0; ; i++) { 825 if (i == ndesc) { 826 for (i = 0; i < ndesc; i++) 827 setbit(sc->sc_descmap, n + i); 828 return sc->sc_desc + n; 829 } 830 if (isset(sc->sc_descmap, n + i)) 831 break; 832 } 833 } 834 return NULL; 835 } 836 837 static void 838 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 839 { 840 int i, n; 841 842 n = fd - sc->sc_desc; 843 for (i = 0; i < ndesc; i++, n++) { 844 #ifdef DIAGNOSTICS 845 if (isclr(sc->sc_descmap, n)) 846 panic("fwohci_desc_put: duplicated free"); 847 #endif 848 clrbit(sc->sc_descmap, n); 849 } 850 } 851 852 /* 853 * Asyncronous/Isochronous Transmit/Receive Context 854 */ 855 static int 856 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 857 int bufcnt, int ctx) 858 { 859 int i, error; 860 struct fwohci_ctx *fc; 861 struct fwohci_buf *fb; 862 struct fwohci_desc *fd; 863 864 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 865 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 866 LIST_INIT(&fc->fc_handler); 867 TAILQ_INIT(&fc->fc_buf); 868 fc->fc_ctx = ctx; 869 fc->fc_bufcnt = bufcnt; 870 fb = (struct fwohci_buf *)&fc[1]; 871 for (i = 0; i < bufcnt; i++, fb++) { 872 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 873 goto fail; 874 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 875 error = ENOBUFS; 876 goto fail; 877 } 878 fb->fb_desc = fd; 879 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 880 ((caddr_t)fd - (caddr_t)sc->sc_desc); 881 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 882 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 883 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 884 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 885 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 886 } 887 *fcp = fc; 888 return 0; 889 890 fail: 891 while (i-- > 0) 892 fwohci_buf_free(sc, --fb); 893 free(fc, M_DEVBUF); 894 return error; 895 } 896 897 static void 898 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 899 { 900 struct fwohci_buf *fb; 901 struct fwohci_handler *fh; 902 903 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 904 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 905 NULL, NULL); 906 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 907 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 908 fwohci_buf_free(sc, fb); 909 } 910 free(fc, M_DEVBUF); 911 } 912 913 static void 914 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 915 { 916 struct fwohci_buf *fb, *nfb; 917 struct fwohci_desc *fd; 918 int n; 919 920 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 921 nfb = TAILQ_NEXT(fb, fb_list); 922 fb->fb_off = 0; 923 fd = fb->fb_desc; 924 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 925 fd->fd_rescount = fd->fd_reqcount; 926 } 927 928 n = fc->fc_ctx; 929 fb = TAILQ_FIRST(&fc->fc_buf); 930 if (fc->fc_isoch) { 931 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 932 fb->fb_daddr | 1); 933 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 934 OHCI_CTXCTL_RX_BUFFER_FILL | 935 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 936 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 937 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 938 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 939 OHCI_CTXCTL_RX_ISOCH_HEADER); 940 } else { 941 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 942 fb->fb_daddr | 1); 943 } 944 } 945 946 /* 947 * DMA data buffer 948 */ 949 static int 950 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 951 { 952 int error; 953 954 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 955 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 956 printf("%s: unable to allocate buffer, error = %d\n", 957 sc->sc_sc1394.sc1394_dev.dv_xname, error); 958 goto fail_0; 959 } 960 961 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 962 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 963 printf("%s: unable to map buffer, error = %d\n", 964 sc->sc_sc1394.sc1394_dev.dv_xname, error); 965 goto fail_1; 966 } 967 968 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 969 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 970 printf("%s: unable to create buffer DMA map, " 971 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 972 error); 973 goto fail_2; 974 } 975 976 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 977 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 978 printf("%s: unable to load buffer DMA map, " 979 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 980 error); 981 goto fail_3; 982 } 983 984 return 0; 985 986 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 987 fail_3: 988 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 989 fail_2: 990 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 991 fail_1: 992 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 993 fail_0: 994 return error; 995 } 996 997 static void 998 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 999 { 1000 1001 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1002 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1003 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1004 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1005 } 1006 1007 static void 1008 fwohci_buf_init(struct fwohci_softc *sc) 1009 { 1010 int i; 1011 1012 /* 1013 * Initialize for Asynchronous Transmit Queue. 1014 */ 1015 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1016 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1017 1018 /* 1019 * Initialize for Asynchronous Receive Queue. 1020 */ 1021 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1022 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1023 1024 /* 1025 * Initialize for Isochronous Receive Queue. 1026 */ 1027 for (i = 0; i < sc->sc_isoctx; i++) { 1028 if (sc->sc_ctx_ir[i] != NULL) 1029 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1030 } 1031 } 1032 1033 static void 1034 fwohci_buf_start(struct fwohci_softc *sc) 1035 { 1036 int i; 1037 1038 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1039 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1040 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1041 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1042 for (i = 0; i < sc->sc_isoctx; i++) { 1043 if (sc->sc_ctx_ir[i] != NULL && 1044 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1045 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1046 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1047 } 1048 } 1049 } 1050 1051 static void 1052 fwohci_buf_stop(struct fwohci_softc *sc) 1053 { 1054 int i, j; 1055 1056 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1057 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1058 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1059 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1060 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1061 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1062 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1063 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1064 for (i = 0; i < sc->sc_isoctx; i++) { 1065 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1066 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1067 } 1068 1069 /* 1070 * Make sure the transmitter is stopped. 1071 */ 1072 for (j = 0; j < OHCI_LOOP; j++) { 1073 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1074 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1075 continue; 1076 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1077 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1078 continue; 1079 break; 1080 } 1081 } 1082 1083 static void 1084 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1085 { 1086 struct fwohci_buf *fb, *tfb; 1087 1088 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1089 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1090 fb->fb_desc->fd_rescount != 0) 1091 break; 1092 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1093 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1094 fb->fb_off = 0; 1095 fb->fb_desc->fd_branch = 0; 1096 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1097 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1098 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1099 } 1100 } 1101 1102 static int 1103 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1104 int len) 1105 { 1106 struct fwohci_buf *fb; 1107 struct fwohci_desc *fd; 1108 int bufend; 1109 1110 fb = TAILQ_FIRST(&fc->fc_buf); 1111 again: 1112 fd = fb->fb_desc; 1113 #ifdef FW_DEBUG 1114 if (fw_verbose) 1115 printf("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1116 " len %d, avail %d\n", 1117 (long)(fd - sc->sc_desc), fb->fb_off, fd->fd_reqcount, 1118 fd->fd_rescount, len, 1119 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1120 #endif 1121 bufend = fd->fd_reqcount - fd->fd_rescount; 1122 if (fb->fb_off >= bufend) { 1123 if (fc->fc_isoch && fb->fb_off > 0) { 1124 fb->fb_off = fd->fd_reqcount; 1125 fd->fd_rescount = 0; 1126 } 1127 if (fd->fd_rescount == 0) { 1128 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1129 goto again; 1130 } 1131 return 0; 1132 } 1133 if (fb->fb_off + len > bufend) 1134 len = bufend - fb->fb_off; 1135 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1136 BUS_DMASYNC_POSTREAD); 1137 *pp = fb->fb_buf + fb->fb_off; 1138 fb->fb_off += roundup(len, 4); 1139 return len; 1140 } 1141 1142 static int 1143 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1144 struct fwohci_pkt *pkt) 1145 { 1146 caddr_t p; 1147 int len, count, i; 1148 1149 memset(pkt, 0, sizeof(*pkt)); 1150 pkt->fp_uio.uio_iov = pkt->fp_iov; 1151 pkt->fp_uio.uio_rw = UIO_WRITE; 1152 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1153 1154 /* get first quadlet */ 1155 count = 4; 1156 if (fc->fc_isoch) { 1157 /* 1158 * get trailer first, may be bogus data unless status update 1159 * in descriptor is set. 1160 */ 1161 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1162 sizeof(*pkt->fp_trail)); 1163 if (len <= 0) { 1164 #ifdef FW_DEBUG 1165 if (fw_verbose) 1166 printf("fwohci_buf_input: no input for is#%d\n", 1167 fc->fc_ctx); 1168 #endif 1169 return 0; 1170 } 1171 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1172 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1173 } 1174 len = fwohci_buf_pktget(sc, fc, &p, count); 1175 if (len <= 0) { 1176 #ifdef FW_DEBUG 1177 if (fw_verbose) 1178 printf("fwohci_buf_input: no input for %d\n", 1179 fc->fc_ctx); 1180 #endif 1181 return 0; 1182 } 1183 pkt->fp_hdr[0] = *(u_int32_t *)p; 1184 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1185 switch (pkt->fp_tcode) { 1186 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1187 case IEEE1394_TCODE_READ_RESP_QUAD: 1188 pkt->fp_hlen = 12; 1189 pkt->fp_dlen = 4; 1190 break; 1191 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1192 case IEEE1394_TCODE_READ_RESP_BLOCK: 1193 case IEEE1394_TCODE_LOCK_REQ: 1194 case IEEE1394_TCODE_LOCK_RESP: 1195 pkt->fp_hlen = 16; 1196 break; 1197 case IEEE1394_TCODE_STREAM_DATA: 1198 pkt->fp_hlen = 4; 1199 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1200 break; 1201 default: 1202 pkt->fp_hlen = 12; 1203 pkt->fp_dlen = 0; 1204 break; 1205 } 1206 1207 /* get header */ 1208 while (count < pkt->fp_hlen) { 1209 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1210 if (len == 0) { 1211 printf("fwohci_buf_input: malformed input 1: %d\n", 1212 pkt->fp_hlen - count); 1213 return 0; 1214 } 1215 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1216 count += len; 1217 } 1218 if (pkt->fp_hlen == 16) 1219 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1220 #ifdef FW_DEBUG 1221 if (fw_verbose) 1222 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1223 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1224 #endif 1225 1226 /* get data */ 1227 count = 0; 1228 i = 0; 1229 while (count < pkt->fp_dlen) { 1230 len = fwohci_buf_pktget(sc, fc, 1231 (caddr_t *)&pkt->fp_iov[i].iov_base, 1232 pkt->fp_dlen - count); 1233 if (len == 0) { 1234 printf("fwohci_buf_input: malformed input 2: %d\n", 1235 pkt->fp_hlen - count); 1236 return 0; 1237 } 1238 pkt->fp_iov[i++].iov_len = len; 1239 count += len; 1240 } 1241 pkt->fp_uio.uio_iovcnt = i; 1242 pkt->fp_uio.uio_resid = count; 1243 1244 if (!fc->fc_isoch) { 1245 /* get trailer */ 1246 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1247 sizeof(*pkt->fp_trail)); 1248 if (len <= 0) { 1249 printf("fwohci_buf_input: malformed input 3: %d\n", 1250 pkt->fp_hlen - count); 1251 return 0; 1252 } 1253 } 1254 return 1; 1255 } 1256 1257 static int 1258 fwohci_handler_set(struct fwohci_softc *sc, 1259 int tcode, u_int32_t key1, u_int32_t key2, 1260 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1261 void *arg) 1262 { 1263 struct fwohci_ctx *fc; 1264 struct fwohci_handler *fh; 1265 int i, j; 1266 1267 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1268 j = sc->sc_isoctx; 1269 fh = NULL; 1270 for (i = 0; i < sc->sc_isoctx; i++) { 1271 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1272 if (j == sc->sc_isoctx) 1273 j = i; 1274 continue; 1275 } 1276 fh = LIST_FIRST(&fc->fc_handler); 1277 if (fh == NULL) { 1278 j = i; 1279 break; 1280 } 1281 if (fh->fh_tcode == tcode && 1282 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1283 break; 1284 fh = NULL; 1285 } 1286 if (fh == NULL) { 1287 if (handler == NULL) 1288 return 0; 1289 if (j == sc->sc_isoctx) { 1290 #ifdef FW_DEBUG 1291 if (fw_verbose) 1292 printf("fwohci_handler_set: " 1293 "no more free context\n"); 1294 #endif 1295 return ENOMEM; 1296 } 1297 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1298 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1299 fc->fc_isoch = 1; 1300 sc->sc_ctx_ir[j] = fc; 1301 } 1302 } 1303 } else { 1304 switch (tcode) { 1305 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1306 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1307 case IEEE1394_TCODE_READ_REQ_QUAD: 1308 case IEEE1394_TCODE_READ_REQ_BLOCK: 1309 case IEEE1394_TCODE_LOCK_REQ: 1310 fc = sc->sc_ctx_arrq; 1311 break; 1312 case IEEE1394_TCODE_WRITE_RESP: 1313 case IEEE1394_TCODE_READ_RESP_QUAD: 1314 case IEEE1394_TCODE_READ_RESP_BLOCK: 1315 case IEEE1394_TCODE_LOCK_RESP: 1316 fc = sc->sc_ctx_arrs; 1317 break; 1318 default: 1319 return EIO; 1320 } 1321 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1322 fh = LIST_NEXT(fh, fh_list)) { 1323 if (fh->fh_tcode == tcode && 1324 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1325 break; 1326 } 1327 } 1328 if (handler == NULL) { 1329 if (fh != NULL) { 1330 LIST_REMOVE(fh, fh_list); 1331 free(fh, M_DEVBUF); 1332 } 1333 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1334 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1335 fwohci_ctx_free(sc, fc); 1336 } 1337 return 0; 1338 } 1339 if (fh == NULL) { 1340 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 1341 if (fh == NULL) 1342 return ENOMEM; 1343 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1344 } 1345 fh->fh_tcode = tcode; 1346 fh->fh_key1 = key1; 1347 fh->fh_key2 = key2; 1348 fh->fh_handler = handler; 1349 fh->fh_handarg = arg; 1350 #ifdef FW_DEBUG 1351 if (fw_verbose) 1352 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1353 fc->fc_ctx, tcode, key1, key2); 1354 #endif 1355 1356 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1357 fwohci_ctx_init(sc, fc); 1358 #ifdef FW_DEBUG 1359 if (fw_verbose) 1360 printf("fwohci_handler_set: SYNC desc %ld\n", 1361 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - 1362 sc->sc_desc)); 1363 #endif 1364 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextMatch, 1365 (OHCI_CTXMATCH_TAG0 << key2) | key1); 1366 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1367 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1368 } 1369 return 0; 1370 } 1371 1372 /* 1373 * Asyncronous Receive Requests input frontend. 1374 */ 1375 static void 1376 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1377 { 1378 int rcode; 1379 u_int32_t key1, key2; 1380 struct fwohci_handler *fh; 1381 struct fwohci_pkt pkt, res; 1382 1383 while (fwohci_buf_input(sc, fc, &pkt)) { 1384 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1385 fwohci_phy_input(sc, &pkt); 1386 continue; 1387 } 1388 key1 = pkt.fp_hdr[1] & 0xffff; 1389 key2 = pkt.fp_hdr[2]; 1390 memset(&res, 0, sizeof(res)); 1391 res.fp_uio.uio_rw = UIO_WRITE; 1392 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1393 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1394 fh = LIST_NEXT(fh, fh_list)) { 1395 if (pkt.fp_tcode == fh->fh_tcode && 1396 key1 == fh->fh_key1 && 1397 key2 == fh->fh_key2) { 1398 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1399 &pkt); 1400 break; 1401 } 1402 } 1403 if (fh == NULL) { 1404 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1405 #ifdef FW_DEBUG 1406 if (fw_verbose) 1407 printf("fwohci_arrq_input: no listener:" 1408 " tcode 0x%x, addr=0x%04x %08x\n", 1409 pkt.fp_tcode, key1, key2); 1410 #endif 1411 } 1412 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1413 OHCI_CTXCTL_EVENT_ACK_PENDING) 1414 continue; 1415 if (rcode != -1) 1416 fwohci_atrs_output(sc, rcode, &pkt, &res); 1417 } 1418 fwohci_buf_next(sc, fc); 1419 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1420 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1421 } 1422 1423 /* 1424 * Asynchronous Receive Response input frontend. 1425 */ 1426 static void 1427 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1428 { 1429 struct fwohci_pkt pkt; 1430 struct fwohci_handler *fh; 1431 u_int16_t srcid; 1432 int rcode, tlabel; 1433 1434 while (fwohci_buf_input(sc, fc, &pkt)) { 1435 srcid = pkt.fp_hdr[1] >> 16; 1436 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1437 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1438 #ifdef FW_DEBUG 1439 if (fw_verbose) 1440 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1441 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1442 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1443 pkt.fp_dlen); 1444 #endif 1445 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1446 fh = LIST_NEXT(fh, fh_list)) { 1447 if (pkt.fp_tcode == fh->fh_tcode && 1448 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1449 tlabel == fh->fh_key2) { 1450 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1451 LIST_REMOVE(fh, fh_list); 1452 free(fh, M_DEVBUF); 1453 break; 1454 } 1455 } 1456 #ifdef FW_DEBUG 1457 if (fw_verbose) 1458 if (fh == NULL) 1459 printf("fwohci_arrs_input: no lister\n"); 1460 #endif 1461 } 1462 fwohci_buf_next(sc, fc); 1463 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1464 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1465 } 1466 1467 /* 1468 * Isochronous Receive input frontend. 1469 */ 1470 static void 1471 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1472 { 1473 int rcode, chan, tag; 1474 struct iovec *iov; 1475 struct fwohci_handler *fh; 1476 struct fwohci_pkt pkt; 1477 1478 while (fwohci_buf_input(sc, fc, &pkt)) { 1479 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1480 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1481 #ifdef FW_DEBUG 1482 if (fw_verbose) 1483 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1484 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1485 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1486 #endif 1487 if (tag == IEEE1394_TAG_GASP) { 1488 /* 1489 * The pkt with tag=3 is GASP format. 1490 * Move GASP header to header part. 1491 */ 1492 if (pkt.fp_dlen < 8) 1493 continue; 1494 iov = pkt.fp_iov; 1495 /* assuming pkt per buffer mode */ 1496 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1497 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1498 iov->iov_base = (caddr_t)iov->iov_base + 8; 1499 iov->iov_len -= 8; 1500 pkt.fp_hlen += 8; 1501 pkt.fp_dlen -= 8; 1502 } 1503 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1504 fh = LIST_NEXT(fh, fh_list)) { 1505 if (pkt.fp_tcode == fh->fh_tcode && 1506 chan == fh->fh_key1 && tag == fh->fh_key2) { 1507 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1508 &pkt); 1509 break; 1510 } 1511 } 1512 #ifdef FW_DEBUG 1513 if (fw_verbose) { 1514 if (fh == NULL) 1515 printf("fwohci_ir_input: no handler\n"); 1516 else 1517 printf("fwohci_ir_input: rcode %d\n", rcode); 1518 } 1519 #endif 1520 } 1521 fwohci_buf_next(sc, fc); 1522 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1523 OHCI_CTXCTL_WAKE); 1524 } 1525 1526 /* 1527 * Asynchronous Transmit common routine. 1528 */ 1529 static int 1530 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1531 struct fwohci_pkt *pkt) 1532 { 1533 struct fwohci_buf *fb; 1534 struct fwohci_desc *fd; 1535 struct mbuf *m, *m0; 1536 int i, ndesc, error, off, len; 1537 u_int32_t val; 1538 1539 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) { 1540 /* We can't send anything during selfid duration */ 1541 return EAGAIN; 1542 } 1543 #ifdef FW_DEBUG 1544 if (fw_verbose) { 1545 struct iovec *iov; 1546 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1547 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1548 if (fw_dump) { 1549 for (i = 0; i < pkt->fp_hlen/4; i++) 1550 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1551 printf("$"); 1552 for (ndesc = 0, iov = pkt->fp_iov; 1553 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1554 for (i = 0; i < iov->iov_len; i++) 1555 printf("%s%02x", 1556 (i%32)?((i%4)?"":" "):"\n\t", 1557 ((u_int8_t *)iov->iov_base)[i]); 1558 printf("$"); 1559 } 1560 } 1561 printf("\n"); 1562 } 1563 #endif 1564 1565 if ((m = pkt->fp_m) != NULL) { 1566 for (ndesc = 2; m != NULL; m = m->m_next) 1567 ndesc++; 1568 if (ndesc > OHCI_DESC_MAX) { 1569 m0 = NULL; 1570 ndesc = 2; 1571 for (off = 0; off < pkt->fp_dlen; off += len) { 1572 if (m0 == NULL) { 1573 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1574 if (m0 != NULL) 1575 M_COPY_PKTHDR(m0, pkt->fp_m); 1576 m = m0; 1577 } else { 1578 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1579 m = m->m_next; 1580 } 1581 if (m != NULL) 1582 MCLGET(m, M_DONTWAIT); 1583 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1584 m_freem(m0); 1585 return ENOMEM; 1586 } 1587 len = pkt->fp_dlen - off; 1588 if (len > m->m_ext.ext_size) 1589 len = m->m_ext.ext_size; 1590 m_copydata(pkt->fp_m, off, len, 1591 mtod(m, caddr_t)); 1592 m->m_len = len; 1593 ndesc++; 1594 } 1595 m_freem(pkt->fp_m); 1596 pkt->fp_m = m0; 1597 } 1598 } else 1599 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1600 1601 if (ndesc > OHCI_DESC_MAX) 1602 return ENOBUFS; 1603 1604 if (fc->fc_bufcnt > 50) /*XXX*/ 1605 return ENOBUFS; 1606 if ((fb = malloc(sizeof(*fb), M_DEVBUF, M_NOWAIT)) == NULL) 1607 return ENOBUFS; 1608 fb->fb_nseg = ndesc; 1609 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1610 if (fb->fb_desc == NULL) { 1611 free(fb, M_DEVBUF); 1612 return ENOBUFS; 1613 } 1614 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1615 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1616 fb->fb_m = pkt->fp_m; 1617 fb->fb_callback = pkt->fp_callback; 1618 1619 if (ndesc > 2) { 1620 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1621 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &fb->fb_dmamap)) != 0) { 1622 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1623 free(fb, M_DEVBUF); 1624 return error; 1625 } 1626 1627 if (pkt->fp_m != NULL) 1628 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1629 pkt->fp_m, BUS_DMA_NOWAIT); 1630 else 1631 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1632 &pkt->fp_uio, BUS_DMA_NOWAIT); 1633 if (error != 0) { 1634 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1635 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1636 free(fb, M_DEVBUF); 1637 return error; 1638 } 1639 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1640 BUS_DMASYNC_PREWRITE); 1641 } 1642 1643 fd = fb->fb_desc; 1644 fd->fd_flags = OHCI_DESC_IMMED; 1645 fd->fd_reqcount = pkt->fp_hlen; 1646 fd->fd_data = 0; 1647 fd->fd_branch = 0; 1648 fd->fd_status = 0; 1649 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1650 i = 3; /* XXX: 3 sec */ 1651 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1652 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1653 ((((val >> 25) + i) & 0x7) << 13); 1654 } else 1655 fd->fd_timestamp = 0; 1656 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1657 for (i = 0; i < ndesc - 2; i++) { 1658 fd = fb->fb_desc + 2 + i; 1659 fd->fd_flags = 0; 1660 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1661 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1662 fd->fd_branch = 0; 1663 fd->fd_status = 0; 1664 fd->fd_timestamp = 0; 1665 } 1666 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1667 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1668 1669 #ifdef FW_DEBUG 1670 if (fw_verbose) { 1671 printf("fwohci_at_output: desc %ld", 1672 (long)(fb->fb_desc - sc->sc_desc)); 1673 for (i = 0; i < ndesc * 4; i++) 1674 printf("%s%08x", i&7?" ":"\n\t", 1675 ((u_int32_t *)fb->fb_desc)[i]); 1676 printf("\n"); 1677 } 1678 #endif 1679 1680 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1681 OHCI_SUBREG_ContextControlClear); 1682 1683 if (val & OHCI_CTXCTL_RUN) { 1684 if (fc->fc_branch == NULL) { 1685 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1686 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1687 goto run; 1688 } 1689 *fc->fc_branch = fb->fb_daddr | ndesc; 1690 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1691 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1692 } else { 1693 run: 1694 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1695 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1696 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1697 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1698 } 1699 fc->fc_branch = &fd->fd_branch; 1700 1701 fc->fc_bufcnt++; 1702 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1703 pkt->fp_m = NULL; 1704 return 0; 1705 } 1706 1707 static void 1708 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1709 { 1710 struct fwohci_buf *fb; 1711 struct fwohci_desc *fd; 1712 int i; 1713 1714 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1715 fd = fb->fb_desc; 1716 #ifdef FW_DEBUG 1717 if (fw_verbose) { 1718 printf("fwohci_at_done: %sdesc %ld (%d)", 1719 force ? "force " : "", 1720 (long)(fd - sc->sc_desc), fb->fb_nseg); 1721 for (i = 0; i < fb->fb_nseg * 4; i++) 1722 printf("%s%08x", i&7?" ":"\n ", 1723 ((u_int32_t *)fd)[i]); 1724 printf("\n"); 1725 } 1726 #endif 1727 if (fb->fb_nseg > 2) 1728 fd += fb->fb_nseg - 1; 1729 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1730 break; 1731 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1732 if (fc->fc_branch == &fd->fd_branch) { 1733 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1734 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1735 fc->fc_branch = NULL; 1736 for (i = 0; i < OHCI_LOOP; i++) { 1737 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1738 OHCI_SUBREG_ContextControlClear) & 1739 OHCI_CTXCTL_ACTIVE)) 1740 break; 1741 } 1742 } 1743 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1744 if (fb->fb_nseg > 2) 1745 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1746 fc->fc_bufcnt--; 1747 if (fb->fb_callback != NULL) { 1748 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1749 fb->fb_callback = NULL; 1750 } else if (fb->fb_m != NULL) 1751 m_freem(fb->fb_m); 1752 free(fb, M_DEVBUF); 1753 } 1754 } 1755 1756 /* 1757 * Asynchronous Transmit Reponse -- in response of request packet. 1758 */ 1759 static void 1760 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1761 struct fwohci_pkt *res) 1762 { 1763 1764 if (((*req->fp_trail & 0x001f0000) >> 16) != 1765 OHCI_CTXCTL_EVENT_ACK_PENDING) 1766 return; 1767 1768 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1769 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1770 switch (req->fp_tcode) { 1771 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1772 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1773 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1774 res->fp_hlen = 12; 1775 break; 1776 case IEEE1394_TCODE_READ_REQ_QUAD: 1777 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1778 res->fp_hlen = 16; 1779 res->fp_dlen = 0; 1780 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1781 res->fp_hdr[3] = 1782 *(u_int32_t *)res->fp_iov[0].iov_base; 1783 res->fp_uio.uio_iovcnt = 0; 1784 break; 1785 case IEEE1394_TCODE_READ_REQ_BLOCK: 1786 case IEEE1394_TCODE_LOCK_REQ: 1787 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1788 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1789 else 1790 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1791 res->fp_hlen = 16; 1792 res->fp_dlen = res->fp_uio.uio_resid; 1793 res->fp_hdr[3] = res->fp_dlen << 16; 1794 break; 1795 } 1796 res->fp_hdr[0] |= (res->fp_tcode << 4); 1797 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1798 } 1799 1800 /* 1801 * APPLICATION LAYER SERVICES 1802 */ 1803 1804 /* 1805 * Initialization for Configuration ROM (no DMA context) 1806 */ 1807 1808 #define CFR_MAXUNIT 20 1809 1810 struct configromctx { 1811 u_int32_t *ptr; 1812 int curunit; 1813 struct { 1814 u_int32_t *start; 1815 int length; 1816 u_int32_t *refer; 1817 int refunit; 1818 } unit[CFR_MAXUNIT]; 1819 }; 1820 1821 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1822 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1823 1824 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1825 1826 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1827 1828 #define CFR_PUT_CRC(cfr, n) \ 1829 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1830 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1831 1832 #define CFR_START_UNIT(cfr, n) \ 1833 do { \ 1834 if ((cfr)->unit[n].refer != NULL) { \ 1835 *(cfr)->unit[n].refer |= \ 1836 (cfr)->ptr - (cfr)->unit[n].refer; \ 1837 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1838 } \ 1839 (cfr)->curunit = (n); \ 1840 (cfr)->unit[n].start = (cfr)->ptr++; \ 1841 } while (0 /* CONSTCOND */) 1842 1843 #define CFR_PUT_REFER(cfr, key, n) \ 1844 do { \ 1845 (cfr)->unit[n].refer = (cfr)->ptr; \ 1846 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1847 *(cfr)->ptr++ = (key) << 24; \ 1848 } while (0 /* CONSTCOND */) 1849 1850 #define CFR_END_UNIT(cfr) \ 1851 do { \ 1852 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1853 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1854 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1855 } while (0 /* CONSTCOND */) 1856 1857 static u_int16_t 1858 fwohci_crc16(u_int32_t *ptr, int len) 1859 { 1860 int shift; 1861 u_int32_t crc, sum, data; 1862 1863 crc = 0; 1864 while (len-- > 0) { 1865 data = *ptr++; 1866 for (shift = 28; shift >= 0; shift -= 4) { 1867 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1868 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1869 } 1870 crc &= 0xffff; 1871 } 1872 return crc; 1873 } 1874 1875 static void 1876 fwohci_configrom_init(struct fwohci_softc *sc) 1877 { 1878 int i; 1879 struct fwohci_buf *fb; 1880 u_int32_t *hdr; 1881 struct configromctx cfr; 1882 1883 fb = &sc->sc_buf_cnfrom; 1884 memset(&cfr, 0, sizeof(cfr)); 1885 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1886 1887 /* headers */ 1888 CFR_START_UNIT(&cfr, 0); 1889 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1890 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1891 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1892 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1893 CFR_END_UNIT(&cfr); 1894 /* copy info_length from crc_length */ 1895 *hdr |= (*hdr & 0x00ff0000) << 8; 1896 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1897 1898 /* root directory */ 1899 CFR_START_UNIT(&cfr, 1); 1900 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1901 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1902 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1903 /* spt,64,fix,lst,drq */ 1904 #ifdef INET 1905 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1906 #endif /* INET */ 1907 #ifdef INET6 1908 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1909 #endif /* INET6 */ 1910 CFR_END_UNIT(&cfr); 1911 1912 CFR_START_UNIT(&cfr, 2); 1913 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1914 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1915 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1916 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1917 CFR_END_UNIT(&cfr); 1918 1919 #ifdef INET 1920 /* IPv4 unit directory */ 1921 CFR_START_UNIT(&cfr, 3); 1922 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1923 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1924 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1925 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1926 CFR_END_UNIT(&cfr); 1927 1928 CFR_START_UNIT(&cfr, 6); 1929 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1930 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1931 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1932 CFR_END_UNIT(&cfr); 1933 1934 CFR_START_UNIT(&cfr, 7); 1935 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1936 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1937 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1938 CFR_END_UNIT(&cfr); 1939 #endif /* INET */ 1940 1941 #ifdef INET6 1942 /* IPv6 unit directory */ 1943 CFR_START_UNIT(&cfr, 4); 1944 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1945 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1946 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 1947 /* XXX: TBA by IANA */ 1948 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1949 CFR_END_UNIT(&cfr); 1950 1951 CFR_START_UNIT(&cfr, 8); 1952 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1953 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1954 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1955 CFR_END_UNIT(&cfr); 1956 1957 CFR_START_UNIT(&cfr, 9); 1958 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1959 CFR_PUT_DATA1(&cfr, 0); 1960 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1961 CFR_END_UNIT(&cfr); 1962 #endif /* INET6 */ 1963 1964 #ifdef FW_DEBUG 1965 if (fw_dump) { 1966 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 1967 for (i = 0; i < cfr.ptr - hdr; i++) 1968 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 1969 printf("\n"); 1970 } 1971 #endif /* FW_DEBUG */ 1972 1973 /* 1974 * Make network byte order for DMA 1975 */ 1976 for (i = 0; i < cfr.ptr - hdr; i++) 1977 HTONL(hdr[i]); 1978 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 1979 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 1980 1981 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 1982 fb->fb_dmamap->dm_segs[0].ds_addr); 1983 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 1984 } 1985 1986 /* 1987 * SelfID buffer (no DMA context) 1988 */ 1989 static void 1990 fwohci_selfid_init(struct fwohci_softc *sc) 1991 { 1992 struct fwohci_buf *fb; 1993 u_int32_t val; 1994 1995 fb = &sc->sc_buf_selfid; 1996 #ifdef DIAGNOSTICS 1997 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 1998 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 1999 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2000 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2001 #endif 2002 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2003 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2004 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2005 2006 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2007 fb->fb_dmamap->dm_segs[0].ds_addr); 2008 2009 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2010 } 2011 2012 static int 2013 fwohci_selfid_input(struct fwohci_softc *sc) 2014 { 2015 int i; 2016 u_int32_t count, val, gen; 2017 u_int32_t *buf; 2018 2019 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2020 if (val & OHCI_SelfID_Error) { 2021 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2022 return -1; 2023 } 2024 count = (val & OHCI_SelfID_Size_MASK) >> OHCI_SelfID_Size_BITPOS; 2025 gen = (val & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS; 2026 2027 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2028 0, count << 2, BUS_DMASYNC_POSTREAD); 2029 2030 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2031 if ((val & OHCI_SelfID_Gen_MASK) != (buf[0] & OHCI_SelfID_Gen_MASK)) { 2032 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2033 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2034 (buf[0] & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS); 2035 return -1; 2036 } 2037 2038 #ifdef FW_DEBUG 2039 if (fw_verbose) { 2040 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2041 val); 2042 for (i = 0; i < count; i++) 2043 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2044 printf("\n"); 2045 } 2046 #endif /* FW_DEBUG */ 2047 2048 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2049 if ((val & OHCI_NodeId_IDValid) == 0) { 2050 sc->sc_nodeid = 0xffff; /* invalid */ 2051 printf("%s: nodeid is invalid\n", 2052 sc->sc_sc1394.sc1394_dev.dv_xname); 2053 return -1; 2054 } 2055 sc->sc_nodeid = val & 0xffff; 2056 2057 for (i = 1; i < count; i += 2) { 2058 if (buf[i] != ~buf[i + 1]) { 2059 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2060 sc->sc_sc1394.sc1394_dev.dv_xname, i, 2061 buf[i], buf[i + 1]); 2062 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2063 /* 2064 * XXX: CXD3222 sometimes fails to DMA 2065 * selfid packet?? 2066 */ 2067 sc->sc_rootid = (count - 1) / 2 - 1; 2068 sc->sc_irmid = sc->sc_rootid; 2069 break; 2070 } 2071 return -1; 2072 } 2073 if (buf[i] & 0x00000001) 2074 continue; /* more pkt */ 2075 if (buf[i] & 0x00800000) 2076 continue; /* external id */ 2077 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2078 if ((buf[i] & 0x00400800) == 0x00400800) 2079 sc->sc_irmid = sc->sc_rootid; 2080 } 2081 #ifdef FW_DEBUG 2082 if (fw_verbose) 2083 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2084 sc->sc_sc1394.sc1394_dev.dv_xname, 2085 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2086 sc->sc_rootid, sc->sc_irmid); 2087 #endif 2088 2089 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2090 return -1; 2091 2092 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2093 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2094 OHCI_LinkControl_CycleMaster); 2095 else 2096 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2097 OHCI_LinkControl_CycleMaster); 2098 return 0; 2099 } 2100 2101 /* 2102 * some CSRs are handled by driver. 2103 */ 2104 static void 2105 fwohci_csr_init(struct fwohci_softc *sc) 2106 { 2107 int i; 2108 static u_int32_t csr[] = { 2109 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2110 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2111 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2112 CSR_SB_BROADCAST_CHANNEL 2113 }; 2114 2115 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2116 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2117 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2118 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2119 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2120 } 2121 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2122 } 2123 2124 static int 2125 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2126 { 2127 struct fwohci_pkt res; 2128 u_int32_t reg; 2129 2130 /* 2131 * XXX need to do special functionality other than just r/w... 2132 */ 2133 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2134 2135 if ((reg & 0x03) != 0) { 2136 /* alignment error */ 2137 return IEEE1394_RCODE_ADDRESS_ERROR; 2138 } 2139 #ifdef FW_DEBUG 2140 if (fw_verbose) 2141 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2142 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2143 #endif 2144 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2145 #ifdef FW_DEBUG 2146 if (fw_verbose) 2147 printf(" -> 0x%08x\n", 2148 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2149 #endif 2150 *(u_int32_t *)&sc->sc_csr[reg] = 2151 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2152 } else { 2153 #ifdef FW_DEBUG 2154 if (fw_verbose) 2155 printf("\n"); 2156 #endif 2157 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2158 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2159 res.fp_iov[0].iov_len = 4; 2160 res.fp_uio.uio_resid = 4; 2161 res.fp_uio.uio_iovcnt = 1; 2162 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2163 return -1; 2164 } 2165 return IEEE1394_RCODE_COMPLETE; 2166 } 2167 2168 /* 2169 * Mapping between nodeid and unique ID (EUI-64). 2170 */ 2171 static void 2172 fwohci_uid_collect(struct fwohci_softc *sc) 2173 { 2174 int i; 2175 struct fwohci_uidtbl *fu; 2176 struct fwohci_pkt pkt; 2177 2178 if (sc->sc_uidtbl != NULL) 2179 free(sc->sc_uidtbl, M_DEVBUF); 2180 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 2181 M_DEVBUF, M_NOWAIT); 2182 if (sc->sc_uidtbl == NULL) 2183 return; 2184 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2185 2186 memset(&pkt, 0, sizeof(pkt)); 2187 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2188 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2189 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2190 fu->fu_valid = 3; 2191 continue; 2192 } 2193 fu->fu_valid = 0; 2194 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2195 pkt.fp_hlen = 12; 2196 pkt.fp_dlen = 0; 2197 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2198 (pkt.fp_tcode << 4); 2199 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2200 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2201 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2202 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2203 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2204 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2205 2206 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2207 (pkt.fp_tcode << 4); 2208 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2209 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2210 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2211 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2212 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2213 } 2214 } 2215 2216 static int 2217 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2218 { 2219 int n, rcode; 2220 struct fwohci_uidtbl *fu; 2221 2222 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2223 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2224 if (rcode != IEEE1394_RCODE_COMPLETE || 2225 sc->sc_uidtbl == NULL || 2226 n > sc->sc_rootid) 2227 return 0; 2228 fu = &sc->sc_uidtbl[n]; 2229 if (arg == 0) { 2230 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2231 fu->fu_valid |= 0x1; 2232 } else { 2233 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2234 fu->fu_valid |= 0x2; 2235 } 2236 #ifdef FW_DEBUG 2237 if (fw_verbose && fu->fu_valid == 0x3) 2238 printf("fwohci_uid_input: " 2239 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2240 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2241 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2242 #endif 2243 return 0; 2244 } 2245 2246 static int 2247 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2248 { 2249 struct fwohci_uidtbl *fu; 2250 int n; 2251 static const u_int8_t bcast[] = 2252 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2253 2254 fu = sc->sc_uidtbl; 2255 if (fu == NULL) { 2256 notfound: 2257 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2258 return IEEE1394_BCAST_PHY_ID; 2259 fwohci_uid_collect(sc); /* try to get */ 2260 return -1; 2261 } 2262 for (n = 0; ; n++, fu++) { 2263 if (n > sc->sc_rootid) 2264 goto notfound; 2265 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2266 break; 2267 } 2268 return n; 2269 } 2270 2271 /* 2272 * functions to support network interface 2273 */ 2274 static int 2275 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2276 void (*handler)(struct device *, struct mbuf *)) 2277 { 2278 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2279 int s; 2280 2281 s = splimp(); 2282 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2283 fwohci_if_input, handler); 2284 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2285 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2286 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2287 splx(s); 2288 return 0; 2289 } 2290 2291 static int 2292 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2293 { 2294 int n, len; 2295 struct mbuf *m; 2296 struct iovec *iov; 2297 void (*handler)(struct device *, struct mbuf *) = arg; 2298 2299 #ifdef FW_DEBUG 2300 if (fw_verbose) { 2301 int i; 2302 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2303 pkt->fp_tcode, pkt->fp_dlen); 2304 if (fw_dump) { 2305 for (i = 0; i < pkt->fp_hlen/4; i++) 2306 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2307 printf("$"); 2308 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2309 iov = &pkt->fp_iov[n]; 2310 for (i = 0; i < iov->iov_len; i++) 2311 printf("%s%02x", 2312 (i%32)?((i%4)?"":" "):"\n\t", 2313 ((u_int8_t *)iov->iov_base)[i]); 2314 printf("$"); 2315 } 2316 } 2317 printf("\n"); 2318 } 2319 #endif /* FW_DEBUG */ 2320 len = pkt->fp_dlen; 2321 MGETHDR(m, M_DONTWAIT, MT_DATA); 2322 if (m == NULL) 2323 return IEEE1394_RCODE_COMPLETE; 2324 m->m_len = 16; 2325 if (len + m->m_len > MHLEN) { 2326 MCLGET(m, M_DONTWAIT); 2327 if ((m->m_flags & M_EXT) == 0) { 2328 m_freem(m); 2329 return IEEE1394_RCODE_COMPLETE; 2330 } 2331 } 2332 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2333 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2334 sc->sc_uidtbl[n].fu_valid != 0x3) { 2335 printf("%s: packet from unknown node: phy id %d\n", 2336 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2337 m_freem(m); 2338 return IEEE1394_RCODE_COMPLETE; 2339 } 2340 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2341 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2342 m->m_flags |= M_BCAST; 2343 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2344 } else { 2345 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2346 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2347 } 2348 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2349 mtod(m, u_int8_t *)[9] = 2350 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2351 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2352 2353 m->m_pkthdr.rcvif = NULL; /* set in child */ 2354 m->m_pkthdr.len = len + m->m_len; 2355 /* 2356 * We may use receive buffer by external mbuf instead of copy here. 2357 * But asynchronous receive buffer must be operate in buffer fill 2358 * mode, so that each receive buffer will shared by multiple mbufs. 2359 * If upper layer doesn't free mbuf soon, e.g. application program 2360 * is suspended, buffer must be reallocated. 2361 * Isochronous buffer must be operate in packet buffer mode, and 2362 * it is easy to map receive buffer to external mbuf. But it is 2363 * used for broadcast/multicast only, and is expected not so 2364 * performance sensitive for now. 2365 * XXX: The performance may be important for multicast case, 2366 * so we should revisit here later. 2367 * -- onoe 2368 */ 2369 n = 0; 2370 iov = pkt->fp_uio.uio_iov; 2371 while (len > 0) { 2372 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2373 iov->iov_len); 2374 m->m_len += iov->iov_len; 2375 len -= iov->iov_len; 2376 iov++; 2377 } 2378 (*handler)(sc->sc_sc1394.sc1394_if, m); 2379 return IEEE1394_RCODE_COMPLETE; 2380 } 2381 2382 static int 2383 fwohci_if_output(struct device *self, struct mbuf *m0, 2384 void (*callback)(struct device *, struct mbuf *)) 2385 { 2386 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2387 struct fwohci_pkt pkt; 2388 u_int8_t *p; 2389 int s, n, error, spd, hdrlen, maxrec; 2390 2391 p = mtod(m0, u_int8_t *); 2392 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2393 spd = IEEE1394_SPD_S100; /*XXX*/ 2394 maxrec = 512; /*XXX*/ 2395 hdrlen = 8; 2396 } else { 2397 n = fwohci_uid_lookup(sc, p); 2398 if (n < 0) { 2399 printf("%s: nodeid unknown:" 2400 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2401 sc->sc_sc1394.sc1394_dev.dv_xname, 2402 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2403 error = EHOSTUNREACH; 2404 goto end; 2405 } 2406 if (n == IEEE1394_BCAST_PHY_ID) { 2407 printf("%s: broadcast with !M_MCAST\n", 2408 sc->sc_sc1394.sc1394_dev.dv_xname); 2409 #ifdef FW_DEBUG 2410 if (fw_dump) { 2411 struct mbuf *m; 2412 printf("packet:"); 2413 for (m = m0; m != NULL; m = m->m_next) { 2414 for (n = 0; n < m->m_len; n++) 2415 printf("%s%02x", (n%32)? 2416 ((n%4)?"":" "):"\n\t", 2417 mtod(m, u_int8_t *)[n]); 2418 printf("$"); 2419 } 2420 printf("\n"); 2421 } 2422 #endif 2423 error = EHOSTUNREACH; 2424 goto end; 2425 } 2426 maxrec = 2 << p[8]; 2427 spd = p[9]; 2428 hdrlen = 0; 2429 } 2430 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2431 #ifdef FW_DEBUG 2432 if (fw_verbose) 2433 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2434 spd, sc->sc_sc1394.sc1394_link_speed); 2435 #endif 2436 spd = sc->sc_sc1394.sc1394_link_speed; 2437 } 2438 if (maxrec > (512 << spd)) { 2439 #ifdef FW_DEBUG 2440 if (fw_verbose) 2441 printf("fwohci_if_output: maxrec (%d) is larger for" 2442 " spd (%d)\n", maxrec, spd); 2443 #endif 2444 maxrec = 512 << spd; 2445 } 2446 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2447 #ifdef FW_DEBUG 2448 if (fw_verbose) 2449 printf("fwohci_if_output: maxrec (%d) is larger than" 2450 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2451 #endif 2452 maxrec >>= 1; 2453 } 2454 if (maxrec < 512) { 2455 #ifdef FW_DEBUG 2456 if (fw_verbose) 2457 printf("fwohci_if_output: maxrec (%d) is smaller" 2458 " than minimum\n", maxrec); 2459 #endif 2460 maxrec = 512; 2461 } 2462 2463 m_adj(m0, 16 - hdrlen); 2464 if (m0->m_pkthdr.len > maxrec) { 2465 #ifdef FW_DEBUG 2466 if (fw_verbose) 2467 printf("fwohci_if_output: packet too big:" 2468 " hdr %d, pktlen %d, maxrec %d\n", 2469 hdrlen, m0->m_pkthdr.len, maxrec); 2470 #endif 2471 error = E2BIG; /*XXX*/ 2472 goto end; 2473 } 2474 2475 memset(&pkt, 0, sizeof(pkt)); 2476 pkt.fp_uio.uio_iov = pkt.fp_iov; 2477 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2478 pkt.fp_uio.uio_rw = UIO_WRITE; 2479 s = splimp(); 2480 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2481 /* construct GASP header */ 2482 p = mtod(m0, u_int8_t *); 2483 p[0] = sc->sc_nodeid >> 8; 2484 p[1] = sc->sc_nodeid & 0xff; 2485 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2486 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2487 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2488 pkt.fp_hlen = 8; 2489 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2490 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2491 OHCI_NodeId_NodeNumber) << 8); 2492 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2493 } else { 2494 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2495 pkt.fp_hlen = 16; 2496 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2497 (spd << 16); 2498 pkt.fp_hdr[1] = 2499 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2500 (p[10] << 8) | p[11]; 2501 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2502 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2503 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2504 } 2505 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2506 pkt.fp_dlen = m0->m_pkthdr.len; 2507 pkt.fp_m = m0; 2508 pkt.fp_callback = callback; 2509 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2510 splx(s); 2511 m0 = pkt.fp_m; 2512 end: 2513 if (m0 != NULL) { 2514 if (callback) 2515 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2516 else 2517 m_freem(m0); 2518 } 2519 return error; 2520 } 2521
Indexes created Fri Sep 26 20:09:58 GMT 2025