fwohci.c revision 1.18
1 /* $NetBSD: fwohci.c,v 1.18 2001/03/12 23:27:53 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/types.h> 51 #include <sys/socket.h> 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/malloc.h> 56 #include <sys/mbuf.h> 57 58 #if __NetBSD_Version__ >= 105010000 59 #include <uvm/uvm_extern.h> 60 #else 61 #include <vm/vm.h> 62 #endif 63 64 #include <machine/bus.h> 65 66 #include <dev/ieee1394/ieee1394reg.h> 67 #include <dev/ieee1394/fwohcireg.h> 68 69 #include <dev/ieee1394/ieee1394var.h> 70 #include <dev/ieee1394/fwohcivar.h> 71 72 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 73 74 #if 0 75 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 76 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 77 #endif 78 static void fwohci_hw_init(struct fwohci_softc *); 79 static void fwohci_power(int, void *); 80 static void fwohci_shutdown(void *); 81 82 static int fwohci_desc_alloc(struct fwohci_softc *); 83 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 84 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 85 86 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 87 int, int); 88 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 89 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 90 91 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 92 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 93 static void fwohci_buf_init(struct fwohci_softc *); 94 static void fwohci_buf_start(struct fwohci_softc *); 95 static void fwohci_buf_stop(struct fwohci_softc *); 96 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 97 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 98 caddr_t *, int); 99 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 100 struct fwohci_pkt *); 101 102 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 103 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 104 static void fwohci_phy_busreset(struct fwohci_softc *); 105 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 106 107 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 108 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 109 void *); 110 111 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 112 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 113 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 114 115 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 116 struct fwohci_pkt *); 117 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 118 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 119 struct fwohci_pkt *); 120 121 static int fwohci_guidrom_init(struct fwohci_softc *); 122 static void fwohci_configrom_init(struct fwohci_softc *); 123 124 static void fwohci_selfid_init(struct fwohci_softc *); 125 static int fwohci_selfid_input(struct fwohci_softc *); 126 127 static void fwohci_csr_init(struct fwohci_softc *); 128 static int fwohci_csr_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 131 static void fwohci_uid_collect(struct fwohci_softc *); 132 static int fwohci_uid_input(struct fwohci_softc *, void *, 133 struct fwohci_pkt *); 134 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 135 136 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 137 void (*)(struct device *, struct mbuf *)); 138 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 139 static int fwohci_if_output(struct device *, struct mbuf *, 140 void (*)(struct device *, struct mbuf *)); 141 142 #ifdef FW_DEBUG 143 int fw_verbose = 1; 144 int fw_dump = 0; 145 #endif 146 147 int 148 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 149 { 150 int i; 151 u_int32_t val; 152 #if 0 153 int error; 154 #endif 155 156 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 157 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 158 159 /* 160 * Wait for reset completion 161 */ 162 for (i = 0; i < OHCI_LOOP; i++) { 163 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 164 if ((val & OHCI_HCControl_SoftReset) == 0) 165 break; 166 } 167 168 /* What dialect of OHCI is this device? 169 */ 170 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 171 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 172 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 173 174 if (fwohci_guidrom_init(sc) != 0) { 175 printf("\n%s: fatal: no global UID ROM\n", 176 sc->sc_sc1394.sc1394_dev.dv_xname); 177 return -1; 178 } 179 180 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 181 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 182 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 183 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 184 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 185 186 /* Get the maximum link speed and receive size 187 */ 188 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 189 sc->sc_sc1394.sc1394_link_speed = 190 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 191 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 192 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 193 } else { 194 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 195 } 196 197 /* MaxRec is encoded as log2(max_rec_octets)-1 198 */ 199 sc->sc_sc1394.sc1394_max_receive = 200 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 201 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 202 203 /* 204 * Count how many isochronous ctx we have. 205 */ 206 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 207 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 208 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 209 for (i = 0; val != 0; val >>= 1) { 210 if (val & 0x1) 211 i++; 212 } 213 sc->sc_isoctx = i; 214 printf(", %d iso_ctx", sc->sc_isoctx); 215 216 printf("\n"); 217 218 #if 0 219 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 220 &sc->sc_configrom_map, 221 (caddr_t *) &sc->sc_configrom, 222 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 223 return error; 224 #endif 225 226 /* 227 * Enable Link Power 228 */ 229 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 230 231 /* 232 * Allocate descriptors 233 */ 234 if (fwohci_desc_alloc(sc)) 235 return -1; 236 237 /* 238 * Allocate DMA Context 239 */ 240 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 241 OHCI_CTX_ASYNC_RX_REQUEST); 242 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 243 OHCI_CTX_ASYNC_RX_RESPONSE); 244 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 245 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 246 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 247 M_DEVBUF, M_WAITOK); 248 for (i = 0; i < sc->sc_isoctx; i++) { 249 sc->sc_ctx_ir[i] = NULL; 250 #if 0 251 fwohci_ctx_alloc(sc, &sc->sc_ctx_ir[i], OHCI_BUF_IR_CNT, i); 252 sc->sc_ctx_ir[i]->fc_isoch = 1; 253 #endif 254 } 255 256 /* 257 * Allocate buffer for configuration ROM and SelfID buffer 258 */ 259 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 260 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 261 262 /* 263 * establish hooks for shutdown and suspend/resume 264 */ 265 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 266 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 267 callout_init(&sc->sc_selfid_callout); 268 269 /* 270 * Initialize hardware registers. 271 */ 272 fwohci_hw_init(sc); 273 274 /* 275 * Initiate Bus Reset 276 */ 277 config_defer(&sc->sc_sc1394.sc1394_dev, 278 (void (*)(struct device *))fwohci_phy_busreset); 279 280 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 281 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 282 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 283 "fw", fwohci_print); 284 285 return 0; 286 } 287 288 int 289 fwohci_intr(void *arg) 290 { 291 struct fwohci_softc * const sc = arg; 292 int i; 293 int progress = 0; 294 u_int32_t intmask, iso; 295 296 for (;;) { 297 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 298 if (intmask == 0) 299 return progress; 300 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 301 intmask & ~OHCI_Int_BusReset); 302 #ifdef FW_DEBUG 303 if (fw_verbose > 1) { 304 printf("%s: intmask=0x%08x:", 305 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 306 if (intmask & OHCI_Int_CycleTooLong) 307 printf(" CycleTooLong"); 308 if (intmask & OHCI_Int_UnrecoverableError) 309 printf(" UnrecoverableError"); 310 if (intmask & OHCI_Int_CycleInconsistent) 311 printf(" CycleInconsistent"); 312 if (intmask & OHCI_Int_BusReset) 313 printf(" BusReset"); 314 if (intmask & OHCI_Int_SelfIDComplete) 315 printf(" SelfIDComplete"); 316 if (intmask & OHCI_Int_LockRespErr) 317 printf(" LockRespErr"); 318 if (intmask & OHCI_Int_PostedWriteErr) 319 printf(" PostedWriteErr"); 320 if (intmask & OHCI_Int_ReqTxComplete) 321 printf(" ReqTxComplete(0x%04x)", 322 OHCI_ASYNC_DMA_READ(sc, 323 OHCI_CTX_ASYNC_TX_REQUEST, 324 OHCI_SUBREG_ContextControlClear)); 325 if (intmask & OHCI_Int_RespTxComplete) 326 printf(" RespTxComplete(0x%04x)", 327 OHCI_ASYNC_DMA_READ(sc, 328 OHCI_CTX_ASYNC_TX_RESPONSE, 329 OHCI_SUBREG_ContextControlClear)); 330 if (intmask & OHCI_Int_ARRS) 331 printf(" ARRS(0x%04x)", 332 OHCI_ASYNC_DMA_READ(sc, 333 OHCI_CTX_ASYNC_RX_RESPONSE, 334 OHCI_SUBREG_ContextControlClear)); 335 if (intmask & OHCI_Int_ARRQ) 336 printf(" ARRQ(0x%04x)", 337 OHCI_ASYNC_DMA_READ(sc, 338 OHCI_CTX_ASYNC_RX_REQUEST, 339 OHCI_SUBREG_ContextControlClear)); 340 if (intmask & OHCI_Int_IsochRx) 341 printf(" IsochRx(0x%08x)", 342 OHCI_CSR_READ(sc, 343 OHCI_REG_IsoRecvIntEventClear)); 344 if (intmask & OHCI_Int_IsochTx) 345 printf(" IsochTx(0x%08x)", 346 OHCI_CSR_READ(sc, 347 OHCI_REG_IsoXmitIntEventClear)); 348 if (intmask & OHCI_Int_RQPkt) 349 printf(" RQPkt(0x%04x)", 350 OHCI_ASYNC_DMA_READ(sc, 351 OHCI_CTX_ASYNC_RX_REQUEST, 352 OHCI_SUBREG_ContextControlClear)); 353 if (intmask & OHCI_Int_RSPkt) 354 printf(" RSPkt(0x%04x)", 355 OHCI_ASYNC_DMA_READ(sc, 356 OHCI_CTX_ASYNC_RX_RESPONSE, 357 OHCI_SUBREG_ContextControlClear)); 358 printf("\n"); 359 } 360 #endif /* FW_DEBUG */ 361 if (intmask & OHCI_Int_BusReset) { 362 /* 363 * According to OHCI spec 6.1.1 "busReset", 364 * All asynchronous transmit must be stopped before 365 * clearing BusReset. Moreover, the BusReset 366 * interrupt bit should not be cleared during the 367 * SelfID phase. Thus we turned off interrupt mask 368 * bit of BusReset instead until SelfID completion 369 * or SelfID timeout. 370 */ 371 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 372 OHCI_Int_BusReset); 373 intmask &= OHCI_Int_SelfIDComplete; 374 fwohci_buf_stop(sc); 375 fwohci_buf_init(sc); 376 if (sc->sc_uidtbl != NULL) { 377 free(sc->sc_uidtbl, M_DEVBUF); 378 sc->sc_uidtbl = NULL; 379 } 380 callout_reset(&sc->sc_selfid_callout, 381 OHCI_SELFID_TIMEOUT, 382 (void (*)(void *))fwohci_phy_busreset, sc); 383 sc->sc_nodeid = 0xffff; /* indicate invalid */ 384 sc->sc_rootid = 0; 385 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 386 } 387 388 if (intmask & OHCI_Int_SelfIDComplete) { 389 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 390 OHCI_Int_BusReset); 391 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 392 OHCI_Int_BusReset); 393 callout_stop(&sc->sc_selfid_callout); 394 if (fwohci_selfid_input(sc) == 0) { 395 fwohci_buf_start(sc); 396 fwohci_uid_collect(sc); 397 } 398 } 399 400 if (intmask & OHCI_Int_ReqTxComplete) 401 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 402 if (intmask & OHCI_Int_RespTxComplete) 403 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 404 if (intmask & OHCI_Int_RQPkt) 405 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 406 if (intmask & OHCI_Int_RSPkt) 407 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 408 409 if (intmask & OHCI_Int_IsochTx) { 410 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 411 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 412 } 413 if (intmask & OHCI_Int_IsochRx) { 414 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 415 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 416 for (i = 0; i < sc->sc_isoctx; i++) { 417 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) 418 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 419 } 420 } 421 422 if (!progress) { 423 sc->sc_intrcnt.ev_count++; 424 progress = 1; 425 } 426 } 427 } 428 429 #if 0 430 static int 431 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 432 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 433 { 434 bus_dma_segment_t segs[1]; 435 int error, nsegs, steps; 436 437 steps = 0; 438 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 439 segs, 1, &nsegs, flags); 440 if (error) 441 goto cleanup; 442 443 steps = 1; 444 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 445 kvap, flags); 446 if (error) 447 goto cleanup; 448 449 if (error == 0) 450 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 451 size, flags, mapp); 452 if (error) 453 goto cleanup; 454 if (error == 0) 455 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 456 if (error) 457 goto cleanup; 458 459 cleanup: 460 switch (steps) { 461 case 1: 462 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 463 } 464 465 return error; 466 } 467 #endif 468 469 int 470 fwohci_print(void *aux, const char *pnp) 471 { 472 char *name = aux; 473 474 if (pnp) 475 printf("%s at %s", name, pnp); 476 477 return UNCONF; 478 } 479 480 static void 481 fwohci_hw_init(struct fwohci_softc *sc) 482 { 483 int i; 484 u_int32_t val; 485 486 /* 487 * Software Reset. 488 */ 489 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 490 for (i = 0; i < OHCI_LOOP; i++) { 491 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 492 if ((val & OHCI_HCControl_SoftReset) == 0) 493 break; 494 } 495 496 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 497 498 /* 499 * First, initilize CSRs with undefined value to default settings. 500 */ 501 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 502 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 503 #if 0 504 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 505 #else 506 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 507 #endif 508 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 509 for (i = 0; i < sc->sc_isoctx; i++) { 510 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 511 ~0); 512 } 513 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 514 515 fwohci_configrom_init(sc); 516 fwohci_selfid_init(sc); 517 fwohci_buf_init(sc); 518 fwohci_csr_init(sc); 519 520 /* 521 * Final CSR settings. 522 */ 523 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 524 OHCI_LinkControl_CycleTimerEnable | 525 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 526 527 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 528 529 /* clear receive filter */ 530 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 531 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 532 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 533 534 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 535 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 536 537 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 538 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 539 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 540 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 541 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 542 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 543 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 544 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 545 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 546 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 547 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 548 549 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 550 551 /* 552 * Start the receivers 553 */ 554 fwohci_buf_start(sc); 555 } 556 557 static void 558 fwohci_power(int why, void *arg) 559 { 560 struct fwohci_softc *sc = arg; 561 int s; 562 563 s = splimp(); 564 switch (why) { 565 case PWR_SUSPEND: 566 case PWR_STANDBY: 567 fwohci_shutdown(sc); 568 break; 569 case PWR_RESUME: 570 fwohci_hw_init(sc); 571 fwohci_phy_busreset(sc); 572 break; 573 case PWR_SOFTSUSPEND: 574 case PWR_SOFTSTANDBY: 575 case PWR_SOFTRESUME: 576 break; 577 } 578 splx(s); 579 } 580 581 static void 582 fwohci_shutdown(void *arg) 583 { 584 struct fwohci_softc *sc = arg; 585 u_int32_t val; 586 587 callout_stop(&sc->sc_selfid_callout); 588 /* disable all interrupt */ 589 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 590 fwohci_buf_stop(sc); 591 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 592 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 593 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 594 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 595 fwohci_phy_busreset(sc); 596 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 597 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 598 } 599 600 /* 601 * COMMON FUNCTIONS 602 */ 603 604 /* 605 * read the PHY Register. 606 */ 607 static u_int8_t 608 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 609 { 610 int i; 611 u_int32_t val; 612 613 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 614 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 615 for (i = 0; i < OHCI_LOOP; i++) { 616 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 617 OHCI_PhyControl_RdDone) 618 break; 619 } 620 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 621 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 622 } 623 624 /* 625 * write the PHY Register. 626 */ 627 static void 628 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 629 { 630 int i; 631 632 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 633 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 634 (val << OHCI_PhyControl_WrData_BITPOS)); 635 for (i = 0; i < OHCI_LOOP; i++) { 636 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 637 OHCI_PhyControl_WrReg)) 638 break; 639 } 640 } 641 642 /* 643 * Initiate Bus Reset 644 */ 645 static void 646 fwohci_phy_busreset(struct fwohci_softc *sc) 647 { 648 int s; 649 u_int8_t val; 650 651 s = splimp(); 652 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 653 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 654 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 655 callout_stop(&sc->sc_selfid_callout); 656 val = fwohci_phy_read(sc, 1); 657 val = (val & 0x80) | /* preserve RHB (force root) */ 658 0x40 | /* Initiate Bus Reset */ 659 0x3f; /* default GAP count */ 660 fwohci_phy_write(sc, 1, val); 661 splx(s); 662 } 663 664 /* 665 * PHY Packet 666 */ 667 static void 668 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 669 { 670 u_int32_t val; 671 u_int8_t key, phyid; 672 673 val = pkt->fp_hdr[1]; 674 if (val != ~pkt->fp_hdr[2]) { 675 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 676 OHCI_CTXCTL_EVENT_BUS_RESET) { 677 #ifdef FW_DEBUG 678 if (fw_verbose > 1) 679 printf("fwohci_phy_input: BusReset: 0x%08x\n", 680 pkt->fp_hdr[2]); 681 #endif 682 } else { 683 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 684 sc->sc_sc1394.sc1394_dev.dv_xname, val, 685 pkt->fp_hdr[2]); 686 } 687 return; 688 } 689 key = (val & 0xc0000000) >> 30; 690 phyid = (val & 0x3f000000) >> 24; 691 switch (key) { 692 case 0: 693 #ifdef FW_DEBUG 694 if (fw_verbose > 1) { 695 printf("fwohci_phy_input: PHY Config from %d:", phyid); 696 if (val & 0x00800000) 697 printf(" ForceRoot"); 698 if (val & 0x00400000) 699 printf(" Gap=%x", (val & 0x003f0000) >> 16); 700 printf("\n"); 701 } 702 #endif 703 break; 704 case 1: 705 #ifdef FW_DEBUG 706 if (fw_verbose > 1) 707 printf("fwohci_phy_input: Link-on from %d\n", phyid); 708 #endif 709 break; 710 case 2: 711 #ifdef FW_DEBUG 712 if (fw_verbose > 1) { 713 printf("fwohci_phy_input: SelfID from %d:", phyid); 714 if (val & 0x00800000) { 715 printf(" #%d", (val & 0x00700000) >> 20); 716 } else { 717 if (val & 0x00400000) 718 printf(" LinkActive"); 719 printf(" Gap=%x", (val & 0x003f0000) >> 16); 720 printf(" Spd=S%d", 721 100 << ((val & 0x0000c000) >> 14)); 722 if (val & 0x00000800) 723 printf(" Cont"); 724 if (val & 0x00000002) 725 printf(" InitiateBusReset"); 726 } 727 if (val & 0x00000001) 728 printf(" +"); 729 printf("\n"); 730 } 731 #endif 732 break; 733 default: 734 printf("%s: unknown PHY packet: 0x%08x\n", 735 sc->sc_sc1394.sc1394_dev.dv_xname, val); 736 break; 737 } 738 } 739 740 /* 741 * Descriptor for context DMA. 742 */ 743 static int 744 fwohci_desc_alloc(struct fwohci_softc *sc) 745 { 746 int error, mapsize, dsize; 747 748 /* 749 * allocate descriptor buffer 750 */ 751 752 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 753 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 754 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 755 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 756 mapsize = howmany(sc->sc_descsize, NBBY); 757 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 758 memset(sc->sc_descmap, 0, mapsize); 759 760 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 761 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 762 printf("%s: unable to allocate descriptor buffer, error = %d\n", 763 sc->sc_sc1394.sc1394_dev.dv_xname, error); 764 goto fail_0; 765 } 766 767 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 768 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 769 != 0) { 770 printf("%s: unable to map descriptor buffer, error = %d\n", 771 sc->sc_sc1394.sc1394_dev.dv_xname, error); 772 goto fail_1; 773 } 774 775 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 776 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 777 printf("%s: unable to create descriptor buffer DMA map, " 778 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 779 goto fail_2; 780 } 781 782 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 783 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 784 printf("%s: unable to load descriptor buffer DMA map, " 785 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 786 goto fail_3; 787 } 788 789 return 0; 790 791 fail_3: 792 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 793 fail_2: 794 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 795 fail_1: 796 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 797 fail_0: 798 return error; 799 } 800 801 static struct fwohci_desc * 802 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 803 { 804 int i, n; 805 806 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 807 for (i = 0; ; i++) { 808 if (i == ndesc) { 809 for (i = 0; i < ndesc; i++) 810 setbit(sc->sc_descmap, n + i); 811 return sc->sc_desc + n; 812 } 813 if (isset(sc->sc_descmap, n + i)) 814 break; 815 } 816 } 817 return NULL; 818 } 819 820 static void 821 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 822 { 823 int i, n; 824 825 n = fd - sc->sc_desc; 826 for (i = 0; i < ndesc; i++, n++) { 827 #ifdef DIAGNOSTICS 828 if (isclr(sc->sc_descmap, n)) 829 panic("fwohci_desc_put: duplicated free"); 830 #endif 831 clrbit(sc->sc_descmap, n); 832 } 833 } 834 835 /* 836 * Asyncronous/Isochronous Transmit/Receive Context 837 */ 838 static int 839 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 840 int bufcnt, int ctx) 841 { 842 int i, error; 843 struct fwohci_ctx *fc; 844 struct fwohci_buf *fb; 845 struct fwohci_desc *fd; 846 847 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 848 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 849 LIST_INIT(&fc->fc_handler); 850 TAILQ_INIT(&fc->fc_buf); 851 fc->fc_ctx = ctx; 852 fc->fc_bufcnt = bufcnt; 853 fb = (struct fwohci_buf *)&fc[1]; 854 for (i = 0; i < bufcnt; i++, fb++) { 855 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 856 goto fail; 857 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 858 error = ENOBUFS; 859 goto fail; 860 } 861 fb->fb_desc = fd; 862 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 863 ((caddr_t)fd - (caddr_t)sc->sc_desc); 864 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 865 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 866 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 867 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 868 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 869 } 870 *fcp = fc; 871 return 0; 872 873 fail: 874 while (i-- > 0) 875 fwohci_buf_free(sc, --fb); 876 free(fc, M_DEVBUF); 877 return error; 878 } 879 880 static void 881 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 882 { 883 struct fwohci_buf *fb; 884 struct fwohci_handler *fh; 885 886 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 887 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 888 NULL, NULL); 889 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 890 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 891 fwohci_buf_free(sc, fb); 892 } 893 free(fc, M_DEVBUF); 894 } 895 896 static void 897 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 898 { 899 struct fwohci_buf *fb, *nfb; 900 struct fwohci_desc *fd; 901 int n; 902 903 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 904 nfb = TAILQ_NEXT(fb, fb_list); 905 fb->fb_off = 0; 906 fd = fb->fb_desc; 907 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 908 fd->fd_rescount = fd->fd_reqcount; 909 } 910 911 n = fc->fc_ctx; 912 fb = TAILQ_FIRST(&fc->fc_buf); 913 if (fc->fc_isoch) { 914 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 915 fb->fb_daddr | 1); 916 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 917 OHCI_CTXCTL_RX_BUFFER_FILL | 918 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 919 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 920 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 921 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 922 OHCI_CTXCTL_RX_ISOCH_HEADER); 923 } else { 924 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 925 fb->fb_daddr | 1); 926 } 927 } 928 929 /* 930 * DMA data buffer 931 */ 932 static int 933 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 934 { 935 int error; 936 937 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 938 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 939 printf("%s: unable to allocate buffer, error = %d\n", 940 sc->sc_sc1394.sc1394_dev.dv_xname, error); 941 goto fail_0; 942 } 943 944 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 945 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 946 printf("%s: unable to map buffer, error = %d\n", 947 sc->sc_sc1394.sc1394_dev.dv_xname, error); 948 goto fail_1; 949 } 950 951 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 952 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 953 printf("%s: unable to create buffer DMA map, " 954 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 955 error); 956 goto fail_2; 957 } 958 959 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 960 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 961 printf("%s: unable to load buffer DMA map, " 962 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 963 error); 964 goto fail_3; 965 } 966 967 return 0; 968 969 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 970 fail_3: 971 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 972 fail_2: 973 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 974 fail_1: 975 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 976 fail_0: 977 return error; 978 } 979 980 static void 981 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 982 { 983 984 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 985 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 986 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 987 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 988 } 989 990 static void 991 fwohci_buf_init(struct fwohci_softc *sc) 992 { 993 int i; 994 995 /* 996 * Initialize for Asynchronous Transmit Queue. 997 */ 998 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 999 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1000 1001 /* 1002 * Initialize for Asynchronous Receive Queue. 1003 */ 1004 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1005 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1006 1007 /* 1008 * Initialize for Isochronous Receive Queue. 1009 */ 1010 for (i = 0; i < sc->sc_isoctx; i++) { 1011 if (sc->sc_ctx_ir[i] != NULL) 1012 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1013 } 1014 } 1015 1016 static void 1017 fwohci_buf_start(struct fwohci_softc *sc) 1018 { 1019 int i; 1020 1021 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1022 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1023 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1024 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1025 for (i = 0; i < sc->sc_isoctx; i++) { 1026 if (sc->sc_ctx_ir[i] != NULL && 1027 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1028 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1029 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1030 } 1031 } 1032 } 1033 1034 static void 1035 fwohci_buf_stop(struct fwohci_softc *sc) 1036 { 1037 int i, j; 1038 1039 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1040 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1041 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1042 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1043 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1044 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1045 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1046 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1047 for (i = 0; i < sc->sc_isoctx; i++) { 1048 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1049 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1050 } 1051 1052 /* 1053 * Make sure the transmitter is stopped. 1054 */ 1055 for (j = 0; j < OHCI_LOOP; j++) { 1056 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1057 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1058 continue; 1059 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1060 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1061 continue; 1062 break; 1063 } 1064 } 1065 1066 static void 1067 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1068 { 1069 struct fwohci_buf *fb, *tfb; 1070 1071 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1072 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1073 fb->fb_desc->fd_rescount != 0) 1074 break; 1075 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1076 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1077 fb->fb_off = 0; 1078 fb->fb_desc->fd_branch = 0; 1079 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1080 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1081 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1082 } 1083 } 1084 1085 static int 1086 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1087 int len) 1088 { 1089 struct fwohci_buf *fb; 1090 struct fwohci_desc *fd; 1091 int bufend; 1092 1093 fb = TAILQ_FIRST(&fc->fc_buf); 1094 again: 1095 fd = fb->fb_desc; 1096 #ifdef FW_DEBUG 1097 if (fw_verbose > 1) 1098 printf("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1099 " len %d, avail %d\n", 1100 (long)(fd - sc->sc_desc), fb->fb_off, fd->fd_reqcount, 1101 fd->fd_rescount, len, 1102 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1103 #endif 1104 bufend = fd->fd_reqcount - fd->fd_rescount; 1105 if (fb->fb_off >= bufend) { 1106 if (fc->fc_isoch && fb->fb_off > 0) { 1107 fb->fb_off = fd->fd_reqcount; 1108 fd->fd_rescount = 0; 1109 } 1110 if (fd->fd_rescount == 0) { 1111 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1112 goto again; 1113 } 1114 return 0; 1115 } 1116 if (fb->fb_off + len > bufend) 1117 len = bufend - fb->fb_off; 1118 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1119 BUS_DMASYNC_POSTREAD); 1120 *pp = fb->fb_buf + fb->fb_off; 1121 fb->fb_off += roundup(len, 4); 1122 return len; 1123 } 1124 1125 static int 1126 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1127 struct fwohci_pkt *pkt) 1128 { 1129 caddr_t p; 1130 int len, count, i; 1131 1132 memset(pkt, 0, sizeof(*pkt)); 1133 pkt->fp_uio.uio_iov = pkt->fp_iov; 1134 pkt->fp_uio.uio_rw = UIO_WRITE; 1135 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1136 1137 /* get first quadlet */ 1138 count = 4; 1139 if (fc->fc_isoch) { 1140 /* 1141 * get trailer first, may be bogus data unless status update 1142 * in descriptor is set. 1143 */ 1144 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1145 sizeof(*pkt->fp_trail)); 1146 if (len <= 0) { 1147 #ifdef FW_DEBUG 1148 if (fw_verbose > 1) 1149 printf("fwohci_buf_input: no input for is#%d\n", 1150 fc->fc_ctx); 1151 #endif 1152 return 0; 1153 } 1154 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1155 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1156 } 1157 len = fwohci_buf_pktget(sc, fc, &p, count); 1158 if (len <= 0) { 1159 #ifdef FW_DEBUG 1160 if (fw_verbose > 1) 1161 printf("fwohci_buf_input: no input for %d\n", 1162 fc->fc_ctx); 1163 #endif 1164 return 0; 1165 } 1166 pkt->fp_hdr[0] = *(u_int32_t *)p; 1167 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1168 switch (pkt->fp_tcode) { 1169 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1170 case IEEE1394_TCODE_READ_RESP_QUAD: 1171 pkt->fp_hlen = 12; 1172 pkt->fp_dlen = 4; 1173 break; 1174 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1175 case IEEE1394_TCODE_READ_RESP_BLOCK: 1176 case IEEE1394_TCODE_LOCK_REQ: 1177 case IEEE1394_TCODE_LOCK_RESP: 1178 pkt->fp_hlen = 16; 1179 break; 1180 case IEEE1394_TCODE_STREAM_DATA: 1181 pkt->fp_hlen = 4; 1182 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1183 break; 1184 default: 1185 pkt->fp_hlen = 12; 1186 pkt->fp_dlen = 0; 1187 break; 1188 } 1189 1190 /* get header */ 1191 while (count < pkt->fp_hlen) { 1192 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1193 if (len == 0) { 1194 printf("fwohci_buf_input: malformed input 1: %d\n", 1195 pkt->fp_hlen - count); 1196 return 0; 1197 } 1198 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1199 count += len; 1200 } 1201 if (pkt->fp_hlen == 16) 1202 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1203 #ifdef FW_DEBUG 1204 if (fw_verbose > 1) 1205 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1206 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1207 #endif 1208 1209 /* get data */ 1210 count = 0; 1211 i = 0; 1212 while (count < pkt->fp_dlen) { 1213 len = fwohci_buf_pktget(sc, fc, 1214 (caddr_t *)&pkt->fp_iov[i].iov_base, 1215 pkt->fp_dlen - count); 1216 if (len == 0) { 1217 printf("fwohci_buf_input: malformed input 2: %d\n", 1218 pkt->fp_hlen - count); 1219 return 0; 1220 } 1221 pkt->fp_iov[i++].iov_len = len; 1222 count += len; 1223 } 1224 pkt->fp_uio.uio_iovcnt = i; 1225 pkt->fp_uio.uio_resid = count; 1226 1227 if (!fc->fc_isoch) { 1228 /* get trailer */ 1229 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1230 sizeof(*pkt->fp_trail)); 1231 if (len <= 0) { 1232 printf("fwohci_buf_input: malformed input 3: %d\n", 1233 pkt->fp_hlen - count); 1234 return 0; 1235 } 1236 } 1237 return 1; 1238 } 1239 1240 static int 1241 fwohci_handler_set(struct fwohci_softc *sc, 1242 int tcode, u_int32_t key1, u_int32_t key2, 1243 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1244 void *arg) 1245 { 1246 struct fwohci_ctx *fc; 1247 struct fwohci_handler *fh; 1248 int i, j; 1249 1250 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1251 j = sc->sc_isoctx; 1252 fh = NULL; 1253 for (i = 0; i < sc->sc_isoctx; i++) { 1254 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1255 if (j == sc->sc_isoctx) 1256 j = i; 1257 continue; 1258 } 1259 fh = LIST_FIRST(&fc->fc_handler); 1260 if (fh == NULL) { 1261 j = i; 1262 break; 1263 } 1264 if (fh->fh_tcode == tcode && 1265 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1266 break; 1267 fh = NULL; 1268 } 1269 if (fh == NULL) { 1270 if (handler == NULL) 1271 return 0; 1272 if (j == sc->sc_isoctx) { 1273 #ifdef FW_DEBUG 1274 if (fw_verbose) 1275 printf("fwohci_handler_set: " 1276 "no more free context\n"); 1277 #endif 1278 return ENOMEM; 1279 } 1280 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1281 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1282 fc->fc_isoch = 1; 1283 sc->sc_ctx_ir[j] = fc; 1284 } 1285 } 1286 } else { 1287 switch (tcode) { 1288 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1289 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1290 case IEEE1394_TCODE_READ_REQ_QUAD: 1291 case IEEE1394_TCODE_READ_REQ_BLOCK: 1292 case IEEE1394_TCODE_LOCK_REQ: 1293 fc = sc->sc_ctx_arrq; 1294 break; 1295 case IEEE1394_TCODE_WRITE_RESP: 1296 case IEEE1394_TCODE_READ_RESP_QUAD: 1297 case IEEE1394_TCODE_READ_RESP_BLOCK: 1298 case IEEE1394_TCODE_LOCK_RESP: 1299 fc = sc->sc_ctx_arrs; 1300 break; 1301 default: 1302 return EIO; 1303 } 1304 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1305 fh = LIST_NEXT(fh, fh_list)) { 1306 if (fh->fh_tcode == tcode && 1307 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1308 break; 1309 } 1310 } 1311 if (handler == NULL) { 1312 if (fh != NULL) { 1313 LIST_REMOVE(fh, fh_list); 1314 free(fh, M_DEVBUF); 1315 } 1316 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1317 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1318 fwohci_ctx_free(sc, fc); 1319 } 1320 return 0; 1321 } 1322 if (fh == NULL) { 1323 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 1324 if (fh == NULL) 1325 return ENOMEM; 1326 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1327 } 1328 fh->fh_tcode = tcode; 1329 fh->fh_key1 = key1; 1330 fh->fh_key2 = key2; 1331 fh->fh_handler = handler; 1332 fh->fh_handarg = arg; 1333 #ifdef FW_DEBUG 1334 if (fw_verbose > 1) 1335 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1336 fc->fc_ctx, tcode, key1, key2); 1337 #endif 1338 1339 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1340 fwohci_ctx_init(sc, fc); 1341 #ifdef FW_DEBUG 1342 if (fw_verbose > 1) 1343 printf("fwohci_handler_set: SYNC desc %ld\n", 1344 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - 1345 sc->sc_desc)); 1346 #endif 1347 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextMatch, 1348 (OHCI_CTXMATCH_TAG0 << key2) | key1); 1349 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1350 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1351 } 1352 return 0; 1353 } 1354 1355 /* 1356 * Asyncronous Receive Requests input frontend. 1357 */ 1358 static void 1359 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1360 { 1361 int rcode; 1362 u_int32_t key1, key2; 1363 struct fwohci_handler *fh; 1364 struct fwohci_pkt pkt, res; 1365 1366 while (fwohci_buf_input(sc, fc, &pkt)) { 1367 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1368 fwohci_phy_input(sc, &pkt); 1369 continue; 1370 } 1371 key1 = pkt.fp_hdr[1] & 0xffff; 1372 key2 = pkt.fp_hdr[2]; 1373 memset(&res, 0, sizeof(res)); 1374 res.fp_uio.uio_rw = UIO_WRITE; 1375 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1376 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1377 fh = LIST_NEXT(fh, fh_list)) { 1378 if (pkt.fp_tcode == fh->fh_tcode && 1379 key1 == fh->fh_key1 && 1380 key2 == fh->fh_key2) { 1381 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1382 &pkt); 1383 break; 1384 } 1385 } 1386 if (fh == NULL) { 1387 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1388 #ifdef FW_DEBUG 1389 if (fw_verbose > 1) 1390 printf("fwohci_arrq_input: no listener:" 1391 " tcode 0x%x, addr=0x%04x %08x\n", 1392 pkt.fp_tcode, key1, key2); 1393 #endif 1394 } 1395 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1396 OHCI_CTXCTL_EVENT_ACK_PENDING) 1397 continue; 1398 if (rcode != -1) 1399 fwohci_atrs_output(sc, rcode, &pkt, &res); 1400 } 1401 fwohci_buf_next(sc, fc); 1402 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1403 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1404 } 1405 1406 /* 1407 * Asynchronous Receive Response input frontend. 1408 */ 1409 static void 1410 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1411 { 1412 struct fwohci_pkt pkt; 1413 struct fwohci_handler *fh; 1414 u_int16_t srcid; 1415 int rcode, tlabel; 1416 1417 while (fwohci_buf_input(sc, fc, &pkt)) { 1418 srcid = pkt.fp_hdr[1] >> 16; 1419 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1420 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1421 #ifdef FW_DEBUG 1422 if (fw_verbose > 1) 1423 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1424 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1425 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1426 pkt.fp_dlen); 1427 #endif 1428 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1429 fh = LIST_NEXT(fh, fh_list)) { 1430 if (pkt.fp_tcode == fh->fh_tcode && 1431 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1432 tlabel == fh->fh_key2) { 1433 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1434 LIST_REMOVE(fh, fh_list); 1435 free(fh, M_DEVBUF); 1436 break; 1437 } 1438 } 1439 #ifdef FW_DEBUG 1440 if (fw_verbose > 1) 1441 if (fh == NULL) 1442 printf("fwohci_arrs_input: no lister\n"); 1443 #endif 1444 } 1445 fwohci_buf_next(sc, fc); 1446 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1447 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1448 } 1449 1450 /* 1451 * Isochronous Receive input frontend. 1452 */ 1453 static void 1454 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1455 { 1456 int rcode, chan, tag; 1457 struct iovec *iov; 1458 struct fwohci_handler *fh; 1459 struct fwohci_pkt pkt; 1460 1461 while (fwohci_buf_input(sc, fc, &pkt)) { 1462 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1463 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1464 #ifdef FW_DEBUG 1465 if (fw_verbose > 1) 1466 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1467 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1468 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1469 #endif 1470 if (tag == IEEE1394_TAG_GASP) { 1471 /* 1472 * The pkt with tag=3 is GASP format. 1473 * Move GASP header to header part. 1474 */ 1475 if (pkt.fp_dlen < 8) 1476 continue; 1477 iov = pkt.fp_iov; 1478 /* assuming pkt per buffer mode */ 1479 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1480 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1481 iov->iov_base = (caddr_t)iov->iov_base + 8; 1482 iov->iov_len -= 8; 1483 pkt.fp_hlen += 8; 1484 pkt.fp_dlen -= 8; 1485 } 1486 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1487 fh = LIST_NEXT(fh, fh_list)) { 1488 if (pkt.fp_tcode == fh->fh_tcode && 1489 chan == fh->fh_key1 && tag == fh->fh_key2) { 1490 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1491 &pkt); 1492 break; 1493 } 1494 } 1495 #ifdef FW_DEBUG 1496 if (fw_verbose > 1) { 1497 if (fh == NULL) 1498 printf("fwohci_ir_input: no handler\n"); 1499 else 1500 printf("fwohci_ir_input: rcode %d\n", rcode); 1501 } 1502 #endif 1503 } 1504 fwohci_buf_next(sc, fc); 1505 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1506 OHCI_CTXCTL_WAKE); 1507 } 1508 1509 /* 1510 * Asynchronous Transmit common routine. 1511 */ 1512 static int 1513 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1514 struct fwohci_pkt *pkt) 1515 { 1516 struct fwohci_buf *fb; 1517 struct fwohci_desc *fd; 1518 struct mbuf *m, *m0; 1519 int i, ndesc, error, off, len; 1520 u_int32_t val; 1521 1522 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) { 1523 /* We can't send anything during selfid duration */ 1524 return EAGAIN; 1525 } 1526 #ifdef FW_DEBUG 1527 if (fw_verbose > 1) { 1528 struct iovec *iov; 1529 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1530 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1531 if (fw_dump) { 1532 for (i = 0; i < pkt->fp_hlen/4; i++) 1533 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1534 printf("$"); 1535 for (ndesc = 0, iov = pkt->fp_iov; 1536 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1537 for (i = 0; i < iov->iov_len; i++) 1538 printf("%s%02x", 1539 (i%32)?((i%4)?"":" "):"\n\t", 1540 ((u_int8_t *)iov->iov_base)[i]); 1541 printf("$"); 1542 } 1543 } 1544 printf("\n"); 1545 } 1546 #endif 1547 1548 if ((m = pkt->fp_m) != NULL) { 1549 for (ndesc = 2; m != NULL; m = m->m_next) 1550 ndesc++; 1551 if (ndesc > OHCI_DESC_MAX) { 1552 m0 = NULL; 1553 ndesc = 2; 1554 for (off = 0; off < pkt->fp_dlen; off += len) { 1555 if (m0 == NULL) { 1556 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1557 if (m0 != NULL) 1558 M_COPY_PKTHDR(m0, pkt->fp_m); 1559 m = m0; 1560 } else { 1561 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1562 m = m->m_next; 1563 } 1564 if (m != NULL) 1565 MCLGET(m, M_DONTWAIT); 1566 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1567 m_freem(m0); 1568 return ENOMEM; 1569 } 1570 len = pkt->fp_dlen - off; 1571 if (len > m->m_ext.ext_size) 1572 len = m->m_ext.ext_size; 1573 m_copydata(pkt->fp_m, off, len, 1574 mtod(m, caddr_t)); 1575 m->m_len = len; 1576 ndesc++; 1577 } 1578 m_freem(pkt->fp_m); 1579 pkt->fp_m = m0; 1580 } 1581 } else 1582 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1583 1584 if (ndesc > OHCI_DESC_MAX) 1585 return ENOBUFS; 1586 1587 if (fc->fc_bufcnt > 50) /*XXX*/ 1588 return ENOBUFS; 1589 if ((fb = malloc(sizeof(*fb), M_DEVBUF, M_NOWAIT)) == NULL) 1590 return ENOBUFS; 1591 fb->fb_nseg = ndesc; 1592 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1593 if (fb->fb_desc == NULL) { 1594 free(fb, M_DEVBUF); 1595 return ENOBUFS; 1596 } 1597 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1598 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1599 fb->fb_m = pkt->fp_m; 1600 fb->fb_callback = pkt->fp_callback; 1601 1602 if (ndesc > 2) { 1603 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1604 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &fb->fb_dmamap)) != 0) { 1605 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1606 free(fb, M_DEVBUF); 1607 return error; 1608 } 1609 1610 if (pkt->fp_m != NULL) 1611 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1612 pkt->fp_m, BUS_DMA_NOWAIT); 1613 else 1614 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1615 &pkt->fp_uio, BUS_DMA_NOWAIT); 1616 if (error != 0) { 1617 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1618 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1619 free(fb, M_DEVBUF); 1620 return error; 1621 } 1622 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1623 BUS_DMASYNC_PREWRITE); 1624 } 1625 1626 fd = fb->fb_desc; 1627 fd->fd_flags = OHCI_DESC_IMMED; 1628 fd->fd_reqcount = pkt->fp_hlen; 1629 fd->fd_data = 0; 1630 fd->fd_branch = 0; 1631 fd->fd_status = 0; 1632 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1633 i = 3; /* XXX: 3 sec */ 1634 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1635 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1636 ((((val >> 25) + i) & 0x7) << 13); 1637 } else 1638 fd->fd_timestamp = 0; 1639 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1640 for (i = 0; i < ndesc - 2; i++) { 1641 fd = fb->fb_desc + 2 + i; 1642 fd->fd_flags = 0; 1643 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1644 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1645 fd->fd_branch = 0; 1646 fd->fd_status = 0; 1647 fd->fd_timestamp = 0; 1648 } 1649 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1650 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1651 1652 #ifdef FW_DEBUG 1653 if (fw_verbose > 1) { 1654 printf("fwohci_at_output: desc %ld", 1655 (long)(fb->fb_desc - sc->sc_desc)); 1656 for (i = 0; i < ndesc * 4; i++) 1657 printf("%s%08x", i&7?" ":"\n\t", 1658 ((u_int32_t *)fb->fb_desc)[i]); 1659 printf("\n"); 1660 } 1661 #endif 1662 1663 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1664 OHCI_SUBREG_ContextControlClear); 1665 1666 if (val & OHCI_CTXCTL_RUN) { 1667 if (fc->fc_branch == NULL) { 1668 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1669 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1670 goto run; 1671 } 1672 *fc->fc_branch = fb->fb_daddr | ndesc; 1673 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1674 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1675 } else { 1676 run: 1677 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1678 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1679 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1680 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1681 } 1682 fc->fc_branch = &fd->fd_branch; 1683 1684 fc->fc_bufcnt++; 1685 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1686 pkt->fp_m = NULL; 1687 return 0; 1688 } 1689 1690 static void 1691 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1692 { 1693 struct fwohci_buf *fb; 1694 struct fwohci_desc *fd; 1695 int i; 1696 1697 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1698 fd = fb->fb_desc; 1699 #ifdef FW_DEBUG 1700 if (fw_verbose > 1) { 1701 printf("fwohci_at_done: %sdesc %ld (%d)", 1702 force ? "force " : "", 1703 (long)(fd - sc->sc_desc), fb->fb_nseg); 1704 for (i = 0; i < fb->fb_nseg * 4; i++) 1705 printf("%s%08x", i&7?" ":"\n ", 1706 ((u_int32_t *)fd)[i]); 1707 printf("\n"); 1708 } 1709 #endif 1710 if (fb->fb_nseg > 2) 1711 fd += fb->fb_nseg - 1; 1712 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1713 break; 1714 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1715 if (fc->fc_branch == &fd->fd_branch) { 1716 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1717 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1718 fc->fc_branch = NULL; 1719 for (i = 0; i < OHCI_LOOP; i++) { 1720 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1721 OHCI_SUBREG_ContextControlClear) & 1722 OHCI_CTXCTL_ACTIVE)) 1723 break; 1724 } 1725 } 1726 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1727 if (fb->fb_nseg > 2) 1728 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1729 fc->fc_bufcnt--; 1730 if (fb->fb_callback != NULL) { 1731 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1732 fb->fb_callback = NULL; 1733 } else if (fb->fb_m != NULL) 1734 m_freem(fb->fb_m); 1735 free(fb, M_DEVBUF); 1736 } 1737 } 1738 1739 /* 1740 * Asynchronous Transmit Reponse -- in response of request packet. 1741 */ 1742 static void 1743 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1744 struct fwohci_pkt *res) 1745 { 1746 1747 if (((*req->fp_trail & 0x001f0000) >> 16) != 1748 OHCI_CTXCTL_EVENT_ACK_PENDING) 1749 return; 1750 1751 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1752 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1753 switch (req->fp_tcode) { 1754 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1755 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1756 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1757 res->fp_hlen = 12; 1758 break; 1759 case IEEE1394_TCODE_READ_REQ_QUAD: 1760 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1761 res->fp_hlen = 16; 1762 res->fp_dlen = 0; 1763 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1764 res->fp_hdr[3] = 1765 *(u_int32_t *)res->fp_iov[0].iov_base; 1766 res->fp_uio.uio_iovcnt = 0; 1767 break; 1768 case IEEE1394_TCODE_READ_REQ_BLOCK: 1769 case IEEE1394_TCODE_LOCK_REQ: 1770 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1771 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1772 else 1773 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1774 res->fp_hlen = 16; 1775 res->fp_dlen = res->fp_uio.uio_resid; 1776 res->fp_hdr[3] = res->fp_dlen << 16; 1777 break; 1778 } 1779 res->fp_hdr[0] |= (res->fp_tcode << 4); 1780 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1781 } 1782 1783 /* 1784 * APPLICATION LAYER SERVICES 1785 */ 1786 1787 /* 1788 * Retrieve Global UID from GUID ROM 1789 */ 1790 static int 1791 fwohci_guidrom_init(struct fwohci_softc *sc) 1792 { 1793 int i, n, off; 1794 u_int32_t val1, val2; 1795 1796 /* Extract the Global UID 1797 */ 1798 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1799 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1800 1801 if (val1 != 0 || val2 != 0) { 1802 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1803 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1804 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1805 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1806 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1807 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1808 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1809 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1810 } else { 1811 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1812 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1813 return -1; 1814 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1815 for (i = 0; i < OHCI_LOOP; i++) { 1816 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1817 if (!(val1 & OHCI_Guid_AddrReset)) 1818 break; 1819 } 1820 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1821 val2 = 0; 1822 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1823 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1824 OHCI_Guid_RdStart); 1825 for (i = 0; i < OHCI_LOOP; i++) { 1826 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1827 if (!(val1 & OHCI_Guid_RdStart)) 1828 break; 1829 } 1830 if (n < off) 1831 continue; 1832 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1833 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1834 val2 |= val1; 1835 } 1836 if (val2 == 0) 1837 return -1; 1838 } 1839 return 0; 1840 } 1841 1842 /* 1843 * Initialization for Configuration ROM (no DMA context) 1844 */ 1845 1846 #define CFR_MAXUNIT 20 1847 1848 struct configromctx { 1849 u_int32_t *ptr; 1850 int curunit; 1851 struct { 1852 u_int32_t *start; 1853 int length; 1854 u_int32_t *refer; 1855 int refunit; 1856 } unit[CFR_MAXUNIT]; 1857 }; 1858 1859 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1860 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1861 1862 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1863 1864 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1865 1866 #define CFR_PUT_CRC(cfr, n) \ 1867 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1868 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1869 1870 #define CFR_START_UNIT(cfr, n) \ 1871 do { \ 1872 if ((cfr)->unit[n].refer != NULL) { \ 1873 *(cfr)->unit[n].refer |= \ 1874 (cfr)->ptr - (cfr)->unit[n].refer; \ 1875 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1876 } \ 1877 (cfr)->curunit = (n); \ 1878 (cfr)->unit[n].start = (cfr)->ptr++; \ 1879 } while (0 /* CONSTCOND */) 1880 1881 #define CFR_PUT_REFER(cfr, key, n) \ 1882 do { \ 1883 (cfr)->unit[n].refer = (cfr)->ptr; \ 1884 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1885 *(cfr)->ptr++ = (key) << 24; \ 1886 } while (0 /* CONSTCOND */) 1887 1888 #define CFR_END_UNIT(cfr) \ 1889 do { \ 1890 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1891 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1892 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1893 } while (0 /* CONSTCOND */) 1894 1895 static u_int16_t 1896 fwohci_crc16(u_int32_t *ptr, int len) 1897 { 1898 int shift; 1899 u_int32_t crc, sum, data; 1900 1901 crc = 0; 1902 while (len-- > 0) { 1903 data = *ptr++; 1904 for (shift = 28; shift >= 0; shift -= 4) { 1905 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1906 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1907 } 1908 crc &= 0xffff; 1909 } 1910 return crc; 1911 } 1912 1913 static void 1914 fwohci_configrom_init(struct fwohci_softc *sc) 1915 { 1916 int i; 1917 struct fwohci_buf *fb; 1918 u_int32_t *hdr; 1919 struct configromctx cfr; 1920 1921 fb = &sc->sc_buf_cnfrom; 1922 memset(&cfr, 0, sizeof(cfr)); 1923 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1924 1925 /* headers */ 1926 CFR_START_UNIT(&cfr, 0); 1927 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1928 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1929 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1930 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1931 CFR_END_UNIT(&cfr); 1932 /* copy info_length from crc_length */ 1933 *hdr |= (*hdr & 0x00ff0000) << 8; 1934 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1935 1936 /* root directory */ 1937 CFR_START_UNIT(&cfr, 1); 1938 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1939 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1940 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1941 /* spt,64,fix,lst,drq */ 1942 #ifdef INET 1943 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1944 #endif /* INET */ 1945 #ifdef INET6 1946 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1947 #endif /* INET6 */ 1948 CFR_END_UNIT(&cfr); 1949 1950 CFR_START_UNIT(&cfr, 2); 1951 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1952 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1953 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1954 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1955 CFR_END_UNIT(&cfr); 1956 1957 #ifdef INET 1958 /* IPv4 unit directory */ 1959 CFR_START_UNIT(&cfr, 3); 1960 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1961 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1962 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1963 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1964 CFR_END_UNIT(&cfr); 1965 1966 CFR_START_UNIT(&cfr, 6); 1967 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1968 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1969 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1970 CFR_END_UNIT(&cfr); 1971 1972 CFR_START_UNIT(&cfr, 7); 1973 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1974 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1975 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1976 CFR_END_UNIT(&cfr); 1977 #endif /* INET */ 1978 1979 #ifdef INET6 1980 /* IPv6 unit directory */ 1981 CFR_START_UNIT(&cfr, 4); 1982 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1983 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1984 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 1985 /* XXX: TBA by IANA */ 1986 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1987 CFR_END_UNIT(&cfr); 1988 1989 CFR_START_UNIT(&cfr, 8); 1990 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1991 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1992 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1993 CFR_END_UNIT(&cfr); 1994 1995 CFR_START_UNIT(&cfr, 9); 1996 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1997 CFR_PUT_DATA1(&cfr, 0); 1998 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1999 CFR_END_UNIT(&cfr); 2000 #endif /* INET6 */ 2001 2002 #ifdef FW_DEBUG 2003 if (fw_dump) { 2004 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 2005 for (i = 0; i < cfr.ptr - hdr; i++) 2006 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 2007 printf("\n"); 2008 } 2009 #endif /* FW_DEBUG */ 2010 2011 /* 2012 * Make network byte order for DMA 2013 */ 2014 for (i = 0; i < cfr.ptr - hdr; i++) 2015 HTONL(hdr[i]); 2016 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2017 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2018 2019 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2020 fb->fb_dmamap->dm_segs[0].ds_addr); 2021 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 2022 } 2023 2024 /* 2025 * SelfID buffer (no DMA context) 2026 */ 2027 static void 2028 fwohci_selfid_init(struct fwohci_softc *sc) 2029 { 2030 struct fwohci_buf *fb; 2031 u_int32_t val; 2032 2033 fb = &sc->sc_buf_selfid; 2034 #ifdef DIAGNOSTICS 2035 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2036 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2037 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2038 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2039 #endif 2040 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2041 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2042 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2043 2044 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2045 fb->fb_dmamap->dm_segs[0].ds_addr); 2046 2047 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2048 } 2049 2050 static int 2051 fwohci_selfid_input(struct fwohci_softc *sc) 2052 { 2053 int i; 2054 u_int32_t count, val, gen; 2055 u_int32_t *buf; 2056 2057 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2058 if (val & OHCI_SelfID_Error) { 2059 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2060 return -1; 2061 } 2062 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2063 gen = OHCI_BITVAL(val, OHCI_SelfID_Gen); 2064 2065 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2066 0, count << 2, BUS_DMASYNC_POSTREAD); 2067 2068 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2069 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2070 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) { 2071 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2072 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2073 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)); 2074 return -1; 2075 } 2076 2077 #ifdef FW_DEBUG 2078 if (fw_verbose > 1) { 2079 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2080 val); 2081 for (i = 0; i < count; i++) 2082 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2083 printf("\n"); 2084 } 2085 #endif /* FW_DEBUG */ 2086 2087 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2088 if ((val & OHCI_NodeId_IDValid) == 0) { 2089 sc->sc_nodeid = 0xffff; /* invalid */ 2090 printf("%s: nodeid is invalid\n", 2091 sc->sc_sc1394.sc1394_dev.dv_xname); 2092 return -1; 2093 } 2094 sc->sc_nodeid = val & 0xffff; 2095 2096 for (i = 1; i < count; i += 2) { 2097 if (buf[i] != ~buf[i + 1]) { 2098 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2099 sc->sc_sc1394.sc1394_dev.dv_xname, i, 2100 buf[i], buf[i + 1]); 2101 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2102 /* 2103 * XXX: CXD3222 sometimes fails to DMA 2104 * selfid packet?? 2105 */ 2106 sc->sc_rootid = (count - 1) / 2 - 1; 2107 sc->sc_irmid = sc->sc_rootid; 2108 break; 2109 } 2110 return -1; 2111 } 2112 if (buf[i] & 0x00000001) 2113 continue; /* more pkt */ 2114 if (buf[i] & 0x00800000) 2115 continue; /* external id */ 2116 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2117 if ((buf[i] & 0x00400800) == 0x00400800) 2118 sc->sc_irmid = sc->sc_rootid; 2119 } 2120 #ifdef FW_DEBUG 2121 if (fw_verbose) 2122 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2123 sc->sc_sc1394.sc1394_dev.dv_xname, 2124 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2125 sc->sc_rootid, sc->sc_irmid); 2126 #endif 2127 2128 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2129 return -1; 2130 2131 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2132 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2133 OHCI_LinkControl_CycleMaster); 2134 else 2135 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2136 OHCI_LinkControl_CycleMaster); 2137 return 0; 2138 } 2139 2140 /* 2141 * some CSRs are handled by driver. 2142 */ 2143 static void 2144 fwohci_csr_init(struct fwohci_softc *sc) 2145 { 2146 int i; 2147 static u_int32_t csr[] = { 2148 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2149 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2150 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2151 CSR_SB_BROADCAST_CHANNEL 2152 }; 2153 2154 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2155 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2156 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2157 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2158 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2159 } 2160 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2161 } 2162 2163 static int 2164 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2165 { 2166 struct fwohci_pkt res; 2167 u_int32_t reg; 2168 2169 /* 2170 * XXX need to do special functionality other than just r/w... 2171 */ 2172 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2173 2174 if ((reg & 0x03) != 0) { 2175 /* alignment error */ 2176 return IEEE1394_RCODE_ADDRESS_ERROR; 2177 } 2178 #ifdef FW_DEBUG 2179 if (fw_verbose > 1) 2180 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2181 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2182 #endif 2183 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2184 #ifdef FW_DEBUG 2185 if (fw_verbose > 1) 2186 printf(" -> 0x%08x\n", 2187 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2188 #endif 2189 *(u_int32_t *)&sc->sc_csr[reg] = 2190 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2191 } else { 2192 #ifdef FW_DEBUG 2193 if (fw_verbose > 1) 2194 printf("\n"); 2195 #endif 2196 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2197 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2198 res.fp_iov[0].iov_len = 4; 2199 res.fp_uio.uio_resid = 4; 2200 res.fp_uio.uio_iovcnt = 1; 2201 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2202 return -1; 2203 } 2204 return IEEE1394_RCODE_COMPLETE; 2205 } 2206 2207 /* 2208 * Mapping between nodeid and unique ID (EUI-64). 2209 */ 2210 static void 2211 fwohci_uid_collect(struct fwohci_softc *sc) 2212 { 2213 int i; 2214 struct fwohci_uidtbl *fu; 2215 struct fwohci_pkt pkt; 2216 2217 if (sc->sc_uidtbl != NULL) 2218 free(sc->sc_uidtbl, M_DEVBUF); 2219 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 2220 M_DEVBUF, M_NOWAIT); 2221 if (sc->sc_uidtbl == NULL) 2222 return; 2223 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2224 2225 memset(&pkt, 0, sizeof(pkt)); 2226 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2227 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2228 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2229 fu->fu_valid = 3; 2230 continue; 2231 } 2232 fu->fu_valid = 0; 2233 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2234 pkt.fp_hlen = 12; 2235 pkt.fp_dlen = 0; 2236 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2237 (pkt.fp_tcode << 4); 2238 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2239 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2240 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2241 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2242 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2243 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2244 2245 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2246 (pkt.fp_tcode << 4); 2247 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2248 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2249 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2250 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2251 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2252 } 2253 } 2254 2255 static int 2256 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2257 { 2258 int n, rcode; 2259 struct fwohci_uidtbl *fu; 2260 2261 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2262 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2263 if (rcode != IEEE1394_RCODE_COMPLETE || 2264 sc->sc_uidtbl == NULL || 2265 n > sc->sc_rootid) 2266 return 0; 2267 fu = &sc->sc_uidtbl[n]; 2268 if (arg == 0) { 2269 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2270 fu->fu_valid |= 0x1; 2271 } else { 2272 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2273 fu->fu_valid |= 0x2; 2274 } 2275 #ifdef FW_DEBUG 2276 if (fw_verbose && fu->fu_valid == 0x3) 2277 printf("fwohci_uid_input: " 2278 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2279 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2280 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2281 #endif 2282 return 0; 2283 } 2284 2285 static int 2286 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2287 { 2288 struct fwohci_uidtbl *fu; 2289 int n; 2290 static const u_int8_t bcast[] = 2291 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2292 2293 fu = sc->sc_uidtbl; 2294 if (fu == NULL) { 2295 notfound: 2296 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2297 return IEEE1394_BCAST_PHY_ID; 2298 fwohci_uid_collect(sc); /* try to get */ 2299 return -1; 2300 } 2301 for (n = 0; ; n++, fu++) { 2302 if (n > sc->sc_rootid) 2303 goto notfound; 2304 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2305 break; 2306 } 2307 return n; 2308 } 2309 2310 /* 2311 * functions to support network interface 2312 */ 2313 static int 2314 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2315 void (*handler)(struct device *, struct mbuf *)) 2316 { 2317 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2318 int s; 2319 2320 s = splimp(); 2321 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2322 fwohci_if_input, handler); 2323 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2324 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2325 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2326 splx(s); 2327 return 0; 2328 } 2329 2330 static int 2331 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2332 { 2333 int n, len; 2334 struct mbuf *m; 2335 struct iovec *iov; 2336 void (*handler)(struct device *, struct mbuf *) = arg; 2337 2338 #ifdef FW_DEBUG 2339 if (fw_verbose > 1) { 2340 int i; 2341 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2342 pkt->fp_tcode, pkt->fp_dlen); 2343 if (fw_dump) { 2344 for (i = 0; i < pkt->fp_hlen/4; i++) 2345 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2346 printf("$"); 2347 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2348 iov = &pkt->fp_iov[n]; 2349 for (i = 0; i < iov->iov_len; i++) 2350 printf("%s%02x", 2351 (i%32)?((i%4)?"":" "):"\n\t", 2352 ((u_int8_t *)iov->iov_base)[i]); 2353 printf("$"); 2354 } 2355 } 2356 printf("\n"); 2357 } 2358 #endif /* FW_DEBUG */ 2359 len = pkt->fp_dlen; 2360 MGETHDR(m, M_DONTWAIT, MT_DATA); 2361 if (m == NULL) 2362 return IEEE1394_RCODE_COMPLETE; 2363 m->m_len = 16; 2364 if (len + m->m_len > MHLEN) { 2365 MCLGET(m, M_DONTWAIT); 2366 if ((m->m_flags & M_EXT) == 0) { 2367 m_freem(m); 2368 return IEEE1394_RCODE_COMPLETE; 2369 } 2370 } 2371 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2372 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2373 sc->sc_uidtbl[n].fu_valid != 0x3) { 2374 printf("%s: packet from unknown node: phy id %d\n", 2375 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2376 m_freem(m); 2377 return IEEE1394_RCODE_COMPLETE; 2378 } 2379 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2380 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2381 m->m_flags |= M_BCAST; 2382 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2383 } else { 2384 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2385 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2386 } 2387 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2388 mtod(m, u_int8_t *)[9] = 2389 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2390 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2391 2392 m->m_pkthdr.rcvif = NULL; /* set in child */ 2393 m->m_pkthdr.len = len + m->m_len; 2394 /* 2395 * We may use receive buffer by external mbuf instead of copy here. 2396 * But asynchronous receive buffer must be operate in buffer fill 2397 * mode, so that each receive buffer will shared by multiple mbufs. 2398 * If upper layer doesn't free mbuf soon, e.g. application program 2399 * is suspended, buffer must be reallocated. 2400 * Isochronous buffer must be operate in packet buffer mode, and 2401 * it is easy to map receive buffer to external mbuf. But it is 2402 * used for broadcast/multicast only, and is expected not so 2403 * performance sensitive for now. 2404 * XXX: The performance may be important for multicast case, 2405 * so we should revisit here later. 2406 * -- onoe 2407 */ 2408 n = 0; 2409 iov = pkt->fp_uio.uio_iov; 2410 while (len > 0) { 2411 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2412 iov->iov_len); 2413 m->m_len += iov->iov_len; 2414 len -= iov->iov_len; 2415 iov++; 2416 } 2417 (*handler)(sc->sc_sc1394.sc1394_if, m); 2418 return IEEE1394_RCODE_COMPLETE; 2419 } 2420 2421 static int 2422 fwohci_if_output(struct device *self, struct mbuf *m0, 2423 void (*callback)(struct device *, struct mbuf *)) 2424 { 2425 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2426 struct fwohci_pkt pkt; 2427 u_int8_t *p; 2428 int s, n, error, spd, hdrlen, maxrec; 2429 2430 p = mtod(m0, u_int8_t *); 2431 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2432 spd = IEEE1394_SPD_S100; /*XXX*/ 2433 maxrec = 512; /*XXX*/ 2434 hdrlen = 8; 2435 } else { 2436 n = fwohci_uid_lookup(sc, p); 2437 if (n < 0) { 2438 printf("%s: nodeid unknown:" 2439 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2440 sc->sc_sc1394.sc1394_dev.dv_xname, 2441 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2442 error = EHOSTUNREACH; 2443 goto end; 2444 } 2445 if (n == IEEE1394_BCAST_PHY_ID) { 2446 printf("%s: broadcast with !M_MCAST\n", 2447 sc->sc_sc1394.sc1394_dev.dv_xname); 2448 #ifdef FW_DEBUG 2449 if (fw_dump) { 2450 struct mbuf *m; 2451 printf("packet:"); 2452 for (m = m0; m != NULL; m = m->m_next) { 2453 for (n = 0; n < m->m_len; n++) 2454 printf("%s%02x", (n%32)? 2455 ((n%4)?"":" "):"\n\t", 2456 mtod(m, u_int8_t *)[n]); 2457 printf("$"); 2458 } 2459 printf("\n"); 2460 } 2461 #endif 2462 error = EHOSTUNREACH; 2463 goto end; 2464 } 2465 maxrec = 2 << p[8]; 2466 spd = p[9]; 2467 hdrlen = 0; 2468 } 2469 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2470 #ifdef FW_DEBUG 2471 if (fw_verbose) 2472 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2473 spd, sc->sc_sc1394.sc1394_link_speed); 2474 #endif 2475 spd = sc->sc_sc1394.sc1394_link_speed; 2476 } 2477 if (maxrec > (512 << spd)) { 2478 #ifdef FW_DEBUG 2479 if (fw_verbose) 2480 printf("fwohci_if_output: maxrec (%d) is larger for" 2481 " spd (%d)\n", maxrec, spd); 2482 #endif 2483 maxrec = 512 << spd; 2484 } 2485 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2486 #ifdef FW_DEBUG 2487 if (fw_verbose) 2488 printf("fwohci_if_output: maxrec (%d) is larger than" 2489 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2490 #endif 2491 maxrec >>= 1; 2492 } 2493 if (maxrec < 512) { 2494 #ifdef FW_DEBUG 2495 if (fw_verbose) 2496 printf("fwohci_if_output: maxrec (%d) is smaller" 2497 " than minimum\n", maxrec); 2498 #endif 2499 maxrec = 512; 2500 } 2501 2502 m_adj(m0, 16 - hdrlen); 2503 if (m0->m_pkthdr.len > maxrec) { 2504 #ifdef FW_DEBUG 2505 if (fw_verbose) 2506 printf("fwohci_if_output: packet too big:" 2507 " hdr %d, pktlen %d, maxrec %d\n", 2508 hdrlen, m0->m_pkthdr.len, maxrec); 2509 #endif 2510 error = E2BIG; /*XXX*/ 2511 goto end; 2512 } 2513 2514 memset(&pkt, 0, sizeof(pkt)); 2515 pkt.fp_uio.uio_iov = pkt.fp_iov; 2516 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2517 pkt.fp_uio.uio_rw = UIO_WRITE; 2518 s = splimp(); 2519 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2520 /* construct GASP header */ 2521 p = mtod(m0, u_int8_t *); 2522 p[0] = sc->sc_nodeid >> 8; 2523 p[1] = sc->sc_nodeid & 0xff; 2524 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2525 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2526 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2527 pkt.fp_hlen = 8; 2528 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2529 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2530 OHCI_NodeId_NodeNumber) << 8); 2531 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2532 } else { 2533 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2534 pkt.fp_hlen = 16; 2535 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2536 (spd << 16); 2537 pkt.fp_hdr[1] = 2538 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2539 (p[10] << 8) | p[11]; 2540 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2541 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2542 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2543 } 2544 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2545 pkt.fp_dlen = m0->m_pkthdr.len; 2546 pkt.fp_m = m0; 2547 pkt.fp_callback = callback; 2548 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2549 splx(s); 2550 m0 = pkt.fp_m; 2551 end: 2552 if (m0 != NULL) { 2553 if (callback) 2554 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2555 else 2556 m_freem(m0); 2557 } 2558 return error; 2559 } 2560
Indexes created Wed Sep 24 05:09:52 GMT 2025