fwohci.c revision 1.21
1 /* $NetBSD: fwohci.c,v 1.21 2001/03/14 06:46:17 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/types.h> 51 #include <sys/socket.h> 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/malloc.h> 56 #include <sys/mbuf.h> 57 58 #if __NetBSD_Version__ >= 105010000 59 #include <uvm/uvm_extern.h> 60 #else 61 #include <vm/vm.h> 62 #endif 63 64 #include <machine/bus.h> 65 66 #include <dev/ieee1394/ieee1394reg.h> 67 #include <dev/ieee1394/fwohcireg.h> 68 69 #include <dev/ieee1394/ieee1394var.h> 70 #include <dev/ieee1394/fwohcivar.h> 71 72 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 73 74 #if 0 75 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 76 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 77 #endif 78 static void fwohci_hw_init(struct fwohci_softc *); 79 static void fwohci_power(int, void *); 80 static void fwohci_shutdown(void *); 81 82 static int fwohci_desc_alloc(struct fwohci_softc *); 83 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 84 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 85 86 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 87 int, int); 88 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 89 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 90 91 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 92 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 93 static void fwohci_buf_init(struct fwohci_softc *); 94 static void fwohci_buf_start(struct fwohci_softc *); 95 static void fwohci_buf_stop(struct fwohci_softc *); 96 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 97 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 98 caddr_t *, int); 99 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 100 struct fwohci_pkt *); 101 102 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 103 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 104 static void fwohci_phy_busreset(struct fwohci_softc *); 105 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 106 107 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 108 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 109 void *); 110 111 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 112 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 113 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 114 115 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 116 struct fwohci_pkt *); 117 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 118 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 119 struct fwohci_pkt *); 120 121 static int fwohci_guidrom_init(struct fwohci_softc *); 122 static void fwohci_configrom_init(struct fwohci_softc *); 123 124 static void fwohci_selfid_init(struct fwohci_softc *); 125 static int fwohci_selfid_input(struct fwohci_softc *); 126 127 static void fwohci_csr_init(struct fwohci_softc *); 128 static int fwohci_csr_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 131 static void fwohci_uid_collect(struct fwohci_softc *); 132 static int fwohci_uid_input(struct fwohci_softc *, void *, 133 struct fwohci_pkt *); 134 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 135 136 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 137 void (*)(struct device *, struct mbuf *)); 138 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 139 static int fwohci_if_output(struct device *, struct mbuf *, 140 void (*)(struct device *, struct mbuf *)); 141 142 #ifdef FW_DEBUG 143 int fw_verbose = 1; 144 int fw_dump = 0; 145 #endif 146 147 int 148 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 149 { 150 int i; 151 u_int32_t val; 152 #if 0 153 int error; 154 #endif 155 156 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 157 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 158 159 /* 160 * Wait for reset completion 161 */ 162 for (i = 0; i < OHCI_LOOP; i++) { 163 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 164 if ((val & OHCI_HCControl_SoftReset) == 0) 165 break; 166 } 167 168 /* What dialect of OHCI is this device? 169 */ 170 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 171 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 172 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 173 174 if (fwohci_guidrom_init(sc) != 0) { 175 printf("\n%s: fatal: no global UID ROM\n", 176 sc->sc_sc1394.sc1394_dev.dv_xname); 177 return -1; 178 } 179 180 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 181 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 182 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 183 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 184 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 185 186 /* Get the maximum link speed and receive size 187 */ 188 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 189 sc->sc_sc1394.sc1394_link_speed = 190 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 191 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 192 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 193 } else { 194 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 195 } 196 197 /* MaxRec is encoded as log2(max_rec_octets)-1 198 */ 199 sc->sc_sc1394.sc1394_max_receive = 200 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 201 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 202 203 /* 204 * Count how many isochronous ctx we have. 205 */ 206 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 207 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 208 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 209 for (i = 0; val != 0; val >>= 1) { 210 if (val & 0x1) 211 i++; 212 } 213 sc->sc_isoctx = i; 214 printf(", %d iso_ctx", sc->sc_isoctx); 215 216 printf("\n"); 217 218 #if 0 219 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 220 &sc->sc_configrom_map, 221 (caddr_t *) &sc->sc_configrom, 222 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 223 return error; 224 #endif 225 226 /* 227 * Enable Link Power 228 */ 229 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 230 231 /* 232 * Allocate descriptors 233 */ 234 if (fwohci_desc_alloc(sc)) 235 return -1; 236 237 /* 238 * Allocate DMA Context 239 */ 240 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 241 OHCI_CTX_ASYNC_RX_REQUEST); 242 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 243 OHCI_CTX_ASYNC_RX_RESPONSE); 244 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 245 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 246 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 247 M_DEVBUF, M_WAITOK); 248 for (i = 0; i < sc->sc_isoctx; i++) 249 sc->sc_ctx_ir[i] = NULL; 250 251 /* 252 * Allocate buffer for configuration ROM and SelfID buffer 253 */ 254 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 255 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 256 257 /* 258 * establish hooks for shutdown and suspend/resume 259 */ 260 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 261 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 262 callout_init(&sc->sc_selfid_callout); 263 264 /* 265 * Initialize hardware registers. 266 */ 267 fwohci_hw_init(sc); 268 269 /* 270 * Initiate Bus Reset 271 */ 272 config_defer(&sc->sc_sc1394.sc1394_dev, 273 (void (*)(struct device *))fwohci_phy_busreset); 274 275 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 276 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 277 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 278 "fw", fwohci_print); 279 280 return 0; 281 } 282 283 int 284 fwohci_intr(void *arg) 285 { 286 struct fwohci_softc * const sc = arg; 287 int i; 288 int progress = 0; 289 u_int32_t intmask, iso; 290 291 for (;;) { 292 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 293 if (intmask == 0) 294 return progress; 295 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 296 intmask & ~OHCI_Int_BusReset); 297 #ifdef FW_DEBUG 298 if (fw_verbose > 1) { 299 printf("%s: intmask=0x%08x:", 300 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 301 if (intmask & OHCI_Int_CycleTooLong) 302 printf(" CycleTooLong"); 303 if (intmask & OHCI_Int_UnrecoverableError) 304 printf(" UnrecoverableError"); 305 if (intmask & OHCI_Int_CycleInconsistent) 306 printf(" CycleInconsistent"); 307 if (intmask & OHCI_Int_BusReset) 308 printf(" BusReset"); 309 if (intmask & OHCI_Int_SelfIDComplete) 310 printf(" SelfIDComplete"); 311 if (intmask & OHCI_Int_LockRespErr) 312 printf(" LockRespErr"); 313 if (intmask & OHCI_Int_PostedWriteErr) 314 printf(" PostedWriteErr"); 315 if (intmask & OHCI_Int_ReqTxComplete) 316 printf(" ReqTxComplete(0x%04x)", 317 OHCI_ASYNC_DMA_READ(sc, 318 OHCI_CTX_ASYNC_TX_REQUEST, 319 OHCI_SUBREG_ContextControlClear)); 320 if (intmask & OHCI_Int_RespTxComplete) 321 printf(" RespTxComplete(0x%04x)", 322 OHCI_ASYNC_DMA_READ(sc, 323 OHCI_CTX_ASYNC_TX_RESPONSE, 324 OHCI_SUBREG_ContextControlClear)); 325 if (intmask & OHCI_Int_ARRS) 326 printf(" ARRS(0x%04x)", 327 OHCI_ASYNC_DMA_READ(sc, 328 OHCI_CTX_ASYNC_RX_RESPONSE, 329 OHCI_SUBREG_ContextControlClear)); 330 if (intmask & OHCI_Int_ARRQ) 331 printf(" ARRQ(0x%04x)", 332 OHCI_ASYNC_DMA_READ(sc, 333 OHCI_CTX_ASYNC_RX_REQUEST, 334 OHCI_SUBREG_ContextControlClear)); 335 if (intmask & OHCI_Int_IsochRx) 336 printf(" IsochRx(0x%08x)", 337 OHCI_CSR_READ(sc, 338 OHCI_REG_IsoRecvIntEventClear)); 339 if (intmask & OHCI_Int_IsochTx) 340 printf(" IsochTx(0x%08x)", 341 OHCI_CSR_READ(sc, 342 OHCI_REG_IsoXmitIntEventClear)); 343 if (intmask & OHCI_Int_RQPkt) 344 printf(" RQPkt(0x%04x)", 345 OHCI_ASYNC_DMA_READ(sc, 346 OHCI_CTX_ASYNC_RX_REQUEST, 347 OHCI_SUBREG_ContextControlClear)); 348 if (intmask & OHCI_Int_RSPkt) 349 printf(" RSPkt(0x%04x)", 350 OHCI_ASYNC_DMA_READ(sc, 351 OHCI_CTX_ASYNC_RX_RESPONSE, 352 OHCI_SUBREG_ContextControlClear)); 353 printf("\n"); 354 } 355 #endif /* FW_DEBUG */ 356 if (intmask & OHCI_Int_BusReset) { 357 /* 358 * According to OHCI spec 6.1.1 "busReset", 359 * All asynchronous transmit must be stopped before 360 * clearing BusReset. Moreover, the BusReset 361 * interrupt bit should not be cleared during the 362 * SelfID phase. Thus we turned off interrupt mask 363 * bit of BusReset instead until SelfID completion 364 * or SelfID timeout. 365 */ 366 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 367 OHCI_Int_BusReset); 368 intmask &= OHCI_Int_SelfIDComplete; 369 fwohci_buf_stop(sc); 370 fwohci_buf_init(sc); 371 if (sc->sc_uidtbl != NULL) { 372 free(sc->sc_uidtbl, M_DEVBUF); 373 sc->sc_uidtbl = NULL; 374 } 375 callout_reset(&sc->sc_selfid_callout, 376 OHCI_SELFID_TIMEOUT, 377 (void (*)(void *))fwohci_phy_busreset, sc); 378 sc->sc_nodeid = 0xffff; /* indicate invalid */ 379 sc->sc_rootid = 0; 380 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 381 } 382 383 if (intmask & OHCI_Int_SelfIDComplete) { 384 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 385 OHCI_Int_BusReset); 386 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 387 OHCI_Int_BusReset); 388 callout_stop(&sc->sc_selfid_callout); 389 if (fwohci_selfid_input(sc) == 0) { 390 fwohci_buf_start(sc); 391 fwohci_uid_collect(sc); 392 } 393 } 394 395 if (intmask & OHCI_Int_ReqTxComplete) 396 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 397 if (intmask & OHCI_Int_RespTxComplete) 398 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 399 if (intmask & OHCI_Int_RQPkt) 400 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 401 if (intmask & OHCI_Int_RSPkt) 402 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 403 404 if (intmask & OHCI_Int_IsochTx) { 405 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 406 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 407 } 408 if (intmask & OHCI_Int_IsochRx) { 409 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 410 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 411 for (i = 0; i < sc->sc_isoctx; i++) { 412 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) 413 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 414 } 415 } 416 417 if (!progress) { 418 sc->sc_intrcnt.ev_count++; 419 progress = 1; 420 } 421 } 422 } 423 424 #if 0 425 static int 426 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 427 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 428 { 429 bus_dma_segment_t segs[1]; 430 int error, nsegs, steps; 431 432 steps = 0; 433 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 434 segs, 1, &nsegs, flags); 435 if (error) 436 goto cleanup; 437 438 steps = 1; 439 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 440 kvap, flags); 441 if (error) 442 goto cleanup; 443 444 if (error == 0) 445 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 446 size, flags, mapp); 447 if (error) 448 goto cleanup; 449 if (error == 0) 450 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 451 if (error) 452 goto cleanup; 453 454 cleanup: 455 switch (steps) { 456 case 1: 457 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 458 } 459 460 return error; 461 } 462 #endif 463 464 int 465 fwohci_print(void *aux, const char *pnp) 466 { 467 char *name = aux; 468 469 if (pnp) 470 printf("%s at %s", name, pnp); 471 472 return UNCONF; 473 } 474 475 static void 476 fwohci_hw_init(struct fwohci_softc *sc) 477 { 478 int i; 479 u_int32_t val; 480 481 /* 482 * Software Reset. 483 */ 484 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 485 for (i = 0; i < OHCI_LOOP; i++) { 486 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 487 if ((val & OHCI_HCControl_SoftReset) == 0) 488 break; 489 } 490 491 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 492 493 /* 494 * First, initilize CSRs with undefined value to default settings. 495 */ 496 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 497 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 498 #if 0 499 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 500 #else 501 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 502 #endif 503 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 504 for (i = 0; i < sc->sc_isoctx; i++) { 505 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 506 ~0); 507 } 508 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 509 510 fwohci_configrom_init(sc); 511 fwohci_selfid_init(sc); 512 fwohci_buf_init(sc); 513 fwohci_csr_init(sc); 514 515 /* 516 * Final CSR settings. 517 */ 518 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 519 OHCI_LinkControl_CycleTimerEnable | 520 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 521 522 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 523 524 /* clear receive filter */ 525 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 526 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 527 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 528 529 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 530 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 531 532 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 533 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 534 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 535 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 536 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 537 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 538 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 539 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 540 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 541 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 542 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 543 544 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 545 546 /* 547 * Start the receivers 548 */ 549 fwohci_buf_start(sc); 550 } 551 552 static void 553 fwohci_power(int why, void *arg) 554 { 555 struct fwohci_softc *sc = arg; 556 int s; 557 558 s = splimp(); 559 switch (why) { 560 case PWR_SUSPEND: 561 case PWR_STANDBY: 562 fwohci_shutdown(sc); 563 break; 564 case PWR_RESUME: 565 fwohci_hw_init(sc); 566 fwohci_phy_busreset(sc); 567 break; 568 case PWR_SOFTSUSPEND: 569 case PWR_SOFTSTANDBY: 570 case PWR_SOFTRESUME: 571 break; 572 } 573 splx(s); 574 } 575 576 static void 577 fwohci_shutdown(void *arg) 578 { 579 struct fwohci_softc *sc = arg; 580 u_int32_t val; 581 582 callout_stop(&sc->sc_selfid_callout); 583 /* disable all interrupt */ 584 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 585 fwohci_buf_stop(sc); 586 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 587 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 588 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 589 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 590 fwohci_phy_busreset(sc); 591 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 592 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 593 } 594 595 /* 596 * COMMON FUNCTIONS 597 */ 598 599 /* 600 * read the PHY Register. 601 */ 602 static u_int8_t 603 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 604 { 605 int i; 606 u_int32_t val; 607 608 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 609 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 610 for (i = 0; i < OHCI_LOOP; i++) { 611 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 612 OHCI_PhyControl_RdDone) 613 break; 614 } 615 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 616 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 617 } 618 619 /* 620 * write the PHY Register. 621 */ 622 static void 623 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 624 { 625 int i; 626 627 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 628 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 629 (val << OHCI_PhyControl_WrData_BITPOS)); 630 for (i = 0; i < OHCI_LOOP; i++) { 631 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 632 OHCI_PhyControl_WrReg)) 633 break; 634 } 635 } 636 637 /* 638 * Initiate Bus Reset 639 */ 640 static void 641 fwohci_phy_busreset(struct fwohci_softc *sc) 642 { 643 int s; 644 u_int8_t val; 645 646 s = splimp(); 647 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 648 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 649 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 650 callout_stop(&sc->sc_selfid_callout); 651 val = fwohci_phy_read(sc, 1); 652 val = (val & 0x80) | /* preserve RHB (force root) */ 653 0x40 | /* Initiate Bus Reset */ 654 0x3f; /* default GAP count */ 655 fwohci_phy_write(sc, 1, val); 656 splx(s); 657 } 658 659 /* 660 * PHY Packet 661 */ 662 static void 663 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 664 { 665 u_int32_t val; 666 u_int8_t key, phyid; 667 668 val = pkt->fp_hdr[1]; 669 if (val != ~pkt->fp_hdr[2]) { 670 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 671 OHCI_CTXCTL_EVENT_BUS_RESET) { 672 #ifdef FW_DEBUG 673 if (fw_verbose > 1) 674 printf("fwohci_phy_input: BusReset: 0x%08x\n", 675 pkt->fp_hdr[2]); 676 #endif 677 } else { 678 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 679 sc->sc_sc1394.sc1394_dev.dv_xname, val, 680 pkt->fp_hdr[2]); 681 } 682 return; 683 } 684 key = (val & 0xc0000000) >> 30; 685 phyid = (val & 0x3f000000) >> 24; 686 switch (key) { 687 case 0: 688 #ifdef FW_DEBUG 689 if (fw_verbose > 1) { 690 printf("fwohci_phy_input: PHY Config from %d:", phyid); 691 if (val & 0x00800000) 692 printf(" ForceRoot"); 693 if (val & 0x00400000) 694 printf(" Gap=%x", (val & 0x003f0000) >> 16); 695 printf("\n"); 696 } 697 #endif 698 break; 699 case 1: 700 #ifdef FW_DEBUG 701 if (fw_verbose > 1) 702 printf("fwohci_phy_input: Link-on from %d\n", phyid); 703 #endif 704 break; 705 case 2: 706 #ifdef FW_DEBUG 707 if (fw_verbose > 1) { 708 printf("fwohci_phy_input: SelfID from %d:", phyid); 709 if (val & 0x00800000) { 710 printf(" #%d", (val & 0x00700000) >> 20); 711 } else { 712 if (val & 0x00400000) 713 printf(" LinkActive"); 714 printf(" Gap=%x", (val & 0x003f0000) >> 16); 715 printf(" Spd=S%d", 716 100 << ((val & 0x0000c000) >> 14)); 717 if (val & 0x00000800) 718 printf(" Cont"); 719 if (val & 0x00000002) 720 printf(" InitiateBusReset"); 721 } 722 if (val & 0x00000001) 723 printf(" +"); 724 printf("\n"); 725 } 726 #endif 727 break; 728 default: 729 printf("%s: unknown PHY packet: 0x%08x\n", 730 sc->sc_sc1394.sc1394_dev.dv_xname, val); 731 break; 732 } 733 } 734 735 /* 736 * Descriptor for context DMA. 737 */ 738 static int 739 fwohci_desc_alloc(struct fwohci_softc *sc) 740 { 741 int error, mapsize, dsize; 742 743 /* 744 * allocate descriptor buffer 745 */ 746 747 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 748 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 749 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 750 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 751 mapsize = howmany(sc->sc_descsize, NBBY); 752 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 753 memset(sc->sc_descmap, 0, mapsize); 754 755 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 756 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 757 printf("%s: unable to allocate descriptor buffer, error = %d\n", 758 sc->sc_sc1394.sc1394_dev.dv_xname, error); 759 goto fail_0; 760 } 761 762 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 763 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 764 != 0) { 765 printf("%s: unable to map descriptor buffer, error = %d\n", 766 sc->sc_sc1394.sc1394_dev.dv_xname, error); 767 goto fail_1; 768 } 769 770 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 771 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 772 printf("%s: unable to create descriptor buffer DMA map, " 773 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 774 goto fail_2; 775 } 776 777 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 778 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 779 printf("%s: unable to load descriptor buffer DMA map, " 780 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 781 goto fail_3; 782 } 783 784 return 0; 785 786 fail_3: 787 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 788 fail_2: 789 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 790 fail_1: 791 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 792 fail_0: 793 return error; 794 } 795 796 static struct fwohci_desc * 797 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 798 { 799 int i, n; 800 801 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 802 for (i = 0; ; i++) { 803 if (i == ndesc) { 804 for (i = 0; i < ndesc; i++) 805 setbit(sc->sc_descmap, n + i); 806 return sc->sc_desc + n; 807 } 808 if (isset(sc->sc_descmap, n + i)) 809 break; 810 } 811 } 812 return NULL; 813 } 814 815 static void 816 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 817 { 818 int i, n; 819 820 n = fd - sc->sc_desc; 821 for (i = 0; i < ndesc; i++, n++) { 822 #ifdef DIAGNOSTICS 823 if (isclr(sc->sc_descmap, n)) 824 panic("fwohci_desc_put: duplicated free"); 825 #endif 826 clrbit(sc->sc_descmap, n); 827 } 828 } 829 830 /* 831 * Asyncronous/Isochronous Transmit/Receive Context 832 */ 833 static int 834 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 835 int bufcnt, int ctx) 836 { 837 int i, error; 838 struct fwohci_ctx *fc; 839 struct fwohci_buf *fb; 840 struct fwohci_desc *fd; 841 842 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 843 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 844 LIST_INIT(&fc->fc_handler); 845 TAILQ_INIT(&fc->fc_buf); 846 fc->fc_ctx = ctx; 847 fc->fc_bufcnt = bufcnt; 848 fb = (struct fwohci_buf *)&fc[1]; 849 for (i = 0; i < bufcnt; i++, fb++) { 850 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 851 goto fail; 852 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 853 error = ENOBUFS; 854 goto fail; 855 } 856 fb->fb_desc = fd; 857 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 858 ((caddr_t)fd - (caddr_t)sc->sc_desc); 859 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 860 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 861 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 862 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 863 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 864 } 865 *fcp = fc; 866 return 0; 867 868 fail: 869 while (i-- > 0) 870 fwohci_buf_free(sc, --fb); 871 free(fc, M_DEVBUF); 872 return error; 873 } 874 875 static void 876 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 877 { 878 struct fwohci_buf *fb; 879 struct fwohci_handler *fh; 880 881 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 882 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 883 NULL, NULL); 884 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 885 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 886 fwohci_buf_free(sc, fb); 887 } 888 free(fc, M_DEVBUF); 889 } 890 891 static void 892 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 893 { 894 struct fwohci_buf *fb, *nfb; 895 struct fwohci_desc *fd; 896 struct fwohci_handler *fh; 897 int n; 898 899 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 900 nfb = TAILQ_NEXT(fb, fb_list); 901 fb->fb_off = 0; 902 fd = fb->fb_desc; 903 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 904 fd->fd_rescount = fd->fd_reqcount; 905 } 906 907 n = fc->fc_ctx; 908 fb = TAILQ_FIRST(&fc->fc_buf); 909 if (fc->fc_isoch) { 910 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 911 fb->fb_daddr | 1); 912 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 913 OHCI_CTXCTL_RX_BUFFER_FILL | 914 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 915 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 916 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 917 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 918 OHCI_CTXCTL_RX_ISOCH_HEADER); 919 fh = LIST_FIRST(&fc->fc_handler); 920 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 921 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 922 } else { 923 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 924 fb->fb_daddr | 1); 925 } 926 } 927 928 /* 929 * DMA data buffer 930 */ 931 static int 932 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 933 { 934 int error; 935 936 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 937 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 938 printf("%s: unable to allocate buffer, error = %d\n", 939 sc->sc_sc1394.sc1394_dev.dv_xname, error); 940 goto fail_0; 941 } 942 943 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 944 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 945 printf("%s: unable to map buffer, error = %d\n", 946 sc->sc_sc1394.sc1394_dev.dv_xname, error); 947 goto fail_1; 948 } 949 950 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 951 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 952 printf("%s: unable to create buffer DMA map, " 953 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 954 error); 955 goto fail_2; 956 } 957 958 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 959 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 960 printf("%s: unable to load buffer DMA map, " 961 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 962 error); 963 goto fail_3; 964 } 965 966 return 0; 967 968 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 969 fail_3: 970 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 971 fail_2: 972 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 973 fail_1: 974 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 975 fail_0: 976 return error; 977 } 978 979 static void 980 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 981 { 982 983 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 984 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 985 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 986 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 987 } 988 989 static void 990 fwohci_buf_init(struct fwohci_softc *sc) 991 { 992 int i; 993 994 /* 995 * Initialize for Asynchronous Transmit Queue. 996 */ 997 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 998 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 999 1000 /* 1001 * Initialize for Asynchronous Receive Queue. 1002 */ 1003 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1004 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1005 1006 /* 1007 * Initialize for Isochronous Receive Queue. 1008 */ 1009 for (i = 0; i < sc->sc_isoctx; i++) { 1010 if (sc->sc_ctx_ir[i] != NULL) 1011 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1012 } 1013 } 1014 1015 static void 1016 fwohci_buf_start(struct fwohci_softc *sc) 1017 { 1018 int i; 1019 1020 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1021 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1022 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1023 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1024 for (i = 0; i < sc->sc_isoctx; i++) { 1025 if (sc->sc_ctx_ir[i] != NULL && 1026 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1027 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1028 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1029 } 1030 } 1031 } 1032 1033 static void 1034 fwohci_buf_stop(struct fwohci_softc *sc) 1035 { 1036 int i, j; 1037 1038 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1039 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1040 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1041 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1042 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1043 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1044 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1045 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1046 for (i = 0; i < sc->sc_isoctx; i++) { 1047 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1048 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1049 } 1050 1051 /* 1052 * Make sure the transmitter is stopped. 1053 */ 1054 for (j = 0; j < OHCI_LOOP; j++) { 1055 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1056 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1057 continue; 1058 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1059 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1060 continue; 1061 break; 1062 } 1063 } 1064 1065 static void 1066 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1067 { 1068 struct fwohci_buf *fb, *tfb; 1069 1070 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1071 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1072 fb->fb_desc->fd_rescount != 0) 1073 break; 1074 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1075 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1076 fb->fb_off = 0; 1077 fb->fb_desc->fd_branch = 0; 1078 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1079 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1080 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1081 } 1082 } 1083 1084 static int 1085 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1086 int len) 1087 { 1088 struct fwohci_buf *fb; 1089 struct fwohci_desc *fd; 1090 int bufend; 1091 1092 fb = TAILQ_FIRST(&fc->fc_buf); 1093 again: 1094 fd = fb->fb_desc; 1095 #ifdef FW_DEBUG 1096 if (fw_verbose > 1) 1097 printf("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1098 " len %d, avail %d\n", 1099 (long)(fd - sc->sc_desc), fb->fb_off, fd->fd_reqcount, 1100 fd->fd_rescount, len, 1101 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1102 #endif 1103 bufend = fd->fd_reqcount - fd->fd_rescount; 1104 if (fb->fb_off >= bufend) { 1105 if (fc->fc_isoch && fb->fb_off > 0) { 1106 fb->fb_off = fd->fd_reqcount; 1107 fd->fd_rescount = 0; 1108 } 1109 if (fd->fd_rescount == 0) { 1110 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1111 goto again; 1112 } 1113 return 0; 1114 } 1115 if (fb->fb_off + len > bufend) 1116 len = bufend - fb->fb_off; 1117 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1118 BUS_DMASYNC_POSTREAD); 1119 *pp = fb->fb_buf + fb->fb_off; 1120 fb->fb_off += roundup(len, 4); 1121 return len; 1122 } 1123 1124 static int 1125 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1126 struct fwohci_pkt *pkt) 1127 { 1128 caddr_t p; 1129 int len, count, i; 1130 1131 memset(pkt, 0, sizeof(*pkt)); 1132 pkt->fp_uio.uio_iov = pkt->fp_iov; 1133 pkt->fp_uio.uio_rw = UIO_WRITE; 1134 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1135 1136 /* get first quadlet */ 1137 count = 4; 1138 if (fc->fc_isoch) { 1139 /* 1140 * get trailer first, may be bogus data unless status update 1141 * in descriptor is set. 1142 */ 1143 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1144 sizeof(*pkt->fp_trail)); 1145 if (len <= 0) { 1146 #ifdef FW_DEBUG 1147 if (fw_verbose > 1) 1148 printf("fwohci_buf_input: no input for is#%d\n", 1149 fc->fc_ctx); 1150 #endif 1151 return 0; 1152 } 1153 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1154 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1155 } 1156 len = fwohci_buf_pktget(sc, fc, &p, count); 1157 if (len <= 0) { 1158 #ifdef FW_DEBUG 1159 if (fw_verbose > 1) 1160 printf("fwohci_buf_input: no input for %d\n", 1161 fc->fc_ctx); 1162 #endif 1163 return 0; 1164 } 1165 pkt->fp_hdr[0] = *(u_int32_t *)p; 1166 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1167 switch (pkt->fp_tcode) { 1168 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1169 case IEEE1394_TCODE_READ_RESP_QUAD: 1170 pkt->fp_hlen = 12; 1171 pkt->fp_dlen = 4; 1172 break; 1173 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1174 case IEEE1394_TCODE_READ_RESP_BLOCK: 1175 case IEEE1394_TCODE_LOCK_REQ: 1176 case IEEE1394_TCODE_LOCK_RESP: 1177 pkt->fp_hlen = 16; 1178 break; 1179 case IEEE1394_TCODE_STREAM_DATA: 1180 pkt->fp_hlen = 4; 1181 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1182 break; 1183 default: 1184 pkt->fp_hlen = 12; 1185 pkt->fp_dlen = 0; 1186 break; 1187 } 1188 1189 /* get header */ 1190 while (count < pkt->fp_hlen) { 1191 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1192 if (len == 0) { 1193 printf("fwohci_buf_input: malformed input 1: %d\n", 1194 pkt->fp_hlen - count); 1195 return 0; 1196 } 1197 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1198 count += len; 1199 } 1200 if (pkt->fp_hlen == 16) 1201 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1202 #ifdef FW_DEBUG 1203 if (fw_verbose > 1) 1204 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1205 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1206 #endif 1207 1208 /* get data */ 1209 count = 0; 1210 i = 0; 1211 while (count < pkt->fp_dlen) { 1212 len = fwohci_buf_pktget(sc, fc, 1213 (caddr_t *)&pkt->fp_iov[i].iov_base, 1214 pkt->fp_dlen - count); 1215 if (len == 0) { 1216 printf("fwohci_buf_input: malformed input 2: %d\n", 1217 pkt->fp_hlen - count); 1218 return 0; 1219 } 1220 pkt->fp_iov[i++].iov_len = len; 1221 count += len; 1222 } 1223 pkt->fp_uio.uio_iovcnt = i; 1224 pkt->fp_uio.uio_resid = count; 1225 1226 if (!fc->fc_isoch) { 1227 /* get trailer */ 1228 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1229 sizeof(*pkt->fp_trail)); 1230 if (len <= 0) { 1231 printf("fwohci_buf_input: malformed input 3: %d\n", 1232 pkt->fp_hlen - count); 1233 return 0; 1234 } 1235 } 1236 return 1; 1237 } 1238 1239 static int 1240 fwohci_handler_set(struct fwohci_softc *sc, 1241 int tcode, u_int32_t key1, u_int32_t key2, 1242 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1243 void *arg) 1244 { 1245 struct fwohci_ctx *fc; 1246 struct fwohci_handler *fh; 1247 int i, j; 1248 1249 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1250 j = sc->sc_isoctx; 1251 fh = NULL; 1252 for (i = 0; i < sc->sc_isoctx; i++) { 1253 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1254 if (j == sc->sc_isoctx) 1255 j = i; 1256 continue; 1257 } 1258 fh = LIST_FIRST(&fc->fc_handler); 1259 if (fh == NULL) { 1260 j = i; 1261 break; 1262 } 1263 if (fh->fh_tcode == tcode && 1264 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1265 break; 1266 fh = NULL; 1267 } 1268 if (fh == NULL) { 1269 if (handler == NULL) 1270 return 0; 1271 if (j == sc->sc_isoctx) { 1272 #ifdef FW_DEBUG 1273 if (fw_verbose) 1274 printf("fwohci_handler_set: " 1275 "no more free context\n"); 1276 #endif 1277 return ENOMEM; 1278 } 1279 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1280 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1281 fc->fc_isoch = 1; 1282 sc->sc_ctx_ir[j] = fc; 1283 } 1284 } 1285 } else { 1286 switch (tcode) { 1287 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1288 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1289 case IEEE1394_TCODE_READ_REQ_QUAD: 1290 case IEEE1394_TCODE_READ_REQ_BLOCK: 1291 case IEEE1394_TCODE_LOCK_REQ: 1292 fc = sc->sc_ctx_arrq; 1293 break; 1294 case IEEE1394_TCODE_WRITE_RESP: 1295 case IEEE1394_TCODE_READ_RESP_QUAD: 1296 case IEEE1394_TCODE_READ_RESP_BLOCK: 1297 case IEEE1394_TCODE_LOCK_RESP: 1298 fc = sc->sc_ctx_arrs; 1299 break; 1300 default: 1301 return EIO; 1302 } 1303 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1304 fh = LIST_NEXT(fh, fh_list)) { 1305 if (fh->fh_tcode == tcode && 1306 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1307 break; 1308 } 1309 } 1310 if (handler == NULL) { 1311 if (fh != NULL) { 1312 LIST_REMOVE(fh, fh_list); 1313 free(fh, M_DEVBUF); 1314 } 1315 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1316 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1317 fwohci_ctx_free(sc, fc); 1318 } 1319 return 0; 1320 } 1321 if (fh == NULL) { 1322 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 1323 if (fh == NULL) 1324 return ENOMEM; 1325 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1326 } 1327 fh->fh_tcode = tcode; 1328 fh->fh_key1 = key1; 1329 fh->fh_key2 = key2; 1330 fh->fh_handler = handler; 1331 fh->fh_handarg = arg; 1332 #ifdef FW_DEBUG 1333 if (fw_verbose > 1) 1334 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1335 fc->fc_ctx, tcode, key1, key2); 1336 #endif 1337 1338 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1339 fwohci_ctx_init(sc, fc); 1340 #ifdef FW_DEBUG 1341 if (fw_verbose > 1) 1342 printf("fwohci_handler_set: SYNC desc %ld\n", 1343 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - 1344 sc->sc_desc)); 1345 #endif 1346 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1347 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1348 } 1349 return 0; 1350 } 1351 1352 /* 1353 * Asyncronous Receive Requests input frontend. 1354 */ 1355 static void 1356 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1357 { 1358 int rcode; 1359 u_int32_t key1, key2; 1360 struct fwohci_handler *fh; 1361 struct fwohci_pkt pkt, res; 1362 1363 while (fwohci_buf_input(sc, fc, &pkt)) { 1364 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1365 fwohci_phy_input(sc, &pkt); 1366 continue; 1367 } 1368 key1 = pkt.fp_hdr[1] & 0xffff; 1369 key2 = pkt.fp_hdr[2]; 1370 memset(&res, 0, sizeof(res)); 1371 res.fp_uio.uio_rw = UIO_WRITE; 1372 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1373 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1374 fh = LIST_NEXT(fh, fh_list)) { 1375 if (pkt.fp_tcode == fh->fh_tcode && 1376 key1 == fh->fh_key1 && 1377 key2 == fh->fh_key2) { 1378 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1379 &pkt); 1380 break; 1381 } 1382 } 1383 if (fh == NULL) { 1384 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1385 #ifdef FW_DEBUG 1386 if (fw_verbose > 1) 1387 printf("fwohci_arrq_input: no listener:" 1388 " tcode 0x%x, addr=0x%04x %08x\n", 1389 pkt.fp_tcode, key1, key2); 1390 #endif 1391 } 1392 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1393 OHCI_CTXCTL_EVENT_ACK_PENDING) 1394 continue; 1395 if (rcode != -1) 1396 fwohci_atrs_output(sc, rcode, &pkt, &res); 1397 } 1398 fwohci_buf_next(sc, fc); 1399 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1400 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1401 } 1402 1403 /* 1404 * Asynchronous Receive Response input frontend. 1405 */ 1406 static void 1407 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1408 { 1409 struct fwohci_pkt pkt; 1410 struct fwohci_handler *fh; 1411 u_int16_t srcid; 1412 int rcode, tlabel; 1413 1414 while (fwohci_buf_input(sc, fc, &pkt)) { 1415 srcid = pkt.fp_hdr[1] >> 16; 1416 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1417 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1418 #ifdef FW_DEBUG 1419 if (fw_verbose > 1) 1420 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1421 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1422 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1423 pkt.fp_dlen); 1424 #endif 1425 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1426 fh = LIST_NEXT(fh, fh_list)) { 1427 if (pkt.fp_tcode == fh->fh_tcode && 1428 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1429 tlabel == fh->fh_key2) { 1430 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1431 LIST_REMOVE(fh, fh_list); 1432 free(fh, M_DEVBUF); 1433 break; 1434 } 1435 } 1436 #ifdef FW_DEBUG 1437 if (fw_verbose > 1) 1438 if (fh == NULL) 1439 printf("fwohci_arrs_input: no lister\n"); 1440 #endif 1441 } 1442 fwohci_buf_next(sc, fc); 1443 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1444 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1445 } 1446 1447 /* 1448 * Isochronous Receive input frontend. 1449 */ 1450 static void 1451 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1452 { 1453 int rcode, chan, tag; 1454 struct iovec *iov; 1455 struct fwohci_handler *fh; 1456 struct fwohci_pkt pkt; 1457 1458 while (fwohci_buf_input(sc, fc, &pkt)) { 1459 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1460 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1461 #ifdef FW_DEBUG 1462 if (fw_verbose > 1) 1463 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1464 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1465 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1466 #endif 1467 if (tag == IEEE1394_TAG_GASP) { 1468 /* 1469 * The pkt with tag=3 is GASP format. 1470 * Move GASP header to header part. 1471 */ 1472 if (pkt.fp_dlen < 8) 1473 continue; 1474 iov = pkt.fp_iov; 1475 /* assuming pkt per buffer mode */ 1476 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1477 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1478 iov->iov_base = (caddr_t)iov->iov_base + 8; 1479 iov->iov_len -= 8; 1480 pkt.fp_hlen += 8; 1481 pkt.fp_dlen -= 8; 1482 } 1483 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1484 fh = LIST_NEXT(fh, fh_list)) { 1485 if (pkt.fp_tcode == fh->fh_tcode && 1486 chan == fh->fh_key1 && tag == fh->fh_key2) { 1487 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1488 &pkt); 1489 break; 1490 } 1491 } 1492 #ifdef FW_DEBUG 1493 if (fw_verbose > 1) { 1494 if (fh == NULL) 1495 printf("fwohci_ir_input: no handler\n"); 1496 else 1497 printf("fwohci_ir_input: rcode %d\n", rcode); 1498 } 1499 #endif 1500 } 1501 fwohci_buf_next(sc, fc); 1502 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1503 OHCI_CTXCTL_WAKE); 1504 } 1505 1506 /* 1507 * Asynchronous Transmit common routine. 1508 */ 1509 static int 1510 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1511 struct fwohci_pkt *pkt) 1512 { 1513 struct fwohci_buf *fb; 1514 struct fwohci_desc *fd; 1515 struct mbuf *m, *m0; 1516 int i, ndesc, error, off, len; 1517 u_int32_t val; 1518 1519 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) { 1520 /* We can't send anything during selfid duration */ 1521 return EAGAIN; 1522 } 1523 #ifdef FW_DEBUG 1524 if (fw_verbose > 1) { 1525 struct iovec *iov; 1526 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1527 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1528 if (fw_dump) { 1529 for (i = 0; i < pkt->fp_hlen/4; i++) 1530 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1531 printf("$"); 1532 for (ndesc = 0, iov = pkt->fp_iov; 1533 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1534 for (i = 0; i < iov->iov_len; i++) 1535 printf("%s%02x", 1536 (i%32)?((i%4)?"":" "):"\n\t", 1537 ((u_int8_t *)iov->iov_base)[i]); 1538 printf("$"); 1539 } 1540 } 1541 printf("\n"); 1542 } 1543 #endif 1544 1545 if ((m = pkt->fp_m) != NULL) { 1546 for (ndesc = 2; m != NULL; m = m->m_next) 1547 ndesc++; 1548 if (ndesc > OHCI_DESC_MAX) { 1549 m0 = NULL; 1550 ndesc = 2; 1551 for (off = 0; off < pkt->fp_dlen; off += len) { 1552 if (m0 == NULL) { 1553 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1554 if (m0 != NULL) 1555 M_COPY_PKTHDR(m0, pkt->fp_m); 1556 m = m0; 1557 } else { 1558 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1559 m = m->m_next; 1560 } 1561 if (m != NULL) 1562 MCLGET(m, M_DONTWAIT); 1563 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1564 m_freem(m0); 1565 return ENOMEM; 1566 } 1567 len = pkt->fp_dlen - off; 1568 if (len > m->m_ext.ext_size) 1569 len = m->m_ext.ext_size; 1570 m_copydata(pkt->fp_m, off, len, 1571 mtod(m, caddr_t)); 1572 m->m_len = len; 1573 ndesc++; 1574 } 1575 m_freem(pkt->fp_m); 1576 pkt->fp_m = m0; 1577 } 1578 } else 1579 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1580 1581 if (ndesc > OHCI_DESC_MAX) 1582 return ENOBUFS; 1583 1584 if (fc->fc_bufcnt > 50) /*XXX*/ 1585 return ENOBUFS; 1586 if ((fb = malloc(sizeof(*fb), M_DEVBUF, M_NOWAIT)) == NULL) 1587 return ENOBUFS; 1588 fb->fb_nseg = ndesc; 1589 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1590 if (fb->fb_desc == NULL) { 1591 free(fb, M_DEVBUF); 1592 return ENOBUFS; 1593 } 1594 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1595 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1596 fb->fb_m = pkt->fp_m; 1597 fb->fb_callback = pkt->fp_callback; 1598 1599 if (ndesc > 2) { 1600 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1601 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &fb->fb_dmamap)) != 0) { 1602 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1603 free(fb, M_DEVBUF); 1604 return error; 1605 } 1606 1607 if (pkt->fp_m != NULL) 1608 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1609 pkt->fp_m, BUS_DMA_NOWAIT); 1610 else 1611 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1612 &pkt->fp_uio, BUS_DMA_NOWAIT); 1613 if (error != 0) { 1614 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1615 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1616 free(fb, M_DEVBUF); 1617 return error; 1618 } 1619 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1620 BUS_DMASYNC_PREWRITE); 1621 } 1622 1623 fd = fb->fb_desc; 1624 fd->fd_flags = OHCI_DESC_IMMED; 1625 fd->fd_reqcount = pkt->fp_hlen; 1626 fd->fd_data = 0; 1627 fd->fd_branch = 0; 1628 fd->fd_status = 0; 1629 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1630 i = 3; /* XXX: 3 sec */ 1631 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1632 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1633 ((((val >> 25) + i) & 0x7) << 13); 1634 } else 1635 fd->fd_timestamp = 0; 1636 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1637 for (i = 0; i < ndesc - 2; i++) { 1638 fd = fb->fb_desc + 2 + i; 1639 fd->fd_flags = 0; 1640 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1641 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1642 fd->fd_branch = 0; 1643 fd->fd_status = 0; 1644 fd->fd_timestamp = 0; 1645 } 1646 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1647 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1648 1649 #ifdef FW_DEBUG 1650 if (fw_verbose > 1) { 1651 printf("fwohci_at_output: desc %ld", 1652 (long)(fb->fb_desc - sc->sc_desc)); 1653 for (i = 0; i < ndesc * 4; i++) 1654 printf("%s%08x", i&7?" ":"\n\t", 1655 ((u_int32_t *)fb->fb_desc)[i]); 1656 printf("\n"); 1657 } 1658 #endif 1659 1660 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1661 OHCI_SUBREG_ContextControlClear); 1662 1663 if (val & OHCI_CTXCTL_RUN) { 1664 if (fc->fc_branch == NULL) { 1665 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1666 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1667 goto run; 1668 } 1669 *fc->fc_branch = fb->fb_daddr | ndesc; 1670 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1671 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1672 } else { 1673 run: 1674 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1675 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1676 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1677 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1678 } 1679 fc->fc_branch = &fd->fd_branch; 1680 1681 fc->fc_bufcnt++; 1682 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1683 pkt->fp_m = NULL; 1684 return 0; 1685 } 1686 1687 static void 1688 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1689 { 1690 struct fwohci_buf *fb; 1691 struct fwohci_desc *fd; 1692 int i; 1693 1694 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1695 fd = fb->fb_desc; 1696 #ifdef FW_DEBUG 1697 if (fw_verbose > 1) { 1698 printf("fwohci_at_done: %sdesc %ld (%d)", 1699 force ? "force " : "", 1700 (long)(fd - sc->sc_desc), fb->fb_nseg); 1701 for (i = 0; i < fb->fb_nseg * 4; i++) 1702 printf("%s%08x", i&7?" ":"\n ", 1703 ((u_int32_t *)fd)[i]); 1704 printf("\n"); 1705 } 1706 #endif 1707 if (fb->fb_nseg > 2) 1708 fd += fb->fb_nseg - 1; 1709 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1710 break; 1711 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1712 if (fc->fc_branch == &fd->fd_branch) { 1713 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1714 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1715 fc->fc_branch = NULL; 1716 for (i = 0; i < OHCI_LOOP; i++) { 1717 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1718 OHCI_SUBREG_ContextControlClear) & 1719 OHCI_CTXCTL_ACTIVE)) 1720 break; 1721 } 1722 } 1723 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1724 if (fb->fb_nseg > 2) 1725 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1726 fc->fc_bufcnt--; 1727 if (fb->fb_callback != NULL) { 1728 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1729 fb->fb_callback = NULL; 1730 } else if (fb->fb_m != NULL) 1731 m_freem(fb->fb_m); 1732 free(fb, M_DEVBUF); 1733 } 1734 } 1735 1736 /* 1737 * Asynchronous Transmit Reponse -- in response of request packet. 1738 */ 1739 static void 1740 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1741 struct fwohci_pkt *res) 1742 { 1743 1744 if (((*req->fp_trail & 0x001f0000) >> 16) != 1745 OHCI_CTXCTL_EVENT_ACK_PENDING) 1746 return; 1747 1748 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1749 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1750 switch (req->fp_tcode) { 1751 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1752 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1753 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1754 res->fp_hlen = 12; 1755 break; 1756 case IEEE1394_TCODE_READ_REQ_QUAD: 1757 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1758 res->fp_hlen = 16; 1759 res->fp_dlen = 0; 1760 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1761 res->fp_hdr[3] = 1762 *(u_int32_t *)res->fp_iov[0].iov_base; 1763 res->fp_uio.uio_iovcnt = 0; 1764 break; 1765 case IEEE1394_TCODE_READ_REQ_BLOCK: 1766 case IEEE1394_TCODE_LOCK_REQ: 1767 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1768 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1769 else 1770 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1771 res->fp_hlen = 16; 1772 res->fp_dlen = res->fp_uio.uio_resid; 1773 res->fp_hdr[3] = res->fp_dlen << 16; 1774 break; 1775 } 1776 res->fp_hdr[0] |= (res->fp_tcode << 4); 1777 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1778 } 1779 1780 /* 1781 * APPLICATION LAYER SERVICES 1782 */ 1783 1784 /* 1785 * Retrieve Global UID from GUID ROM 1786 */ 1787 static int 1788 fwohci_guidrom_init(struct fwohci_softc *sc) 1789 { 1790 int i, n, off; 1791 u_int32_t val1, val2; 1792 1793 /* Extract the Global UID 1794 */ 1795 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1796 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1797 1798 if (val1 != 0 || val2 != 0) { 1799 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1800 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1801 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1802 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1803 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1804 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1805 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1806 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1807 } else { 1808 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1809 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1810 return -1; 1811 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1812 for (i = 0; i < OHCI_LOOP; i++) { 1813 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1814 if (!(val1 & OHCI_Guid_AddrReset)) 1815 break; 1816 } 1817 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1818 val2 = 0; 1819 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1820 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1821 OHCI_Guid_RdStart); 1822 for (i = 0; i < OHCI_LOOP; i++) { 1823 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1824 if (!(val1 & OHCI_Guid_RdStart)) 1825 break; 1826 } 1827 if (n < off) 1828 continue; 1829 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1830 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1831 val2 |= val1; 1832 } 1833 if (val2 == 0) 1834 return -1; 1835 } 1836 return 0; 1837 } 1838 1839 /* 1840 * Initialization for Configuration ROM (no DMA context) 1841 */ 1842 1843 #define CFR_MAXUNIT 20 1844 1845 struct configromctx { 1846 u_int32_t *ptr; 1847 int curunit; 1848 struct { 1849 u_int32_t *start; 1850 int length; 1851 u_int32_t *refer; 1852 int refunit; 1853 } unit[CFR_MAXUNIT]; 1854 }; 1855 1856 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1857 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1858 1859 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1860 1861 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1862 1863 #define CFR_PUT_CRC(cfr, n) \ 1864 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1865 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1866 1867 #define CFR_START_UNIT(cfr, n) \ 1868 do { \ 1869 if ((cfr)->unit[n].refer != NULL) { \ 1870 *(cfr)->unit[n].refer |= \ 1871 (cfr)->ptr - (cfr)->unit[n].refer; \ 1872 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1873 } \ 1874 (cfr)->curunit = (n); \ 1875 (cfr)->unit[n].start = (cfr)->ptr++; \ 1876 } while (0 /* CONSTCOND */) 1877 1878 #define CFR_PUT_REFER(cfr, key, n) \ 1879 do { \ 1880 (cfr)->unit[n].refer = (cfr)->ptr; \ 1881 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1882 *(cfr)->ptr++ = (key) << 24; \ 1883 } while (0 /* CONSTCOND */) 1884 1885 #define CFR_END_UNIT(cfr) \ 1886 do { \ 1887 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1888 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1889 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1890 } while (0 /* CONSTCOND */) 1891 1892 static u_int16_t 1893 fwohci_crc16(u_int32_t *ptr, int len) 1894 { 1895 int shift; 1896 u_int32_t crc, sum, data; 1897 1898 crc = 0; 1899 while (len-- > 0) { 1900 data = *ptr++; 1901 for (shift = 28; shift >= 0; shift -= 4) { 1902 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1903 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1904 } 1905 crc &= 0xffff; 1906 } 1907 return crc; 1908 } 1909 1910 static void 1911 fwohci_configrom_init(struct fwohci_softc *sc) 1912 { 1913 int i; 1914 struct fwohci_buf *fb; 1915 u_int32_t *hdr; 1916 struct configromctx cfr; 1917 1918 fb = &sc->sc_buf_cnfrom; 1919 memset(&cfr, 0, sizeof(cfr)); 1920 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1921 1922 /* headers */ 1923 CFR_START_UNIT(&cfr, 0); 1924 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1925 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1926 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1927 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1928 CFR_END_UNIT(&cfr); 1929 /* copy info_length from crc_length */ 1930 *hdr |= (*hdr & 0x00ff0000) << 8; 1931 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1932 1933 /* root directory */ 1934 CFR_START_UNIT(&cfr, 1); 1935 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1936 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1937 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1938 /* spt,64,fix,lst,drq */ 1939 #ifdef INET 1940 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1941 #endif /* INET */ 1942 #ifdef INET6 1943 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1944 #endif /* INET6 */ 1945 CFR_END_UNIT(&cfr); 1946 1947 CFR_START_UNIT(&cfr, 2); 1948 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1949 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1950 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1951 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1952 CFR_END_UNIT(&cfr); 1953 1954 #ifdef INET 1955 /* IPv4 unit directory */ 1956 CFR_START_UNIT(&cfr, 3); 1957 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1958 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1959 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1960 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1961 CFR_END_UNIT(&cfr); 1962 1963 CFR_START_UNIT(&cfr, 6); 1964 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1965 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1966 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1967 CFR_END_UNIT(&cfr); 1968 1969 CFR_START_UNIT(&cfr, 7); 1970 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1971 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1972 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1973 CFR_END_UNIT(&cfr); 1974 #endif /* INET */ 1975 1976 #ifdef INET6 1977 /* IPv6 unit directory */ 1978 CFR_START_UNIT(&cfr, 4); 1979 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1980 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1981 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 1982 /* XXX: TBA by IANA */ 1983 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1984 CFR_END_UNIT(&cfr); 1985 1986 CFR_START_UNIT(&cfr, 8); 1987 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1988 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1989 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1990 CFR_END_UNIT(&cfr); 1991 1992 CFR_START_UNIT(&cfr, 9); 1993 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1994 CFR_PUT_DATA1(&cfr, 0); 1995 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1996 CFR_END_UNIT(&cfr); 1997 #endif /* INET6 */ 1998 1999 #ifdef FW_DEBUG 2000 if (fw_dump) { 2001 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 2002 for (i = 0; i < cfr.ptr - hdr; i++) 2003 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 2004 printf("\n"); 2005 } 2006 #endif /* FW_DEBUG */ 2007 2008 /* 2009 * Make network byte order for DMA 2010 */ 2011 for (i = 0; i < cfr.ptr - hdr; i++) 2012 HTONL(hdr[i]); 2013 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2014 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2015 2016 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2017 fb->fb_dmamap->dm_segs[0].ds_addr); 2018 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 2019 } 2020 2021 /* 2022 * SelfID buffer (no DMA context) 2023 */ 2024 static void 2025 fwohci_selfid_init(struct fwohci_softc *sc) 2026 { 2027 struct fwohci_buf *fb; 2028 2029 fb = &sc->sc_buf_selfid; 2030 #ifdef DIAGNOSTICS 2031 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2032 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2033 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2034 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2035 #endif 2036 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2037 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2038 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2039 2040 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2041 fb->fb_dmamap->dm_segs[0].ds_addr); 2042 } 2043 2044 static int 2045 fwohci_selfid_input(struct fwohci_softc *sc) 2046 { 2047 int i; 2048 u_int32_t count, val, gen; 2049 u_int32_t *buf; 2050 2051 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2052 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2053 again: 2054 if (val & OHCI_SelfID_Error) { 2055 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2056 return -1; 2057 } 2058 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2059 2060 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2061 0, count << 2, BUS_DMASYNC_POSTREAD); 2062 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2063 2064 #ifdef FW_DEBUG 2065 if (fw_verbose > 1) { 2066 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2067 val); 2068 for (i = 0; i < count; i++) 2069 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2070 printf("\n"); 2071 } 2072 #endif /* FW_DEBUG */ 2073 2074 for (i = 1; i < count; i += 2) { 2075 if (buf[i] != ~buf[i + 1]) 2076 break; 2077 if (buf[i] & 0x00000001) 2078 continue; /* more pkt */ 2079 if (buf[i] & 0x00800000) 2080 continue; /* external id */ 2081 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2082 if ((buf[i] & 0x00400800) == 0x00400800) 2083 sc->sc_irmid = sc->sc_rootid; 2084 } 2085 2086 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2087 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2088 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2089 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2090 goto again; 2091 #ifdef FW_DEBUG 2092 if (fw_verbose) 2093 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2094 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2095 OHCI_BITVAL(val, OHCI_SelfID_Gen)); 2096 #endif 2097 return -1; 2098 } 2099 if (i != count) { 2100 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2101 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2102 #if 1 2103 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2104 /* 2105 * XXX: CXD3222 sometimes fails to DMA 2106 * selfid packet?? 2107 */ 2108 sc->sc_rootid = (count - 1) / 2 - 1; 2109 sc->sc_irmid = sc->sc_rootid; 2110 } else 2111 #endif 2112 return -1; 2113 } 2114 2115 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2116 if ((val & OHCI_NodeId_IDValid) == 0) { 2117 sc->sc_nodeid = 0xffff; /* invalid */ 2118 printf("%s: nodeid is invalid\n", 2119 sc->sc_sc1394.sc1394_dev.dv_xname); 2120 return -1; 2121 } 2122 sc->sc_nodeid = val & 0xffff; 2123 2124 #ifdef FW_DEBUG 2125 if (fw_verbose) 2126 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2127 sc->sc_sc1394.sc1394_dev.dv_xname, 2128 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2129 sc->sc_rootid, sc->sc_irmid); 2130 #endif 2131 2132 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2133 return -1; 2134 2135 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2136 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2137 OHCI_LinkControl_CycleMaster); 2138 else 2139 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2140 OHCI_LinkControl_CycleMaster); 2141 return 0; 2142 } 2143 2144 /* 2145 * some CSRs are handled by driver. 2146 */ 2147 static void 2148 fwohci_csr_init(struct fwohci_softc *sc) 2149 { 2150 int i; 2151 static u_int32_t csr[] = { 2152 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2153 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2154 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2155 CSR_SB_BROADCAST_CHANNEL 2156 }; 2157 2158 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2159 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2160 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2161 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2162 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2163 } 2164 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2165 } 2166 2167 static int 2168 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2169 { 2170 struct fwohci_pkt res; 2171 u_int32_t reg; 2172 2173 /* 2174 * XXX need to do special functionality other than just r/w... 2175 */ 2176 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2177 2178 if ((reg & 0x03) != 0) { 2179 /* alignment error */ 2180 return IEEE1394_RCODE_ADDRESS_ERROR; 2181 } 2182 #ifdef FW_DEBUG 2183 if (fw_verbose > 1) 2184 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2185 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2186 #endif 2187 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2188 #ifdef FW_DEBUG 2189 if (fw_verbose > 1) 2190 printf(" -> 0x%08x\n", 2191 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2192 #endif 2193 *(u_int32_t *)&sc->sc_csr[reg] = 2194 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2195 } else { 2196 #ifdef FW_DEBUG 2197 if (fw_verbose > 1) 2198 printf("\n"); 2199 #endif 2200 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2201 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2202 res.fp_iov[0].iov_len = 4; 2203 res.fp_uio.uio_resid = 4; 2204 res.fp_uio.uio_iovcnt = 1; 2205 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2206 return -1; 2207 } 2208 return IEEE1394_RCODE_COMPLETE; 2209 } 2210 2211 /* 2212 * Mapping between nodeid and unique ID (EUI-64). 2213 */ 2214 static void 2215 fwohci_uid_collect(struct fwohci_softc *sc) 2216 { 2217 int i; 2218 struct fwohci_uidtbl *fu; 2219 struct fwohci_pkt pkt; 2220 2221 if (sc->sc_uidtbl != NULL) 2222 free(sc->sc_uidtbl, M_DEVBUF); 2223 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 2224 M_DEVBUF, M_NOWAIT); 2225 if (sc->sc_uidtbl == NULL) 2226 return; 2227 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2228 2229 memset(&pkt, 0, sizeof(pkt)); 2230 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2231 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2232 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2233 fu->fu_valid = 3; 2234 continue; 2235 } 2236 fu->fu_valid = 0; 2237 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2238 pkt.fp_hlen = 12; 2239 pkt.fp_dlen = 0; 2240 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2241 (pkt.fp_tcode << 4); 2242 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2243 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2244 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2245 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2246 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2247 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2248 2249 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2250 (pkt.fp_tcode << 4); 2251 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2252 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2253 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2254 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2255 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2256 } 2257 } 2258 2259 static int 2260 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2261 { 2262 int n, rcode; 2263 struct fwohci_uidtbl *fu; 2264 2265 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2266 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2267 if (rcode != IEEE1394_RCODE_COMPLETE || 2268 sc->sc_uidtbl == NULL || 2269 n > sc->sc_rootid) 2270 return 0; 2271 fu = &sc->sc_uidtbl[n]; 2272 if (arg == 0) { 2273 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2274 fu->fu_valid |= 0x1; 2275 } else { 2276 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2277 fu->fu_valid |= 0x2; 2278 } 2279 #ifdef FW_DEBUG 2280 if (fw_verbose && fu->fu_valid == 0x3) 2281 printf("fwohci_uid_input: " 2282 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2283 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2284 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2285 #endif 2286 return 0; 2287 } 2288 2289 static int 2290 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2291 { 2292 struct fwohci_uidtbl *fu; 2293 int n; 2294 static const u_int8_t bcast[] = 2295 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2296 2297 fu = sc->sc_uidtbl; 2298 if (fu == NULL) { 2299 notfound: 2300 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2301 return IEEE1394_BCAST_PHY_ID; 2302 fwohci_uid_collect(sc); /* try to get */ 2303 return -1; 2304 } 2305 for (n = 0; ; n++, fu++) { 2306 if (n > sc->sc_rootid) 2307 goto notfound; 2308 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2309 break; 2310 } 2311 return n; 2312 } 2313 2314 /* 2315 * functions to support network interface 2316 */ 2317 static int 2318 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2319 void (*handler)(struct device *, struct mbuf *)) 2320 { 2321 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2322 int s; 2323 2324 s = splimp(); 2325 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2326 fwohci_if_input, handler); 2327 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2328 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2329 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2330 splx(s); 2331 return 0; 2332 } 2333 2334 static int 2335 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2336 { 2337 int n, len; 2338 struct mbuf *m; 2339 struct iovec *iov; 2340 void (*handler)(struct device *, struct mbuf *) = arg; 2341 2342 #ifdef FW_DEBUG 2343 if (fw_verbose > 1) { 2344 int i; 2345 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2346 pkt->fp_tcode, pkt->fp_dlen); 2347 if (fw_dump) { 2348 for (i = 0; i < pkt->fp_hlen/4; i++) 2349 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2350 printf("$"); 2351 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2352 iov = &pkt->fp_iov[n]; 2353 for (i = 0; i < iov->iov_len; i++) 2354 printf("%s%02x", 2355 (i%32)?((i%4)?"":" "):"\n\t", 2356 ((u_int8_t *)iov->iov_base)[i]); 2357 printf("$"); 2358 } 2359 } 2360 printf("\n"); 2361 } 2362 #endif /* FW_DEBUG */ 2363 len = pkt->fp_dlen; 2364 MGETHDR(m, M_DONTWAIT, MT_DATA); 2365 if (m == NULL) 2366 return IEEE1394_RCODE_COMPLETE; 2367 m->m_len = 16; 2368 if (len + m->m_len > MHLEN) { 2369 MCLGET(m, M_DONTWAIT); 2370 if ((m->m_flags & M_EXT) == 0) { 2371 m_freem(m); 2372 return IEEE1394_RCODE_COMPLETE; 2373 } 2374 } 2375 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2376 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2377 sc->sc_uidtbl[n].fu_valid != 0x3) { 2378 printf("%s: packet from unknown node: phy id %d\n", 2379 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2380 m_freem(m); 2381 return IEEE1394_RCODE_COMPLETE; 2382 } 2383 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2384 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2385 m->m_flags |= M_BCAST; 2386 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2387 } else { 2388 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2389 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2390 } 2391 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2392 mtod(m, u_int8_t *)[9] = 2393 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2394 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2395 2396 m->m_pkthdr.rcvif = NULL; /* set in child */ 2397 m->m_pkthdr.len = len + m->m_len; 2398 /* 2399 * We may use receive buffer by external mbuf instead of copy here. 2400 * But asynchronous receive buffer must be operate in buffer fill 2401 * mode, so that each receive buffer will shared by multiple mbufs. 2402 * If upper layer doesn't free mbuf soon, e.g. application program 2403 * is suspended, buffer must be reallocated. 2404 * Isochronous buffer must be operate in packet buffer mode, and 2405 * it is easy to map receive buffer to external mbuf. But it is 2406 * used for broadcast/multicast only, and is expected not so 2407 * performance sensitive for now. 2408 * XXX: The performance may be important for multicast case, 2409 * so we should revisit here later. 2410 * -- onoe 2411 */ 2412 n = 0; 2413 iov = pkt->fp_uio.uio_iov; 2414 while (len > 0) { 2415 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2416 iov->iov_len); 2417 m->m_len += iov->iov_len; 2418 len -= iov->iov_len; 2419 iov++; 2420 } 2421 (*handler)(sc->sc_sc1394.sc1394_if, m); 2422 return IEEE1394_RCODE_COMPLETE; 2423 } 2424 2425 static int 2426 fwohci_if_output(struct device *self, struct mbuf *m0, 2427 void (*callback)(struct device *, struct mbuf *)) 2428 { 2429 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2430 struct fwohci_pkt pkt; 2431 u_int8_t *p; 2432 int s, n, error, spd, hdrlen, maxrec; 2433 2434 p = mtod(m0, u_int8_t *); 2435 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2436 spd = IEEE1394_SPD_S100; /*XXX*/ 2437 maxrec = 512; /*XXX*/ 2438 hdrlen = 8; 2439 } else { 2440 n = fwohci_uid_lookup(sc, p); 2441 if (n < 0) { 2442 printf("%s: nodeid unknown:" 2443 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2444 sc->sc_sc1394.sc1394_dev.dv_xname, 2445 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2446 error = EHOSTUNREACH; 2447 goto end; 2448 } 2449 if (n == IEEE1394_BCAST_PHY_ID) { 2450 printf("%s: broadcast with !M_MCAST\n", 2451 sc->sc_sc1394.sc1394_dev.dv_xname); 2452 #ifdef FW_DEBUG 2453 if (fw_dump) { 2454 struct mbuf *m; 2455 printf("packet:"); 2456 for (m = m0; m != NULL; m = m->m_next) { 2457 for (n = 0; n < m->m_len; n++) 2458 printf("%s%02x", (n%32)? 2459 ((n%4)?"":" "):"\n\t", 2460 mtod(m, u_int8_t *)[n]); 2461 printf("$"); 2462 } 2463 printf("\n"); 2464 } 2465 #endif 2466 error = EHOSTUNREACH; 2467 goto end; 2468 } 2469 maxrec = 2 << p[8]; 2470 spd = p[9]; 2471 hdrlen = 0; 2472 } 2473 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2474 #ifdef FW_DEBUG 2475 if (fw_verbose) 2476 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2477 spd, sc->sc_sc1394.sc1394_link_speed); 2478 #endif 2479 spd = sc->sc_sc1394.sc1394_link_speed; 2480 } 2481 if (maxrec > (512 << spd)) { 2482 #ifdef FW_DEBUG 2483 if (fw_verbose) 2484 printf("fwohci_if_output: maxrec (%d) is larger for" 2485 " spd (%d)\n", maxrec, spd); 2486 #endif 2487 maxrec = 512 << spd; 2488 } 2489 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2490 #ifdef FW_DEBUG 2491 if (fw_verbose) 2492 printf("fwohci_if_output: maxrec (%d) is larger than" 2493 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2494 #endif 2495 maxrec >>= 1; 2496 } 2497 if (maxrec < 512) { 2498 #ifdef FW_DEBUG 2499 if (fw_verbose) 2500 printf("fwohci_if_output: maxrec (%d) is smaller" 2501 " than minimum\n", maxrec); 2502 #endif 2503 maxrec = 512; 2504 } 2505 2506 m_adj(m0, 16 - hdrlen); 2507 if (m0->m_pkthdr.len > maxrec) { 2508 #ifdef FW_DEBUG 2509 if (fw_verbose) 2510 printf("fwohci_if_output: packet too big:" 2511 " hdr %d, pktlen %d, maxrec %d\n", 2512 hdrlen, m0->m_pkthdr.len, maxrec); 2513 #endif 2514 error = E2BIG; /*XXX*/ 2515 goto end; 2516 } 2517 2518 memset(&pkt, 0, sizeof(pkt)); 2519 pkt.fp_uio.uio_iov = pkt.fp_iov; 2520 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2521 pkt.fp_uio.uio_rw = UIO_WRITE; 2522 s = splimp(); 2523 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2524 /* construct GASP header */ 2525 p = mtod(m0, u_int8_t *); 2526 p[0] = sc->sc_nodeid >> 8; 2527 p[1] = sc->sc_nodeid & 0xff; 2528 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2529 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2530 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2531 pkt.fp_hlen = 8; 2532 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2533 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2534 OHCI_NodeId_NodeNumber) << 8); 2535 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2536 } else { 2537 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2538 pkt.fp_hlen = 16; 2539 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2540 (spd << 16); 2541 pkt.fp_hdr[1] = 2542 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2543 (p[10] << 8) | p[11]; 2544 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2545 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2546 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2547 } 2548 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2549 pkt.fp_dlen = m0->m_pkthdr.len; 2550 pkt.fp_m = m0; 2551 pkt.fp_callback = callback; 2552 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2553 splx(s); 2554 m0 = pkt.fp_m; 2555 end: 2556 if (m0 != NULL) { 2557 if (callback) 2558 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2559 else 2560 m_freem(m0); 2561 } 2562 return error; 2563 } 2564
Indexes created Fri Sep 26 08:10:20 GMT 2025