fwohci.c revision 1.22
1 /* $NetBSD: fwohci.c,v 1.22 2001/03/15 23:01:33 enami Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/types.h> 51 #include <sys/socket.h> 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/malloc.h> 56 #include <sys/mbuf.h> 57 58 #if __NetBSD_Version__ >= 105010000 59 #include <uvm/uvm_extern.h> 60 #else 61 #include <vm/vm.h> 62 #endif 63 64 #include <machine/bus.h> 65 66 #include <dev/ieee1394/ieee1394reg.h> 67 #include <dev/ieee1394/fwohcireg.h> 68 69 #include <dev/ieee1394/ieee1394var.h> 70 #include <dev/ieee1394/fwohcivar.h> 71 72 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 73 74 #if 0 75 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 76 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 77 #endif 78 static void fwohci_hw_init(struct fwohci_softc *); 79 static void fwohci_power(int, void *); 80 static void fwohci_shutdown(void *); 81 82 static int fwohci_desc_alloc(struct fwohci_softc *); 83 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 84 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 85 86 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 87 int, int); 88 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 89 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 90 91 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 92 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 93 static void fwohci_buf_init(struct fwohci_softc *); 94 static void fwohci_buf_start(struct fwohci_softc *); 95 static void fwohci_buf_stop(struct fwohci_softc *); 96 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 97 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 98 caddr_t *, int); 99 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 100 struct fwohci_pkt *); 101 102 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 103 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 104 static void fwohci_phy_busreset(struct fwohci_softc *); 105 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 106 107 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 108 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 109 void *); 110 111 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 112 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 113 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 114 115 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 116 struct fwohci_pkt *); 117 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 118 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 119 struct fwohci_pkt *); 120 121 static int fwohci_guidrom_init(struct fwohci_softc *); 122 static void fwohci_configrom_init(struct fwohci_softc *); 123 124 static void fwohci_selfid_init(struct fwohci_softc *); 125 static int fwohci_selfid_input(struct fwohci_softc *); 126 127 static void fwohci_csr_init(struct fwohci_softc *); 128 static int fwohci_csr_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 131 static void fwohci_uid_collect(struct fwohci_softc *); 132 static int fwohci_uid_input(struct fwohci_softc *, void *, 133 struct fwohci_pkt *); 134 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 135 136 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 137 void (*)(struct device *, struct mbuf *)); 138 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 139 static int fwohci_if_output(struct device *, struct mbuf *, 140 void (*)(struct device *, struct mbuf *)); 141 142 #ifdef FW_DEBUG 143 int fw_verbose = 1; 144 int fw_dump = 0; 145 #endif 146 147 int 148 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 149 { 150 int i; 151 u_int32_t val; 152 #if 0 153 int error; 154 #endif 155 156 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 157 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 158 159 /* 160 * Wait for reset completion 161 */ 162 for (i = 0; i < OHCI_LOOP; i++) { 163 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 164 if ((val & OHCI_HCControl_SoftReset) == 0) 165 break; 166 } 167 168 /* What dialect of OHCI is this device? 169 */ 170 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 171 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 172 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 173 174 if (fwohci_guidrom_init(sc) != 0) { 175 printf("\n%s: fatal: no global UID ROM\n", 176 sc->sc_sc1394.sc1394_dev.dv_xname); 177 return -1; 178 } 179 180 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 181 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 182 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 183 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 184 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 185 186 /* Get the maximum link speed and receive size 187 */ 188 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 189 sc->sc_sc1394.sc1394_link_speed = 190 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 191 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 192 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 193 } else { 194 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 195 } 196 197 /* MaxRec is encoded as log2(max_rec_octets)-1 198 */ 199 sc->sc_sc1394.sc1394_max_receive = 200 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 201 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 202 203 /* 204 * Count how many isochronous ctx we have. 205 */ 206 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 207 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 208 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 209 for (i = 0; val != 0; val >>= 1) { 210 if (val & 0x1) 211 i++; 212 } 213 sc->sc_isoctx = i; 214 printf(", %d iso_ctx", sc->sc_isoctx); 215 216 printf("\n"); 217 218 #if 0 219 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 220 &sc->sc_configrom_map, 221 (caddr_t *) &sc->sc_configrom, 222 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 223 return error; 224 #endif 225 226 /* 227 * Enable Link Power 228 */ 229 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 230 231 /* 232 * Allocate descriptors 233 */ 234 if (fwohci_desc_alloc(sc)) 235 return -1; 236 237 /* 238 * Allocate DMA Context 239 */ 240 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 241 OHCI_CTX_ASYNC_RX_REQUEST); 242 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 243 OHCI_CTX_ASYNC_RX_RESPONSE); 244 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 245 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 246 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 247 M_DEVBUF, M_WAITOK); 248 for (i = 0; i < sc->sc_isoctx; i++) 249 sc->sc_ctx_ir[i] = NULL; 250 251 /* 252 * Allocate buffer for configuration ROM and SelfID buffer 253 */ 254 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 255 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 256 257 /* 258 * establish hooks for shutdown and suspend/resume 259 */ 260 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 261 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 262 callout_init(&sc->sc_selfid_callout); 263 264 /* 265 * Initialize hardware registers. 266 */ 267 fwohci_hw_init(sc); 268 269 /* 270 * Initiate Bus Reset 271 */ 272 config_defer(&sc->sc_sc1394.sc1394_dev, 273 (void (*)(struct device *))fwohci_phy_busreset); 274 275 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 276 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 277 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 278 "fw", fwohci_print); 279 280 return 0; 281 } 282 283 int 284 fwohci_intr(void *arg) 285 { 286 struct fwohci_softc * const sc = arg; 287 int i; 288 int progress = 0; 289 u_int32_t intmask, iso; 290 291 for (;;) { 292 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 293 if (intmask == 0) 294 return progress; 295 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 296 intmask & ~OHCI_Int_BusReset); 297 #ifdef FW_DEBUG 298 if (fw_verbose > 1) { 299 printf("%s: intmask=0x%08x:", 300 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 301 if (intmask & OHCI_Int_CycleTooLong) 302 printf(" CycleTooLong"); 303 if (intmask & OHCI_Int_UnrecoverableError) 304 printf(" UnrecoverableError"); 305 if (intmask & OHCI_Int_CycleInconsistent) 306 printf(" CycleInconsistent"); 307 if (intmask & OHCI_Int_BusReset) 308 printf(" BusReset"); 309 if (intmask & OHCI_Int_SelfIDComplete) 310 printf(" SelfIDComplete"); 311 if (intmask & OHCI_Int_LockRespErr) 312 printf(" LockRespErr"); 313 if (intmask & OHCI_Int_PostedWriteErr) 314 printf(" PostedWriteErr"); 315 if (intmask & OHCI_Int_ReqTxComplete) 316 printf(" ReqTxComplete(0x%04x)", 317 OHCI_ASYNC_DMA_READ(sc, 318 OHCI_CTX_ASYNC_TX_REQUEST, 319 OHCI_SUBREG_ContextControlClear)); 320 if (intmask & OHCI_Int_RespTxComplete) 321 printf(" RespTxComplete(0x%04x)", 322 OHCI_ASYNC_DMA_READ(sc, 323 OHCI_CTX_ASYNC_TX_RESPONSE, 324 OHCI_SUBREG_ContextControlClear)); 325 if (intmask & OHCI_Int_ARRS) 326 printf(" ARRS(0x%04x)", 327 OHCI_ASYNC_DMA_READ(sc, 328 OHCI_CTX_ASYNC_RX_RESPONSE, 329 OHCI_SUBREG_ContextControlClear)); 330 if (intmask & OHCI_Int_ARRQ) 331 printf(" ARRQ(0x%04x)", 332 OHCI_ASYNC_DMA_READ(sc, 333 OHCI_CTX_ASYNC_RX_REQUEST, 334 OHCI_SUBREG_ContextControlClear)); 335 if (intmask & OHCI_Int_IsochRx) 336 printf(" IsochRx(0x%08x)", 337 OHCI_CSR_READ(sc, 338 OHCI_REG_IsoRecvIntEventClear)); 339 if (intmask & OHCI_Int_IsochTx) 340 printf(" IsochTx(0x%08x)", 341 OHCI_CSR_READ(sc, 342 OHCI_REG_IsoXmitIntEventClear)); 343 if (intmask & OHCI_Int_RQPkt) 344 printf(" RQPkt(0x%04x)", 345 OHCI_ASYNC_DMA_READ(sc, 346 OHCI_CTX_ASYNC_RX_REQUEST, 347 OHCI_SUBREG_ContextControlClear)); 348 if (intmask & OHCI_Int_RSPkt) 349 printf(" RSPkt(0x%04x)", 350 OHCI_ASYNC_DMA_READ(sc, 351 OHCI_CTX_ASYNC_RX_RESPONSE, 352 OHCI_SUBREG_ContextControlClear)); 353 printf("\n"); 354 } 355 #endif /* FW_DEBUG */ 356 if (intmask & OHCI_Int_BusReset) { 357 /* 358 * According to OHCI spec 6.1.1 "busReset", 359 * All asynchronous transmit must be stopped before 360 * clearing BusReset. Moreover, the BusReset 361 * interrupt bit should not be cleared during the 362 * SelfID phase. Thus we turned off interrupt mask 363 * bit of BusReset instead until SelfID completion 364 * or SelfID timeout. 365 */ 366 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 367 OHCI_Int_BusReset); 368 intmask &= OHCI_Int_SelfIDComplete; 369 fwohci_buf_stop(sc); 370 fwohci_buf_init(sc); 371 if (sc->sc_uidtbl != NULL) { 372 free(sc->sc_uidtbl, M_DEVBUF); 373 sc->sc_uidtbl = NULL; 374 } 375 callout_reset(&sc->sc_selfid_callout, 376 OHCI_SELFID_TIMEOUT, 377 (void (*)(void *))fwohci_phy_busreset, sc); 378 sc->sc_nodeid = 0xffff; /* indicate invalid */ 379 sc->sc_rootid = 0; 380 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 381 } 382 383 if (intmask & OHCI_Int_SelfIDComplete) { 384 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 385 OHCI_Int_BusReset); 386 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 387 OHCI_Int_BusReset); 388 callout_stop(&sc->sc_selfid_callout); 389 if (fwohci_selfid_input(sc) == 0) { 390 fwohci_buf_start(sc); 391 fwohci_uid_collect(sc); 392 } 393 } 394 395 if (intmask & OHCI_Int_ReqTxComplete) 396 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 397 if (intmask & OHCI_Int_RespTxComplete) 398 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 399 if (intmask & OHCI_Int_RQPkt) 400 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 401 if (intmask & OHCI_Int_RSPkt) 402 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 403 404 if (intmask & OHCI_Int_IsochTx) { 405 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 406 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 407 } 408 if (intmask & OHCI_Int_IsochRx) { 409 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 410 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 411 for (i = 0; i < sc->sc_isoctx; i++) { 412 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) 413 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 414 } 415 } 416 417 if (!progress) { 418 sc->sc_intrcnt.ev_count++; 419 progress = 1; 420 } 421 } 422 } 423 424 #if 0 425 static int 426 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 427 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 428 { 429 bus_dma_segment_t segs[1]; 430 int error, nsegs, steps; 431 432 steps = 0; 433 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 434 segs, 1, &nsegs, flags); 435 if (error) 436 goto cleanup; 437 438 steps = 1; 439 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 440 kvap, flags); 441 if (error) 442 goto cleanup; 443 444 if (error == 0) 445 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 446 size, flags, mapp); 447 if (error) 448 goto cleanup; 449 if (error == 0) 450 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 451 if (error) 452 goto cleanup; 453 454 cleanup: 455 switch (steps) { 456 case 1: 457 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 458 } 459 460 return error; 461 } 462 #endif 463 464 int 465 fwohci_print(void *aux, const char *pnp) 466 { 467 char *name = aux; 468 469 if (pnp) 470 printf("%s at %s", name, pnp); 471 472 return UNCONF; 473 } 474 475 static void 476 fwohci_hw_init(struct fwohci_softc *sc) 477 { 478 int i; 479 u_int32_t val; 480 481 /* 482 * Software Reset. 483 */ 484 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 485 for (i = 0; i < OHCI_LOOP; i++) { 486 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 487 if ((val & OHCI_HCControl_SoftReset) == 0) 488 break; 489 } 490 491 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 492 493 /* 494 * First, initilize CSRs with undefined value to default settings. 495 */ 496 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 497 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 498 #if 0 499 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 500 #else 501 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 502 #endif 503 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 504 for (i = 0; i < sc->sc_isoctx; i++) { 505 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 506 ~0); 507 } 508 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 509 510 fwohci_configrom_init(sc); 511 fwohci_selfid_init(sc); 512 fwohci_buf_init(sc); 513 fwohci_csr_init(sc); 514 515 /* 516 * Final CSR settings. 517 */ 518 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 519 OHCI_LinkControl_CycleTimerEnable | 520 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 521 522 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 523 524 /* clear receive filter */ 525 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 526 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 527 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 528 529 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 530 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 531 #if BYTE_ORDER == BIG_ENDIAN 532 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 533 OHCI_HCControl_NoByteSwapData); 534 #endif 535 536 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 537 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 538 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 539 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 540 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 541 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 542 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 543 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 544 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 545 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 546 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 547 548 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 549 550 /* 551 * Start the receivers 552 */ 553 fwohci_buf_start(sc); 554 } 555 556 static void 557 fwohci_power(int why, void *arg) 558 { 559 struct fwohci_softc *sc = arg; 560 int s; 561 562 s = splimp(); 563 switch (why) { 564 case PWR_SUSPEND: 565 case PWR_STANDBY: 566 fwohci_shutdown(sc); 567 break; 568 case PWR_RESUME: 569 fwohci_hw_init(sc); 570 fwohci_phy_busreset(sc); 571 break; 572 case PWR_SOFTSUSPEND: 573 case PWR_SOFTSTANDBY: 574 case PWR_SOFTRESUME: 575 break; 576 } 577 splx(s); 578 } 579 580 static void 581 fwohci_shutdown(void *arg) 582 { 583 struct fwohci_softc *sc = arg; 584 u_int32_t val; 585 586 callout_stop(&sc->sc_selfid_callout); 587 /* disable all interrupt */ 588 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 589 fwohci_buf_stop(sc); 590 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 591 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 592 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 593 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 594 fwohci_phy_busreset(sc); 595 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 596 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 597 } 598 599 /* 600 * COMMON FUNCTIONS 601 */ 602 603 /* 604 * read the PHY Register. 605 */ 606 static u_int8_t 607 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 608 { 609 int i; 610 u_int32_t val; 611 612 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 613 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 614 for (i = 0; i < OHCI_LOOP; i++) { 615 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 616 OHCI_PhyControl_RdDone) 617 break; 618 } 619 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 620 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 621 } 622 623 /* 624 * write the PHY Register. 625 */ 626 static void 627 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 628 { 629 int i; 630 631 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 632 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 633 (val << OHCI_PhyControl_WrData_BITPOS)); 634 for (i = 0; i < OHCI_LOOP; i++) { 635 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 636 OHCI_PhyControl_WrReg)) 637 break; 638 } 639 } 640 641 /* 642 * Initiate Bus Reset 643 */ 644 static void 645 fwohci_phy_busreset(struct fwohci_softc *sc) 646 { 647 int s; 648 u_int8_t val; 649 650 s = splimp(); 651 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 652 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 653 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 654 callout_stop(&sc->sc_selfid_callout); 655 val = fwohci_phy_read(sc, 1); 656 val = (val & 0x80) | /* preserve RHB (force root) */ 657 0x40 | /* Initiate Bus Reset */ 658 0x3f; /* default GAP count */ 659 fwohci_phy_write(sc, 1, val); 660 splx(s); 661 } 662 663 /* 664 * PHY Packet 665 */ 666 static void 667 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 668 { 669 u_int32_t val; 670 u_int8_t key, phyid; 671 672 val = pkt->fp_hdr[1]; 673 if (val != ~pkt->fp_hdr[2]) { 674 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 675 OHCI_CTXCTL_EVENT_BUS_RESET) { 676 #ifdef FW_DEBUG 677 if (fw_verbose > 1) 678 printf("fwohci_phy_input: BusReset: 0x%08x\n", 679 pkt->fp_hdr[2]); 680 #endif 681 } else { 682 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 683 sc->sc_sc1394.sc1394_dev.dv_xname, val, 684 pkt->fp_hdr[2]); 685 } 686 return; 687 } 688 key = (val & 0xc0000000) >> 30; 689 phyid = (val & 0x3f000000) >> 24; 690 switch (key) { 691 case 0: 692 #ifdef FW_DEBUG 693 if (fw_verbose > 1) { 694 printf("fwohci_phy_input: PHY Config from %d:", phyid); 695 if (val & 0x00800000) 696 printf(" ForceRoot"); 697 if (val & 0x00400000) 698 printf(" Gap=%x", (val & 0x003f0000) >> 16); 699 printf("\n"); 700 } 701 #endif 702 break; 703 case 1: 704 #ifdef FW_DEBUG 705 if (fw_verbose > 1) 706 printf("fwohci_phy_input: Link-on from %d\n", phyid); 707 #endif 708 break; 709 case 2: 710 #ifdef FW_DEBUG 711 if (fw_verbose > 1) { 712 printf("fwohci_phy_input: SelfID from %d:", phyid); 713 if (val & 0x00800000) { 714 printf(" #%d", (val & 0x00700000) >> 20); 715 } else { 716 if (val & 0x00400000) 717 printf(" LinkActive"); 718 printf(" Gap=%x", (val & 0x003f0000) >> 16); 719 printf(" Spd=S%d", 720 100 << ((val & 0x0000c000) >> 14)); 721 if (val & 0x00000800) 722 printf(" Cont"); 723 if (val & 0x00000002) 724 printf(" InitiateBusReset"); 725 } 726 if (val & 0x00000001) 727 printf(" +"); 728 printf("\n"); 729 } 730 #endif 731 break; 732 default: 733 printf("%s: unknown PHY packet: 0x%08x\n", 734 sc->sc_sc1394.sc1394_dev.dv_xname, val); 735 break; 736 } 737 } 738 739 /* 740 * Descriptor for context DMA. 741 */ 742 static int 743 fwohci_desc_alloc(struct fwohci_softc *sc) 744 { 745 int error, mapsize, dsize; 746 747 /* 748 * allocate descriptor buffer 749 */ 750 751 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 752 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 753 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 754 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 755 mapsize = howmany(sc->sc_descsize, NBBY); 756 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 757 memset(sc->sc_descmap, 0, mapsize); 758 759 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 760 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 761 printf("%s: unable to allocate descriptor buffer, error = %d\n", 762 sc->sc_sc1394.sc1394_dev.dv_xname, error); 763 goto fail_0; 764 } 765 766 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 767 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 768 != 0) { 769 printf("%s: unable to map descriptor buffer, error = %d\n", 770 sc->sc_sc1394.sc1394_dev.dv_xname, error); 771 goto fail_1; 772 } 773 774 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 775 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 776 printf("%s: unable to create descriptor buffer DMA map, " 777 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 778 goto fail_2; 779 } 780 781 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 782 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 783 printf("%s: unable to load descriptor buffer DMA map, " 784 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 785 goto fail_3; 786 } 787 788 return 0; 789 790 fail_3: 791 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 792 fail_2: 793 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 794 fail_1: 795 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 796 fail_0: 797 return error; 798 } 799 800 static struct fwohci_desc * 801 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 802 { 803 int i, n; 804 805 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 806 for (i = 0; ; i++) { 807 if (i == ndesc) { 808 for (i = 0; i < ndesc; i++) 809 setbit(sc->sc_descmap, n + i); 810 return sc->sc_desc + n; 811 } 812 if (isset(sc->sc_descmap, n + i)) 813 break; 814 } 815 } 816 return NULL; 817 } 818 819 static void 820 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 821 { 822 int i, n; 823 824 n = fd - sc->sc_desc; 825 for (i = 0; i < ndesc; i++, n++) { 826 #ifdef DIAGNOSTICS 827 if (isclr(sc->sc_descmap, n)) 828 panic("fwohci_desc_put: duplicated free"); 829 #endif 830 clrbit(sc->sc_descmap, n); 831 } 832 } 833 834 /* 835 * Asyncronous/Isochronous Transmit/Receive Context 836 */ 837 static int 838 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 839 int bufcnt, int ctx) 840 { 841 int i, error; 842 struct fwohci_ctx *fc; 843 struct fwohci_buf *fb; 844 struct fwohci_desc *fd; 845 846 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 847 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 848 LIST_INIT(&fc->fc_handler); 849 TAILQ_INIT(&fc->fc_buf); 850 fc->fc_ctx = ctx; 851 fc->fc_bufcnt = bufcnt; 852 fb = (struct fwohci_buf *)&fc[1]; 853 for (i = 0; i < bufcnt; i++, fb++) { 854 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 855 goto fail; 856 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 857 error = ENOBUFS; 858 goto fail; 859 } 860 fb->fb_desc = fd; 861 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 862 ((caddr_t)fd - (caddr_t)sc->sc_desc); 863 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 864 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 865 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 866 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 867 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 868 } 869 *fcp = fc; 870 return 0; 871 872 fail: 873 while (i-- > 0) 874 fwohci_buf_free(sc, --fb); 875 free(fc, M_DEVBUF); 876 return error; 877 } 878 879 static void 880 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 881 { 882 struct fwohci_buf *fb; 883 struct fwohci_handler *fh; 884 885 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 886 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 887 NULL, NULL); 888 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 889 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 890 fwohci_buf_free(sc, fb); 891 } 892 free(fc, M_DEVBUF); 893 } 894 895 static void 896 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 897 { 898 struct fwohci_buf *fb, *nfb; 899 struct fwohci_desc *fd; 900 struct fwohci_handler *fh; 901 int n; 902 903 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 904 nfb = TAILQ_NEXT(fb, fb_list); 905 fb->fb_off = 0; 906 fd = fb->fb_desc; 907 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 908 fd->fd_rescount = fd->fd_reqcount; 909 } 910 911 n = fc->fc_ctx; 912 fb = TAILQ_FIRST(&fc->fc_buf); 913 if (fc->fc_isoch) { 914 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 915 fb->fb_daddr | 1); 916 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 917 OHCI_CTXCTL_RX_BUFFER_FILL | 918 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 919 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 920 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 921 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 922 OHCI_CTXCTL_RX_ISOCH_HEADER); 923 fh = LIST_FIRST(&fc->fc_handler); 924 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 925 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 926 } else { 927 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 928 fb->fb_daddr | 1); 929 } 930 } 931 932 /* 933 * DMA data buffer 934 */ 935 static int 936 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 937 { 938 int error; 939 940 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 941 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 942 printf("%s: unable to allocate buffer, error = %d\n", 943 sc->sc_sc1394.sc1394_dev.dv_xname, error); 944 goto fail_0; 945 } 946 947 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 948 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 949 printf("%s: unable to map buffer, error = %d\n", 950 sc->sc_sc1394.sc1394_dev.dv_xname, error); 951 goto fail_1; 952 } 953 954 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 955 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 956 printf("%s: unable to create buffer DMA map, " 957 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 958 error); 959 goto fail_2; 960 } 961 962 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 963 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 964 printf("%s: unable to load buffer DMA map, " 965 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 966 error); 967 goto fail_3; 968 } 969 970 return 0; 971 972 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 973 fail_3: 974 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 975 fail_2: 976 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 977 fail_1: 978 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 979 fail_0: 980 return error; 981 } 982 983 static void 984 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 985 { 986 987 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 988 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 989 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 990 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 991 } 992 993 static void 994 fwohci_buf_init(struct fwohci_softc *sc) 995 { 996 int i; 997 998 /* 999 * Initialize for Asynchronous Transmit Queue. 1000 */ 1001 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1002 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1003 1004 /* 1005 * Initialize for Asynchronous Receive Queue. 1006 */ 1007 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1008 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1009 1010 /* 1011 * Initialize for Isochronous Receive Queue. 1012 */ 1013 for (i = 0; i < sc->sc_isoctx; i++) { 1014 if (sc->sc_ctx_ir[i] != NULL) 1015 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1016 } 1017 } 1018 1019 static void 1020 fwohci_buf_start(struct fwohci_softc *sc) 1021 { 1022 int i; 1023 1024 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1025 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1026 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1027 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1028 for (i = 0; i < sc->sc_isoctx; i++) { 1029 if (sc->sc_ctx_ir[i] != NULL && 1030 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1031 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1032 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1033 } 1034 } 1035 } 1036 1037 static void 1038 fwohci_buf_stop(struct fwohci_softc *sc) 1039 { 1040 int i, j; 1041 1042 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1043 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1044 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1045 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1046 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1047 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1048 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1049 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1050 for (i = 0; i < sc->sc_isoctx; i++) { 1051 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1052 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1053 } 1054 1055 /* 1056 * Make sure the transmitter is stopped. 1057 */ 1058 for (j = 0; j < OHCI_LOOP; j++) { 1059 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1060 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1061 continue; 1062 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1063 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1064 continue; 1065 break; 1066 } 1067 } 1068 1069 static void 1070 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1071 { 1072 struct fwohci_buf *fb, *tfb; 1073 1074 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1075 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1076 fb->fb_desc->fd_rescount != 0) 1077 break; 1078 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1079 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1080 fb->fb_off = 0; 1081 fb->fb_desc->fd_branch = 0; 1082 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1083 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1084 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1085 } 1086 } 1087 1088 static int 1089 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1090 int len) 1091 { 1092 struct fwohci_buf *fb; 1093 struct fwohci_desc *fd; 1094 int bufend; 1095 1096 fb = TAILQ_FIRST(&fc->fc_buf); 1097 again: 1098 fd = fb->fb_desc; 1099 #ifdef FW_DEBUG 1100 if (fw_verbose > 1) 1101 printf("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1102 " len %d, avail %d\n", 1103 (long)(fd - sc->sc_desc), fb->fb_off, fd->fd_reqcount, 1104 fd->fd_rescount, len, 1105 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1106 #endif 1107 bufend = fd->fd_reqcount - fd->fd_rescount; 1108 if (fb->fb_off >= bufend) { 1109 if (fc->fc_isoch && fb->fb_off > 0) { 1110 fb->fb_off = fd->fd_reqcount; 1111 fd->fd_rescount = 0; 1112 } 1113 if (fd->fd_rescount == 0) { 1114 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1115 goto again; 1116 } 1117 return 0; 1118 } 1119 if (fb->fb_off + len > bufend) 1120 len = bufend - fb->fb_off; 1121 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1122 BUS_DMASYNC_POSTREAD); 1123 *pp = fb->fb_buf + fb->fb_off; 1124 fb->fb_off += roundup(len, 4); 1125 return len; 1126 } 1127 1128 static int 1129 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1130 struct fwohci_pkt *pkt) 1131 { 1132 caddr_t p; 1133 int len, count, i; 1134 1135 memset(pkt, 0, sizeof(*pkt)); 1136 pkt->fp_uio.uio_iov = pkt->fp_iov; 1137 pkt->fp_uio.uio_rw = UIO_WRITE; 1138 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1139 1140 /* get first quadlet */ 1141 count = 4; 1142 if (fc->fc_isoch) { 1143 /* 1144 * get trailer first, may be bogus data unless status update 1145 * in descriptor is set. 1146 */ 1147 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1148 sizeof(*pkt->fp_trail)); 1149 if (len <= 0) { 1150 #ifdef FW_DEBUG 1151 if (fw_verbose > 1) 1152 printf("fwohci_buf_input: no input for is#%d\n", 1153 fc->fc_ctx); 1154 #endif 1155 return 0; 1156 } 1157 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1158 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1159 } 1160 len = fwohci_buf_pktget(sc, fc, &p, count); 1161 if (len <= 0) { 1162 #ifdef FW_DEBUG 1163 if (fw_verbose > 1) 1164 printf("fwohci_buf_input: no input for %d\n", 1165 fc->fc_ctx); 1166 #endif 1167 return 0; 1168 } 1169 pkt->fp_hdr[0] = *(u_int32_t *)p; 1170 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1171 switch (pkt->fp_tcode) { 1172 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1173 case IEEE1394_TCODE_READ_RESP_QUAD: 1174 pkt->fp_hlen = 12; 1175 pkt->fp_dlen = 4; 1176 break; 1177 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1178 case IEEE1394_TCODE_READ_RESP_BLOCK: 1179 case IEEE1394_TCODE_LOCK_REQ: 1180 case IEEE1394_TCODE_LOCK_RESP: 1181 pkt->fp_hlen = 16; 1182 break; 1183 case IEEE1394_TCODE_STREAM_DATA: 1184 pkt->fp_hlen = 4; 1185 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1186 break; 1187 default: 1188 pkt->fp_hlen = 12; 1189 pkt->fp_dlen = 0; 1190 break; 1191 } 1192 1193 /* get header */ 1194 while (count < pkt->fp_hlen) { 1195 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1196 if (len == 0) { 1197 printf("fwohci_buf_input: malformed input 1: %d\n", 1198 pkt->fp_hlen - count); 1199 return 0; 1200 } 1201 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1202 count += len; 1203 } 1204 if (pkt->fp_hlen == 16) 1205 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1206 #ifdef FW_DEBUG 1207 if (fw_verbose > 1) 1208 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1209 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1210 #endif 1211 1212 /* get data */ 1213 count = 0; 1214 i = 0; 1215 while (count < pkt->fp_dlen) { 1216 len = fwohci_buf_pktget(sc, fc, 1217 (caddr_t *)&pkt->fp_iov[i].iov_base, 1218 pkt->fp_dlen - count); 1219 if (len == 0) { 1220 printf("fwohci_buf_input: malformed input 2: %d\n", 1221 pkt->fp_hlen - count); 1222 return 0; 1223 } 1224 pkt->fp_iov[i++].iov_len = len; 1225 count += len; 1226 } 1227 pkt->fp_uio.uio_iovcnt = i; 1228 pkt->fp_uio.uio_resid = count; 1229 1230 if (!fc->fc_isoch) { 1231 /* get trailer */ 1232 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1233 sizeof(*pkt->fp_trail)); 1234 if (len <= 0) { 1235 printf("fwohci_buf_input: malformed input 3: %d\n", 1236 pkt->fp_hlen - count); 1237 return 0; 1238 } 1239 } 1240 return 1; 1241 } 1242 1243 static int 1244 fwohci_handler_set(struct fwohci_softc *sc, 1245 int tcode, u_int32_t key1, u_int32_t key2, 1246 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1247 void *arg) 1248 { 1249 struct fwohci_ctx *fc; 1250 struct fwohci_handler *fh; 1251 int i, j; 1252 1253 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1254 j = sc->sc_isoctx; 1255 fh = NULL; 1256 for (i = 0; i < sc->sc_isoctx; i++) { 1257 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1258 if (j == sc->sc_isoctx) 1259 j = i; 1260 continue; 1261 } 1262 fh = LIST_FIRST(&fc->fc_handler); 1263 if (fh == NULL) { 1264 j = i; 1265 break; 1266 } 1267 if (fh->fh_tcode == tcode && 1268 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1269 break; 1270 fh = NULL; 1271 } 1272 if (fh == NULL) { 1273 if (handler == NULL) 1274 return 0; 1275 if (j == sc->sc_isoctx) { 1276 #ifdef FW_DEBUG 1277 if (fw_verbose) 1278 printf("fwohci_handler_set: " 1279 "no more free context\n"); 1280 #endif 1281 return ENOMEM; 1282 } 1283 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1284 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1285 fc->fc_isoch = 1; 1286 sc->sc_ctx_ir[j] = fc; 1287 } 1288 } 1289 } else { 1290 switch (tcode) { 1291 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1292 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1293 case IEEE1394_TCODE_READ_REQ_QUAD: 1294 case IEEE1394_TCODE_READ_REQ_BLOCK: 1295 case IEEE1394_TCODE_LOCK_REQ: 1296 fc = sc->sc_ctx_arrq; 1297 break; 1298 case IEEE1394_TCODE_WRITE_RESP: 1299 case IEEE1394_TCODE_READ_RESP_QUAD: 1300 case IEEE1394_TCODE_READ_RESP_BLOCK: 1301 case IEEE1394_TCODE_LOCK_RESP: 1302 fc = sc->sc_ctx_arrs; 1303 break; 1304 default: 1305 return EIO; 1306 } 1307 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1308 fh = LIST_NEXT(fh, fh_list)) { 1309 if (fh->fh_tcode == tcode && 1310 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1311 break; 1312 } 1313 } 1314 if (handler == NULL) { 1315 if (fh != NULL) { 1316 LIST_REMOVE(fh, fh_list); 1317 free(fh, M_DEVBUF); 1318 } 1319 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1320 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1321 fwohci_ctx_free(sc, fc); 1322 } 1323 return 0; 1324 } 1325 if (fh == NULL) { 1326 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 1327 if (fh == NULL) 1328 return ENOMEM; 1329 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1330 } 1331 fh->fh_tcode = tcode; 1332 fh->fh_key1 = key1; 1333 fh->fh_key2 = key2; 1334 fh->fh_handler = handler; 1335 fh->fh_handarg = arg; 1336 #ifdef FW_DEBUG 1337 if (fw_verbose > 1) 1338 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1339 fc->fc_ctx, tcode, key1, key2); 1340 #endif 1341 1342 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1343 fwohci_ctx_init(sc, fc); 1344 #ifdef FW_DEBUG 1345 if (fw_verbose > 1) 1346 printf("fwohci_handler_set: SYNC desc %ld\n", 1347 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - 1348 sc->sc_desc)); 1349 #endif 1350 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1351 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1352 } 1353 return 0; 1354 } 1355 1356 /* 1357 * Asyncronous Receive Requests input frontend. 1358 */ 1359 static void 1360 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1361 { 1362 int rcode; 1363 u_int32_t key1, key2; 1364 struct fwohci_handler *fh; 1365 struct fwohci_pkt pkt, res; 1366 1367 while (fwohci_buf_input(sc, fc, &pkt)) { 1368 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1369 fwohci_phy_input(sc, &pkt); 1370 continue; 1371 } 1372 key1 = pkt.fp_hdr[1] & 0xffff; 1373 key2 = pkt.fp_hdr[2]; 1374 memset(&res, 0, sizeof(res)); 1375 res.fp_uio.uio_rw = UIO_WRITE; 1376 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1377 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1378 fh = LIST_NEXT(fh, fh_list)) { 1379 if (pkt.fp_tcode == fh->fh_tcode && 1380 key1 == fh->fh_key1 && 1381 key2 == fh->fh_key2) { 1382 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1383 &pkt); 1384 break; 1385 } 1386 } 1387 if (fh == NULL) { 1388 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1389 #ifdef FW_DEBUG 1390 if (fw_verbose > 1) 1391 printf("fwohci_arrq_input: no listener:" 1392 " tcode 0x%x, addr=0x%04x %08x\n", 1393 pkt.fp_tcode, key1, key2); 1394 #endif 1395 } 1396 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1397 OHCI_CTXCTL_EVENT_ACK_PENDING) 1398 continue; 1399 if (rcode != -1) 1400 fwohci_atrs_output(sc, rcode, &pkt, &res); 1401 } 1402 fwohci_buf_next(sc, fc); 1403 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1404 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1405 } 1406 1407 /* 1408 * Asynchronous Receive Response input frontend. 1409 */ 1410 static void 1411 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1412 { 1413 struct fwohci_pkt pkt; 1414 struct fwohci_handler *fh; 1415 u_int16_t srcid; 1416 int rcode, tlabel; 1417 1418 while (fwohci_buf_input(sc, fc, &pkt)) { 1419 srcid = pkt.fp_hdr[1] >> 16; 1420 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1421 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1422 #ifdef FW_DEBUG 1423 if (fw_verbose > 1) 1424 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1425 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1426 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1427 pkt.fp_dlen); 1428 #endif 1429 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1430 fh = LIST_NEXT(fh, fh_list)) { 1431 if (pkt.fp_tcode == fh->fh_tcode && 1432 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1433 tlabel == fh->fh_key2) { 1434 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1435 LIST_REMOVE(fh, fh_list); 1436 free(fh, M_DEVBUF); 1437 break; 1438 } 1439 } 1440 #ifdef FW_DEBUG 1441 if (fw_verbose > 1) 1442 if (fh == NULL) 1443 printf("fwohci_arrs_input: no lister\n"); 1444 #endif 1445 } 1446 fwohci_buf_next(sc, fc); 1447 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1448 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1449 } 1450 1451 /* 1452 * Isochronous Receive input frontend. 1453 */ 1454 static void 1455 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1456 { 1457 int rcode, chan, tag; 1458 struct iovec *iov; 1459 struct fwohci_handler *fh; 1460 struct fwohci_pkt pkt; 1461 1462 while (fwohci_buf_input(sc, fc, &pkt)) { 1463 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1464 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1465 #ifdef FW_DEBUG 1466 if (fw_verbose > 1) 1467 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1468 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1469 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1470 #endif 1471 if (tag == IEEE1394_TAG_GASP) { 1472 /* 1473 * The pkt with tag=3 is GASP format. 1474 * Move GASP header to header part. 1475 */ 1476 if (pkt.fp_dlen < 8) 1477 continue; 1478 iov = pkt.fp_iov; 1479 /* assuming pkt per buffer mode */ 1480 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1481 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1482 iov->iov_base = (caddr_t)iov->iov_base + 8; 1483 iov->iov_len -= 8; 1484 pkt.fp_hlen += 8; 1485 pkt.fp_dlen -= 8; 1486 } 1487 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1488 fh = LIST_NEXT(fh, fh_list)) { 1489 if (pkt.fp_tcode == fh->fh_tcode && 1490 chan == fh->fh_key1 && tag == fh->fh_key2) { 1491 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1492 &pkt); 1493 break; 1494 } 1495 } 1496 #ifdef FW_DEBUG 1497 if (fw_verbose > 1) { 1498 if (fh == NULL) 1499 printf("fwohci_ir_input: no handler\n"); 1500 else 1501 printf("fwohci_ir_input: rcode %d\n", rcode); 1502 } 1503 #endif 1504 } 1505 fwohci_buf_next(sc, fc); 1506 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1507 OHCI_CTXCTL_WAKE); 1508 } 1509 1510 /* 1511 * Asynchronous Transmit common routine. 1512 */ 1513 static int 1514 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1515 struct fwohci_pkt *pkt) 1516 { 1517 struct fwohci_buf *fb; 1518 struct fwohci_desc *fd; 1519 struct mbuf *m, *m0; 1520 int i, ndesc, error, off, len; 1521 u_int32_t val; 1522 1523 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) { 1524 /* We can't send anything during selfid duration */ 1525 return EAGAIN; 1526 } 1527 #ifdef FW_DEBUG 1528 if (fw_verbose > 1) { 1529 struct iovec *iov; 1530 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1531 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1532 if (fw_dump) { 1533 for (i = 0; i < pkt->fp_hlen/4; i++) 1534 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1535 printf("$"); 1536 for (ndesc = 0, iov = pkt->fp_iov; 1537 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1538 for (i = 0; i < iov->iov_len; i++) 1539 printf("%s%02x", 1540 (i%32)?((i%4)?"":" "):"\n\t", 1541 ((u_int8_t *)iov->iov_base)[i]); 1542 printf("$"); 1543 } 1544 } 1545 printf("\n"); 1546 } 1547 #endif 1548 1549 if ((m = pkt->fp_m) != NULL) { 1550 for (ndesc = 2; m != NULL; m = m->m_next) 1551 ndesc++; 1552 if (ndesc > OHCI_DESC_MAX) { 1553 m0 = NULL; 1554 ndesc = 2; 1555 for (off = 0; off < pkt->fp_dlen; off += len) { 1556 if (m0 == NULL) { 1557 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1558 if (m0 != NULL) 1559 M_COPY_PKTHDR(m0, pkt->fp_m); 1560 m = m0; 1561 } else { 1562 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1563 m = m->m_next; 1564 } 1565 if (m != NULL) 1566 MCLGET(m, M_DONTWAIT); 1567 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1568 m_freem(m0); 1569 return ENOMEM; 1570 } 1571 len = pkt->fp_dlen - off; 1572 if (len > m->m_ext.ext_size) 1573 len = m->m_ext.ext_size; 1574 m_copydata(pkt->fp_m, off, len, 1575 mtod(m, caddr_t)); 1576 m->m_len = len; 1577 ndesc++; 1578 } 1579 m_freem(pkt->fp_m); 1580 pkt->fp_m = m0; 1581 } 1582 } else 1583 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1584 1585 if (ndesc > OHCI_DESC_MAX) 1586 return ENOBUFS; 1587 1588 if (fc->fc_bufcnt > 50) /*XXX*/ 1589 return ENOBUFS; 1590 if ((fb = malloc(sizeof(*fb), M_DEVBUF, M_NOWAIT)) == NULL) 1591 return ENOBUFS; 1592 fb->fb_nseg = ndesc; 1593 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1594 if (fb->fb_desc == NULL) { 1595 free(fb, M_DEVBUF); 1596 return ENOBUFS; 1597 } 1598 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1599 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1600 fb->fb_m = pkt->fp_m; 1601 fb->fb_callback = pkt->fp_callback; 1602 1603 if (ndesc > 2) { 1604 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1605 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &fb->fb_dmamap)) != 0) { 1606 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1607 free(fb, M_DEVBUF); 1608 return error; 1609 } 1610 1611 if (pkt->fp_m != NULL) 1612 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1613 pkt->fp_m, BUS_DMA_NOWAIT); 1614 else 1615 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1616 &pkt->fp_uio, BUS_DMA_NOWAIT); 1617 if (error != 0) { 1618 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1619 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1620 free(fb, M_DEVBUF); 1621 return error; 1622 } 1623 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1624 BUS_DMASYNC_PREWRITE); 1625 } 1626 1627 fd = fb->fb_desc; 1628 fd->fd_flags = OHCI_DESC_IMMED; 1629 fd->fd_reqcount = pkt->fp_hlen; 1630 fd->fd_data = 0; 1631 fd->fd_branch = 0; 1632 fd->fd_status = 0; 1633 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1634 i = 3; /* XXX: 3 sec */ 1635 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1636 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1637 ((((val >> 25) + i) & 0x7) << 13); 1638 } else 1639 fd->fd_timestamp = 0; 1640 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1641 for (i = 0; i < ndesc - 2; i++) { 1642 fd = fb->fb_desc + 2 + i; 1643 fd->fd_flags = 0; 1644 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1645 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1646 fd->fd_branch = 0; 1647 fd->fd_status = 0; 1648 fd->fd_timestamp = 0; 1649 } 1650 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1651 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1652 1653 #ifdef FW_DEBUG 1654 if (fw_verbose > 1) { 1655 printf("fwohci_at_output: desc %ld", 1656 (long)(fb->fb_desc - sc->sc_desc)); 1657 for (i = 0; i < ndesc * 4; i++) 1658 printf("%s%08x", i&7?" ":"\n\t", 1659 ((u_int32_t *)fb->fb_desc)[i]); 1660 printf("\n"); 1661 } 1662 #endif 1663 1664 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1665 OHCI_SUBREG_ContextControlClear); 1666 1667 if (val & OHCI_CTXCTL_RUN) { 1668 if (fc->fc_branch == NULL) { 1669 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1670 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1671 goto run; 1672 } 1673 *fc->fc_branch = fb->fb_daddr | ndesc; 1674 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1675 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1676 } else { 1677 run: 1678 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1679 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1680 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1681 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1682 } 1683 fc->fc_branch = &fd->fd_branch; 1684 1685 fc->fc_bufcnt++; 1686 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1687 pkt->fp_m = NULL; 1688 return 0; 1689 } 1690 1691 static void 1692 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1693 { 1694 struct fwohci_buf *fb; 1695 struct fwohci_desc *fd; 1696 int i; 1697 1698 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1699 fd = fb->fb_desc; 1700 #ifdef FW_DEBUG 1701 if (fw_verbose > 1) { 1702 printf("fwohci_at_done: %sdesc %ld (%d)", 1703 force ? "force " : "", 1704 (long)(fd - sc->sc_desc), fb->fb_nseg); 1705 for (i = 0; i < fb->fb_nseg * 4; i++) 1706 printf("%s%08x", i&7?" ":"\n ", 1707 ((u_int32_t *)fd)[i]); 1708 printf("\n"); 1709 } 1710 #endif 1711 if (fb->fb_nseg > 2) 1712 fd += fb->fb_nseg - 1; 1713 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1714 break; 1715 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1716 if (fc->fc_branch == &fd->fd_branch) { 1717 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1718 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1719 fc->fc_branch = NULL; 1720 for (i = 0; i < OHCI_LOOP; i++) { 1721 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1722 OHCI_SUBREG_ContextControlClear) & 1723 OHCI_CTXCTL_ACTIVE)) 1724 break; 1725 } 1726 } 1727 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1728 if (fb->fb_nseg > 2) 1729 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1730 fc->fc_bufcnt--; 1731 if (fb->fb_callback != NULL) { 1732 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1733 fb->fb_callback = NULL; 1734 } else if (fb->fb_m != NULL) 1735 m_freem(fb->fb_m); 1736 free(fb, M_DEVBUF); 1737 } 1738 } 1739 1740 /* 1741 * Asynchronous Transmit Reponse -- in response of request packet. 1742 */ 1743 static void 1744 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1745 struct fwohci_pkt *res) 1746 { 1747 1748 if (((*req->fp_trail & 0x001f0000) >> 16) != 1749 OHCI_CTXCTL_EVENT_ACK_PENDING) 1750 return; 1751 1752 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1753 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1754 switch (req->fp_tcode) { 1755 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1756 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1757 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1758 res->fp_hlen = 12; 1759 break; 1760 case IEEE1394_TCODE_READ_REQ_QUAD: 1761 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1762 res->fp_hlen = 16; 1763 res->fp_dlen = 0; 1764 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1765 res->fp_hdr[3] = 1766 *(u_int32_t *)res->fp_iov[0].iov_base; 1767 res->fp_uio.uio_iovcnt = 0; 1768 break; 1769 case IEEE1394_TCODE_READ_REQ_BLOCK: 1770 case IEEE1394_TCODE_LOCK_REQ: 1771 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1772 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1773 else 1774 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1775 res->fp_hlen = 16; 1776 res->fp_dlen = res->fp_uio.uio_resid; 1777 res->fp_hdr[3] = res->fp_dlen << 16; 1778 break; 1779 } 1780 res->fp_hdr[0] |= (res->fp_tcode << 4); 1781 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1782 } 1783 1784 /* 1785 * APPLICATION LAYER SERVICES 1786 */ 1787 1788 /* 1789 * Retrieve Global UID from GUID ROM 1790 */ 1791 static int 1792 fwohci_guidrom_init(struct fwohci_softc *sc) 1793 { 1794 int i, n, off; 1795 u_int32_t val1, val2; 1796 1797 /* Extract the Global UID 1798 */ 1799 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1800 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1801 1802 if (val1 != 0 || val2 != 0) { 1803 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1804 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1805 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1806 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1807 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1808 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1809 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1810 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1811 } else { 1812 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1813 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1814 return -1; 1815 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1816 for (i = 0; i < OHCI_LOOP; i++) { 1817 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1818 if (!(val1 & OHCI_Guid_AddrReset)) 1819 break; 1820 } 1821 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1822 val2 = 0; 1823 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1824 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1825 OHCI_Guid_RdStart); 1826 for (i = 0; i < OHCI_LOOP; i++) { 1827 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1828 if (!(val1 & OHCI_Guid_RdStart)) 1829 break; 1830 } 1831 if (n < off) 1832 continue; 1833 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1834 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1835 val2 |= val1; 1836 } 1837 if (val2 == 0) 1838 return -1; 1839 } 1840 return 0; 1841 } 1842 1843 /* 1844 * Initialization for Configuration ROM (no DMA context) 1845 */ 1846 1847 #define CFR_MAXUNIT 20 1848 1849 struct configromctx { 1850 u_int32_t *ptr; 1851 int curunit; 1852 struct { 1853 u_int32_t *start; 1854 int length; 1855 u_int32_t *refer; 1856 int refunit; 1857 } unit[CFR_MAXUNIT]; 1858 }; 1859 1860 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1861 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1862 1863 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1864 1865 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1866 1867 #define CFR_PUT_CRC(cfr, n) \ 1868 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1869 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1870 1871 #define CFR_START_UNIT(cfr, n) \ 1872 do { \ 1873 if ((cfr)->unit[n].refer != NULL) { \ 1874 *(cfr)->unit[n].refer |= \ 1875 (cfr)->ptr - (cfr)->unit[n].refer; \ 1876 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1877 } \ 1878 (cfr)->curunit = (n); \ 1879 (cfr)->unit[n].start = (cfr)->ptr++; \ 1880 } while (0 /* CONSTCOND */) 1881 1882 #define CFR_PUT_REFER(cfr, key, n) \ 1883 do { \ 1884 (cfr)->unit[n].refer = (cfr)->ptr; \ 1885 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1886 *(cfr)->ptr++ = (key) << 24; \ 1887 } while (0 /* CONSTCOND */) 1888 1889 #define CFR_END_UNIT(cfr) \ 1890 do { \ 1891 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1892 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1893 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1894 } while (0 /* CONSTCOND */) 1895 1896 static u_int16_t 1897 fwohci_crc16(u_int32_t *ptr, int len) 1898 { 1899 int shift; 1900 u_int32_t crc, sum, data; 1901 1902 crc = 0; 1903 while (len-- > 0) { 1904 data = *ptr++; 1905 for (shift = 28; shift >= 0; shift -= 4) { 1906 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1907 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1908 } 1909 crc &= 0xffff; 1910 } 1911 return crc; 1912 } 1913 1914 static void 1915 fwohci_configrom_init(struct fwohci_softc *sc) 1916 { 1917 int i; 1918 struct fwohci_buf *fb; 1919 u_int32_t *hdr; 1920 struct configromctx cfr; 1921 1922 fb = &sc->sc_buf_cnfrom; 1923 memset(&cfr, 0, sizeof(cfr)); 1924 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1925 1926 /* headers */ 1927 CFR_START_UNIT(&cfr, 0); 1928 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1929 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1930 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1931 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1932 CFR_END_UNIT(&cfr); 1933 /* copy info_length from crc_length */ 1934 *hdr |= (*hdr & 0x00ff0000) << 8; 1935 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1936 1937 /* root directory */ 1938 CFR_START_UNIT(&cfr, 1); 1939 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1940 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1941 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1942 /* spt,64,fix,lst,drq */ 1943 #ifdef INET 1944 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1945 #endif /* INET */ 1946 #ifdef INET6 1947 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1948 #endif /* INET6 */ 1949 CFR_END_UNIT(&cfr); 1950 1951 CFR_START_UNIT(&cfr, 2); 1952 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1953 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1954 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1955 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1956 CFR_END_UNIT(&cfr); 1957 1958 #ifdef INET 1959 /* IPv4 unit directory */ 1960 CFR_START_UNIT(&cfr, 3); 1961 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1962 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1963 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1964 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1965 CFR_END_UNIT(&cfr); 1966 1967 CFR_START_UNIT(&cfr, 6); 1968 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1969 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1970 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1971 CFR_END_UNIT(&cfr); 1972 1973 CFR_START_UNIT(&cfr, 7); 1974 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1975 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1976 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1977 CFR_END_UNIT(&cfr); 1978 #endif /* INET */ 1979 1980 #ifdef INET6 1981 /* IPv6 unit directory */ 1982 CFR_START_UNIT(&cfr, 4); 1983 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1984 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1985 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 1986 /* XXX: TBA by IANA */ 1987 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1988 CFR_END_UNIT(&cfr); 1989 1990 CFR_START_UNIT(&cfr, 8); 1991 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1992 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1993 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1994 CFR_END_UNIT(&cfr); 1995 1996 CFR_START_UNIT(&cfr, 9); 1997 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1998 CFR_PUT_DATA1(&cfr, 0); 1999 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2000 CFR_END_UNIT(&cfr); 2001 #endif /* INET6 */ 2002 2003 #ifdef FW_DEBUG 2004 if (fw_dump) { 2005 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 2006 for (i = 0; i < cfr.ptr - hdr; i++) 2007 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 2008 printf("\n"); 2009 } 2010 #endif /* FW_DEBUG */ 2011 2012 /* 2013 * Make network byte order for DMA 2014 */ 2015 for (i = 0; i < cfr.ptr - hdr; i++) 2016 HTONL(hdr[i]); 2017 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2018 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2019 2020 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2021 fb->fb_dmamap->dm_segs[0].ds_addr); 2022 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 2023 } 2024 2025 /* 2026 * SelfID buffer (no DMA context) 2027 */ 2028 static void 2029 fwohci_selfid_init(struct fwohci_softc *sc) 2030 { 2031 struct fwohci_buf *fb; 2032 2033 fb = &sc->sc_buf_selfid; 2034 #ifdef DIAGNOSTICS 2035 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2036 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2037 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2038 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2039 #endif 2040 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2041 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2042 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2043 2044 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2045 fb->fb_dmamap->dm_segs[0].ds_addr); 2046 } 2047 2048 static int 2049 fwohci_selfid_input(struct fwohci_softc *sc) 2050 { 2051 int i; 2052 u_int32_t count, val, gen; 2053 u_int32_t *buf; 2054 2055 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2056 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2057 again: 2058 if (val & OHCI_SelfID_Error) { 2059 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2060 return -1; 2061 } 2062 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2063 2064 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2065 0, count << 2, BUS_DMASYNC_POSTREAD); 2066 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2067 2068 #ifdef FW_DEBUG 2069 if (fw_verbose > 1) { 2070 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2071 val); 2072 for (i = 0; i < count; i++) 2073 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2074 printf("\n"); 2075 } 2076 #endif /* FW_DEBUG */ 2077 2078 for (i = 1; i < count; i += 2) { 2079 if (buf[i] != ~buf[i + 1]) 2080 break; 2081 if (buf[i] & 0x00000001) 2082 continue; /* more pkt */ 2083 if (buf[i] & 0x00800000) 2084 continue; /* external id */ 2085 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2086 if ((buf[i] & 0x00400800) == 0x00400800) 2087 sc->sc_irmid = sc->sc_rootid; 2088 } 2089 2090 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2091 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2092 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2093 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2094 goto again; 2095 #ifdef FW_DEBUG 2096 if (fw_verbose) 2097 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2098 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2099 OHCI_BITVAL(val, OHCI_SelfID_Gen)); 2100 #endif 2101 return -1; 2102 } 2103 if (i != count) { 2104 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2105 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2106 #if 1 2107 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2108 /* 2109 * XXX: CXD3222 sometimes fails to DMA 2110 * selfid packet?? 2111 */ 2112 sc->sc_rootid = (count - 1) / 2 - 1; 2113 sc->sc_irmid = sc->sc_rootid; 2114 } else 2115 #endif 2116 return -1; 2117 } 2118 2119 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2120 if ((val & OHCI_NodeId_IDValid) == 0) { 2121 sc->sc_nodeid = 0xffff; /* invalid */ 2122 printf("%s: nodeid is invalid\n", 2123 sc->sc_sc1394.sc1394_dev.dv_xname); 2124 return -1; 2125 } 2126 sc->sc_nodeid = val & 0xffff; 2127 2128 #ifdef FW_DEBUG 2129 if (fw_verbose) 2130 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2131 sc->sc_sc1394.sc1394_dev.dv_xname, 2132 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2133 sc->sc_rootid, sc->sc_irmid); 2134 #endif 2135 2136 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2137 return -1; 2138 2139 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2140 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2141 OHCI_LinkControl_CycleMaster); 2142 else 2143 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2144 OHCI_LinkControl_CycleMaster); 2145 return 0; 2146 } 2147 2148 /* 2149 * some CSRs are handled by driver. 2150 */ 2151 static void 2152 fwohci_csr_init(struct fwohci_softc *sc) 2153 { 2154 int i; 2155 static u_int32_t csr[] = { 2156 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2157 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2158 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2159 CSR_SB_BROADCAST_CHANNEL 2160 }; 2161 2162 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2163 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2164 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2165 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2166 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2167 } 2168 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2169 } 2170 2171 static int 2172 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2173 { 2174 struct fwohci_pkt res; 2175 u_int32_t reg; 2176 2177 /* 2178 * XXX need to do special functionality other than just r/w... 2179 */ 2180 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2181 2182 if ((reg & 0x03) != 0) { 2183 /* alignment error */ 2184 return IEEE1394_RCODE_ADDRESS_ERROR; 2185 } 2186 #ifdef FW_DEBUG 2187 if (fw_verbose > 1) 2188 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2189 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2190 #endif 2191 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2192 #ifdef FW_DEBUG 2193 if (fw_verbose > 1) 2194 printf(" -> 0x%08x\n", 2195 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2196 #endif 2197 *(u_int32_t *)&sc->sc_csr[reg] = 2198 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2199 } else { 2200 #ifdef FW_DEBUG 2201 if (fw_verbose > 1) 2202 printf("\n"); 2203 #endif 2204 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2205 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2206 res.fp_iov[0].iov_len = 4; 2207 res.fp_uio.uio_resid = 4; 2208 res.fp_uio.uio_iovcnt = 1; 2209 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2210 return -1; 2211 } 2212 return IEEE1394_RCODE_COMPLETE; 2213 } 2214 2215 /* 2216 * Mapping between nodeid and unique ID (EUI-64). 2217 */ 2218 static void 2219 fwohci_uid_collect(struct fwohci_softc *sc) 2220 { 2221 int i; 2222 struct fwohci_uidtbl *fu; 2223 struct fwohci_pkt pkt; 2224 2225 if (sc->sc_uidtbl != NULL) 2226 free(sc->sc_uidtbl, M_DEVBUF); 2227 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 2228 M_DEVBUF, M_NOWAIT); 2229 if (sc->sc_uidtbl == NULL) 2230 return; 2231 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2232 2233 memset(&pkt, 0, sizeof(pkt)); 2234 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2235 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2236 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2237 fu->fu_valid = 3; 2238 continue; 2239 } 2240 fu->fu_valid = 0; 2241 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2242 pkt.fp_hlen = 12; 2243 pkt.fp_dlen = 0; 2244 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2245 (pkt.fp_tcode << 4); 2246 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2247 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2248 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2249 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2250 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2251 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2252 2253 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2254 (pkt.fp_tcode << 4); 2255 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2256 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2257 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2258 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2259 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2260 } 2261 } 2262 2263 static int 2264 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2265 { 2266 int n, rcode; 2267 struct fwohci_uidtbl *fu; 2268 2269 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2270 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2271 if (rcode != IEEE1394_RCODE_COMPLETE || 2272 sc->sc_uidtbl == NULL || 2273 n > sc->sc_rootid) 2274 return 0; 2275 fu = &sc->sc_uidtbl[n]; 2276 if (arg == 0) { 2277 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2278 fu->fu_valid |= 0x1; 2279 } else { 2280 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2281 fu->fu_valid |= 0x2; 2282 } 2283 #ifdef FW_DEBUG 2284 if (fw_verbose && fu->fu_valid == 0x3) 2285 printf("fwohci_uid_input: " 2286 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2287 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2288 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2289 #endif 2290 return 0; 2291 } 2292 2293 static int 2294 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2295 { 2296 struct fwohci_uidtbl *fu; 2297 int n; 2298 static const u_int8_t bcast[] = 2299 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2300 2301 fu = sc->sc_uidtbl; 2302 if (fu == NULL) { 2303 notfound: 2304 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2305 return IEEE1394_BCAST_PHY_ID; 2306 fwohci_uid_collect(sc); /* try to get */ 2307 return -1; 2308 } 2309 for (n = 0; ; n++, fu++) { 2310 if (n > sc->sc_rootid) 2311 goto notfound; 2312 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2313 break; 2314 } 2315 return n; 2316 } 2317 2318 /* 2319 * functions to support network interface 2320 */ 2321 static int 2322 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2323 void (*handler)(struct device *, struct mbuf *)) 2324 { 2325 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2326 int s; 2327 2328 s = splimp(); 2329 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2330 fwohci_if_input, handler); 2331 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2332 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2333 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2334 splx(s); 2335 return 0; 2336 } 2337 2338 static int 2339 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2340 { 2341 int n, len; 2342 struct mbuf *m; 2343 struct iovec *iov; 2344 void (*handler)(struct device *, struct mbuf *) = arg; 2345 2346 #ifdef FW_DEBUG 2347 if (fw_verbose > 1) { 2348 int i; 2349 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2350 pkt->fp_tcode, pkt->fp_dlen); 2351 if (fw_dump) { 2352 for (i = 0; i < pkt->fp_hlen/4; i++) 2353 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2354 printf("$"); 2355 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2356 iov = &pkt->fp_iov[n]; 2357 for (i = 0; i < iov->iov_len; i++) 2358 printf("%s%02x", 2359 (i%32)?((i%4)?"":" "):"\n\t", 2360 ((u_int8_t *)iov->iov_base)[i]); 2361 printf("$"); 2362 } 2363 } 2364 printf("\n"); 2365 } 2366 #endif /* FW_DEBUG */ 2367 len = pkt->fp_dlen; 2368 MGETHDR(m, M_DONTWAIT, MT_DATA); 2369 if (m == NULL) 2370 return IEEE1394_RCODE_COMPLETE; 2371 m->m_len = 16; 2372 if (len + m->m_len > MHLEN) { 2373 MCLGET(m, M_DONTWAIT); 2374 if ((m->m_flags & M_EXT) == 0) { 2375 m_freem(m); 2376 return IEEE1394_RCODE_COMPLETE; 2377 } 2378 } 2379 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2380 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2381 sc->sc_uidtbl[n].fu_valid != 0x3) { 2382 printf("%s: packet from unknown node: phy id %d\n", 2383 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2384 m_freem(m); 2385 return IEEE1394_RCODE_COMPLETE; 2386 } 2387 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2388 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2389 m->m_flags |= M_BCAST; 2390 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2391 } else { 2392 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2393 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2394 } 2395 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2396 mtod(m, u_int8_t *)[9] = 2397 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2398 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2399 2400 m->m_pkthdr.rcvif = NULL; /* set in child */ 2401 m->m_pkthdr.len = len + m->m_len; 2402 /* 2403 * We may use receive buffer by external mbuf instead of copy here. 2404 * But asynchronous receive buffer must be operate in buffer fill 2405 * mode, so that each receive buffer will shared by multiple mbufs. 2406 * If upper layer doesn't free mbuf soon, e.g. application program 2407 * is suspended, buffer must be reallocated. 2408 * Isochronous buffer must be operate in packet buffer mode, and 2409 * it is easy to map receive buffer to external mbuf. But it is 2410 * used for broadcast/multicast only, and is expected not so 2411 * performance sensitive for now. 2412 * XXX: The performance may be important for multicast case, 2413 * so we should revisit here later. 2414 * -- onoe 2415 */ 2416 n = 0; 2417 iov = pkt->fp_uio.uio_iov; 2418 while (len > 0) { 2419 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2420 iov->iov_len); 2421 m->m_len += iov->iov_len; 2422 len -= iov->iov_len; 2423 iov++; 2424 } 2425 (*handler)(sc->sc_sc1394.sc1394_if, m); 2426 return IEEE1394_RCODE_COMPLETE; 2427 } 2428 2429 static int 2430 fwohci_if_output(struct device *self, struct mbuf *m0, 2431 void (*callback)(struct device *, struct mbuf *)) 2432 { 2433 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2434 struct fwohci_pkt pkt; 2435 u_int8_t *p; 2436 int s, n, error, spd, hdrlen, maxrec; 2437 2438 p = mtod(m0, u_int8_t *); 2439 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2440 spd = IEEE1394_SPD_S100; /*XXX*/ 2441 maxrec = 512; /*XXX*/ 2442 hdrlen = 8; 2443 } else { 2444 n = fwohci_uid_lookup(sc, p); 2445 if (n < 0) { 2446 printf("%s: nodeid unknown:" 2447 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2448 sc->sc_sc1394.sc1394_dev.dv_xname, 2449 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2450 error = EHOSTUNREACH; 2451 goto end; 2452 } 2453 if (n == IEEE1394_BCAST_PHY_ID) { 2454 printf("%s: broadcast with !M_MCAST\n", 2455 sc->sc_sc1394.sc1394_dev.dv_xname); 2456 #ifdef FW_DEBUG 2457 if (fw_dump) { 2458 struct mbuf *m; 2459 printf("packet:"); 2460 for (m = m0; m != NULL; m = m->m_next) { 2461 for (n = 0; n < m->m_len; n++) 2462 printf("%s%02x", (n%32)? 2463 ((n%4)?"":" "):"\n\t", 2464 mtod(m, u_int8_t *)[n]); 2465 printf("$"); 2466 } 2467 printf("\n"); 2468 } 2469 #endif 2470 error = EHOSTUNREACH; 2471 goto end; 2472 } 2473 maxrec = 2 << p[8]; 2474 spd = p[9]; 2475 hdrlen = 0; 2476 } 2477 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2478 #ifdef FW_DEBUG 2479 if (fw_verbose) 2480 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2481 spd, sc->sc_sc1394.sc1394_link_speed); 2482 #endif 2483 spd = sc->sc_sc1394.sc1394_link_speed; 2484 } 2485 if (maxrec > (512 << spd)) { 2486 #ifdef FW_DEBUG 2487 if (fw_verbose) 2488 printf("fwohci_if_output: maxrec (%d) is larger for" 2489 " spd (%d)\n", maxrec, spd); 2490 #endif 2491 maxrec = 512 << spd; 2492 } 2493 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2494 #ifdef FW_DEBUG 2495 if (fw_verbose) 2496 printf("fwohci_if_output: maxrec (%d) is larger than" 2497 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2498 #endif 2499 maxrec >>= 1; 2500 } 2501 if (maxrec < 512) { 2502 #ifdef FW_DEBUG 2503 if (fw_verbose) 2504 printf("fwohci_if_output: maxrec (%d) is smaller" 2505 " than minimum\n", maxrec); 2506 #endif 2507 maxrec = 512; 2508 } 2509 2510 m_adj(m0, 16 - hdrlen); 2511 if (m0->m_pkthdr.len > maxrec) { 2512 #ifdef FW_DEBUG 2513 if (fw_verbose) 2514 printf("fwohci_if_output: packet too big:" 2515 " hdr %d, pktlen %d, maxrec %d\n", 2516 hdrlen, m0->m_pkthdr.len, maxrec); 2517 #endif 2518 error = E2BIG; /*XXX*/ 2519 goto end; 2520 } 2521 2522 memset(&pkt, 0, sizeof(pkt)); 2523 pkt.fp_uio.uio_iov = pkt.fp_iov; 2524 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2525 pkt.fp_uio.uio_rw = UIO_WRITE; 2526 s = splimp(); 2527 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2528 /* construct GASP header */ 2529 p = mtod(m0, u_int8_t *); 2530 p[0] = sc->sc_nodeid >> 8; 2531 p[1] = sc->sc_nodeid & 0xff; 2532 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2533 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2534 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2535 pkt.fp_hlen = 8; 2536 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2537 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2538 OHCI_NodeId_NodeNumber) << 8); 2539 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2540 } else { 2541 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2542 pkt.fp_hlen = 16; 2543 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2544 (spd << 16); 2545 pkt.fp_hdr[1] = 2546 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2547 (p[10] << 8) | p[11]; 2548 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2549 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2550 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2551 } 2552 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2553 pkt.fp_dlen = m0->m_pkthdr.len; 2554 pkt.fp_m = m0; 2555 pkt.fp_callback = callback; 2556 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2557 splx(s); 2558 m0 = pkt.fp_m; 2559 end: 2560 if (m0 != NULL) { 2561 if (callback) 2562 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2563 else 2564 m_freem(m0); 2565 } 2566 return error; 2567 } 2568
Indexes created Mon Oct 13 05:10:05 GMT 2025