fwohci.c revision 1.24
1 /* $NetBSD: fwohci.c,v 1.24 2001/05/01 04:48:11 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 78 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 115 void *); 116 117 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 119 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 120 121 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 122 struct fwohci_pkt *); 123 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 124 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 125 struct fwohci_pkt *); 126 127 static int fwohci_guidrom_init(struct fwohci_softc *); 128 static void fwohci_configrom_init(struct fwohci_softc *); 129 static int fwohci_configrom_input(struct fwohci_softc *, void *, 130 struct fwohci_pkt *); 131 static void fwohci_selfid_init(struct fwohci_softc *); 132 static int fwohci_selfid_input(struct fwohci_softc *); 133 134 static void fwohci_csr_init(struct fwohci_softc *); 135 static int fwohci_csr_input(struct fwohci_softc *, void *, 136 struct fwohci_pkt *); 137 138 static void fwohci_uid_collect(struct fwohci_softc *); 139 static int fwohci_uid_input(struct fwohci_softc *, void *, 140 struct fwohci_pkt *); 141 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 142 static void fwohci_check_nodes(struct fwohci_softc *); 143 144 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 145 void (*)(struct device *, struct mbuf *)); 146 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 147 static int fwohci_if_output(struct device *, struct mbuf *, 148 void (*)(struct device *, struct mbuf *)); 149 static int fwohci_input(struct ieee1394_abuf *); 150 static int fwohci_output(struct ieee1394_abuf *); 151 static int fwohci_extract_resp(struct fwohci_softc *, void *, 152 struct fwohci_pkt *); 153 static int fwohci_multi_resp(struct fwohci_softc *, void *, 154 struct fwohci_pkt *); 155 static int fwohci_inreg(struct ieee1394_abuf *, int); 156 static int fwohci_parse_input(struct fwohci_softc *, void *, 157 struct fwohci_pkt *); 158 159 #ifdef FW_DEBUG 160 int fw_verbose = 1; 161 int fw_dump = 1; 162 #endif 163 164 int 165 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 166 { 167 int i; 168 u_int32_t val; 169 #if 0 170 int error; 171 #endif 172 173 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 174 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 175 176 /* 177 * Wait for reset completion 178 */ 179 for (i = 0; i < OHCI_LOOP; i++) { 180 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 181 if ((val & OHCI_HCControl_SoftReset) == 0) 182 break; 183 } 184 185 /* What dialect of OHCI is this device? 186 */ 187 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 188 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 189 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 190 191 LIST_INIT(&sc->sc_nodelist); 192 193 if (fwohci_guidrom_init(sc) != 0) { 194 printf("\n%s: fatal: no global UID ROM\n", 195 sc->sc_sc1394.sc1394_dev.dv_xname); 196 return -1; 197 } 198 199 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 200 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 201 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 202 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 203 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 204 205 /* Get the maximum link speed and receive size 206 */ 207 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 208 sc->sc_sc1394.sc1394_link_speed = 209 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 210 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 211 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 212 } else { 213 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 214 } 215 216 /* MaxRec is encoded as log2(max_rec_octets)-1 217 */ 218 sc->sc_sc1394.sc1394_max_receive = 219 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 220 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 221 222 /* 223 * Count how many isochronous ctx we have. 224 */ 225 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 226 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 227 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 228 for (i = 0; val != 0; val >>= 1) { 229 if (val & 0x1) 230 i++; 231 } 232 sc->sc_isoctx = i; 233 printf(", %d iso_ctx", sc->sc_isoctx); 234 235 printf("\n"); 236 237 #if 0 238 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 239 &sc->sc_configrom_map, 240 (caddr_t *) &sc->sc_configrom, 241 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 242 return error; 243 #endif 244 245 sc->sc_dying = 0; 246 247 kthread_create(fwohci_create_event_thread, sc); 248 return 0; 249 } 250 251 int 252 fwohci_intr(void *arg) 253 { 254 struct fwohci_softc * const sc = arg; 255 int progress = 0; 256 u_int32_t intmask, iso; 257 258 for (;;) { 259 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 260 261 /* 262 * On a bus reset, everything except bus reset gets cleared. That 263 * can't get cleared until the selfid phase completes (which 264 * happens outside the interrupt routines). So if just a bus 265 * reset is left in the mask and it's already in the sc_intmask, 266 * just return. 267 */ 268 269 if ((intmask == 0) || 270 (progress && (intmask == OHCI_Int_BusReset) && 271 (sc->sc_intmask & OHCI_Int_BusReset))) { 272 if (progress) 273 wakeup(fwohci_event_thread); 274 return progress; 275 } 276 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 277 intmask & ~OHCI_Int_BusReset); 278 #ifdef FW_DEBUG 279 if (fw_verbose > 1) { 280 printf("%s: intmask=0x%08x:", 281 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 282 if (intmask & OHCI_Int_CycleTooLong) 283 printf(" CycleTooLong"); 284 if (intmask & OHCI_Int_UnrecoverableError) 285 printf(" UnrecoverableError"); 286 if (intmask & OHCI_Int_CycleInconsistent) 287 printf(" CycleInconsistent"); 288 if (intmask & OHCI_Int_BusReset) 289 printf(" BusReset"); 290 if (intmask & OHCI_Int_SelfIDComplete) 291 printf(" SelfIDComplete"); 292 if (intmask & OHCI_Int_LockRespErr) 293 printf(" LockRespErr"); 294 if (intmask & OHCI_Int_PostedWriteErr) 295 printf(" PostedWriteErr"); 296 if (intmask & OHCI_Int_ReqTxComplete) 297 printf(" ReqTxComplete(0x%04x)", 298 OHCI_ASYNC_DMA_READ(sc, 299 OHCI_CTX_ASYNC_TX_REQUEST, 300 OHCI_SUBREG_ContextControlClear)); 301 if (intmask & OHCI_Int_RespTxComplete) 302 printf(" RespTxComplete(0x%04x)", 303 OHCI_ASYNC_DMA_READ(sc, 304 OHCI_CTX_ASYNC_TX_RESPONSE, 305 OHCI_SUBREG_ContextControlClear)); 306 if (intmask & OHCI_Int_ARRS) 307 printf(" ARRS(0x%04x)", 308 OHCI_ASYNC_DMA_READ(sc, 309 OHCI_CTX_ASYNC_RX_RESPONSE, 310 OHCI_SUBREG_ContextControlClear)); 311 if (intmask & OHCI_Int_ARRQ) 312 printf(" ARRQ(0x%04x)", 313 OHCI_ASYNC_DMA_READ(sc, 314 OHCI_CTX_ASYNC_RX_REQUEST, 315 OHCI_SUBREG_ContextControlClear)); 316 if (intmask & OHCI_Int_IsochRx) 317 printf(" IsochRx(0x%08x)", 318 OHCI_CSR_READ(sc, 319 OHCI_REG_IsoRecvIntEventClear)); 320 if (intmask & OHCI_Int_IsochTx) 321 printf(" IsochTx(0x%08x)", 322 OHCI_CSR_READ(sc, 323 OHCI_REG_IsoXmitIntEventClear)); 324 if (intmask & OHCI_Int_RQPkt) 325 printf(" RQPkt(0x%04x)", 326 OHCI_ASYNC_DMA_READ(sc, 327 OHCI_CTX_ASYNC_RX_REQUEST, 328 OHCI_SUBREG_ContextControlClear)); 329 if (intmask & OHCI_Int_RSPkt) 330 printf(" RSPkt(0x%04x)", 331 OHCI_ASYNC_DMA_READ(sc, 332 OHCI_CTX_ASYNC_RX_RESPONSE, 333 OHCI_SUBREG_ContextControlClear)); 334 printf("\n"); 335 } 336 #endif /* FW_DEBUG */ 337 if (intmask & OHCI_Int_BusReset) { 338 /* 339 * According to OHCI spec 6.1.1 "busReset", 340 * All asynchronous transmit must be stopped before 341 * clearing BusReset. Moreover, the BusReset 342 * interrupt bit should not be cleared during the 343 * SelfID phase. Thus we turned off interrupt mask 344 * bit of BusReset instead until SelfID completion 345 * or SelfID timeout. 346 */ 347 intmask &= OHCI_Int_SelfIDComplete; 348 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 349 OHCI_Int_BusReset); 350 sc->sc_intmask = intmask; 351 sc->sc_intmask |= OHCI_Int_BusReset; 352 353 } 354 355 if (intmask & OHCI_Int_SelfIDComplete) 356 sc->sc_intmask |= OHCI_Int_SelfIDComplete; 357 358 if (intmask & OHCI_Int_ReqTxComplete) 359 sc->sc_intmask |= OHCI_Int_ReqTxComplete; 360 if (intmask & OHCI_Int_RespTxComplete) 361 sc->sc_intmask |= OHCI_Int_RespTxComplete; 362 if (intmask & OHCI_Int_RQPkt) 363 sc->sc_intmask |= OHCI_Int_RQPkt; 364 if (intmask & OHCI_Int_RSPkt) 365 sc->sc_intmask |= OHCI_Int_RSPkt; 366 if (intmask & OHCI_Int_IsochTx) { 367 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 368 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 369 sc->sc_intmask |= OHCI_Int_IsochTx; 370 } 371 if (intmask & OHCI_Int_IsochRx) { 372 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 373 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 374 sc->sc_iso |= iso; 375 sc->sc_intmask |= OHCI_Int_IsochRx; 376 } 377 378 if (!progress) { 379 sc->sc_intrcnt.ev_count++; 380 progress = 1; 381 } 382 } 383 } 384 385 static void 386 fwohci_create_event_thread(void *arg) 387 { 388 struct fwohci_softc *sc = arg; 389 390 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 391 sc->sc_sc1394.sc1394_dev.dv_xname)) { 392 printf("%s: unable to create event thread\n", 393 sc->sc_sc1394.sc1394_dev.dv_xname); 394 panic("fwohci_create_event_thread"); 395 } 396 } 397 398 static void 399 fwohci_thread_init(void *arg) 400 { 401 struct fwohci_softc *sc = arg; 402 int i; 403 404 /* 405 * Allocate descriptors 406 */ 407 if (fwohci_desc_alloc(sc)) { 408 printf("%s: not enabling interrupts\n", 409 sc->sc_sc1394.sc1394_dev.dv_xname); 410 kthread_exit(1); 411 } 412 413 /* 414 * Enable Link Power 415 */ 416 417 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 418 419 /* 420 * Allocate DMA Context 421 */ 422 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 423 OHCI_CTX_ASYNC_RX_REQUEST); 424 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 425 OHCI_CTX_ASYNC_RX_RESPONSE); 426 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 427 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 428 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 429 M_DEVBUF, M_WAITOK); 430 for (i = 0; i < sc->sc_isoctx; i++) 431 sc->sc_ctx_ir[i] = NULL; 432 433 /* 434 * Allocate buffer for configuration ROM and SelfID buffer 435 */ 436 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 437 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 438 439 callout_init(&sc->sc_selfid_callout); 440 441 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 442 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 443 444 /* 445 * establish hooks for shutdown and suspend/resume 446 */ 447 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 448 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 449 450 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 451 fwohci_print); 452 453 /* Main loop. It's not coming back normally. */ 454 455 fwohci_event_thread(sc); 456 457 kthread_exit(0); 458 } 459 460 static void 461 fwohci_event_thread(struct fwohci_softc *sc) 462 { 463 int i, s; 464 u_int32_t intmask, iso; 465 466 s=splbio(); 467 468 /* 469 * Initialize hardware registers. 470 */ 471 472 fwohci_hw_init(sc); 473 474 /* Initial Bus Reset */ 475 fwohci_phy_busreset(sc); 476 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 477 splx(s); 478 479 while (!sc->sc_dying) { 480 while (1) { 481 s=splbio(); 482 intmask = sc->sc_intmask; 483 if (intmask) { 484 splx(s); 485 if (intmask & OHCI_Int_BusReset) { 486 s=splbio(); 487 sc->sc_intmask &= ~OHCI_Int_BusReset; 488 splx(s); 489 fwohci_buf_stop(sc); 490 fwohci_buf_init(sc); 491 if (sc->sc_uidtbl != NULL) { 492 free(sc->sc_uidtbl, M_DEVBUF); 493 sc->sc_uidtbl = NULL; 494 } 495 496 callout_reset(&sc->sc_selfid_callout, OHCI_SELFID_TIMEOUT, 497 (void (*)(void *))fwohci_phy_busreset, sc); 498 sc->sc_nodeid = 0xffff; /* indicate invalid */ 499 sc->sc_rootid = 0; 500 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 501 } 502 if (intmask & OHCI_Int_SelfIDComplete) { 503 s=splbio(); 504 sc->sc_intmask &= ~OHCI_Int_SelfIDComplete; 505 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 506 OHCI_Int_BusReset); 507 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 508 OHCI_Int_BusReset); 509 splx(s); 510 callout_stop(&sc->sc_selfid_callout); 511 if (fwohci_selfid_input(sc) == 0) { 512 fwohci_buf_start(sc); 513 fwohci_uid_collect(sc); 514 } 515 } 516 if (intmask & OHCI_Int_ReqTxComplete) { 517 s=splbio(); 518 sc->sc_intmask &= ~OHCI_Int_ReqTxComplete; 519 splx(s); 520 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 521 } 522 if (intmask & OHCI_Int_RespTxComplete) { 523 s=splbio(); 524 sc->sc_intmask &= ~OHCI_Int_RespTxComplete; 525 splx(s); 526 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 527 } 528 if (intmask & OHCI_Int_RQPkt) { 529 s=splbio(); 530 sc->sc_intmask &= ~OHCI_Int_RQPkt; 531 splx(s); 532 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 533 } 534 if (intmask & OHCI_Int_RSPkt) { 535 s=splbio(); 536 sc->sc_intmask &= ~OHCI_Int_RSPkt; 537 splx(s); 538 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 539 } 540 if (intmask & OHCI_Int_IsochTx) { 541 s=splbio(); 542 sc->sc_intmask &= ~OHCI_Int_IsochTx; 543 splx(s); 544 } 545 if (intmask & OHCI_Int_IsochRx) { 546 s=splbio(); 547 sc->sc_intmask &= ~OHCI_Int_IsochRx; 548 iso = sc->sc_iso; 549 sc->sc_iso = 0; 550 splx(s); 551 for (i = 0; i < sc->sc_isoctx; i++) { 552 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) 553 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 554 555 } 556 } 557 } else 558 break; 559 } 560 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 561 splx(s); 562 } 563 } 564 565 #if 0 566 static int 567 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 568 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 569 { 570 bus_dma_segment_t segs[1]; 571 int error, nsegs, steps; 572 573 steps = 0; 574 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 575 segs, 1, &nsegs, flags); 576 if (error) 577 goto cleanup; 578 579 steps = 1; 580 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 581 kvap, flags); 582 if (error) 583 goto cleanup; 584 585 if (error == 0) 586 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 587 size, flags, mapp); 588 if (error) 589 goto cleanup; 590 if (error == 0) 591 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 592 if (error) 593 goto cleanup; 594 595 cleanup: 596 switch (steps) { 597 case 1: 598 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 599 } 600 601 return error; 602 } 603 #endif 604 605 int 606 fwohci_print(void *aux, const char *pnp) 607 { 608 char *name = aux; 609 610 if (pnp) 611 printf("%s at %s", name, pnp); 612 613 return UNCONF; 614 } 615 616 static void 617 fwohci_hw_init(struct fwohci_softc *sc) 618 { 619 int i; 620 u_int32_t val; 621 622 /* 623 * Software Reset. 624 */ 625 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 626 for (i = 0; i < OHCI_LOOP; i++) { 627 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 628 if ((val & OHCI_HCControl_SoftReset) == 0) 629 break; 630 } 631 632 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 633 634 /* 635 * First, initilize CSRs with undefined value to default settings. 636 */ 637 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 638 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 639 #if 0 640 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 641 #else 642 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 643 #endif 644 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 645 for (i = 0; i < sc->sc_isoctx; i++) { 646 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 647 ~0); 648 } 649 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 650 651 fwohci_configrom_init(sc); 652 fwohci_selfid_init(sc); 653 fwohci_buf_init(sc); 654 fwohci_csr_init(sc); 655 656 /* 657 * Final CSR settings. 658 */ 659 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 660 OHCI_LinkControl_CycleTimerEnable | 661 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 662 663 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 664 665 /* clear receive filter */ 666 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 667 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 668 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 669 670 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 671 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 672 #if BYTE_ORDER == BIG_ENDIAN 673 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 674 OHCI_HCControl_NoByteSwapData); 675 #endif 676 677 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 678 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 679 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 680 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 681 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 682 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 683 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 684 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 685 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 686 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 687 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 688 689 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 690 691 /* 692 * Start the receivers 693 */ 694 fwohci_buf_start(sc); 695 } 696 697 static void 698 fwohci_power(int why, void *arg) 699 { 700 struct fwohci_softc *sc = arg; 701 int s; 702 703 s = splbio(); 704 switch (why) { 705 case PWR_SUSPEND: 706 case PWR_STANDBY: 707 fwohci_shutdown(sc); 708 break; 709 case PWR_RESUME: 710 fwohci_hw_init(sc); 711 fwohci_phy_busreset(sc); 712 break; 713 case PWR_SOFTSUSPEND: 714 case PWR_SOFTSTANDBY: 715 case PWR_SOFTRESUME: 716 break; 717 } 718 splx(s); 719 } 720 721 static void 722 fwohci_shutdown(void *arg) 723 { 724 struct fwohci_softc *sc = arg; 725 u_int32_t val; 726 727 callout_stop(&sc->sc_selfid_callout); 728 /* disable all interrupt */ 729 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 730 fwohci_buf_stop(sc); 731 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 732 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 733 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 734 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 735 fwohci_phy_busreset(sc); 736 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 737 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 738 } 739 740 /* 741 * COMMON FUNCTIONS 742 */ 743 744 /* 745 * read the PHY Register. 746 */ 747 static u_int8_t 748 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 749 { 750 int i; 751 u_int32_t val; 752 753 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 754 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 755 for (i = 0; i < OHCI_LOOP; i++) { 756 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 757 OHCI_PhyControl_RdDone) 758 break; 759 } 760 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 761 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 762 } 763 764 /* 765 * write the PHY Register. 766 */ 767 static void 768 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 769 { 770 int i; 771 772 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 773 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 774 (val << OHCI_PhyControl_WrData_BITPOS)); 775 for (i = 0; i < OHCI_LOOP; i++) { 776 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 777 OHCI_PhyControl_WrReg)) 778 break; 779 } 780 } 781 782 /* 783 * Initiate Bus Reset 784 */ 785 static void 786 fwohci_phy_busreset(struct fwohci_softc *sc) 787 { 788 int s; 789 u_int8_t val; 790 791 s = splbio(); 792 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 793 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 794 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 795 callout_stop(&sc->sc_selfid_callout); 796 val = fwohci_phy_read(sc, 1); 797 val = (val & 0x80) | /* preserve RHB (force root) */ 798 0x40 | /* Initiate Bus Reset */ 799 0x3f; /* default GAP count */ 800 fwohci_phy_write(sc, 1, val); 801 splx(s); 802 } 803 804 /* 805 * PHY Packet 806 */ 807 static void 808 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 809 { 810 u_int32_t val; 811 u_int8_t key, phyid; 812 813 val = pkt->fp_hdr[1]; 814 if (val != ~pkt->fp_hdr[2]) { 815 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 816 OHCI_CTXCTL_EVENT_BUS_RESET) { 817 #ifdef FW_DEBUG 818 if (fw_verbose > 1) 819 printf("fwohci_phy_input: BusReset: 0x%08x\n", 820 pkt->fp_hdr[2]); 821 #endif 822 } else { 823 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 824 sc->sc_sc1394.sc1394_dev.dv_xname, val, 825 pkt->fp_hdr[2]); 826 } 827 return; 828 } 829 key = (val & 0xc0000000) >> 30; 830 phyid = (val & 0x3f000000) >> 24; 831 switch (key) { 832 case 0: 833 #ifdef FW_DEBUG 834 if (fw_verbose > 1) { 835 printf("fwohci_phy_input: PHY Config from %d:", phyid); 836 if (val & 0x00800000) 837 printf(" ForceRoot"); 838 if (val & 0x00400000) 839 printf(" Gap=%x", (val & 0x003f0000) >> 16); 840 printf("\n"); 841 } 842 #endif 843 break; 844 case 1: 845 #ifdef FW_DEBUG 846 if (fw_verbose > 1) 847 printf("fwohci_phy_input: Link-on from %d\n", phyid); 848 #endif 849 break; 850 case 2: 851 #ifdef FW_DEBUG 852 if (fw_verbose > 1) { 853 printf("fwohci_phy_input: SelfID from %d:", phyid); 854 if (val & 0x00800000) { 855 printf(" #%d", (val & 0x00700000) >> 20); 856 } else { 857 if (val & 0x00400000) 858 printf(" LinkActive"); 859 printf(" Gap=%x", (val & 0x003f0000) >> 16); 860 printf(" Spd=S%d", 861 100 << ((val & 0x0000c000) >> 14)); 862 if (val & 0x00000800) 863 printf(" Cont"); 864 if (val & 0x00000002) 865 printf(" InitiateBusReset"); 866 } 867 if (val & 0x00000001) 868 printf(" +"); 869 printf("\n"); 870 } 871 #endif 872 break; 873 default: 874 printf("%s: unknown PHY packet: 0x%08x\n", 875 sc->sc_sc1394.sc1394_dev.dv_xname, val); 876 break; 877 } 878 } 879 880 /* 881 * Descriptor for context DMA. 882 */ 883 static int 884 fwohci_desc_alloc(struct fwohci_softc *sc) 885 { 886 int error, mapsize, dsize; 887 888 /* 889 * allocate descriptor buffer 890 */ 891 892 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 893 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 894 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 895 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 896 mapsize = howmany(sc->sc_descsize, NBBY); 897 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 898 memset(sc->sc_descmap, 0, mapsize); 899 900 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 901 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 902 printf("%s: unable to allocate descriptor buffer, error = %d\n", 903 sc->sc_sc1394.sc1394_dev.dv_xname, error); 904 goto fail_0; 905 } 906 907 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 908 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 909 != 0) { 910 printf("%s: unable to map descriptor buffer, error = %d\n", 911 sc->sc_sc1394.sc1394_dev.dv_xname, error); 912 goto fail_1; 913 } 914 915 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 916 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 917 printf("%s: unable to create descriptor buffer DMA map, " 918 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 919 goto fail_2; 920 } 921 922 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 923 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 924 printf("%s: unable to load descriptor buffer DMA map, " 925 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 926 goto fail_3; 927 } 928 929 return 0; 930 931 fail_3: 932 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 933 fail_2: 934 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 935 fail_1: 936 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 937 fail_0: 938 return error; 939 } 940 941 static struct fwohci_desc * 942 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 943 { 944 int i, n; 945 946 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 947 for (i = 0; ; i++) { 948 if (i == ndesc) { 949 for (i = 0; i < ndesc; i++) 950 setbit(sc->sc_descmap, n + i); 951 return sc->sc_desc + n; 952 } 953 if (isset(sc->sc_descmap, n + i)) 954 break; 955 } 956 } 957 return NULL; 958 } 959 960 static void 961 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 962 { 963 int i, n; 964 965 n = fd - sc->sc_desc; 966 for (i = 0; i < ndesc; i++, n++) { 967 #ifdef DIAGNOSTICS 968 if (isclr(sc->sc_descmap, n)) 969 panic("fwohci_desc_put: duplicated free"); 970 #endif 971 clrbit(sc->sc_descmap, n); 972 } 973 } 974 975 /* 976 * Asyncronous/Isochronous Transmit/Receive Context 977 */ 978 static int 979 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 980 int bufcnt, int ctx) 981 { 982 int i, error; 983 struct fwohci_ctx *fc; 984 struct fwohci_buf *fb; 985 struct fwohci_desc *fd; 986 987 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 988 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 989 LIST_INIT(&fc->fc_handler); 990 TAILQ_INIT(&fc->fc_buf); 991 fc->fc_ctx = ctx; 992 fc->fc_bufcnt = bufcnt; 993 fb = (struct fwohci_buf *)&fc[1]; 994 for (i = 0; i < bufcnt; i++, fb++) { 995 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 996 goto fail; 997 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 998 error = ENOBUFS; 999 goto fail; 1000 } 1001 fb->fb_desc = fd; 1002 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1003 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1004 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1005 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1006 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1007 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1008 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1009 } 1010 *fcp = fc; 1011 return 0; 1012 1013 fail: 1014 while (i-- > 0) 1015 fwohci_buf_free(sc, --fb); 1016 free(fc, M_DEVBUF); 1017 return error; 1018 } 1019 1020 static void 1021 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1022 { 1023 struct fwohci_buf *fb; 1024 struct fwohci_handler *fh; 1025 1026 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1027 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1028 NULL, NULL); 1029 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1030 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1031 fwohci_buf_free(sc, fb); 1032 } 1033 free(fc, M_DEVBUF); 1034 } 1035 1036 static void 1037 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1038 { 1039 struct fwohci_buf *fb, *nfb; 1040 struct fwohci_desc *fd; 1041 struct fwohci_handler *fh; 1042 int n; 1043 1044 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1045 nfb = TAILQ_NEXT(fb, fb_list); 1046 fb->fb_off = 0; 1047 fd = fb->fb_desc; 1048 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1049 fd->fd_rescount = fd->fd_reqcount; 1050 } 1051 1052 n = fc->fc_ctx; 1053 fb = TAILQ_FIRST(&fc->fc_buf); 1054 if (fc->fc_isoch) { 1055 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1056 fb->fb_daddr | 1); 1057 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1058 OHCI_CTXCTL_RX_BUFFER_FILL | 1059 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1060 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1061 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1062 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1063 OHCI_CTXCTL_RX_ISOCH_HEADER); 1064 fh = LIST_FIRST(&fc->fc_handler); 1065 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1066 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1067 } else { 1068 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1069 fb->fb_daddr | 1); 1070 } 1071 } 1072 1073 /* 1074 * DMA data buffer 1075 */ 1076 static int 1077 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1078 { 1079 int error; 1080 1081 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1082 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1083 printf("%s: unable to allocate buffer, error = %d\n", 1084 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1085 goto fail_0; 1086 } 1087 1088 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1089 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1090 printf("%s: unable to map buffer, error = %d\n", 1091 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1092 goto fail_1; 1093 } 1094 1095 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1096 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1097 printf("%s: unable to create buffer DMA map, " 1098 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1099 error); 1100 goto fail_2; 1101 } 1102 1103 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1104 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1105 printf("%s: unable to load buffer DMA map, " 1106 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1107 error); 1108 goto fail_3; 1109 } 1110 1111 return 0; 1112 1113 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1114 fail_3: 1115 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1116 fail_2: 1117 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1118 fail_1: 1119 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1120 fail_0: 1121 return error; 1122 } 1123 1124 static void 1125 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1126 { 1127 1128 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1129 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1130 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1131 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1132 } 1133 1134 static void 1135 fwohci_buf_init(struct fwohci_softc *sc) 1136 { 1137 int i; 1138 1139 /* 1140 * Initialize for Asynchronous Transmit Queue. 1141 */ 1142 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1143 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1144 1145 /* 1146 * Initialize for Asynchronous Receive Queue. 1147 */ 1148 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1149 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1150 1151 /* 1152 * Initialize for Isochronous Receive Queue. 1153 */ 1154 for (i = 0; i < sc->sc_isoctx; i++) { 1155 if (sc->sc_ctx_ir[i] != NULL) 1156 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1157 } 1158 } 1159 1160 static void 1161 fwohci_buf_start(struct fwohci_softc *sc) 1162 { 1163 int i; 1164 1165 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1166 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1167 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1168 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1169 for (i = 0; i < sc->sc_isoctx; i++) { 1170 if (sc->sc_ctx_ir[i] != NULL && 1171 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1172 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1173 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1174 } 1175 } 1176 } 1177 1178 static void 1179 fwohci_buf_stop(struct fwohci_softc *sc) 1180 { 1181 int i, j; 1182 1183 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1184 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1185 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1186 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1187 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1188 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1189 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1190 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1191 for (i = 0; i < sc->sc_isoctx; i++) { 1192 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1193 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1194 } 1195 1196 /* 1197 * Make sure the transmitter is stopped. 1198 */ 1199 for (j = 0; j < OHCI_LOOP; j++) { 1200 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1201 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1202 continue; 1203 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1204 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1205 continue; 1206 break; 1207 } 1208 } 1209 1210 static void 1211 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1212 { 1213 struct fwohci_buf *fb, *tfb; 1214 1215 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1216 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1217 fb->fb_desc->fd_rescount != 0) 1218 break; 1219 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1220 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1221 fb->fb_off = 0; 1222 fb->fb_desc->fd_branch = 0; 1223 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1224 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1225 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1226 } 1227 } 1228 1229 static int 1230 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1231 int len) 1232 { 1233 struct fwohci_buf *fb; 1234 struct fwohci_desc *fd; 1235 int bufend; 1236 1237 fb = TAILQ_FIRST(&fc->fc_buf); 1238 again: 1239 fd = fb->fb_desc; 1240 #ifdef FW_DEBUG 1241 if (fw_verbose > 1) 1242 printf("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1243 " len %d, avail %d\n", 1244 (long)(fd - sc->sc_desc), fb->fb_off, fd->fd_reqcount, 1245 fd->fd_rescount, len, 1246 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1247 #endif 1248 bufend = fd->fd_reqcount - fd->fd_rescount; 1249 if (fb->fb_off >= bufend) { 1250 if (fc->fc_isoch && fb->fb_off > 0) { 1251 fb->fb_off = fd->fd_reqcount; 1252 fd->fd_rescount = 0; 1253 } 1254 if (fd->fd_rescount == 0) { 1255 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1256 goto again; 1257 } 1258 return 0; 1259 } 1260 if (fb->fb_off + len > bufend) 1261 len = bufend - fb->fb_off; 1262 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1263 BUS_DMASYNC_POSTREAD); 1264 *pp = fb->fb_buf + fb->fb_off; 1265 fb->fb_off += roundup(len, 4); 1266 return len; 1267 } 1268 1269 static int 1270 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1271 struct fwohci_pkt *pkt) 1272 { 1273 caddr_t p; 1274 int len, count, i; 1275 1276 memset(pkt, 0, sizeof(*pkt)); 1277 pkt->fp_uio.uio_iov = pkt->fp_iov; 1278 pkt->fp_uio.uio_rw = UIO_WRITE; 1279 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1280 1281 /* get first quadlet */ 1282 count = 4; 1283 if (fc->fc_isoch) { 1284 /* 1285 * get trailer first, may be bogus data unless status update 1286 * in descriptor is set. 1287 */ 1288 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1289 sizeof(*pkt->fp_trail)); 1290 if (len <= 0) { 1291 #ifdef FW_DEBUG 1292 if (fw_verbose > 1) 1293 printf("fwohci_buf_input: no input for is#%d\n", 1294 fc->fc_ctx); 1295 #endif 1296 return 0; 1297 } 1298 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1299 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1300 } 1301 len = fwohci_buf_pktget(sc, fc, &p, count); 1302 if (len <= 0) { 1303 #ifdef FW_DEBUG 1304 if (fw_verbose > 1) 1305 printf("fwohci_buf_input: no input for %d\n", 1306 fc->fc_ctx); 1307 #endif 1308 return 0; 1309 } 1310 pkt->fp_hdr[0] = *(u_int32_t *)p; 1311 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1312 switch (pkt->fp_tcode) { 1313 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1314 case IEEE1394_TCODE_READ_RESP_QUAD: 1315 pkt->fp_hlen = 12; 1316 pkt->fp_dlen = 4; 1317 break; 1318 case IEEE1394_TCODE_READ_REQ_BLOCK: 1319 pkt->fp_hlen = 16; 1320 pkt->fp_dlen = 0; 1321 break; 1322 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1323 case IEEE1394_TCODE_READ_RESP_BLOCK: 1324 case IEEE1394_TCODE_LOCK_REQ: 1325 case IEEE1394_TCODE_LOCK_RESP: 1326 pkt->fp_hlen = 16; 1327 break; 1328 case IEEE1394_TCODE_STREAM_DATA: 1329 pkt->fp_hlen = 4; 1330 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1331 break; 1332 default: 1333 pkt->fp_hlen = 12; 1334 pkt->fp_dlen = 0; 1335 break; 1336 } 1337 1338 /* get header */ 1339 while (count < pkt->fp_hlen) { 1340 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1341 if (len == 0) { 1342 printf("fwohci_buf_input: malformed input 1: %d\n", 1343 pkt->fp_hlen - count); 1344 return 0; 1345 } 1346 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1347 count += len; 1348 } 1349 if ((pkt->fp_hlen == 16) && 1350 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1351 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1352 #ifdef FW_DEBUG 1353 if (fw_verbose > 1) 1354 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1355 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1356 #endif 1357 1358 /* get data */ 1359 count = 0; 1360 i = 0; 1361 while (count < pkt->fp_dlen) { 1362 len = fwohci_buf_pktget(sc, fc, 1363 (caddr_t *)&pkt->fp_iov[i].iov_base, 1364 pkt->fp_dlen - count); 1365 if (len == 0) { 1366 printf("fwohci_buf_input: malformed input 2: %d\n", 1367 pkt->fp_hlen - count); 1368 return 0; 1369 } 1370 pkt->fp_iov[i++].iov_len = len; 1371 count += len; 1372 } 1373 pkt->fp_uio.uio_iovcnt = i; 1374 pkt->fp_uio.uio_resid = count; 1375 1376 if (!fc->fc_isoch) { 1377 /* get trailer */ 1378 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1379 sizeof(*pkt->fp_trail)); 1380 if (len <= 0) { 1381 printf("fwohci_buf_input: malformed input 3: %d\n", 1382 pkt->fp_hlen - count); 1383 return 0; 1384 } 1385 } 1386 return 1; 1387 } 1388 1389 static int 1390 fwohci_handler_set(struct fwohci_softc *sc, 1391 int tcode, u_int32_t key1, u_int32_t key2, 1392 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1393 void *arg) 1394 { 1395 struct fwohci_ctx *fc; 1396 struct fwohci_handler *fh; 1397 int i, j; 1398 1399 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1400 j = sc->sc_isoctx; 1401 fh = NULL; 1402 for (i = 0; i < sc->sc_isoctx; i++) { 1403 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1404 if (j == sc->sc_isoctx) 1405 j = i; 1406 continue; 1407 } 1408 fh = LIST_FIRST(&fc->fc_handler); 1409 if (fh == NULL) { 1410 j = i; 1411 break; 1412 } 1413 if (fh->fh_tcode == tcode && 1414 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1415 break; 1416 fh = NULL; 1417 } 1418 if (fh == NULL) { 1419 if (handler == NULL) 1420 return 0; 1421 if (j == sc->sc_isoctx) { 1422 #ifdef FW_DEBUG 1423 if (fw_verbose) 1424 printf("fwohci_handler_set: " 1425 "no more free context\n"); 1426 #endif 1427 return ENOMEM; 1428 } 1429 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1430 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1431 fc->fc_isoch = 1; 1432 sc->sc_ctx_ir[j] = fc; 1433 } 1434 } 1435 } else { 1436 switch (tcode) { 1437 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1438 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1439 case IEEE1394_TCODE_READ_REQ_QUAD: 1440 case IEEE1394_TCODE_READ_REQ_BLOCK: 1441 case IEEE1394_TCODE_LOCK_REQ: 1442 fc = sc->sc_ctx_arrq; 1443 break; 1444 case IEEE1394_TCODE_WRITE_RESP: 1445 case IEEE1394_TCODE_READ_RESP_QUAD: 1446 case IEEE1394_TCODE_READ_RESP_BLOCK: 1447 case IEEE1394_TCODE_LOCK_RESP: 1448 fc = sc->sc_ctx_arrs; 1449 break; 1450 default: 1451 return EIO; 1452 } 1453 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1454 fh = LIST_NEXT(fh, fh_list)) { 1455 if (fh->fh_tcode == tcode && 1456 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1457 break; 1458 } 1459 } 1460 if (handler == NULL) { 1461 if (fh != NULL) { 1462 LIST_REMOVE(fh, fh_list); 1463 free(fh, M_DEVBUF); 1464 } 1465 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1466 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1467 fwohci_ctx_free(sc, fc); 1468 } 1469 return 0; 1470 } 1471 if (fh == NULL) { 1472 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1473 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1474 } 1475 fh->fh_tcode = tcode; 1476 fh->fh_key1 = key1; 1477 fh->fh_key2 = key2; 1478 fh->fh_handler = handler; 1479 fh->fh_handarg = arg; 1480 #ifdef FW_DEBUG 1481 if (fw_verbose > 1) 1482 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1483 fc->fc_ctx, tcode, key1, key2); 1484 #endif 1485 1486 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1487 fwohci_ctx_init(sc, fc); 1488 #ifdef FW_DEBUG 1489 if (fw_verbose > 1) 1490 printf("fwohci_handler_set: SYNC desc %ld\n", 1491 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - 1492 sc->sc_desc)); 1493 #endif 1494 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1495 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1496 } 1497 return 0; 1498 } 1499 1500 /* 1501 * Asyncronous Receive Requests input frontend. 1502 */ 1503 static void 1504 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1505 { 1506 int rcode; 1507 u_int32_t key1, key2; 1508 struct fwohci_handler *fh; 1509 struct fwohci_pkt pkt, res; 1510 1511 while (fwohci_buf_input(sc, fc, &pkt)) { 1512 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1513 fwohci_phy_input(sc, &pkt); 1514 return; 1515 } 1516 key1 = pkt.fp_hdr[1] & 0xffff; 1517 key2 = pkt.fp_hdr[2]; 1518 memset(&res, 0, sizeof(res)); 1519 res.fp_uio.uio_rw = UIO_WRITE; 1520 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1521 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1522 fh = LIST_NEXT(fh, fh_list)) { 1523 if (pkt.fp_tcode == fh->fh_tcode && 1524 key1 == fh->fh_key1 && 1525 key2 == fh->fh_key2) { 1526 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1527 break; 1528 } 1529 } 1530 if (fh == NULL) { 1531 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1532 #ifdef FW_DEBUG 1533 if (fw_verbose > 1) 1534 printf("fwohci_arrq_input: no listener:" 1535 " tcode 0x%x, addr=0x%04x %08x\n", 1536 pkt.fp_tcode, key1, key2); 1537 #endif 1538 } 1539 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1540 OHCI_CTXCTL_EVENT_ACK_PENDING) 1541 return; 1542 if (rcode != -1) 1543 fwohci_atrs_output(sc, rcode, &pkt, &res); 1544 } 1545 fwohci_buf_next(sc, fc); 1546 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1547 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1548 } 1549 1550 1551 /* 1552 * Asynchronous Receive Response input frontend. 1553 */ 1554 static void 1555 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1556 { 1557 struct fwohci_pkt pkt; 1558 struct fwohci_handler *fh; 1559 u_int16_t srcid; 1560 int rcode, tlabel; 1561 1562 while (fwohci_buf_input(sc, fc, &pkt)) { 1563 srcid = pkt.fp_hdr[1] >> 16; 1564 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1565 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1566 #ifdef FW_DEBUG 1567 if (fw_verbose > 1) 1568 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1569 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1570 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1571 pkt.fp_dlen); 1572 #endif 1573 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1574 fh = LIST_NEXT(fh, fh_list)) { 1575 if (pkt.fp_tcode == fh->fh_tcode && 1576 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1577 tlabel == fh->fh_key2) { 1578 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1579 LIST_REMOVE(fh, fh_list); 1580 free(fh, M_DEVBUF); 1581 break; 1582 } 1583 } 1584 #ifdef FW_DEBUG 1585 if (fw_verbose > 1) 1586 if (fh == NULL) { 1587 printf("fwohci_arrs_input: no listner\n"); 1588 printf("src: %d, rcode: %d, tlabel: %d, tcode: " 1589 "%d hdr[3]: 0x%08x, data: 0x%08lx\n", srcid, 1590 rcode, tlabel, pkt.fp_tcode, pkt.fp_hdr[3], 1591 (unsigned long)(*((int *)pkt.fp_iov[0].iov_base))); 1592 } 1593 #endif 1594 } 1595 fwohci_buf_next(sc, fc); 1596 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1597 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1598 } 1599 1600 /* 1601 * Isochronous Receive input frontend. 1602 */ 1603 static void 1604 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1605 { 1606 int rcode, chan, tag; 1607 struct iovec *iov; 1608 struct fwohci_handler *fh; 1609 struct fwohci_pkt pkt; 1610 1611 while (fwohci_buf_input(sc, fc, &pkt)) { 1612 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1613 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1614 #ifdef FW_DEBUG 1615 if (fw_verbose > 1) 1616 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1617 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1618 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1619 #endif 1620 if (tag == IEEE1394_TAG_GASP) { 1621 /* 1622 * The pkt with tag=3 is GASP format. 1623 * Move GASP header to header part. 1624 */ 1625 if (pkt.fp_dlen < 8) 1626 continue; 1627 iov = pkt.fp_iov; 1628 /* assuming pkt per buffer mode */ 1629 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1630 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1631 iov->iov_base = (caddr_t)iov->iov_base + 8; 1632 iov->iov_len -= 8; 1633 pkt.fp_hlen += 8; 1634 pkt.fp_dlen -= 8; 1635 } 1636 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1637 fh = LIST_NEXT(fh, fh_list)) { 1638 if (pkt.fp_tcode == fh->fh_tcode && 1639 chan == fh->fh_key1 && tag == fh->fh_key2) { 1640 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1641 &pkt); 1642 break; 1643 } 1644 } 1645 #ifdef FW_DEBUG 1646 if (fw_verbose > 1) { 1647 if (fh == NULL) 1648 printf("fwohci_ir_input: no handler\n"); 1649 else 1650 printf("fwohci_ir_input: rcode %d\n", rcode); 1651 } 1652 #endif 1653 } 1654 fwohci_buf_next(sc, fc); 1655 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1656 OHCI_CTXCTL_WAKE); 1657 } 1658 1659 /* 1660 * Asynchronous Transmit common routine. 1661 */ 1662 static int 1663 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1664 struct fwohci_pkt *pkt) 1665 { 1666 struct fwohci_buf *fb; 1667 struct fwohci_desc *fd; 1668 struct mbuf *m, *m0; 1669 int i, ndesc, error, off, len; 1670 u_int32_t val; 1671 1672 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1673 /* We can't send anything during selfid duration */ 1674 return EAGAIN; 1675 1676 #ifdef FW_DEBUG 1677 if (fw_verbose > 1) { 1678 struct iovec *iov; 1679 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1680 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1681 if (fw_dump) { 1682 for (i = 0; i < pkt->fp_hlen/4; i++) 1683 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1684 printf("$"); 1685 for (ndesc = 0, iov = pkt->fp_iov; 1686 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1687 for (i = 0; i < iov->iov_len; i++) 1688 printf("%s%02x", 1689 (i%32)?((i%4)?"":" "):"\n\t", 1690 ((u_int8_t *)iov->iov_base)[i]); 1691 printf("$"); 1692 } 1693 } 1694 printf("\n"); 1695 } 1696 #endif 1697 1698 if ((m = pkt->fp_m) != NULL) { 1699 for (ndesc = 2; m != NULL; m = m->m_next) 1700 ndesc++; 1701 if (ndesc > OHCI_DESC_MAX) { 1702 m0 = NULL; 1703 ndesc = 2; 1704 for (off = 0; off < pkt->fp_dlen; off += len) { 1705 if (m0 == NULL) { 1706 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1707 if (m0 != NULL) 1708 M_COPY_PKTHDR(m0, pkt->fp_m); 1709 m = m0; 1710 } else { 1711 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1712 m = m->m_next; 1713 } 1714 if (m != NULL) 1715 MCLGET(m, M_DONTWAIT); 1716 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1717 m_freem(m0); 1718 return ENOMEM; 1719 } 1720 len = pkt->fp_dlen - off; 1721 if (len > m->m_ext.ext_size) 1722 len = m->m_ext.ext_size; 1723 m_copydata(pkt->fp_m, off, len, 1724 mtod(m, caddr_t)); 1725 m->m_len = len; 1726 ndesc++; 1727 } 1728 m_freem(pkt->fp_m); 1729 pkt->fp_m = m0; 1730 } 1731 } else 1732 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1733 1734 if (ndesc > OHCI_DESC_MAX) 1735 return ENOBUFS; 1736 1737 if (fc->fc_bufcnt > 50) /*XXX*/ 1738 return ENOBUFS; 1739 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1740 fb->fb_nseg = ndesc; 1741 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1742 if (fb->fb_desc == NULL) { 1743 free(fb, M_DEVBUF); 1744 return ENOBUFS; 1745 } 1746 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1747 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1748 fb->fb_m = pkt->fp_m; 1749 fb->fb_callback = pkt->fp_callback; 1750 1751 if (ndesc > 2) { 1752 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1753 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1754 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1755 free(fb, M_DEVBUF); 1756 return error; 1757 } 1758 1759 if (pkt->fp_m != NULL) 1760 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1761 pkt->fp_m, BUS_DMA_WAITOK); 1762 else 1763 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1764 &pkt->fp_uio, BUS_DMA_WAITOK); 1765 if (error != 0) { 1766 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1767 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1768 free(fb, M_DEVBUF); 1769 return error; 1770 } 1771 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1772 BUS_DMASYNC_PREWRITE); 1773 } 1774 1775 fd = fb->fb_desc; 1776 fd->fd_flags = OHCI_DESC_IMMED; 1777 fd->fd_reqcount = pkt->fp_hlen; 1778 fd->fd_data = 0; 1779 fd->fd_branch = 0; 1780 fd->fd_status = 0; 1781 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1782 i = 3; /* XXX: 3 sec */ 1783 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1784 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1785 ((((val >> 25) + i) & 0x7) << 13); 1786 } else 1787 fd->fd_timestamp = 0; 1788 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1789 for (i = 0; i < ndesc - 2; i++) { 1790 fd = fb->fb_desc + 2 + i; 1791 fd->fd_flags = 0; 1792 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1793 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1794 fd->fd_branch = 0; 1795 fd->fd_status = 0; 1796 fd->fd_timestamp = 0; 1797 } 1798 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1799 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1800 1801 #ifdef FW_DEBUG 1802 if (fw_verbose > 1) { 1803 printf("fwohci_at_output: desc %ld", 1804 (long)(fb->fb_desc - sc->sc_desc)); 1805 for (i = 0; i < ndesc * 4; i++) 1806 printf("%s%08x", i&7?" ":"\n\t", 1807 ((u_int32_t *)fb->fb_desc)[i]); 1808 printf("\n"); 1809 } 1810 #endif 1811 1812 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1813 OHCI_SUBREG_ContextControlClear); 1814 1815 if (val & OHCI_CTXCTL_RUN) { 1816 if (fc->fc_branch == NULL) { 1817 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1818 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1819 goto run; 1820 } 1821 *fc->fc_branch = fb->fb_daddr | ndesc; 1822 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1823 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1824 } else { 1825 run: 1826 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1827 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1828 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1829 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1830 } 1831 fc->fc_branch = &fd->fd_branch; 1832 1833 fc->fc_bufcnt++; 1834 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1835 pkt->fp_m = NULL; 1836 return 0; 1837 } 1838 1839 static void 1840 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1841 { 1842 struct fwohci_buf *fb; 1843 struct fwohci_desc *fd; 1844 int i; 1845 1846 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1847 fd = fb->fb_desc; 1848 #ifdef FW_DEBUG 1849 if (fw_verbose > 1) { 1850 printf("fwohci_at_done: %sdesc %ld (%d)", 1851 force ? "force " : "", 1852 (long)(fd - sc->sc_desc), fb->fb_nseg); 1853 for (i = 0; i < fb->fb_nseg * 4; i++) 1854 printf("%s%08x", i&7?" ":"\n ", 1855 ((u_int32_t *)fd)[i]); 1856 printf("\n"); 1857 } 1858 #endif 1859 if (fb->fb_nseg > 2) 1860 fd += fb->fb_nseg - 1; 1861 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1862 break; 1863 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1864 if (fc->fc_branch == &fd->fd_branch) { 1865 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1866 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1867 fc->fc_branch = NULL; 1868 for (i = 0; i < OHCI_LOOP; i++) { 1869 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1870 OHCI_SUBREG_ContextControlClear) & 1871 OHCI_CTXCTL_ACTIVE)) 1872 break; 1873 } 1874 } 1875 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1876 if (fb->fb_nseg > 2) 1877 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1878 fc->fc_bufcnt--; 1879 if (fb->fb_callback != NULL) { 1880 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1881 fb->fb_callback = NULL; 1882 } else if (fb->fb_m != NULL) 1883 m_freem(fb->fb_m); 1884 free(fb, M_DEVBUF); 1885 } 1886 } 1887 1888 /* 1889 * Asynchronous Transmit Reponse -- in response of request packet. 1890 */ 1891 static void 1892 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1893 struct fwohci_pkt *res) 1894 { 1895 1896 if (((*req->fp_trail & 0x001f0000) >> 16) != 1897 OHCI_CTXCTL_EVENT_ACK_PENDING) 1898 return; 1899 1900 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1901 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1902 switch (req->fp_tcode) { 1903 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1904 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1905 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1906 res->fp_hlen = 12; 1907 break; 1908 case IEEE1394_TCODE_READ_REQ_QUAD: 1909 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1910 res->fp_hlen = 16; 1911 res->fp_dlen = 0; 1912 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1913 res->fp_hdr[3] = 1914 *(u_int32_t *)res->fp_iov[0].iov_base; 1915 res->fp_uio.uio_iovcnt = 0; 1916 break; 1917 case IEEE1394_TCODE_READ_REQ_BLOCK: 1918 case IEEE1394_TCODE_LOCK_REQ: 1919 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1920 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1921 else 1922 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1923 res->fp_hlen = 16; 1924 res->fp_dlen = res->fp_uio.uio_resid; 1925 res->fp_hdr[3] = res->fp_dlen << 16; 1926 break; 1927 } 1928 res->fp_hdr[0] |= (res->fp_tcode << 4); 1929 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1930 } 1931 1932 /* 1933 * APPLICATION LAYER SERVICES 1934 */ 1935 1936 /* 1937 * Retrieve Global UID from GUID ROM 1938 */ 1939 static int 1940 fwohci_guidrom_init(struct fwohci_softc *sc) 1941 { 1942 int i, n, off; 1943 u_int32_t val1, val2; 1944 1945 /* Extract the Global UID 1946 */ 1947 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1948 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1949 1950 if (val1 != 0 || val2 != 0) { 1951 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1952 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1953 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1954 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1955 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1956 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1957 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1958 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1959 } else { 1960 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1961 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1962 return -1; 1963 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1964 for (i = 0; i < OHCI_LOOP; i++) { 1965 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1966 if (!(val1 & OHCI_Guid_AddrReset)) 1967 break; 1968 } 1969 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1970 val2 = 0; 1971 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1972 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1973 OHCI_Guid_RdStart); 1974 for (i = 0; i < OHCI_LOOP; i++) { 1975 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1976 if (!(val1 & OHCI_Guid_RdStart)) 1977 break; 1978 } 1979 if (n < off) 1980 continue; 1981 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1982 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1983 val2 |= val1; 1984 } 1985 if (val2 == 0) 1986 return -1; 1987 } 1988 return 0; 1989 } 1990 1991 /* 1992 * Initialization for Configuration ROM (no DMA context) 1993 */ 1994 1995 #define CFR_MAXUNIT 20 1996 1997 struct configromctx { 1998 u_int32_t *ptr; 1999 int curunit; 2000 struct { 2001 u_int32_t *start; 2002 int length; 2003 u_int32_t *refer; 2004 int refunit; 2005 } unit[CFR_MAXUNIT]; 2006 }; 2007 2008 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2009 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2010 2011 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2012 2013 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2014 2015 #define CFR_PUT_CRC(cfr, n) \ 2016 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2017 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2018 2019 #define CFR_START_UNIT(cfr, n) \ 2020 do { \ 2021 if ((cfr)->unit[n].refer != NULL) { \ 2022 *(cfr)->unit[n].refer |= \ 2023 (cfr)->ptr - (cfr)->unit[n].refer; \ 2024 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2025 } \ 2026 (cfr)->curunit = (n); \ 2027 (cfr)->unit[n].start = (cfr)->ptr++; \ 2028 } while (0 /* CONSTCOND */) 2029 2030 #define CFR_PUT_REFER(cfr, key, n) \ 2031 do { \ 2032 (cfr)->unit[n].refer = (cfr)->ptr; \ 2033 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2034 *(cfr)->ptr++ = (key) << 24; \ 2035 } while (0 /* CONSTCOND */) 2036 2037 #define CFR_END_UNIT(cfr) \ 2038 do { \ 2039 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2040 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2041 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2042 } while (0 /* CONSTCOND */) 2043 2044 static u_int16_t 2045 fwohci_crc16(u_int32_t *ptr, int len) 2046 { 2047 int shift; 2048 u_int32_t crc, sum, data; 2049 2050 crc = 0; 2051 while (len-- > 0) { 2052 data = *ptr++; 2053 for (shift = 28; shift >= 0; shift -= 4) { 2054 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2055 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2056 } 2057 crc &= 0xffff; 2058 } 2059 return crc; 2060 } 2061 2062 static void 2063 fwohci_configrom_init(struct fwohci_softc *sc) 2064 { 2065 int i; 2066 struct fwohci_buf *fb; 2067 u_int32_t *hdr; 2068 struct configromctx cfr; 2069 2070 fb = &sc->sc_buf_cnfrom; 2071 memset(&cfr, 0, sizeof(cfr)); 2072 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2073 2074 /* headers */ 2075 CFR_START_UNIT(&cfr, 0); 2076 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2077 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2078 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2079 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2080 CFR_END_UNIT(&cfr); 2081 /* copy info_length from crc_length */ 2082 *hdr |= (*hdr & 0x00ff0000) << 8; 2083 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2084 2085 /* root directory */ 2086 CFR_START_UNIT(&cfr, 1); 2087 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2088 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2089 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2090 /* spt,64,fix,lst,drq */ 2091 #ifdef INET 2092 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2093 #endif /* INET */ 2094 #ifdef INET6 2095 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2096 #endif /* INET6 */ 2097 CFR_END_UNIT(&cfr); 2098 2099 CFR_START_UNIT(&cfr, 2); 2100 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2101 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2102 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2103 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2104 CFR_END_UNIT(&cfr); 2105 2106 #ifdef INET 2107 /* IPv4 unit directory */ 2108 CFR_START_UNIT(&cfr, 3); 2109 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2110 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2111 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2112 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2113 CFR_END_UNIT(&cfr); 2114 2115 CFR_START_UNIT(&cfr, 6); 2116 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2117 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2118 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2119 CFR_END_UNIT(&cfr); 2120 2121 CFR_START_UNIT(&cfr, 7); 2122 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2123 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2124 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2125 CFR_END_UNIT(&cfr); 2126 #endif /* INET */ 2127 2128 #ifdef INET6 2129 /* IPv6 unit directory */ 2130 CFR_START_UNIT(&cfr, 4); 2131 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2132 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2133 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2134 /* XXX: TBA by IANA */ 2135 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2136 CFR_END_UNIT(&cfr); 2137 2138 CFR_START_UNIT(&cfr, 8); 2139 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2140 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2141 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2142 CFR_END_UNIT(&cfr); 2143 2144 CFR_START_UNIT(&cfr, 9); 2145 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2146 CFR_PUT_DATA1(&cfr, 0); 2147 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2148 CFR_END_UNIT(&cfr); 2149 #endif /* INET6 */ 2150 2151 fb->fb_off = cfr.ptr - hdr; 2152 #ifdef FW_DEBUG 2153 if (fw_dump) { 2154 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 2155 for (i = 0; i < fb->fb_off; i++) 2156 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 2157 printf("\n"); 2158 } 2159 #endif /* FW_DEBUG */ 2160 2161 /* 2162 * Make network byte order for DMA 2163 */ 2164 for (i = 0; i < fb->fb_off; i++) 2165 HTONL(hdr[i]); 2166 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2167 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2168 2169 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2170 fb->fb_dmamap->dm_segs[0].ds_addr); 2171 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 2172 2173 /* Just allow quad reads of the rom. */ 2174 for (i = 0; i < fb->fb_off; i++) 2175 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2176 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2177 fwohci_configrom_input, NULL); 2178 } 2179 2180 static int 2181 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2182 struct fwohci_pkt *pkt) 2183 { 2184 struct fwohci_pkt res; 2185 u_int32_t loc, *rom; 2186 2187 /* This will be used as an array index so size accordingly. */ 2188 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2189 if ((loc & 0x03) != 0) { 2190 /* alignment error */ 2191 return IEEE1394_RCODE_ADDRESS_ERROR; 2192 } 2193 else 2194 loc /= 4; 2195 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2196 2197 #ifdef FW_DEBUG 2198 if (fw_verbose > 1) 2199 printf("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", 2200 loc, ntohl(rom[loc])); 2201 #endif 2202 2203 memset(&res, 0, sizeof(res)); 2204 res.fp_hdr[3] = rom[loc]; 2205 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2206 return -1; 2207 } 2208 2209 /* 2210 * SelfID buffer (no DMA context) 2211 */ 2212 static void 2213 fwohci_selfid_init(struct fwohci_softc *sc) 2214 { 2215 struct fwohci_buf *fb; 2216 2217 fb = &sc->sc_buf_selfid; 2218 #ifdef DIAGNOSTICS 2219 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2220 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2221 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2222 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2223 #endif 2224 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2225 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2226 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2227 2228 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2229 fb->fb_dmamap->dm_segs[0].ds_addr); 2230 } 2231 2232 static int 2233 fwohci_selfid_input(struct fwohci_softc *sc) 2234 { 2235 int i; 2236 u_int32_t count, val, gen; 2237 u_int32_t *buf; 2238 2239 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2240 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2241 again: 2242 if (val & OHCI_SelfID_Error) { 2243 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2244 return -1; 2245 } 2246 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2247 2248 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2249 0, count << 2, BUS_DMASYNC_POSTREAD); 2250 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2251 2252 #ifdef FW_DEBUG 2253 if (fw_verbose > 1) { 2254 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2255 val); 2256 for (i = 0; i < count; i++) 2257 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2258 printf("\n"); 2259 } 2260 #endif /* FW_DEBUG */ 2261 2262 for (i = 1; i < count; i += 2) { 2263 if (buf[i] != ~buf[i + 1]) 2264 break; 2265 if (buf[i] & 0x00000001) 2266 continue; /* more pkt */ 2267 if (buf[i] & 0x00800000) 2268 continue; /* external id */ 2269 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2270 if ((buf[i] & 0x00400800) == 0x00400800) 2271 sc->sc_irmid = sc->sc_rootid; 2272 } 2273 2274 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2275 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2276 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2277 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2278 goto again; 2279 #ifdef FW_DEBUG 2280 if (fw_verbose) 2281 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2282 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2283 OHCI_BITVAL(val, OHCI_SelfID_Gen)); 2284 #endif 2285 return -1; 2286 } 2287 if (i != count) { 2288 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2289 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2290 #if 1 2291 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2292 /* 2293 * XXX: CXD3222 sometimes fails to DMA 2294 * selfid packet?? 2295 */ 2296 sc->sc_rootid = (count - 1) / 2 - 1; 2297 sc->sc_irmid = sc->sc_rootid; 2298 } else 2299 #endif 2300 return -1; 2301 } 2302 2303 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2304 if ((val & OHCI_NodeId_IDValid) == 0) { 2305 sc->sc_nodeid = 0xffff; /* invalid */ 2306 printf("%s: nodeid is invalid\n", 2307 sc->sc_sc1394.sc1394_dev.dv_xname); 2308 return -1; 2309 } 2310 sc->sc_nodeid = val & 0xffff; 2311 2312 #ifdef FW_DEBUG 2313 if (fw_verbose) 2314 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2315 sc->sc_sc1394.sc1394_dev.dv_xname, 2316 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2317 sc->sc_rootid, sc->sc_irmid); 2318 #endif 2319 2320 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2321 return -1; 2322 2323 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2324 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2325 OHCI_LinkControl_CycleMaster); 2326 else 2327 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2328 OHCI_LinkControl_CycleMaster); 2329 return 0; 2330 } 2331 2332 /* 2333 * some CSRs are handled by driver. 2334 */ 2335 static void 2336 fwohci_csr_init(struct fwohci_softc *sc) 2337 { 2338 int i; 2339 static u_int32_t csr[] = { 2340 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2341 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2342 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2343 CSR_SB_BROADCAST_CHANNEL 2344 }; 2345 2346 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2347 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2348 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2349 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2350 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2351 } 2352 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2353 } 2354 2355 static int 2356 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2357 { 2358 struct fwohci_pkt res; 2359 u_int32_t reg; 2360 2361 /* 2362 * XXX need to do special functionality other than just r/w... 2363 */ 2364 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2365 2366 if ((reg & 0x03) != 0) { 2367 /* alignment error */ 2368 return IEEE1394_RCODE_ADDRESS_ERROR; 2369 } 2370 #ifdef FW_DEBUG 2371 if (fw_verbose > 1) 2372 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2373 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2374 #endif 2375 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2376 #ifdef FW_DEBUG 2377 if (fw_verbose > 1) 2378 printf(" -> 0x%08x\n", 2379 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2380 #endif 2381 *(u_int32_t *)&sc->sc_csr[reg] = 2382 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2383 } else { 2384 #ifdef FW_DEBUG 2385 if (fw_verbose > 1) 2386 printf("\n"); 2387 #endif 2388 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2389 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2390 res.fp_iov[0].iov_len = 4; 2391 res.fp_uio.uio_resid = 4; 2392 res.fp_uio.uio_iovcnt = 1; 2393 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2394 return -1; 2395 } 2396 return IEEE1394_RCODE_COMPLETE; 2397 } 2398 2399 /* 2400 * Mapping between nodeid and unique ID (EUI-64). 2401 * 2402 * Track old mappings and simply update their devices with the new id's when 2403 * they match an existing EUI. This allows proper renumeration of the bus. 2404 */ 2405 static void 2406 fwohci_uid_collect(struct fwohci_softc *sc) 2407 { 2408 int i; 2409 struct fwohci_uidtbl *fu; 2410 struct fwohci_pkt pkt; 2411 struct ieee1394_softc *iea; 2412 2413 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2414 iea->sc1394_node_id = 0xffff; 2415 2416 if (sc->sc_uidtbl != NULL) 2417 free(sc->sc_uidtbl, M_DEVBUF); 2418 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2419 M_WAITOK); 2420 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2421 2422 memset(&pkt, 0, sizeof(pkt)); 2423 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2424 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2425 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2426 fu->fu_valid = 3; 2427 2428 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2429 if (iea) { 2430 iea->sc1394_node_id = i; 2431 #ifdef FW_DEBUG 2432 if (fw_verbose) 2433 printf("%s: Updating nodeid to %d\n", 2434 iea->sc1394_dev.dv_xname, 2435 iea->sc1394_node_id); 2436 #endif 2437 } 2438 continue; 2439 } 2440 fu->fu_valid = 0; 2441 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2442 pkt.fp_hlen = 12; 2443 pkt.fp_dlen = 0; 2444 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2445 (pkt.fp_tcode << 4); 2446 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2447 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2448 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2449 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2450 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2451 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2452 2453 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2454 (pkt.fp_tcode << 4); 2455 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2456 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2457 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2458 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2459 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2460 2461 } 2462 if (sc->sc_rootid == 0) 2463 fwohci_check_nodes(sc); 2464 2465 } 2466 2467 static int 2468 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2469 { 2470 struct fwohci_uidtbl *fu; 2471 struct ieee1394_softc *iea; 2472 struct ieee1394_attach_args fwa; 2473 int i, n, done, rcode, found; 2474 2475 found = 0; 2476 2477 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2478 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2479 if (rcode != IEEE1394_RCODE_COMPLETE || 2480 sc->sc_uidtbl == NULL || 2481 n > sc->sc_rootid) 2482 return 0; 2483 fu = &sc->sc_uidtbl[n]; 2484 if (arg == 0) { 2485 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2486 fu->fu_valid |= 0x1; 2487 } else { 2488 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2489 fu->fu_valid |= 0x2; 2490 } 2491 #ifdef FW_DEBUG 2492 if ((fw_verbose > 1) && fu->fu_valid == 0x3) 2493 printf("fwohci_uid_input: " 2494 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2495 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2496 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2497 #endif 2498 if (fu->fu_valid == 0x3) { 2499 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2500 if (memcmp (iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2501 found = 1; 2502 iea->sc1394_node_id = n; 2503 #ifdef FW_DEBUG 2504 if (fw_verbose) 2505 printf("%s: Updating nodeid to %d\n", 2506 iea->sc1394_dev.dv_xname, 2507 iea->sc1394_node_id); 2508 #endif 2509 break; 2510 } 2511 if (!found) { 2512 strcpy (fwa.name, "fwnode"); 2513 memcpy (fwa.uid, fu->fu_uid, 8); 2514 fwa.nodeid = n; 2515 fwa.input = fwohci_input; 2516 fwa.output = fwohci_output; 2517 fwa.inreg = fwohci_inreg; 2518 iea = (struct ieee1394_softc *) 2519 config_found(&sc->sc_sc1394.sc1394_dev, &fwa, 2520 fwohci_print); 2521 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, sc1394_node); 2522 } 2523 } 2524 done = 1; 2525 2526 for (i = 0; i < sc->sc_rootid + 1; i++) { 2527 fu = &sc->sc_uidtbl[i]; 2528 if (fu->fu_valid != 0x3) { 2529 done = 0; 2530 break; 2531 } 2532 } 2533 if (done) 2534 fwohci_check_nodes(sc); 2535 2536 return 0; 2537 } 2538 2539 static void 2540 fwohci_check_nodes(struct fwohci_softc *sc) 2541 { 2542 struct device *detach = NULL; 2543 struct ieee1394_softc *iea; 2544 2545 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2546 /* 2547 * Have to defer detachment until the next 2548 * loop iteration since config_detach 2549 * free's the softc and the loop iterator 2550 * needs data from the softc to move 2551 * forward. 2552 */ 2553 2554 if (detach) { 2555 config_detach (detach, 0); 2556 detach = NULL; 2557 } 2558 if (iea->sc1394_node_id == 0xffff) { 2559 detach = (struct device *)iea; 2560 LIST_REMOVE(iea, sc1394_node); 2561 } 2562 } 2563 if (detach) 2564 config_detach (detach, 0); 2565 } 2566 2567 static int 2568 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2569 { 2570 struct fwohci_uidtbl *fu; 2571 int n; 2572 static const u_int8_t bcast[] = 2573 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2574 2575 fu = sc->sc_uidtbl; 2576 if (fu == NULL) { 2577 notfound: 2578 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2579 return IEEE1394_BCAST_PHY_ID; 2580 fwohci_uid_collect(sc); /* try to get */ 2581 return -1; 2582 } 2583 for (n = 0; ; n++, fu++) { 2584 if (n > sc->sc_rootid) 2585 goto notfound; 2586 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2587 break; 2588 } 2589 return n; 2590 } 2591 2592 /* 2593 * functions to support network interface 2594 */ 2595 static int 2596 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2597 void (*handler)(struct device *, struct mbuf *)) 2598 { 2599 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2600 2601 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2602 fwohci_if_input, handler); 2603 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2604 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2605 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2606 return 0; 2607 } 2608 2609 static int 2610 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2611 { 2612 int n, len; 2613 struct mbuf *m; 2614 struct iovec *iov; 2615 void (*handler)(struct device *, struct mbuf *) = arg; 2616 2617 #ifdef FW_DEBUG 2618 if (fw_verbose > 1) { 2619 int i; 2620 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2621 pkt->fp_tcode, pkt->fp_dlen); 2622 if (fw_dump) { 2623 for (i = 0; i < pkt->fp_hlen/4; i++) 2624 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2625 printf("$"); 2626 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2627 iov = &pkt->fp_iov[n]; 2628 for (i = 0; i < iov->iov_len; i++) 2629 printf("%s%02x", 2630 (i%32)?((i%4)?"":" "):"\n\t", 2631 ((u_int8_t *)iov->iov_base)[i]); 2632 printf("$"); 2633 } 2634 } 2635 printf("\n"); 2636 } 2637 #endif /* FW_DEBUG */ 2638 len = pkt->fp_dlen; 2639 MGETHDR(m, M_DONTWAIT, MT_DATA); 2640 if (m == NULL) 2641 return IEEE1394_RCODE_COMPLETE; 2642 m->m_len = 16; 2643 if (len + m->m_len > MHLEN) { 2644 MCLGET(m, M_DONTWAIT); 2645 if ((m->m_flags & M_EXT) == 0) { 2646 m_freem(m); 2647 return IEEE1394_RCODE_COMPLETE; 2648 } 2649 } 2650 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2651 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2652 sc->sc_uidtbl[n].fu_valid != 0x3) { 2653 printf("%s: packet from unknown node: phy id %d\n", 2654 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2655 m_freem(m); 2656 return IEEE1394_RCODE_COMPLETE; 2657 } 2658 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2659 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2660 m->m_flags |= M_BCAST; 2661 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2662 } else { 2663 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2664 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2665 } 2666 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2667 mtod(m, u_int8_t *)[9] = 2668 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2669 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2670 2671 m->m_pkthdr.rcvif = NULL; /* set in child */ 2672 m->m_pkthdr.len = len + m->m_len; 2673 /* 2674 * We may use receive buffer by external mbuf instead of copy here. 2675 * But asynchronous receive buffer must be operate in buffer fill 2676 * mode, so that each receive buffer will shared by multiple mbufs. 2677 * If upper layer doesn't free mbuf soon, e.g. application program 2678 * is suspended, buffer must be reallocated. 2679 * Isochronous buffer must be operate in packet buffer mode, and 2680 * it is easy to map receive buffer to external mbuf. But it is 2681 * used for broadcast/multicast only, and is expected not so 2682 * performance sensitive for now. 2683 * XXX: The performance may be important for multicast case, 2684 * so we should revisit here later. 2685 * -- onoe 2686 */ 2687 n = 0; 2688 iov = pkt->fp_uio.uio_iov; 2689 while (len > 0) { 2690 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2691 iov->iov_len); 2692 m->m_len += iov->iov_len; 2693 len -= iov->iov_len; 2694 iov++; 2695 } 2696 (*handler)(sc->sc_sc1394.sc1394_if, m); 2697 return IEEE1394_RCODE_COMPLETE; 2698 } 2699 2700 static int 2701 fwohci_if_output(struct device *self, struct mbuf *m0, 2702 void (*callback)(struct device *, struct mbuf *)) 2703 { 2704 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2705 struct fwohci_pkt pkt; 2706 u_int8_t *p; 2707 int n, error, spd, hdrlen, maxrec; 2708 2709 p = mtod(m0, u_int8_t *); 2710 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2711 spd = IEEE1394_SPD_S100; /*XXX*/ 2712 maxrec = 512; /*XXX*/ 2713 hdrlen = 8; 2714 } else { 2715 n = fwohci_uid_lookup(sc, p); 2716 if (n < 0) { 2717 printf("%s: nodeid unknown:" 2718 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2719 sc->sc_sc1394.sc1394_dev.dv_xname, 2720 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2721 error = EHOSTUNREACH; 2722 goto end; 2723 } 2724 if (n == IEEE1394_BCAST_PHY_ID) { 2725 printf("%s: broadcast with !M_MCAST\n", 2726 sc->sc_sc1394.sc1394_dev.dv_xname); 2727 #ifdef FW_DEBUG 2728 if (fw_dump) { 2729 struct mbuf *m; 2730 printf("packet:"); 2731 for (m = m0; m != NULL; m = m->m_next) { 2732 for (n = 0; n < m->m_len; n++) 2733 printf("%s%02x", (n%32)? 2734 ((n%4)?"":" "):"\n\t", 2735 mtod(m, u_int8_t *)[n]); 2736 printf("$"); 2737 } 2738 printf("\n"); 2739 } 2740 #endif 2741 error = EHOSTUNREACH; 2742 goto end; 2743 } 2744 maxrec = 2 << p[8]; 2745 spd = p[9]; 2746 hdrlen = 0; 2747 } 2748 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2749 #ifdef FW_DEBUG 2750 if (fw_verbose) 2751 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2752 spd, sc->sc_sc1394.sc1394_link_speed); 2753 #endif 2754 spd = sc->sc_sc1394.sc1394_link_speed; 2755 } 2756 if (maxrec > (512 << spd)) { 2757 #ifdef FW_DEBUG 2758 if (fw_verbose) 2759 printf("fwohci_if_output: maxrec (%d) is larger for" 2760 " spd (%d)\n", maxrec, spd); 2761 #endif 2762 maxrec = 512 << spd; 2763 } 2764 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2765 #ifdef FW_DEBUG 2766 if (fw_verbose) 2767 printf("fwohci_if_output: maxrec (%d) is larger than" 2768 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2769 #endif 2770 maxrec >>= 1; 2771 } 2772 if (maxrec < 512) { 2773 #ifdef FW_DEBUG 2774 if (fw_verbose) 2775 printf("fwohci_if_output: maxrec (%d) is smaller" 2776 " than minimum\n", maxrec); 2777 #endif 2778 maxrec = 512; 2779 } 2780 2781 m_adj(m0, 16 - hdrlen); 2782 if (m0->m_pkthdr.len > maxrec) { 2783 #ifdef FW_DEBUG 2784 if (fw_verbose) 2785 printf("fwohci_if_output: packet too big:" 2786 " hdr %d, pktlen %d, maxrec %d\n", 2787 hdrlen, m0->m_pkthdr.len, maxrec); 2788 #endif 2789 error = E2BIG; /*XXX*/ 2790 goto end; 2791 } 2792 2793 memset(&pkt, 0, sizeof(pkt)); 2794 pkt.fp_uio.uio_iov = pkt.fp_iov; 2795 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2796 pkt.fp_uio.uio_rw = UIO_WRITE; 2797 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2798 /* construct GASP header */ 2799 p = mtod(m0, u_int8_t *); 2800 p[0] = sc->sc_nodeid >> 8; 2801 p[1] = sc->sc_nodeid & 0xff; 2802 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2803 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2804 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2805 pkt.fp_hlen = 8; 2806 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2807 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2808 OHCI_NodeId_NodeNumber) << 8); 2809 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2810 } else { 2811 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2812 pkt.fp_hlen = 16; 2813 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2814 (spd << 16); 2815 pkt.fp_hdr[1] = 2816 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2817 (p[10] << 8) | p[11]; 2818 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2819 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2820 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2821 } 2822 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2823 pkt.fp_dlen = m0->m_pkthdr.len; 2824 pkt.fp_m = m0; 2825 pkt.fp_callback = callback; 2826 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2827 m0 = pkt.fp_m; 2828 end: 2829 if (m0 != NULL) { 2830 if (callback) 2831 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2832 else 2833 m_freem(m0); 2834 } 2835 return error; 2836 } 2837 2838 /* 2839 * High level routines to provide abstraction to attaching layers to 2840 * send/receive data. 2841 */ 2842 2843 static int 2844 fwohci_input(struct ieee1394_abuf *ab) 2845 { 2846 struct fwohci_pkt pkt; 2847 struct ieee1394_softc *sc = ab->ab_node; 2848 struct fwohci_softc *psc = 2849 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2850 u_int32_t high, lo; 2851 int rv, tcode; 2852 2853 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2854 lo = (ab->ab_csr & 0x00000000ffffffff); 2855 2856 memset(&pkt, 0, sizeof(pkt)); 2857 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | high; 2858 pkt.fp_hdr[2] = lo; 2859 pkt.fp_dlen = 0; 2860 2861 if (ab->ab_length == 4) { 2862 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2863 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2864 pkt.fp_hlen = 12; 2865 } else { 2866 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2867 pkt.fp_hlen = 16; 2868 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2869 pkt.fp_hdr[3] = (ab->ab_length << 16); 2870 } 2871 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2872 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2873 2874 rv = fwohci_handler_set(psc, tcode, ab->ab_node->sc1394_node_id, 2875 psc->sc_tlabel, fwohci_extract_resp, ab); 2876 if (rv) 2877 return rv; 2878 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2879 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2880 return rv; 2881 } 2882 2883 static int 2884 fwohci_output(struct ieee1394_abuf *ab) 2885 { 2886 struct fwohci_pkt pkt; 2887 struct ieee1394_softc *sc = ab->ab_node; 2888 struct fwohci_softc *psc = 2889 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2890 u_int32_t high, lo; 2891 int rv; 2892 2893 if (ab->ab_length > sc->sc1394_max_receive) { 2894 #ifdef FW_DEBUG 2895 if (fw_verbose) 2896 printf("Packet too large: %d\n", ab->ab_length); 2897 #endif 2898 return E2BIG; 2899 } 2900 2901 memset(&pkt, 0, sizeof(pkt)); 2902 2903 pkt.fp_tcode = ab->ab_tcode; 2904 pkt.fp_uio.uio_iov = pkt.fp_iov; 2905 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2906 pkt.fp_uio.uio_rw = UIO_WRITE; 2907 2908 switch (ab->ab_tcode) { 2909 case IEEE1394_TCODE_WRITE_RESP: 2910 pkt.fp_hlen = 12; 2911 case IEEE1394_TCODE_READ_RESP_QUAD: 2912 case IEEE1394_TCODE_READ_RESP_BLOCK: 2913 if (!pkt.fp_hlen) 2914 pkt.fp_hlen = 16; 2915 high = ab->ab_retlen; 2916 ab->ab_retlen = 0; 2917 lo = 0; 2918 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2919 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2920 break; 2921 default: 2922 pkt.fp_hlen = 16; 2923 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2924 lo = (ab->ab_csr & 0x00000000ffffffff); 2925 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2926 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2927 break; 2928 } 2929 2930 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | high; 2931 pkt.fp_hdr[2] = lo; 2932 if (pkt.fp_hlen == 16) { 2933 if (ab->ab_length == 4) { 2934 pkt.fp_hdr[3] = ab->ab_data[0]; 2935 pkt.fp_dlen = 0; 2936 } else { 2937 pkt.fp_hdr[3] = (ab->ab_length << 16); 2938 pkt.fp_dlen = ab->ab_length; 2939 pkt.fp_uio.uio_iovcnt = 1; 2940 pkt.fp_uio.uio_resid = ab->ab_length; 2941 pkt.fp_iov[0].iov_base = ab->ab_data; 2942 pkt.fp_iov[0].iov_len = ab->ab_length; 2943 } 2944 } 2945 switch (ab->ab_tcode) { 2946 case IEEE1394_TCODE_WRITE_RESP: 2947 case IEEE1394_TCODE_READ_RESP_QUAD: 2948 case IEEE1394_TCODE_READ_RESP_BLOCK: 2949 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2950 break; 2951 default: 2952 rv = fwohci_handler_set(psc, IEEE1394_TCODE_WRITE_RESP, 2953 ab->ab_node->sc1394_node_id, psc->sc_tlabel, fwohci_extract_resp, 2954 ab); 2955 if (rv) 2956 return rv; 2957 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2958 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2959 break; 2960 } 2961 return rv; 2962 } 2963 2964 static int 2965 fwohci_extract_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2966 { 2967 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 2968 struct fwohci_pkt newpkt; 2969 u_int32_t *cur, high, lo; 2970 int i, rcode, rv; 2971 2972 /* No callback just means we want to have something clean up the abuf. */ 2973 if (!ab->ab_cb) { 2974 if (ab->ab_data) 2975 free (ab->ab_data, M_1394DATA); 2976 if (ab) 2977 free (ab, M_1394DATA); 2978 return 0; 2979 } 2980 2981 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2982 2983 /* Some area's (like the config rom want to be read as quadlets only. */ 2984 2985 if (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2986 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2987 (pkt->fp_tcode == IEEE1394_TCODE_READ_RESP_BLOCK)) { 2988 2989 /* Read the area in quadlet chunks (internally track this). */ 2990 2991 memset(&newpkt, 0, sizeof(newpkt)); 2992 2993 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2994 lo = (ab->ab_csr & 0x00000000ffffffff); 2995 2996 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2997 newpkt.fp_hlen = 12; 2998 newpkt.fp_dlen = 0; 2999 newpkt.fp_hdr[1] = ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | 3000 high; 3001 newpkt.fp_hdr[2] = lo; 3002 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3003 (newpkt.fp_tcode << 4); 3004 3005 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3006 ab->ab_node->sc1394_node_id, sc->sc_tlabel, 3007 fwohci_multi_resp, ab); 3008 if (rv) 3009 return rv; 3010 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3011 printf("Calling at_output\n"); 3012 fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3013 } else { 3014 3015 /* Recombine all the iov data into 1 chunk for higher level code. */ 3016 3017 cur = ab->ab_data; 3018 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3019 /* Make sure and don't exceed the buffer allocated for return. */ 3020 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > ab->ab_length) { 3021 memcpy(cur, pkt->fp_iov[i].iov_base, 3022 (ab->ab_length - ab->ab_retlen)); 3023 ab->ab_retlen = ab->ab_length; 3024 break; 3025 } 3026 memcpy (cur, pkt->fp_iov[i].iov_base, pkt->fp_iov[i].iov_len); 3027 cur += pkt->fp_iov[i].iov_len; 3028 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3029 } 3030 (*ab->ab_cb)(ab, rcode); 3031 } 3032 return IEEE1394_RCODE_COMPLETE; 3033 } 3034 3035 static int 3036 fwohci_multi_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3037 { 3038 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3039 struct fwohci_pkt newpkt; 3040 u_int32_t high, lo; 3041 int rcode, rv; 3042 3043 /* 3044 * Bad return codes from the wire, just return what's already in the 3045 * buf. 3046 */ 3047 3048 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3049 3050 if (rcode) { 3051 (*ab->ab_cb)(ab, rcode); 3052 return rcode; 3053 } 3054 3055 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3056 memcpy(((char *)ab->ab_data + ab->ab_retlen), pkt->fp_iov[0].iov_base, 3057 (ab->ab_length - ab->ab_retlen)); 3058 ab->ab_retlen = ab->ab_length; 3059 } else { 3060 memcpy(((char *)ab->ab_data + ab->ab_retlen), pkt->fp_iov[0].iov_base, 3061 4); 3062 ab->ab_retlen += 4; 3063 } 3064 /* Still more, loop and read 4 more bytes. */ 3065 if (ab->ab_retlen < ab->ab_length) { 3066 memset(&newpkt, 0, sizeof(newpkt)); 3067 3068 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3069 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3070 3071 3072 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3073 newpkt.fp_hlen = 12; 3074 newpkt.fp_dlen = 0; 3075 newpkt.fp_hdr[1] = ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | 3076 high; 3077 newpkt.fp_hdr[2] = lo; 3078 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3079 (newpkt.fp_tcode << 4); 3080 3081 /* Bad return code..Just give up and return what's come in now. */ 3082 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3083 ab->ab_node->sc1394_node_id, sc->sc_tlabel, 3084 fwohci_multi_resp, ab); 3085 if (rv) { 3086 (*ab->ab_cb)(ab, rcode); 3087 return IEEE1394_RCODE_DATA_ERROR; 3088 } 3089 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3090 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3091 if (rv) { 3092 (*ab->ab_cb)(ab, rcode); 3093 return IEEE1394_RCODE_DATA_ERROR; 3094 } 3095 } else 3096 (*ab->ab_cb)(ab, rcode); 3097 return IEEE1394_RCODE_COMPLETE; 3098 } 3099 3100 static int 3101 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3102 { 3103 struct ieee1394_softc *sc = ab->ab_node; 3104 struct fwohci_softc *psc = 3105 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3106 u_int32_t high, lo; 3107 int i, rv; 3108 3109 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3110 lo = (ab->ab_csr & 0x00000000ffffffff); 3111 3112 switch (ab->ab_tcode) { 3113 case IEEE1394_TCODE_READ_REQ_QUAD: 3114 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3115 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, fwohci_parse_input, 3116 ab); 3117 break; 3118 case IEEE1394_TCODE_READ_REQ_BLOCK: 3119 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3120 if (allow) { 3121 for (i = 0; i < (ab->ab_length / 4); i++) { 3122 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo + (i * 4), 3123 fwohci_parse_input, ab); 3124 if (rv) 3125 return rv; 3126 } 3127 ab->ab_data = (void *)1; 3128 } else 3129 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3130 fwohci_parse_input, ab); 3131 break; 3132 default: 3133 #ifdef FW_DEBUG 3134 if (fw_verbose) 3135 printf("Invalid registration tcode: %d\n", ab->ab_tcode); 3136 #endif 3137 return -1; 3138 break; 3139 } 3140 return rv; 3141 } 3142 3143 static int 3144 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3145 { 3146 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3147 u_int64_t csr; 3148 u_int32_t *cur; 3149 int i, count; 3150 3151 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3152 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3153 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3154 3155 switch (ab->ab_tcode) { 3156 case IEEE1394_TCODE_READ_REQ_QUAD: 3157 ab->ab_retlen = 4; 3158 break; 3159 case IEEE1394_TCODE_READ_REQ_BLOCK: 3160 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3161 printf("csr: 0x%016qx retlen: %d\n", csr, ab->ab_retlen); 3162 if (ab->ab_data) { 3163 if ((csr + ab->ab_retlen) > (ab->ab_csr + ab->ab_length)) 3164 return IEEE1394_RCODE_ADDRESS_ERROR; 3165 ab->ab_data = NULL; 3166 } else 3167 if (ab->ab_retlen != ab->ab_length) 3168 return IEEE1394_RCODE_ADDRESS_ERROR; 3169 break; 3170 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3171 ab->ab_retlen = 4; 3172 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3173 if (!ab->ab_retlen) 3174 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3175 if (ab->ab_data) { 3176 if ((csr + ab->ab_retlen) > (ab->ab_csr + ab->ab_length)) 3177 return IEEE1394_RCODE_ADDRESS_ERROR; 3178 ab->ab_data = NULL; 3179 } else 3180 if (ab->ab_retlen != ab->ab_length) 3181 return IEEE1394_RCODE_ADDRESS_ERROR; 3182 3183 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3184 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3185 ab->ab_data[0] = pkt->fp_hdr[3]; 3186 else { 3187 count = 0; 3188 cur = ab->ab_data; 3189 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3190 memcpy (cur, pkt->fp_iov[i].iov_base, pkt->fp_iov[i].iov_len); 3191 cur += pkt->fp_iov[i].iov_len; 3192 count += pkt->fp_iov[i].iov_len; 3193 } 3194 if (ab->ab_retlen != count) 3195 panic ("Packet claims %d length but only %d bytes returned\n", 3196 ab->ab_retlen, count); 3197 } 3198 break; 3199 default: 3200 panic("Got a callback for a tcode that wasn't requested: %d\n", 3201 ab->ab_tcode); 3202 break; 3203 } 3204 ab->ab_csr = csr; 3205 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3206 return -1; 3207 } 3208
Indexes created Wed Sep 24 05:09:52 GMT 2025