fwohci.c revision 1.26
1 /* $NetBSD: fwohci.c,v 1.26 2001/05/01 06:15:42 enami Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 115 void *); 116 117 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 119 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 120 121 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 122 struct fwohci_pkt *); 123 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 124 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 125 struct fwohci_pkt *); 126 127 static int fwohci_guidrom_init(struct fwohci_softc *); 128 static void fwohci_configrom_init(struct fwohci_softc *); 129 static int fwohci_configrom_input(struct fwohci_softc *, void *, 130 struct fwohci_pkt *); 131 static void fwohci_selfid_init(struct fwohci_softc *); 132 static int fwohci_selfid_input(struct fwohci_softc *); 133 134 static void fwohci_csr_init(struct fwohci_softc *); 135 static int fwohci_csr_input(struct fwohci_softc *, void *, 136 struct fwohci_pkt *); 137 138 static void fwohci_uid_collect(struct fwohci_softc *); 139 static int fwohci_uid_input(struct fwohci_softc *, void *, 140 struct fwohci_pkt *); 141 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 142 static void fwohci_check_nodes(struct fwohci_softc *); 143 144 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 145 void (*)(struct device *, struct mbuf *)); 146 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 147 static int fwohci_if_output(struct device *, struct mbuf *, 148 void (*)(struct device *, struct mbuf *)); 149 static int fwohci_input(struct ieee1394_abuf *); 150 static int fwohci_output(struct ieee1394_abuf *); 151 static int fwohci_extract_resp(struct fwohci_softc *, void *, 152 struct fwohci_pkt *); 153 static int fwohci_multi_resp(struct fwohci_softc *, void *, 154 struct fwohci_pkt *); 155 static int fwohci_inreg(struct ieee1394_abuf *, int); 156 static int fwohci_parse_input(struct fwohci_softc *, void *, 157 struct fwohci_pkt *); 158 159 #ifdef FW_DEBUG 160 int fw_verbose = 1; 161 int fw_dump = 1; 162 #endif 163 164 int 165 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 166 { 167 int i; 168 u_int32_t val; 169 #if 0 170 int error; 171 #endif 172 173 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 174 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 175 176 /* 177 * Wait for reset completion 178 */ 179 for (i = 0; i < OHCI_LOOP; i++) { 180 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 181 if ((val & OHCI_HCControl_SoftReset) == 0) 182 break; 183 } 184 185 /* What dialect of OHCI is this device? 186 */ 187 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 188 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 189 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 190 191 LIST_INIT(&sc->sc_nodelist); 192 193 if (fwohci_guidrom_init(sc) != 0) { 194 printf("\n%s: fatal: no global UID ROM\n", 195 sc->sc_sc1394.sc1394_dev.dv_xname); 196 return -1; 197 } 198 199 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 200 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 201 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 202 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 203 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 204 205 /* Get the maximum link speed and receive size 206 */ 207 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 208 sc->sc_sc1394.sc1394_link_speed = 209 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 210 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 211 printf(", %s", 212 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 213 } else { 214 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 215 } 216 217 /* MaxRec is encoded as log2(max_rec_octets)-1 218 */ 219 sc->sc_sc1394.sc1394_max_receive = 220 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 221 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 222 223 /* 224 * Count how many isochronous ctx we have. 225 */ 226 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 227 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 228 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 229 for (i = 0; val != 0; val >>= 1) { 230 if (val & 0x1) 231 i++; 232 } 233 sc->sc_isoctx = i; 234 printf(", %d iso_ctx", sc->sc_isoctx); 235 236 printf("\n"); 237 238 #if 0 239 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 240 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 241 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 242 return error; 243 #endif 244 245 sc->sc_dying = 0; 246 247 kthread_create(fwohci_create_event_thread, sc); 248 return 0; 249 } 250 251 int 252 fwohci_intr(void *arg) 253 { 254 struct fwohci_softc * const sc = arg; 255 int progress = 0; 256 u_int32_t intmask, iso; 257 258 for (;;) { 259 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 260 261 /* 262 * On a bus reset, everything except bus reset gets 263 * cleared. That can't get cleared until the selfid 264 * phase completes (which happens outside the 265 * interrupt routines). So if just a bus reset is left 266 * in the mask and it's already in the sc_intmask, 267 * just return. 268 */ 269 270 if ((intmask == 0) || 271 (progress && (intmask == OHCI_Int_BusReset) && 272 (sc->sc_intmask & OHCI_Int_BusReset))) { 273 if (progress) 274 wakeup(fwohci_event_thread); 275 return progress; 276 } 277 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 278 intmask & ~OHCI_Int_BusReset); 279 #ifdef FW_DEBUG 280 if (fw_verbose > 1) { 281 printf("%s: intmask=0x%08x:", 282 sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 283 if (intmask & OHCI_Int_CycleTooLong) 284 printf(" CycleTooLong"); 285 if (intmask & OHCI_Int_UnrecoverableError) 286 printf(" UnrecoverableError"); 287 if (intmask & OHCI_Int_CycleInconsistent) 288 printf(" CycleInconsistent"); 289 if (intmask & OHCI_Int_BusReset) 290 printf(" BusReset"); 291 if (intmask & OHCI_Int_SelfIDComplete) 292 printf(" SelfIDComplete"); 293 if (intmask & OHCI_Int_LockRespErr) 294 printf(" LockRespErr"); 295 if (intmask & OHCI_Int_PostedWriteErr) 296 printf(" PostedWriteErr"); 297 if (intmask & OHCI_Int_ReqTxComplete) 298 printf(" ReqTxComplete(0x%04x)", 299 OHCI_ASYNC_DMA_READ(sc, 300 OHCI_CTX_ASYNC_TX_REQUEST, 301 OHCI_SUBREG_ContextControlClear)); 302 if (intmask & OHCI_Int_RespTxComplete) 303 printf(" RespTxComplete(0x%04x)", 304 OHCI_ASYNC_DMA_READ(sc, 305 OHCI_CTX_ASYNC_TX_RESPONSE, 306 OHCI_SUBREG_ContextControlClear)); 307 if (intmask & OHCI_Int_ARRS) 308 printf(" ARRS(0x%04x)", 309 OHCI_ASYNC_DMA_READ(sc, 310 OHCI_CTX_ASYNC_RX_RESPONSE, 311 OHCI_SUBREG_ContextControlClear)); 312 if (intmask & OHCI_Int_ARRQ) 313 printf(" ARRQ(0x%04x)", 314 OHCI_ASYNC_DMA_READ(sc, 315 OHCI_CTX_ASYNC_RX_REQUEST, 316 OHCI_SUBREG_ContextControlClear)); 317 if (intmask & OHCI_Int_IsochRx) 318 printf(" IsochRx(0x%08x)", 319 OHCI_CSR_READ(sc, 320 OHCI_REG_IsoRecvIntEventClear)); 321 if (intmask & OHCI_Int_IsochTx) 322 printf(" IsochTx(0x%08x)", 323 OHCI_CSR_READ(sc, 324 OHCI_REG_IsoXmitIntEventClear)); 325 if (intmask & OHCI_Int_RQPkt) 326 printf(" RQPkt(0x%04x)", 327 OHCI_ASYNC_DMA_READ(sc, 328 OHCI_CTX_ASYNC_RX_REQUEST, 329 OHCI_SUBREG_ContextControlClear)); 330 if (intmask & OHCI_Int_RSPkt) 331 printf(" RSPkt(0x%04x)", 332 OHCI_ASYNC_DMA_READ(sc, 333 OHCI_CTX_ASYNC_RX_RESPONSE, 334 OHCI_SUBREG_ContextControlClear)); 335 printf("\n"); 336 } 337 #endif /* FW_DEBUG */ 338 if (intmask & OHCI_Int_BusReset) { 339 /* 340 * According to OHCI spec 6.1.1 "busReset", 341 * All asynchronous transmit must be stopped before 342 * clearing BusReset. Moreover, the BusReset 343 * interrupt bit should not be cleared during the 344 * SelfID phase. Thus we turned off interrupt mask 345 * bit of BusReset instead until SelfID completion 346 * or SelfID timeout. 347 */ 348 intmask &= OHCI_Int_SelfIDComplete; 349 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 350 OHCI_Int_BusReset); 351 sc->sc_intmask = intmask; 352 sc->sc_intmask |= OHCI_Int_BusReset; 353 } 354 355 if (intmask & OHCI_Int_SelfIDComplete) 356 sc->sc_intmask |= OHCI_Int_SelfIDComplete; 357 358 if (intmask & OHCI_Int_ReqTxComplete) 359 sc->sc_intmask |= OHCI_Int_ReqTxComplete; 360 if (intmask & OHCI_Int_RespTxComplete) 361 sc->sc_intmask |= OHCI_Int_RespTxComplete; 362 if (intmask & OHCI_Int_RQPkt) 363 sc->sc_intmask |= OHCI_Int_RQPkt; 364 if (intmask & OHCI_Int_RSPkt) 365 sc->sc_intmask |= OHCI_Int_RSPkt; 366 if (intmask & OHCI_Int_IsochTx) { 367 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 368 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 369 sc->sc_intmask |= OHCI_Int_IsochTx; 370 } 371 if (intmask & OHCI_Int_IsochRx) { 372 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 373 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 374 sc->sc_iso |= iso; 375 sc->sc_intmask |= OHCI_Int_IsochRx; 376 } 377 378 if (!progress) { 379 sc->sc_intrcnt.ev_count++; 380 progress = 1; 381 } 382 } 383 } 384 385 static void 386 fwohci_create_event_thread(void *arg) 387 { 388 struct fwohci_softc *sc = arg; 389 390 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 391 sc->sc_sc1394.sc1394_dev.dv_xname)) { 392 printf("%s: unable to create event thread\n", 393 sc->sc_sc1394.sc1394_dev.dv_xname); 394 panic("fwohci_create_event_thread"); 395 } 396 } 397 398 static void 399 fwohci_thread_init(void *arg) 400 { 401 struct fwohci_softc *sc = arg; 402 int i; 403 404 /* 405 * Allocate descriptors 406 */ 407 if (fwohci_desc_alloc(sc)) { 408 printf("%s: not enabling interrupts\n", 409 sc->sc_sc1394.sc1394_dev.dv_xname); 410 kthread_exit(1); 411 } 412 413 /* 414 * Enable Link Power 415 */ 416 417 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 418 419 /* 420 * Allocate DMA Context 421 */ 422 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 423 OHCI_CTX_ASYNC_RX_REQUEST); 424 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 425 OHCI_CTX_ASYNC_RX_RESPONSE); 426 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 427 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 428 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 429 M_DEVBUF, M_WAITOK); 430 for (i = 0; i < sc->sc_isoctx; i++) 431 sc->sc_ctx_ir[i] = NULL; 432 433 /* 434 * Allocate buffer for configuration ROM and SelfID buffer 435 */ 436 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 437 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 438 439 callout_init(&sc->sc_selfid_callout); 440 441 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 442 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 443 444 /* 445 * establish hooks for shutdown and suspend/resume 446 */ 447 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 448 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 449 450 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 451 fwohci_print); 452 453 /* Main loop. It's not coming back normally. */ 454 455 fwohci_event_thread(sc); 456 457 kthread_exit(0); 458 } 459 460 static void 461 fwohci_event_thread(struct fwohci_softc *sc) 462 { 463 int i, s; 464 u_int32_t intmask, iso; 465 466 s = splbio(); 467 468 /* 469 * Initialize hardware registers. 470 */ 471 472 fwohci_hw_init(sc); 473 474 /* Initial Bus Reset */ 475 fwohci_phy_busreset(sc); 476 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 477 splx(s); 478 479 while (!sc->sc_dying) { 480 while (1) { 481 s = splbio(); 482 intmask = sc->sc_intmask; 483 if (intmask) { 484 splx(s); 485 if (intmask & OHCI_Int_BusReset) { 486 s = splbio(); 487 sc->sc_intmask &= ~OHCI_Int_BusReset; 488 splx(s); 489 fwohci_buf_stop(sc); 490 fwohci_buf_init(sc); 491 if (sc->sc_uidtbl != NULL) { 492 free(sc->sc_uidtbl, M_DEVBUF); 493 sc->sc_uidtbl = NULL; 494 } 495 496 callout_reset(&sc->sc_selfid_callout, 497 OHCI_SELFID_TIMEOUT, 498 (void (*)(void *)) 499 fwohci_phy_busreset, sc); 500 sc->sc_nodeid = 0xffff; /* indicate 501 invalid */ 502 sc->sc_rootid = 0; 503 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 504 } 505 if (intmask & OHCI_Int_SelfIDComplete) { 506 s = splbio(); 507 sc->sc_intmask &= 508 ~OHCI_Int_SelfIDComplete; 509 OHCI_CSR_WRITE(sc, 510 OHCI_REG_IntEventClear, 511 OHCI_Int_BusReset); 512 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 513 OHCI_Int_BusReset); 514 splx(s); 515 callout_stop(&sc->sc_selfid_callout); 516 if (fwohci_selfid_input(sc) == 0) { 517 fwohci_buf_start(sc); 518 fwohci_uid_collect(sc); 519 } 520 } 521 if (intmask & OHCI_Int_ReqTxComplete) { 522 s = splbio(); 523 sc->sc_intmask &= 524 ~OHCI_Int_ReqTxComplete; 525 splx(s); 526 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 527 } 528 if (intmask & OHCI_Int_RespTxComplete) { 529 s = splbio(); 530 sc->sc_intmask &= 531 ~OHCI_Int_RespTxComplete; 532 splx(s); 533 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 534 } 535 if (intmask & OHCI_Int_RQPkt) { 536 s = splbio(); 537 sc->sc_intmask &= ~OHCI_Int_RQPkt; 538 splx(s); 539 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 540 } 541 if (intmask & OHCI_Int_RSPkt) { 542 s = splbio(); 543 sc->sc_intmask &= ~OHCI_Int_RSPkt; 544 splx(s); 545 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 546 } 547 if (intmask & OHCI_Int_IsochTx) { 548 s = splbio(); 549 sc->sc_intmask &= ~OHCI_Int_IsochTx; 550 splx(s); 551 } 552 if (intmask & OHCI_Int_IsochRx) { 553 s = splbio(); 554 sc->sc_intmask &= ~OHCI_Int_IsochRx; 555 iso = sc->sc_iso; 556 sc->sc_iso = 0; 557 splx(s); 558 for (i = 0; i < sc->sc_isoctx; i++) { 559 if ((iso & (1 << i)) && 560 sc->sc_ctx_ir[i] != NULL) 561 fwohci_ir_input(sc, 562 sc->sc_ctx_ir[i]); 563 } 564 } 565 } else 566 break; 567 } 568 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 569 splx(s); 570 } 571 } 572 573 #if 0 574 static int 575 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 576 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 577 { 578 bus_dma_segment_t segs[1]; 579 int error, nsegs, steps; 580 581 steps = 0; 582 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 583 segs, 1, &nsegs, flags); 584 if (error) 585 goto cleanup; 586 587 steps = 1; 588 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 589 kvap, flags); 590 if (error) 591 goto cleanup; 592 593 if (error == 0) 594 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 595 size, flags, mapp); 596 if (error) 597 goto cleanup; 598 if (error == 0) 599 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 600 flags); 601 if (error) 602 goto cleanup; 603 604 cleanup: 605 switch (steps) { 606 case 1: 607 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 608 } 609 610 return error; 611 } 612 #endif 613 614 int 615 fwohci_print(void *aux, const char *pnp) 616 { 617 char *name = aux; 618 619 if (pnp) 620 printf("%s at %s", name, pnp); 621 622 return UNCONF; 623 } 624 625 static void 626 fwohci_hw_init(struct fwohci_softc *sc) 627 { 628 int i; 629 u_int32_t val; 630 631 /* 632 * Software Reset. 633 */ 634 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 635 for (i = 0; i < OHCI_LOOP; i++) { 636 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 637 if ((val & OHCI_HCControl_SoftReset) == 0) 638 break; 639 } 640 641 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 642 643 /* 644 * First, initilize CSRs with undefined value to default settings. 645 */ 646 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 647 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 648 #if 0 649 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 650 #else 651 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 652 #endif 653 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 654 for (i = 0; i < sc->sc_isoctx; i++) { 655 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 656 ~0); 657 } 658 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 659 660 fwohci_configrom_init(sc); 661 fwohci_selfid_init(sc); 662 fwohci_buf_init(sc); 663 fwohci_csr_init(sc); 664 665 /* 666 * Final CSR settings. 667 */ 668 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 669 OHCI_LinkControl_CycleTimerEnable | 670 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 671 672 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 673 674 /* clear receive filter */ 675 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 676 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 677 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 678 679 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 680 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 681 #if BYTE_ORDER == BIG_ENDIAN 682 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 683 OHCI_HCControl_NoByteSwapData); 684 #endif 685 686 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 687 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 688 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 689 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 690 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 691 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 692 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 693 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 694 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 695 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 696 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 697 698 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 699 700 /* 701 * Start the receivers 702 */ 703 fwohci_buf_start(sc); 704 } 705 706 static void 707 fwohci_power(int why, void *arg) 708 { 709 struct fwohci_softc *sc = arg; 710 int s; 711 712 s = splbio(); 713 switch (why) { 714 case PWR_SUSPEND: 715 case PWR_STANDBY: 716 fwohci_shutdown(sc); 717 break; 718 case PWR_RESUME: 719 fwohci_hw_init(sc); 720 fwohci_phy_busreset(sc); 721 break; 722 case PWR_SOFTSUSPEND: 723 case PWR_SOFTSTANDBY: 724 case PWR_SOFTRESUME: 725 break; 726 } 727 splx(s); 728 } 729 730 static void 731 fwohci_shutdown(void *arg) 732 { 733 struct fwohci_softc *sc = arg; 734 u_int32_t val; 735 736 callout_stop(&sc->sc_selfid_callout); 737 /* disable all interrupt */ 738 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 739 fwohci_buf_stop(sc); 740 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 741 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 742 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 743 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 744 fwohci_phy_busreset(sc); 745 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 746 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 747 } 748 749 /* 750 * COMMON FUNCTIONS 751 */ 752 753 /* 754 * read the PHY Register. 755 */ 756 static u_int8_t 757 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 758 { 759 int i; 760 u_int32_t val; 761 762 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 763 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 764 for (i = 0; i < OHCI_LOOP; i++) { 765 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 766 OHCI_PhyControl_RdDone) 767 break; 768 } 769 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 770 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 771 } 772 773 /* 774 * write the PHY Register. 775 */ 776 static void 777 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 778 { 779 int i; 780 781 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 782 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 783 (val << OHCI_PhyControl_WrData_BITPOS)); 784 for (i = 0; i < OHCI_LOOP; i++) { 785 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 786 OHCI_PhyControl_WrReg)) 787 break; 788 } 789 } 790 791 /* 792 * Initiate Bus Reset 793 */ 794 static void 795 fwohci_phy_busreset(struct fwohci_softc *sc) 796 { 797 int s; 798 u_int8_t val; 799 800 s = splbio(); 801 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 802 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 803 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 804 callout_stop(&sc->sc_selfid_callout); 805 val = fwohci_phy_read(sc, 1); 806 val = (val & 0x80) | /* preserve RHB (force root) */ 807 0x40 | /* Initiate Bus Reset */ 808 0x3f; /* default GAP count */ 809 fwohci_phy_write(sc, 1, val); 810 splx(s); 811 } 812 813 /* 814 * PHY Packet 815 */ 816 static void 817 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 818 { 819 u_int32_t val; 820 u_int8_t key, phyid; 821 822 val = pkt->fp_hdr[1]; 823 if (val != ~pkt->fp_hdr[2]) { 824 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 825 OHCI_CTXCTL_EVENT_BUS_RESET) { 826 #ifdef FW_DEBUG 827 if (fw_verbose > 1) 828 printf("fwohci_phy_input: BusReset: 0x%08x\n", 829 pkt->fp_hdr[2]); 830 #endif 831 } else { 832 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 833 sc->sc_sc1394.sc1394_dev.dv_xname, val, 834 pkt->fp_hdr[2]); 835 } 836 return; 837 } 838 key = (val & 0xc0000000) >> 30; 839 phyid = (val & 0x3f000000) >> 24; 840 switch (key) { 841 case 0: 842 #ifdef FW_DEBUG 843 if (fw_verbose > 1) { 844 printf("fwohci_phy_input: PHY Config from %d:", phyid); 845 if (val & 0x00800000) 846 printf(" ForceRoot"); 847 if (val & 0x00400000) 848 printf(" Gap=%x", (val & 0x003f0000) >> 16); 849 printf("\n"); 850 } 851 #endif 852 break; 853 case 1: 854 #ifdef FW_DEBUG 855 if (fw_verbose > 1) 856 printf("fwohci_phy_input: Link-on from %d\n", phyid); 857 #endif 858 break; 859 case 2: 860 #ifdef FW_DEBUG 861 if (fw_verbose > 1) { 862 printf("fwohci_phy_input: SelfID from %d:", phyid); 863 if (val & 0x00800000) { 864 printf(" #%d", (val & 0x00700000) >> 20); 865 } else { 866 if (val & 0x00400000) 867 printf(" LinkActive"); 868 printf(" Gap=%x", (val & 0x003f0000) >> 16); 869 printf(" Spd=S%d", 870 100 << ((val & 0x0000c000) >> 14)); 871 if (val & 0x00000800) 872 printf(" Cont"); 873 if (val & 0x00000002) 874 printf(" InitiateBusReset"); 875 } 876 if (val & 0x00000001) 877 printf(" +"); 878 printf("\n"); 879 } 880 #endif 881 break; 882 default: 883 printf("%s: unknown PHY packet: 0x%08x\n", 884 sc->sc_sc1394.sc1394_dev.dv_xname, val); 885 break; 886 } 887 } 888 889 /* 890 * Descriptor for context DMA. 891 */ 892 static int 893 fwohci_desc_alloc(struct fwohci_softc *sc) 894 { 895 int error, mapsize, dsize; 896 897 /* 898 * allocate descriptor buffer 899 */ 900 901 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 902 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 903 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 904 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 905 mapsize = howmany(sc->sc_descsize, NBBY); 906 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 907 memset(sc->sc_descmap, 0, mapsize); 908 909 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 910 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 911 printf("%s: unable to allocate descriptor buffer, error = %d\n", 912 sc->sc_sc1394.sc1394_dev.dv_xname, error); 913 goto fail_0; 914 } 915 916 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 917 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 918 != 0) { 919 printf("%s: unable to map descriptor buffer, error = %d\n", 920 sc->sc_sc1394.sc1394_dev.dv_xname, error); 921 goto fail_1; 922 } 923 924 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 925 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 926 printf("%s: unable to create descriptor buffer DMA map, " 927 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 928 goto fail_2; 929 } 930 931 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 932 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 933 printf("%s: unable to load descriptor buffer DMA map, " 934 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 935 goto fail_3; 936 } 937 938 return 0; 939 940 fail_3: 941 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 942 fail_2: 943 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 944 fail_1: 945 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 946 fail_0: 947 return error; 948 } 949 950 static struct fwohci_desc * 951 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 952 { 953 int i, n; 954 955 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 956 for (i = 0; ; i++) { 957 if (i == ndesc) { 958 for (i = 0; i < ndesc; i++) 959 setbit(sc->sc_descmap, n + i); 960 return sc->sc_desc + n; 961 } 962 if (isset(sc->sc_descmap, n + i)) 963 break; 964 } 965 } 966 return NULL; 967 } 968 969 static void 970 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 971 { 972 int i, n; 973 974 n = fd - sc->sc_desc; 975 for (i = 0; i < ndesc; i++, n++) { 976 #ifdef DIAGNOSTICS 977 if (isclr(sc->sc_descmap, n)) 978 panic("fwohci_desc_put: duplicated free"); 979 #endif 980 clrbit(sc->sc_descmap, n); 981 } 982 } 983 984 /* 985 * Asyncronous/Isochronous Transmit/Receive Context 986 */ 987 static int 988 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 989 int bufcnt, int ctx) 990 { 991 int i, error; 992 struct fwohci_ctx *fc; 993 struct fwohci_buf *fb; 994 struct fwohci_desc *fd; 995 996 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 997 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 998 LIST_INIT(&fc->fc_handler); 999 TAILQ_INIT(&fc->fc_buf); 1000 fc->fc_ctx = ctx; 1001 fc->fc_bufcnt = bufcnt; 1002 fb = (struct fwohci_buf *)&fc[1]; 1003 for (i = 0; i < bufcnt; i++, fb++) { 1004 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 1005 goto fail; 1006 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 1007 error = ENOBUFS; 1008 goto fail; 1009 } 1010 fb->fb_desc = fd; 1011 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1012 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1013 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1014 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1015 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1016 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1017 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1018 } 1019 *fcp = fc; 1020 return 0; 1021 1022 fail: 1023 while (i-- > 0) 1024 fwohci_buf_free(sc, --fb); 1025 free(fc, M_DEVBUF); 1026 return error; 1027 } 1028 1029 static void 1030 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1031 { 1032 struct fwohci_buf *fb; 1033 struct fwohci_handler *fh; 1034 1035 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1036 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1037 NULL, NULL); 1038 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1039 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1040 fwohci_buf_free(sc, fb); 1041 } 1042 free(fc, M_DEVBUF); 1043 } 1044 1045 static void 1046 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1047 { 1048 struct fwohci_buf *fb, *nfb; 1049 struct fwohci_desc *fd; 1050 struct fwohci_handler *fh; 1051 int n; 1052 1053 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1054 nfb = TAILQ_NEXT(fb, fb_list); 1055 fb->fb_off = 0; 1056 fd = fb->fb_desc; 1057 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1058 fd->fd_rescount = fd->fd_reqcount; 1059 } 1060 1061 n = fc->fc_ctx; 1062 fb = TAILQ_FIRST(&fc->fc_buf); 1063 if (fc->fc_isoch) { 1064 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1065 fb->fb_daddr | 1); 1066 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1067 OHCI_CTXCTL_RX_BUFFER_FILL | 1068 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1069 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1070 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1071 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1072 OHCI_CTXCTL_RX_ISOCH_HEADER); 1073 fh = LIST_FIRST(&fc->fc_handler); 1074 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1075 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1076 } else { 1077 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1078 fb->fb_daddr | 1); 1079 } 1080 } 1081 1082 /* 1083 * DMA data buffer 1084 */ 1085 static int 1086 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1087 { 1088 int error; 1089 1090 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1091 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1092 printf("%s: unable to allocate buffer, error = %d\n", 1093 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1094 goto fail_0; 1095 } 1096 1097 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1098 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1099 printf("%s: unable to map buffer, error = %d\n", 1100 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1101 goto fail_1; 1102 } 1103 1104 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1105 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1106 printf("%s: unable to create buffer DMA map, " 1107 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1108 error); 1109 goto fail_2; 1110 } 1111 1112 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1113 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1114 printf("%s: unable to load buffer DMA map, " 1115 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1116 error); 1117 goto fail_3; 1118 } 1119 1120 return 0; 1121 1122 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1123 fail_3: 1124 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1125 fail_2: 1126 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1127 fail_1: 1128 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1129 fail_0: 1130 return error; 1131 } 1132 1133 static void 1134 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1135 { 1136 1137 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1138 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1139 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1140 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1141 } 1142 1143 static void 1144 fwohci_buf_init(struct fwohci_softc *sc) 1145 { 1146 int i; 1147 1148 /* 1149 * Initialize for Asynchronous Transmit Queue. 1150 */ 1151 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1152 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1153 1154 /* 1155 * Initialize for Asynchronous Receive Queue. 1156 */ 1157 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1158 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1159 1160 /* 1161 * Initialize for Isochronous Receive Queue. 1162 */ 1163 for (i = 0; i < sc->sc_isoctx; i++) { 1164 if (sc->sc_ctx_ir[i] != NULL) 1165 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1166 } 1167 } 1168 1169 static void 1170 fwohci_buf_start(struct fwohci_softc *sc) 1171 { 1172 int i; 1173 1174 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1175 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1176 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1177 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1178 for (i = 0; i < sc->sc_isoctx; i++) { 1179 if (sc->sc_ctx_ir[i] != NULL && 1180 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1181 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1182 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1183 } 1184 } 1185 } 1186 1187 static void 1188 fwohci_buf_stop(struct fwohci_softc *sc) 1189 { 1190 int i, j; 1191 1192 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1193 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1194 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1195 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1196 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1197 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1198 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1199 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1200 for (i = 0; i < sc->sc_isoctx; i++) { 1201 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1202 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1203 } 1204 1205 /* 1206 * Make sure the transmitter is stopped. 1207 */ 1208 for (j = 0; j < OHCI_LOOP; j++) { 1209 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1210 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1211 continue; 1212 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1213 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1214 continue; 1215 break; 1216 } 1217 } 1218 1219 static void 1220 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1221 { 1222 struct fwohci_buf *fb, *tfb; 1223 1224 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1225 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1226 fb->fb_desc->fd_rescount != 0) 1227 break; 1228 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1229 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1230 fb->fb_off = 0; 1231 fb->fb_desc->fd_branch = 0; 1232 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1233 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1234 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1235 } 1236 } 1237 1238 static int 1239 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1240 int len) 1241 { 1242 struct fwohci_buf *fb; 1243 struct fwohci_desc *fd; 1244 int bufend; 1245 1246 fb = TAILQ_FIRST(&fc->fc_buf); 1247 again: 1248 fd = fb->fb_desc; 1249 #ifdef FW_DEBUG 1250 if (fw_verbose > 1) 1251 printf("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1252 " len %d, avail %d\n", 1253 (long)(fd - sc->sc_desc), fb->fb_off, fd->fd_reqcount, 1254 fd->fd_rescount, len, 1255 fd->fd_reqcount - fd->fd_rescount - fb->fb_off); 1256 #endif 1257 bufend = fd->fd_reqcount - fd->fd_rescount; 1258 if (fb->fb_off >= bufend) { 1259 if (fc->fc_isoch && fb->fb_off > 0) { 1260 fb->fb_off = fd->fd_reqcount; 1261 fd->fd_rescount = 0; 1262 } 1263 if (fd->fd_rescount == 0) { 1264 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1265 goto again; 1266 } 1267 return 0; 1268 } 1269 if (fb->fb_off + len > bufend) 1270 len = bufend - fb->fb_off; 1271 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1272 BUS_DMASYNC_POSTREAD); 1273 *pp = fb->fb_buf + fb->fb_off; 1274 fb->fb_off += roundup(len, 4); 1275 return len; 1276 } 1277 1278 static int 1279 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1280 struct fwohci_pkt *pkt) 1281 { 1282 caddr_t p; 1283 int len, count, i; 1284 1285 memset(pkt, 0, sizeof(*pkt)); 1286 pkt->fp_uio.uio_iov = pkt->fp_iov; 1287 pkt->fp_uio.uio_rw = UIO_WRITE; 1288 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1289 1290 /* get first quadlet */ 1291 count = 4; 1292 if (fc->fc_isoch) { 1293 /* 1294 * get trailer first, may be bogus data unless status update 1295 * in descriptor is set. 1296 */ 1297 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1298 sizeof(*pkt->fp_trail)); 1299 if (len <= 0) { 1300 #ifdef FW_DEBUG 1301 if (fw_verbose > 1) 1302 printf("fwohci_buf_input: no input for is#%d\n", 1303 fc->fc_ctx); 1304 #endif 1305 return 0; 1306 } 1307 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1308 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1309 } 1310 len = fwohci_buf_pktget(sc, fc, &p, count); 1311 if (len <= 0) { 1312 #ifdef FW_DEBUG 1313 if (fw_verbose > 1) 1314 printf("fwohci_buf_input: no input for %d\n", 1315 fc->fc_ctx); 1316 #endif 1317 return 0; 1318 } 1319 pkt->fp_hdr[0] = *(u_int32_t *)p; 1320 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1321 switch (pkt->fp_tcode) { 1322 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1323 case IEEE1394_TCODE_READ_RESP_QUAD: 1324 pkt->fp_hlen = 12; 1325 pkt->fp_dlen = 4; 1326 break; 1327 case IEEE1394_TCODE_READ_REQ_BLOCK: 1328 pkt->fp_hlen = 16; 1329 pkt->fp_dlen = 0; 1330 break; 1331 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1332 case IEEE1394_TCODE_READ_RESP_BLOCK: 1333 case IEEE1394_TCODE_LOCK_REQ: 1334 case IEEE1394_TCODE_LOCK_RESP: 1335 pkt->fp_hlen = 16; 1336 break; 1337 case IEEE1394_TCODE_STREAM_DATA: 1338 pkt->fp_hlen = 4; 1339 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1340 break; 1341 default: 1342 pkt->fp_hlen = 12; 1343 pkt->fp_dlen = 0; 1344 break; 1345 } 1346 1347 /* get header */ 1348 while (count < pkt->fp_hlen) { 1349 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1350 if (len == 0) { 1351 printf("fwohci_buf_input: malformed input 1: %d\n", 1352 pkt->fp_hlen - count); 1353 return 0; 1354 } 1355 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1356 count += len; 1357 } 1358 if ((pkt->fp_hlen == 16) && 1359 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1360 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1361 #ifdef FW_DEBUG 1362 if (fw_verbose > 1) 1363 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1364 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1365 #endif 1366 1367 /* get data */ 1368 count = 0; 1369 i = 0; 1370 while (count < pkt->fp_dlen) { 1371 len = fwohci_buf_pktget(sc, fc, 1372 (caddr_t *)&pkt->fp_iov[i].iov_base, 1373 pkt->fp_dlen - count); 1374 if (len == 0) { 1375 printf("fwohci_buf_input: malformed input 2: %d\n", 1376 pkt->fp_hlen - count); 1377 return 0; 1378 } 1379 pkt->fp_iov[i++].iov_len = len; 1380 count += len; 1381 } 1382 pkt->fp_uio.uio_iovcnt = i; 1383 pkt->fp_uio.uio_resid = count; 1384 1385 if (!fc->fc_isoch) { 1386 /* get trailer */ 1387 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1388 sizeof(*pkt->fp_trail)); 1389 if (len <= 0) { 1390 printf("fwohci_buf_input: malformed input 3: %d\n", 1391 pkt->fp_hlen - count); 1392 return 0; 1393 } 1394 } 1395 return 1; 1396 } 1397 1398 static int 1399 fwohci_handler_set(struct fwohci_softc *sc, 1400 int tcode, u_int32_t key1, u_int32_t key2, 1401 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1402 void *arg) 1403 { 1404 struct fwohci_ctx *fc; 1405 struct fwohci_handler *fh; 1406 int i, j; 1407 1408 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1409 j = sc->sc_isoctx; 1410 fh = NULL; 1411 for (i = 0; i < sc->sc_isoctx; i++) { 1412 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1413 if (j == sc->sc_isoctx) 1414 j = i; 1415 continue; 1416 } 1417 fh = LIST_FIRST(&fc->fc_handler); 1418 if (fh == NULL) { 1419 j = i; 1420 break; 1421 } 1422 if (fh->fh_tcode == tcode && 1423 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1424 break; 1425 fh = NULL; 1426 } 1427 if (fh == NULL) { 1428 if (handler == NULL) 1429 return 0; 1430 if (j == sc->sc_isoctx) { 1431 #ifdef FW_DEBUG 1432 if (fw_verbose) 1433 printf("fwohci_handler_set: " 1434 "no more free context\n"); 1435 #endif 1436 return ENOMEM; 1437 } 1438 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1439 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1440 fc->fc_isoch = 1; 1441 sc->sc_ctx_ir[j] = fc; 1442 } 1443 } 1444 } else { 1445 switch (tcode) { 1446 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1447 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1448 case IEEE1394_TCODE_READ_REQ_QUAD: 1449 case IEEE1394_TCODE_READ_REQ_BLOCK: 1450 case IEEE1394_TCODE_LOCK_REQ: 1451 fc = sc->sc_ctx_arrq; 1452 break; 1453 case IEEE1394_TCODE_WRITE_RESP: 1454 case IEEE1394_TCODE_READ_RESP_QUAD: 1455 case IEEE1394_TCODE_READ_RESP_BLOCK: 1456 case IEEE1394_TCODE_LOCK_RESP: 1457 fc = sc->sc_ctx_arrs; 1458 break; 1459 default: 1460 return EIO; 1461 } 1462 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1463 fh = LIST_NEXT(fh, fh_list)) { 1464 if (fh->fh_tcode == tcode && 1465 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1466 break; 1467 } 1468 } 1469 if (handler == NULL) { 1470 if (fh != NULL) { 1471 LIST_REMOVE(fh, fh_list); 1472 free(fh, M_DEVBUF); 1473 } 1474 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1475 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1476 fwohci_ctx_free(sc, fc); 1477 } 1478 return 0; 1479 } 1480 if (fh == NULL) { 1481 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1482 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1483 } 1484 fh->fh_tcode = tcode; 1485 fh->fh_key1 = key1; 1486 fh->fh_key2 = key2; 1487 fh->fh_handler = handler; 1488 fh->fh_handarg = arg; 1489 #ifdef FW_DEBUG 1490 if (fw_verbose > 1) 1491 printf("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1492 fc->fc_ctx, tcode, key1, key2); 1493 #endif 1494 1495 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1496 fwohci_ctx_init(sc, fc); 1497 #ifdef FW_DEBUG 1498 if (fw_verbose > 1) 1499 printf("fwohci_handler_set: SYNC desc %ld\n", 1500 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - 1501 sc->sc_desc)); 1502 #endif 1503 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1504 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1505 } 1506 return 0; 1507 } 1508 1509 /* 1510 * Asyncronous Receive Requests input frontend. 1511 */ 1512 static void 1513 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1514 { 1515 int rcode; 1516 u_int32_t key1, key2; 1517 struct fwohci_handler *fh; 1518 struct fwohci_pkt pkt, res; 1519 1520 while (fwohci_buf_input(sc, fc, &pkt)) { 1521 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1522 fwohci_phy_input(sc, &pkt); 1523 return; 1524 } 1525 key1 = pkt.fp_hdr[1] & 0xffff; 1526 key2 = pkt.fp_hdr[2]; 1527 memset(&res, 0, sizeof(res)); 1528 res.fp_uio.uio_rw = UIO_WRITE; 1529 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1530 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1531 fh = LIST_NEXT(fh, fh_list)) { 1532 if (pkt.fp_tcode == fh->fh_tcode && 1533 key1 == fh->fh_key1 && 1534 key2 == fh->fh_key2) { 1535 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1536 &pkt); 1537 break; 1538 } 1539 } 1540 if (fh == NULL) { 1541 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1542 #ifdef FW_DEBUG 1543 if (fw_verbose > 1) 1544 printf("fwohci_arrq_input: no listener:" 1545 " tcode 0x%x, addr=0x%04x %08x\n", 1546 pkt.fp_tcode, key1, key2); 1547 #endif 1548 } 1549 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1550 OHCI_CTXCTL_EVENT_ACK_PENDING) 1551 return; 1552 if (rcode != -1) 1553 fwohci_atrs_output(sc, rcode, &pkt, &res); 1554 } 1555 fwohci_buf_next(sc, fc); 1556 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1557 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1558 } 1559 1560 1561 /* 1562 * Asynchronous Receive Response input frontend. 1563 */ 1564 static void 1565 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1566 { 1567 struct fwohci_pkt pkt; 1568 struct fwohci_handler *fh; 1569 u_int16_t srcid; 1570 int rcode, tlabel; 1571 1572 while (fwohci_buf_input(sc, fc, &pkt)) { 1573 srcid = pkt.fp_hdr[1] >> 16; 1574 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1575 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1576 #ifdef FW_DEBUG 1577 if (fw_verbose > 1) 1578 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1579 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1580 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1581 pkt.fp_dlen); 1582 #endif 1583 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1584 fh = LIST_NEXT(fh, fh_list)) { 1585 if (pkt.fp_tcode == fh->fh_tcode && 1586 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1587 tlabel == fh->fh_key2) { 1588 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1589 LIST_REMOVE(fh, fh_list); 1590 free(fh, M_DEVBUF); 1591 break; 1592 } 1593 } 1594 #ifdef FW_DEBUG 1595 if (fw_verbose > 1) 1596 if (fh == NULL) { 1597 printf("fwohci_arrs_input: no listner\n"); 1598 printf("src: %d, rcode: %d, tlabel: %d, tcode: " 1599 "%d hdr[3]: 0x%08x, data: 0x%08lx\n", srcid, 1600 rcode, tlabel, pkt.fp_tcode, pkt.fp_hdr[3], 1601 (unsigned long)(*((int *)pkt.fp_iov[0].iov_base))); 1602 } 1603 #endif 1604 } 1605 fwohci_buf_next(sc, fc); 1606 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1607 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1608 } 1609 1610 /* 1611 * Isochronous Receive input frontend. 1612 */ 1613 static void 1614 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1615 { 1616 int rcode, chan, tag; 1617 struct iovec *iov; 1618 struct fwohci_handler *fh; 1619 struct fwohci_pkt pkt; 1620 1621 while (fwohci_buf_input(sc, fc, &pkt)) { 1622 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1623 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1624 #ifdef FW_DEBUG 1625 if (fw_verbose > 1) 1626 printf("fwohci_ir_input: hdr 0x%08x, tcode %d," 1627 " hlen %d, dlen %d\n", pkt.fp_hdr[0], 1628 pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1629 #endif 1630 if (tag == IEEE1394_TAG_GASP) { 1631 /* 1632 * The pkt with tag=3 is GASP format. 1633 * Move GASP header to header part. 1634 */ 1635 if (pkt.fp_dlen < 8) 1636 continue; 1637 iov = pkt.fp_iov; 1638 /* assuming pkt per buffer mode */ 1639 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1640 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1641 iov->iov_base = (caddr_t)iov->iov_base + 8; 1642 iov->iov_len -= 8; 1643 pkt.fp_hlen += 8; 1644 pkt.fp_dlen -= 8; 1645 } 1646 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1647 fh = LIST_NEXT(fh, fh_list)) { 1648 if (pkt.fp_tcode == fh->fh_tcode && 1649 chan == fh->fh_key1 && tag == fh->fh_key2) { 1650 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1651 &pkt); 1652 break; 1653 } 1654 } 1655 #ifdef FW_DEBUG 1656 if (fw_verbose > 1) { 1657 if (fh == NULL) 1658 printf("fwohci_ir_input: no handler\n"); 1659 else 1660 printf("fwohci_ir_input: rcode %d\n", rcode); 1661 } 1662 #endif 1663 } 1664 fwohci_buf_next(sc, fc); 1665 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1666 OHCI_CTXCTL_WAKE); 1667 } 1668 1669 /* 1670 * Asynchronous Transmit common routine. 1671 */ 1672 static int 1673 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1674 struct fwohci_pkt *pkt) 1675 { 1676 struct fwohci_buf *fb; 1677 struct fwohci_desc *fd; 1678 struct mbuf *m, *m0; 1679 int i, ndesc, error, off, len; 1680 u_int32_t val; 1681 1682 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1683 /* We can't send anything during selfid duration */ 1684 return EAGAIN; 1685 1686 #ifdef FW_DEBUG 1687 if (fw_verbose > 1) { 1688 struct iovec *iov; 1689 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1690 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1691 if (fw_dump) { 1692 for (i = 0; i < pkt->fp_hlen/4; i++) 1693 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1694 printf("$"); 1695 for (ndesc = 0, iov = pkt->fp_iov; 1696 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1697 for (i = 0; i < iov->iov_len; i++) 1698 printf("%s%02x", 1699 (i%32)?((i%4)?"":" "):"\n\t", 1700 ((u_int8_t *)iov->iov_base)[i]); 1701 printf("$"); 1702 } 1703 } 1704 printf("\n"); 1705 } 1706 #endif 1707 1708 if ((m = pkt->fp_m) != NULL) { 1709 for (ndesc = 2; m != NULL; m = m->m_next) 1710 ndesc++; 1711 if (ndesc > OHCI_DESC_MAX) { 1712 m0 = NULL; 1713 ndesc = 2; 1714 for (off = 0; off < pkt->fp_dlen; off += len) { 1715 if (m0 == NULL) { 1716 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1717 if (m0 != NULL) 1718 M_COPY_PKTHDR(m0, pkt->fp_m); 1719 m = m0; 1720 } else { 1721 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1722 m = m->m_next; 1723 } 1724 if (m != NULL) 1725 MCLGET(m, M_DONTWAIT); 1726 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1727 m_freem(m0); 1728 return ENOMEM; 1729 } 1730 len = pkt->fp_dlen - off; 1731 if (len > m->m_ext.ext_size) 1732 len = m->m_ext.ext_size; 1733 m_copydata(pkt->fp_m, off, len, 1734 mtod(m, caddr_t)); 1735 m->m_len = len; 1736 ndesc++; 1737 } 1738 m_freem(pkt->fp_m); 1739 pkt->fp_m = m0; 1740 } 1741 } else 1742 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1743 1744 if (ndesc > OHCI_DESC_MAX) 1745 return ENOBUFS; 1746 1747 if (fc->fc_bufcnt > 50) /*XXX*/ 1748 return ENOBUFS; 1749 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1750 fb->fb_nseg = ndesc; 1751 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1752 if (fb->fb_desc == NULL) { 1753 free(fb, M_DEVBUF); 1754 return ENOBUFS; 1755 } 1756 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1757 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1758 fb->fb_m = pkt->fp_m; 1759 fb->fb_callback = pkt->fp_callback; 1760 1761 if (ndesc > 2) { 1762 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1763 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1764 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1765 free(fb, M_DEVBUF); 1766 return error; 1767 } 1768 1769 if (pkt->fp_m != NULL) 1770 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1771 pkt->fp_m, BUS_DMA_WAITOK); 1772 else 1773 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1774 &pkt->fp_uio, BUS_DMA_WAITOK); 1775 if (error != 0) { 1776 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1777 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1778 free(fb, M_DEVBUF); 1779 return error; 1780 } 1781 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1782 BUS_DMASYNC_PREWRITE); 1783 } 1784 1785 fd = fb->fb_desc; 1786 fd->fd_flags = OHCI_DESC_IMMED; 1787 fd->fd_reqcount = pkt->fp_hlen; 1788 fd->fd_data = 0; 1789 fd->fd_branch = 0; 1790 fd->fd_status = 0; 1791 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1792 i = 3; /* XXX: 3 sec */ 1793 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1794 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1795 ((((val >> 25) + i) & 0x7) << 13); 1796 } else 1797 fd->fd_timestamp = 0; 1798 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1799 for (i = 0; i < ndesc - 2; i++) { 1800 fd = fb->fb_desc + 2 + i; 1801 fd->fd_flags = 0; 1802 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1803 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1804 fd->fd_branch = 0; 1805 fd->fd_status = 0; 1806 fd->fd_timestamp = 0; 1807 } 1808 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1809 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1810 1811 #ifdef FW_DEBUG 1812 if (fw_verbose > 1) { 1813 printf("fwohci_at_output: desc %ld", 1814 (long)(fb->fb_desc - sc->sc_desc)); 1815 for (i = 0; i < ndesc * 4; i++) 1816 printf("%s%08x", i&7?" ":"\n\t", 1817 ((u_int32_t *)fb->fb_desc)[i]); 1818 printf("\n"); 1819 } 1820 #endif 1821 1822 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1823 OHCI_SUBREG_ContextControlClear); 1824 1825 if (val & OHCI_CTXCTL_RUN) { 1826 if (fc->fc_branch == NULL) { 1827 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1828 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1829 goto run; 1830 } 1831 *fc->fc_branch = fb->fb_daddr | ndesc; 1832 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1833 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1834 } else { 1835 run: 1836 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1837 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1838 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1839 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1840 } 1841 fc->fc_branch = &fd->fd_branch; 1842 1843 fc->fc_bufcnt++; 1844 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1845 pkt->fp_m = NULL; 1846 return 0; 1847 } 1848 1849 static void 1850 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1851 { 1852 struct fwohci_buf *fb; 1853 struct fwohci_desc *fd; 1854 int i; 1855 1856 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1857 fd = fb->fb_desc; 1858 #ifdef FW_DEBUG 1859 if (fw_verbose > 1) { 1860 printf("fwohci_at_done: %sdesc %ld (%d)", 1861 force ? "force " : "", 1862 (long)(fd - sc->sc_desc), fb->fb_nseg); 1863 for (i = 0; i < fb->fb_nseg * 4; i++) 1864 printf("%s%08x", i&7?" ":"\n ", 1865 ((u_int32_t *)fd)[i]); 1866 printf("\n"); 1867 } 1868 #endif 1869 if (fb->fb_nseg > 2) 1870 fd += fb->fb_nseg - 1; 1871 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1872 break; 1873 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1874 if (fc->fc_branch == &fd->fd_branch) { 1875 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1876 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1877 fc->fc_branch = NULL; 1878 for (i = 0; i < OHCI_LOOP; i++) { 1879 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1880 OHCI_SUBREG_ContextControlClear) & 1881 OHCI_CTXCTL_ACTIVE)) 1882 break; 1883 } 1884 } 1885 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1886 if (fb->fb_nseg > 2) 1887 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1888 fc->fc_bufcnt--; 1889 if (fb->fb_callback != NULL) { 1890 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1891 fb->fb_callback = NULL; 1892 } else if (fb->fb_m != NULL) 1893 m_freem(fb->fb_m); 1894 free(fb, M_DEVBUF); 1895 } 1896 } 1897 1898 /* 1899 * Asynchronous Transmit Reponse -- in response of request packet. 1900 */ 1901 static void 1902 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1903 struct fwohci_pkt *res) 1904 { 1905 1906 if (((*req->fp_trail & 0x001f0000) >> 16) != 1907 OHCI_CTXCTL_EVENT_ACK_PENDING) 1908 return; 1909 1910 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1911 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1912 switch (req->fp_tcode) { 1913 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1914 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1915 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1916 res->fp_hlen = 12; 1917 break; 1918 case IEEE1394_TCODE_READ_REQ_QUAD: 1919 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1920 res->fp_hlen = 16; 1921 res->fp_dlen = 0; 1922 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1923 res->fp_hdr[3] = 1924 *(u_int32_t *)res->fp_iov[0].iov_base; 1925 res->fp_uio.uio_iovcnt = 0; 1926 break; 1927 case IEEE1394_TCODE_READ_REQ_BLOCK: 1928 case IEEE1394_TCODE_LOCK_REQ: 1929 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1930 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1931 else 1932 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1933 res->fp_hlen = 16; 1934 res->fp_dlen = res->fp_uio.uio_resid; 1935 res->fp_hdr[3] = res->fp_dlen << 16; 1936 break; 1937 } 1938 res->fp_hdr[0] |= (res->fp_tcode << 4); 1939 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1940 } 1941 1942 /* 1943 * APPLICATION LAYER SERVICES 1944 */ 1945 1946 /* 1947 * Retrieve Global UID from GUID ROM 1948 */ 1949 static int 1950 fwohci_guidrom_init(struct fwohci_softc *sc) 1951 { 1952 int i, n, off; 1953 u_int32_t val1, val2; 1954 1955 /* Extract the Global UID 1956 */ 1957 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1958 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1959 1960 if (val1 != 0 || val2 != 0) { 1961 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1962 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1963 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1964 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1965 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1966 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1967 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1968 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1969 } else { 1970 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1971 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1972 return -1; 1973 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1974 for (i = 0; i < OHCI_LOOP; i++) { 1975 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1976 if (!(val1 & OHCI_Guid_AddrReset)) 1977 break; 1978 } 1979 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1980 val2 = 0; 1981 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1982 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1983 OHCI_Guid_RdStart); 1984 for (i = 0; i < OHCI_LOOP; i++) { 1985 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1986 if (!(val1 & OHCI_Guid_RdStart)) 1987 break; 1988 } 1989 if (n < off) 1990 continue; 1991 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1992 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1993 val2 |= val1; 1994 } 1995 if (val2 == 0) 1996 return -1; 1997 } 1998 return 0; 1999 } 2000 2001 /* 2002 * Initialization for Configuration ROM (no DMA context) 2003 */ 2004 2005 #define CFR_MAXUNIT 20 2006 2007 struct configromctx { 2008 u_int32_t *ptr; 2009 int curunit; 2010 struct { 2011 u_int32_t *start; 2012 int length; 2013 u_int32_t *refer; 2014 int refunit; 2015 } unit[CFR_MAXUNIT]; 2016 }; 2017 2018 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2019 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2020 2021 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2022 2023 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2024 2025 #define CFR_PUT_CRC(cfr, n) \ 2026 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2027 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2028 2029 #define CFR_START_UNIT(cfr, n) \ 2030 do { \ 2031 if ((cfr)->unit[n].refer != NULL) { \ 2032 *(cfr)->unit[n].refer |= \ 2033 (cfr)->ptr - (cfr)->unit[n].refer; \ 2034 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2035 } \ 2036 (cfr)->curunit = (n); \ 2037 (cfr)->unit[n].start = (cfr)->ptr++; \ 2038 } while (0 /* CONSTCOND */) 2039 2040 #define CFR_PUT_REFER(cfr, key, n) \ 2041 do { \ 2042 (cfr)->unit[n].refer = (cfr)->ptr; \ 2043 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2044 *(cfr)->ptr++ = (key) << 24; \ 2045 } while (0 /* CONSTCOND */) 2046 2047 #define CFR_END_UNIT(cfr) \ 2048 do { \ 2049 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2050 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2051 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2052 } while (0 /* CONSTCOND */) 2053 2054 static u_int16_t 2055 fwohci_crc16(u_int32_t *ptr, int len) 2056 { 2057 int shift; 2058 u_int32_t crc, sum, data; 2059 2060 crc = 0; 2061 while (len-- > 0) { 2062 data = *ptr++; 2063 for (shift = 28; shift >= 0; shift -= 4) { 2064 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2065 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2066 } 2067 crc &= 0xffff; 2068 } 2069 return crc; 2070 } 2071 2072 static void 2073 fwohci_configrom_init(struct fwohci_softc *sc) 2074 { 2075 int i; 2076 struct fwohci_buf *fb; 2077 u_int32_t *hdr; 2078 struct configromctx cfr; 2079 2080 fb = &sc->sc_buf_cnfrom; 2081 memset(&cfr, 0, sizeof(cfr)); 2082 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2083 2084 /* headers */ 2085 CFR_START_UNIT(&cfr, 0); 2086 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2087 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2088 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2089 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2090 CFR_END_UNIT(&cfr); 2091 /* copy info_length from crc_length */ 2092 *hdr |= (*hdr & 0x00ff0000) << 8; 2093 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2094 2095 /* root directory */ 2096 CFR_START_UNIT(&cfr, 1); 2097 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2098 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2099 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2100 /* spt,64,fix,lst,drq */ 2101 #ifdef INET 2102 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2103 #endif /* INET */ 2104 #ifdef INET6 2105 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2106 #endif /* INET6 */ 2107 CFR_END_UNIT(&cfr); 2108 2109 CFR_START_UNIT(&cfr, 2); 2110 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2111 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2112 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2113 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2114 CFR_END_UNIT(&cfr); 2115 2116 #ifdef INET 2117 /* IPv4 unit directory */ 2118 CFR_START_UNIT(&cfr, 3); 2119 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2120 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2121 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2122 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2123 CFR_END_UNIT(&cfr); 2124 2125 CFR_START_UNIT(&cfr, 6); 2126 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2127 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2128 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2129 CFR_END_UNIT(&cfr); 2130 2131 CFR_START_UNIT(&cfr, 7); 2132 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2133 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2134 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2135 CFR_END_UNIT(&cfr); 2136 #endif /* INET */ 2137 2138 #ifdef INET6 2139 /* IPv6 unit directory */ 2140 CFR_START_UNIT(&cfr, 4); 2141 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2142 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2143 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2144 /* XXX: TBA by IANA */ 2145 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2146 CFR_END_UNIT(&cfr); 2147 2148 CFR_START_UNIT(&cfr, 8); 2149 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2150 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2151 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2152 CFR_END_UNIT(&cfr); 2153 2154 CFR_START_UNIT(&cfr, 9); 2155 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2156 CFR_PUT_DATA1(&cfr, 0); 2157 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2158 CFR_END_UNIT(&cfr); 2159 #endif /* INET6 */ 2160 2161 fb->fb_off = cfr.ptr - hdr; 2162 #ifdef FW_DEBUG 2163 if (fw_dump) { 2164 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 2165 for (i = 0; i < fb->fb_off; i++) 2166 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 2167 printf("\n"); 2168 } 2169 #endif /* FW_DEBUG */ 2170 2171 /* 2172 * Make network byte order for DMA 2173 */ 2174 for (i = 0; i < fb->fb_off; i++) 2175 HTONL(hdr[i]); 2176 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2177 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2178 2179 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2180 fb->fb_dmamap->dm_segs[0].ds_addr); 2181 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 2182 2183 /* Just allow quad reads of the rom. */ 2184 for (i = 0; i < fb->fb_off; i++) 2185 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2186 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2187 fwohci_configrom_input, NULL); 2188 } 2189 2190 static int 2191 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2192 struct fwohci_pkt *pkt) 2193 { 2194 struct fwohci_pkt res; 2195 u_int32_t loc, *rom; 2196 2197 /* This will be used as an array index so size accordingly. */ 2198 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2199 if ((loc & 0x03) != 0) { 2200 /* alignment error */ 2201 return IEEE1394_RCODE_ADDRESS_ERROR; 2202 } 2203 else 2204 loc /= 4; 2205 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2206 2207 #ifdef FW_DEBUG 2208 if (fw_verbose > 1) 2209 printf("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", 2210 loc, ntohl(rom[loc])); 2211 #endif 2212 2213 memset(&res, 0, sizeof(res)); 2214 res.fp_hdr[3] = rom[loc]; 2215 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2216 return -1; 2217 } 2218 2219 /* 2220 * SelfID buffer (no DMA context) 2221 */ 2222 static void 2223 fwohci_selfid_init(struct fwohci_softc *sc) 2224 { 2225 struct fwohci_buf *fb; 2226 2227 fb = &sc->sc_buf_selfid; 2228 #ifdef DIAGNOSTICS 2229 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2230 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2231 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2232 fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2233 #endif 2234 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2235 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2236 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2237 2238 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2239 fb->fb_dmamap->dm_segs[0].ds_addr); 2240 } 2241 2242 static int 2243 fwohci_selfid_input(struct fwohci_softc *sc) 2244 { 2245 int i; 2246 u_int32_t count, val, gen; 2247 u_int32_t *buf; 2248 2249 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2250 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2251 again: 2252 if (val & OHCI_SelfID_Error) { 2253 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2254 return -1; 2255 } 2256 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2257 2258 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2259 0, count << 2, BUS_DMASYNC_POSTREAD); 2260 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2261 2262 #ifdef FW_DEBUG 2263 if (fw_verbose > 1) { 2264 printf("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2265 val); 2266 for (i = 0; i < count; i++) 2267 printf("%s%08x", i&7?" ":"\n ", buf[i]); 2268 printf("\n"); 2269 } 2270 #endif /* FW_DEBUG */ 2271 2272 for (i = 1; i < count; i += 2) { 2273 if (buf[i] != ~buf[i + 1]) 2274 break; 2275 if (buf[i] & 0x00000001) 2276 continue; /* more pkt */ 2277 if (buf[i] & 0x00800000) 2278 continue; /* external id */ 2279 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2280 if ((buf[i] & 0x00400800) == 0x00400800) 2281 sc->sc_irmid = sc->sc_rootid; 2282 } 2283 2284 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2285 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2286 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2287 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2288 goto again; 2289 #ifdef FW_DEBUG 2290 if (fw_verbose) 2291 printf("%s: SelfID Gen mismatch (%d, %d)\n", 2292 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2293 OHCI_BITVAL(val, OHCI_SelfID_Gen)); 2294 #endif 2295 return -1; 2296 } 2297 if (i != count) { 2298 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2299 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2300 #if 1 2301 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2302 /* 2303 * XXX: CXD3222 sometimes fails to DMA 2304 * selfid packet?? 2305 */ 2306 sc->sc_rootid = (count - 1) / 2 - 1; 2307 sc->sc_irmid = sc->sc_rootid; 2308 } else 2309 #endif 2310 return -1; 2311 } 2312 2313 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2314 if ((val & OHCI_NodeId_IDValid) == 0) { 2315 sc->sc_nodeid = 0xffff; /* invalid */ 2316 printf("%s: nodeid is invalid\n", 2317 sc->sc_sc1394.sc1394_dev.dv_xname); 2318 return -1; 2319 } 2320 sc->sc_nodeid = val & 0xffff; 2321 2322 #ifdef FW_DEBUG 2323 if (fw_verbose) 2324 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2325 sc->sc_sc1394.sc1394_dev.dv_xname, 2326 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 2327 sc->sc_rootid, sc->sc_irmid); 2328 #endif 2329 2330 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2331 return -1; 2332 2333 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2334 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2335 OHCI_LinkControl_CycleMaster); 2336 else 2337 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2338 OHCI_LinkControl_CycleMaster); 2339 return 0; 2340 } 2341 2342 /* 2343 * some CSRs are handled by driver. 2344 */ 2345 static void 2346 fwohci_csr_init(struct fwohci_softc *sc) 2347 { 2348 int i; 2349 static u_int32_t csr[] = { 2350 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2351 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2352 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2353 CSR_SB_BROADCAST_CHANNEL 2354 }; 2355 2356 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2357 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2358 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2359 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2360 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2361 } 2362 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2363 } 2364 2365 static int 2366 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2367 { 2368 struct fwohci_pkt res; 2369 u_int32_t reg; 2370 2371 /* 2372 * XXX need to do special functionality other than just r/w... 2373 */ 2374 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2375 2376 if ((reg & 0x03) != 0) { 2377 /* alignment error */ 2378 return IEEE1394_RCODE_ADDRESS_ERROR; 2379 } 2380 #ifdef FW_DEBUG 2381 if (fw_verbose > 1) 2382 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x", 2383 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 2384 #endif 2385 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2386 #ifdef FW_DEBUG 2387 if (fw_verbose > 1) 2388 printf(" -> 0x%08x\n", 2389 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 2390 #endif 2391 *(u_int32_t *)&sc->sc_csr[reg] = 2392 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2393 } else { 2394 #ifdef FW_DEBUG 2395 if (fw_verbose > 1) 2396 printf("\n"); 2397 #endif 2398 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2399 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2400 res.fp_iov[0].iov_len = 4; 2401 res.fp_uio.uio_resid = 4; 2402 res.fp_uio.uio_iovcnt = 1; 2403 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2404 return -1; 2405 } 2406 return IEEE1394_RCODE_COMPLETE; 2407 } 2408 2409 /* 2410 * Mapping between nodeid and unique ID (EUI-64). 2411 * 2412 * Track old mappings and simply update their devices with the new id's when 2413 * they match an existing EUI. This allows proper renumeration of the bus. 2414 */ 2415 static void 2416 fwohci_uid_collect(struct fwohci_softc *sc) 2417 { 2418 int i; 2419 struct fwohci_uidtbl *fu; 2420 struct fwohci_pkt pkt; 2421 struct ieee1394_softc *iea; 2422 2423 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2424 iea->sc1394_node_id = 0xffff; 2425 2426 if (sc->sc_uidtbl != NULL) 2427 free(sc->sc_uidtbl, M_DEVBUF); 2428 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2429 M_WAITOK); 2430 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2431 2432 memset(&pkt, 0, sizeof(pkt)); 2433 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2434 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2435 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2436 fu->fu_valid = 3; 2437 2438 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2439 if (iea) { 2440 iea->sc1394_node_id = i; 2441 #ifdef FW_DEBUG 2442 if (fw_verbose) 2443 printf("%s: Updating nodeid to %d\n", 2444 iea->sc1394_dev.dv_xname, 2445 iea->sc1394_node_id); 2446 #endif 2447 } 2448 continue; 2449 } 2450 fu->fu_valid = 0; 2451 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2452 pkt.fp_hlen = 12; 2453 pkt.fp_dlen = 0; 2454 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2455 (pkt.fp_tcode << 4); 2456 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2457 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2458 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2459 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2460 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2461 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2462 2463 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2464 (pkt.fp_tcode << 4); 2465 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2466 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2467 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2468 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2469 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2470 2471 } 2472 if (sc->sc_rootid == 0) 2473 fwohci_check_nodes(sc); 2474 } 2475 2476 static int 2477 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2478 { 2479 struct fwohci_uidtbl *fu; 2480 struct ieee1394_softc *iea; 2481 struct ieee1394_attach_args fwa; 2482 int i, n, done, rcode, found; 2483 2484 found = 0; 2485 2486 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2487 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2488 if (rcode != IEEE1394_RCODE_COMPLETE || 2489 sc->sc_uidtbl == NULL || 2490 n > sc->sc_rootid) 2491 return 0; 2492 fu = &sc->sc_uidtbl[n]; 2493 if (arg == 0) { 2494 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2495 fu->fu_valid |= 0x1; 2496 } else { 2497 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2498 fu->fu_valid |= 0x2; 2499 } 2500 #ifdef FW_DEBUG 2501 if ((fw_verbose > 1) && fu->fu_valid == 0x3) 2502 printf("fwohci_uid_input: " 2503 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2504 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2505 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7]); 2506 #endif 2507 if (fu->fu_valid == 0x3) { 2508 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2509 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2510 found = 1; 2511 iea->sc1394_node_id = n; 2512 #ifdef FW_DEBUG 2513 if (fw_verbose) 2514 printf("%s: Updating nodeid to %d\n", 2515 iea->sc1394_dev.dv_xname, 2516 iea->sc1394_node_id); 2517 #endif 2518 break; 2519 } 2520 if (!found) { 2521 strcpy(fwa.name, "fwnode"); 2522 memcpy(fwa.uid, fu->fu_uid, 8); 2523 fwa.nodeid = n; 2524 fwa.input = fwohci_input; 2525 fwa.output = fwohci_output; 2526 fwa.inreg = fwohci_inreg; 2527 iea = (struct ieee1394_softc *) 2528 config_found(&sc->sc_sc1394.sc1394_dev, &fwa, 2529 fwohci_print); 2530 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, sc1394_node); 2531 } 2532 } 2533 done = 1; 2534 2535 for (i = 0; i < sc->sc_rootid + 1; i++) { 2536 fu = &sc->sc_uidtbl[i]; 2537 if (fu->fu_valid != 0x3) { 2538 done = 0; 2539 break; 2540 } 2541 } 2542 if (done) 2543 fwohci_check_nodes(sc); 2544 2545 return 0; 2546 } 2547 2548 static void 2549 fwohci_check_nodes(struct fwohci_softc *sc) 2550 { 2551 struct device *detach = NULL; 2552 struct ieee1394_softc *iea; 2553 2554 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2555 /* 2556 * Have to defer detachment until the next 2557 * loop iteration since config_detach 2558 * free's the softc and the loop iterator 2559 * needs data from the softc to move 2560 * forward. 2561 */ 2562 2563 if (detach) { 2564 config_detach(detach, 0); 2565 detach = NULL; 2566 } 2567 if (iea->sc1394_node_id == 0xffff) { 2568 detach = (struct device *)iea; 2569 LIST_REMOVE(iea, sc1394_node); 2570 } 2571 } 2572 if (detach) 2573 config_detach(detach, 0); 2574 } 2575 2576 static int 2577 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2578 { 2579 struct fwohci_uidtbl *fu; 2580 int n; 2581 static const u_int8_t bcast[] = 2582 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2583 2584 fu = sc->sc_uidtbl; 2585 if (fu == NULL) { 2586 notfound: 2587 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2588 return IEEE1394_BCAST_PHY_ID; 2589 fwohci_uid_collect(sc); /* try to get */ 2590 return -1; 2591 } 2592 for (n = 0; ; n++, fu++) { 2593 if (n > sc->sc_rootid) 2594 goto notfound; 2595 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2596 break; 2597 } 2598 return n; 2599 } 2600 2601 /* 2602 * functions to support network interface 2603 */ 2604 static int 2605 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2606 void (*handler)(struct device *, struct mbuf *)) 2607 { 2608 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2609 2610 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2611 fwohci_if_input, handler); 2612 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2613 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2614 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2615 return 0; 2616 } 2617 2618 static int 2619 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2620 { 2621 int n, len; 2622 struct mbuf *m; 2623 struct iovec *iov; 2624 void (*handler)(struct device *, struct mbuf *) = arg; 2625 2626 #ifdef FW_DEBUG 2627 if (fw_verbose > 1) { 2628 int i; 2629 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 2630 pkt->fp_tcode, pkt->fp_dlen); 2631 if (fw_dump) { 2632 for (i = 0; i < pkt->fp_hlen/4; i++) 2633 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 2634 printf("$"); 2635 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2636 iov = &pkt->fp_iov[n]; 2637 for (i = 0; i < iov->iov_len; i++) 2638 printf("%s%02x", 2639 (i%32)?((i%4)?"":" "):"\n\t", 2640 ((u_int8_t *)iov->iov_base)[i]); 2641 printf("$"); 2642 } 2643 } 2644 printf("\n"); 2645 } 2646 #endif /* FW_DEBUG */ 2647 len = pkt->fp_dlen; 2648 MGETHDR(m, M_DONTWAIT, MT_DATA); 2649 if (m == NULL) 2650 return IEEE1394_RCODE_COMPLETE; 2651 m->m_len = 16; 2652 if (len + m->m_len > MHLEN) { 2653 MCLGET(m, M_DONTWAIT); 2654 if ((m->m_flags & M_EXT) == 0) { 2655 m_freem(m); 2656 return IEEE1394_RCODE_COMPLETE; 2657 } 2658 } 2659 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2660 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2661 sc->sc_uidtbl[n].fu_valid != 0x3) { 2662 printf("%s: packet from unknown node: phy id %d\n", 2663 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2664 m_freem(m); 2665 return IEEE1394_RCODE_COMPLETE; 2666 } 2667 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2668 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2669 m->m_flags |= M_BCAST; 2670 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2671 } else { 2672 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2673 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2674 } 2675 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2676 mtod(m, u_int8_t *)[9] = 2677 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2678 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2679 2680 m->m_pkthdr.rcvif = NULL; /* set in child */ 2681 m->m_pkthdr.len = len + m->m_len; 2682 /* 2683 * We may use receive buffer by external mbuf instead of copy here. 2684 * But asynchronous receive buffer must be operate in buffer fill 2685 * mode, so that each receive buffer will shared by multiple mbufs. 2686 * If upper layer doesn't free mbuf soon, e.g. application program 2687 * is suspended, buffer must be reallocated. 2688 * Isochronous buffer must be operate in packet buffer mode, and 2689 * it is easy to map receive buffer to external mbuf. But it is 2690 * used for broadcast/multicast only, and is expected not so 2691 * performance sensitive for now. 2692 * XXX: The performance may be important for multicast case, 2693 * so we should revisit here later. 2694 * -- onoe 2695 */ 2696 n = 0; 2697 iov = pkt->fp_uio.uio_iov; 2698 while (len > 0) { 2699 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2700 iov->iov_len); 2701 m->m_len += iov->iov_len; 2702 len -= iov->iov_len; 2703 iov++; 2704 } 2705 (*handler)(sc->sc_sc1394.sc1394_if, m); 2706 return IEEE1394_RCODE_COMPLETE; 2707 } 2708 2709 static int 2710 fwohci_if_output(struct device *self, struct mbuf *m0, 2711 void (*callback)(struct device *, struct mbuf *)) 2712 { 2713 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2714 struct fwohci_pkt pkt; 2715 u_int8_t *p; 2716 int n, error, spd, hdrlen, maxrec; 2717 2718 p = mtod(m0, u_int8_t *); 2719 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2720 spd = IEEE1394_SPD_S100; /*XXX*/ 2721 maxrec = 512; /*XXX*/ 2722 hdrlen = 8; 2723 } else { 2724 n = fwohci_uid_lookup(sc, p); 2725 if (n < 0) { 2726 printf("%s: nodeid unknown:" 2727 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2728 sc->sc_sc1394.sc1394_dev.dv_xname, 2729 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2730 error = EHOSTUNREACH; 2731 goto end; 2732 } 2733 if (n == IEEE1394_BCAST_PHY_ID) { 2734 printf("%s: broadcast with !M_MCAST\n", 2735 sc->sc_sc1394.sc1394_dev.dv_xname); 2736 #ifdef FW_DEBUG 2737 if (fw_dump) { 2738 struct mbuf *m; 2739 printf("packet:"); 2740 for (m = m0; m != NULL; m = m->m_next) { 2741 for (n = 0; n < m->m_len; n++) 2742 printf("%s%02x", (n%32)? 2743 ((n%4)?"":" "):"\n\t", 2744 mtod(m, u_int8_t *)[n]); 2745 printf("$"); 2746 } 2747 printf("\n"); 2748 } 2749 #endif 2750 error = EHOSTUNREACH; 2751 goto end; 2752 } 2753 maxrec = 2 << p[8]; 2754 spd = p[9]; 2755 hdrlen = 0; 2756 } 2757 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2758 #ifdef FW_DEBUG 2759 if (fw_verbose) 2760 printf("fwohci_if_output: spd (%d) is faster than %d\n", 2761 spd, sc->sc_sc1394.sc1394_link_speed); 2762 #endif 2763 spd = sc->sc_sc1394.sc1394_link_speed; 2764 } 2765 if (maxrec > (512 << spd)) { 2766 #ifdef FW_DEBUG 2767 if (fw_verbose) 2768 printf("fwohci_if_output: maxrec (%d) is larger for" 2769 " spd (%d)\n", maxrec, spd); 2770 #endif 2771 maxrec = 512 << spd; 2772 } 2773 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2774 #ifdef FW_DEBUG 2775 if (fw_verbose) 2776 printf("fwohci_if_output: maxrec (%d) is larger than" 2777 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive); 2778 #endif 2779 maxrec >>= 1; 2780 } 2781 if (maxrec < 512) { 2782 #ifdef FW_DEBUG 2783 if (fw_verbose) 2784 printf("fwohci_if_output: maxrec (%d) is smaller" 2785 " than minimum\n", maxrec); 2786 #endif 2787 maxrec = 512; 2788 } 2789 2790 m_adj(m0, 16 - hdrlen); 2791 if (m0->m_pkthdr.len > maxrec) { 2792 #ifdef FW_DEBUG 2793 if (fw_verbose) 2794 printf("fwohci_if_output: packet too big:" 2795 " hdr %d, pktlen %d, maxrec %d\n", 2796 hdrlen, m0->m_pkthdr.len, maxrec); 2797 #endif 2798 error = E2BIG; /*XXX*/ 2799 goto end; 2800 } 2801 2802 memset(&pkt, 0, sizeof(pkt)); 2803 pkt.fp_uio.uio_iov = pkt.fp_iov; 2804 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2805 pkt.fp_uio.uio_rw = UIO_WRITE; 2806 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2807 /* construct GASP header */ 2808 p = mtod(m0, u_int8_t *); 2809 p[0] = sc->sc_nodeid >> 8; 2810 p[1] = sc->sc_nodeid & 0xff; 2811 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2812 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2813 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2814 pkt.fp_hlen = 8; 2815 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2816 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2817 OHCI_NodeId_NodeNumber) << 8); 2818 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2819 } else { 2820 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2821 pkt.fp_hlen = 16; 2822 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2823 (spd << 16); 2824 pkt.fp_hdr[1] = 2825 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2826 (p[10] << 8) | p[11]; 2827 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2828 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2829 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2830 } 2831 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2832 pkt.fp_dlen = m0->m_pkthdr.len; 2833 pkt.fp_m = m0; 2834 pkt.fp_callback = callback; 2835 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2836 m0 = pkt.fp_m; 2837 end: 2838 if (m0 != NULL) { 2839 if (callback) 2840 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2841 else 2842 m_freem(m0); 2843 } 2844 return error; 2845 } 2846 2847 /* 2848 * High level routines to provide abstraction to attaching layers to 2849 * send/receive data. 2850 */ 2851 2852 static int 2853 fwohci_input(struct ieee1394_abuf *ab) 2854 { 2855 struct fwohci_pkt pkt; 2856 struct ieee1394_softc *sc = ab->ab_node; 2857 struct fwohci_softc *psc = 2858 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2859 u_int32_t high, lo; 2860 int rv, tcode; 2861 2862 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2863 lo = (ab->ab_csr & 0x00000000ffffffff); 2864 2865 memset(&pkt, 0, sizeof(pkt)); 2866 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | high; 2867 pkt.fp_hdr[2] = lo; 2868 pkt.fp_dlen = 0; 2869 2870 if (ab->ab_length == 4) { 2871 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2872 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2873 pkt.fp_hlen = 12; 2874 } else { 2875 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2876 pkt.fp_hlen = 16; 2877 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2878 pkt.fp_hdr[3] = (ab->ab_length << 16); 2879 } 2880 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2881 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2882 2883 rv = fwohci_handler_set(psc, tcode, ab->ab_node->sc1394_node_id, 2884 psc->sc_tlabel, fwohci_extract_resp, ab); 2885 if (rv) 2886 return rv; 2887 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2888 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2889 return rv; 2890 } 2891 2892 static int 2893 fwohci_output(struct ieee1394_abuf *ab) 2894 { 2895 struct fwohci_pkt pkt; 2896 struct ieee1394_softc *sc = ab->ab_node; 2897 struct fwohci_softc *psc = 2898 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2899 u_int32_t high, lo; 2900 int rv; 2901 2902 if (ab->ab_length > sc->sc1394_max_receive) { 2903 #ifdef FW_DEBUG 2904 if (fw_verbose) 2905 printf("Packet too large: %d\n", ab->ab_length); 2906 #endif 2907 return E2BIG; 2908 } 2909 2910 memset(&pkt, 0, sizeof(pkt)); 2911 2912 pkt.fp_tcode = ab->ab_tcode; 2913 pkt.fp_uio.uio_iov = pkt.fp_iov; 2914 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2915 pkt.fp_uio.uio_rw = UIO_WRITE; 2916 2917 switch (ab->ab_tcode) { 2918 case IEEE1394_TCODE_WRITE_RESP: 2919 pkt.fp_hlen = 12; 2920 case IEEE1394_TCODE_READ_RESP_QUAD: 2921 case IEEE1394_TCODE_READ_RESP_BLOCK: 2922 if (!pkt.fp_hlen) 2923 pkt.fp_hlen = 16; 2924 high = ab->ab_retlen; 2925 ab->ab_retlen = 0; 2926 lo = 0; 2927 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2928 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2929 break; 2930 default: 2931 pkt.fp_hlen = 16; 2932 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2933 lo = (ab->ab_csr & 0x00000000ffffffff); 2934 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2935 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2936 break; 2937 } 2938 2939 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | high; 2940 pkt.fp_hdr[2] = lo; 2941 if (pkt.fp_hlen == 16) { 2942 if (ab->ab_length == 4) { 2943 pkt.fp_hdr[3] = ab->ab_data[0]; 2944 pkt.fp_dlen = 0; 2945 } else { 2946 pkt.fp_hdr[3] = (ab->ab_length << 16); 2947 pkt.fp_dlen = ab->ab_length; 2948 pkt.fp_uio.uio_iovcnt = 1; 2949 pkt.fp_uio.uio_resid = ab->ab_length; 2950 pkt.fp_iov[0].iov_base = ab->ab_data; 2951 pkt.fp_iov[0].iov_len = ab->ab_length; 2952 } 2953 } 2954 switch (ab->ab_tcode) { 2955 case IEEE1394_TCODE_WRITE_RESP: 2956 case IEEE1394_TCODE_READ_RESP_QUAD: 2957 case IEEE1394_TCODE_READ_RESP_BLOCK: 2958 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2959 break; 2960 default: 2961 rv = fwohci_handler_set(psc, IEEE1394_TCODE_WRITE_RESP, 2962 ab->ab_node->sc1394_node_id, psc->sc_tlabel, 2963 fwohci_extract_resp, ab); 2964 if (rv) 2965 return rv; 2966 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2967 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2968 break; 2969 } 2970 return rv; 2971 } 2972 2973 static int 2974 fwohci_extract_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2975 { 2976 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 2977 struct fwohci_pkt newpkt; 2978 u_int32_t *cur, high, lo; 2979 int i, rcode, rv; 2980 2981 /* 2982 * No callback just means we want to have something clean up the abuf. 2983 */ 2984 if (!ab->ab_cb) { 2985 if (ab->ab_data) 2986 free(ab->ab_data, M_1394DATA); 2987 if (ab) 2988 free(ab, M_1394DATA); 2989 return 0; 2990 } 2991 2992 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2993 2994 /* Some area's (like the config rom want to be read as quadlets only. */ 2995 2996 if (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2997 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2998 (pkt->fp_tcode == IEEE1394_TCODE_READ_RESP_BLOCK)) { 2999 3000 /* Read the area in quadlet chunks (internally track this). */ 3001 3002 memset(&newpkt, 0, sizeof(newpkt)); 3003 3004 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3005 lo = (ab->ab_csr & 0x00000000ffffffff); 3006 3007 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3008 newpkt.fp_hlen = 12; 3009 newpkt.fp_dlen = 0; 3010 newpkt.fp_hdr[1] = 3011 ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | high; 3012 newpkt.fp_hdr[2] = lo; 3013 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3014 (newpkt.fp_tcode << 4); 3015 3016 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3017 ab->ab_node->sc1394_node_id, sc->sc_tlabel, 3018 fwohci_multi_resp, ab); 3019 if (rv) 3020 return rv; 3021 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3022 fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3023 } else { 3024 3025 /* 3026 * Recombine all the iov data into 1 chunk for higher 3027 * level code. 3028 */ 3029 3030 cur = ab->ab_data; 3031 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3032 /* 3033 * Make sure and don't exceed the buffer 3034 * allocated for return. 3035 */ 3036 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3037 ab->ab_length) { 3038 memcpy(cur, pkt->fp_iov[i].iov_base, 3039 (ab->ab_length - ab->ab_retlen)); 3040 ab->ab_retlen = ab->ab_length; 3041 break; 3042 } 3043 memcpy(cur, pkt->fp_iov[i].iov_base, 3044 pkt->fp_iov[i].iov_len); 3045 cur += pkt->fp_iov[i].iov_len; 3046 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3047 } 3048 (*ab->ab_cb)(ab, rcode); 3049 } 3050 return IEEE1394_RCODE_COMPLETE; 3051 } 3052 3053 static int 3054 fwohci_multi_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3055 { 3056 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3057 struct fwohci_pkt newpkt; 3058 u_int32_t high, lo; 3059 int rcode, rv; 3060 3061 /* 3062 * Bad return codes from the wire, just return what's already in the 3063 * buf. 3064 */ 3065 3066 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3067 3068 if (rcode) { 3069 (*ab->ab_cb)(ab, rcode); 3070 return rcode; 3071 } 3072 3073 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3074 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3075 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3076 ab->ab_retlen = ab->ab_length; 3077 } else { 3078 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3079 pkt->fp_iov[0].iov_base, 4); 3080 ab->ab_retlen += 4; 3081 } 3082 /* Still more, loop and read 4 more bytes. */ 3083 if (ab->ab_retlen < ab->ab_length) { 3084 memset(&newpkt, 0, sizeof(newpkt)); 3085 3086 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3087 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3088 3089 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3090 newpkt.fp_hlen = 12; 3091 newpkt.fp_dlen = 0; 3092 newpkt.fp_hdr[1] = 3093 ((0xffc0 | ab->ab_node->sc1394_node_id) << 16) | high; 3094 newpkt.fp_hdr[2] = lo; 3095 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3096 (newpkt.fp_tcode << 4); 3097 3098 /* 3099 * Bad return code. Just give up and return what's 3100 * come in now. 3101 */ 3102 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3103 ab->ab_node->sc1394_node_id, sc->sc_tlabel, 3104 fwohci_multi_resp, ab); 3105 if (rv) { 3106 (*ab->ab_cb)(ab, rcode); 3107 return IEEE1394_RCODE_DATA_ERROR; 3108 } 3109 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3110 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3111 if (rv) { 3112 (*ab->ab_cb)(ab, rcode); 3113 return IEEE1394_RCODE_DATA_ERROR; 3114 } 3115 } else 3116 (*ab->ab_cb)(ab, rcode); 3117 return IEEE1394_RCODE_COMPLETE; 3118 } 3119 3120 static int 3121 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3122 { 3123 struct ieee1394_softc *sc = ab->ab_node; 3124 struct fwohci_softc *psc = 3125 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3126 u_int32_t high, lo; 3127 int i, rv; 3128 3129 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3130 lo = (ab->ab_csr & 0x00000000ffffffff); 3131 3132 switch (ab->ab_tcode) { 3133 case IEEE1394_TCODE_READ_REQ_QUAD: 3134 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3135 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3136 fwohci_parse_input, ab); 3137 break; 3138 case IEEE1394_TCODE_READ_REQ_BLOCK: 3139 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3140 if (allow) { 3141 for (i = 0; i < (ab->ab_length / 4); i++) { 3142 rv = fwohci_handler_set(psc, ab->ab_tcode, 3143 high, lo + (i * 4), 3144 fwohci_parse_input, ab); 3145 if (rv) 3146 return rv; 3147 } 3148 ab->ab_data = (void *)1; 3149 } else 3150 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3151 fwohci_parse_input, ab); 3152 break; 3153 default: 3154 #ifdef FW_DEBUG 3155 if (fw_verbose) 3156 printf("Invalid registration tcode: %d\n", 3157 ab->ab_tcode); 3158 #endif 3159 return -1; 3160 break; 3161 } 3162 return rv; 3163 } 3164 3165 static int 3166 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3167 { 3168 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3169 u_int64_t csr; 3170 u_int32_t *cur; 3171 int i, count; 3172 3173 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3174 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3175 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3176 3177 switch (ab->ab_tcode) { 3178 case IEEE1394_TCODE_READ_REQ_QUAD: 3179 ab->ab_retlen = 4; 3180 break; 3181 case IEEE1394_TCODE_READ_REQ_BLOCK: 3182 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3183 if (ab->ab_data) { 3184 if ((csr + ab->ab_retlen) > 3185 (ab->ab_csr + ab->ab_length)) 3186 return IEEE1394_RCODE_ADDRESS_ERROR; 3187 ab->ab_data = NULL; 3188 } else 3189 if (ab->ab_retlen != ab->ab_length) 3190 return IEEE1394_RCODE_ADDRESS_ERROR; 3191 break; 3192 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3193 ab->ab_retlen = 4; 3194 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3195 if (!ab->ab_retlen) 3196 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3197 if (ab->ab_data) { 3198 if ((csr + ab->ab_retlen) > 3199 (ab->ab_csr + ab->ab_length)) 3200 return IEEE1394_RCODE_ADDRESS_ERROR; 3201 ab->ab_data = NULL; 3202 } else 3203 if (ab->ab_retlen != ab->ab_length) 3204 return IEEE1394_RCODE_ADDRESS_ERROR; 3205 3206 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3207 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3208 ab->ab_data[0] = pkt->fp_hdr[3]; 3209 else { 3210 count = 0; 3211 cur = ab->ab_data; 3212 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3213 memcpy(cur, pkt->fp_iov[i].iov_base, 3214 pkt->fp_iov[i].iov_len); 3215 cur += pkt->fp_iov[i].iov_len; 3216 count += pkt->fp_iov[i].iov_len; 3217 } 3218 if (ab->ab_retlen != count) 3219 panic("Packet claims %d length " 3220 "but only %d bytes returned\n", 3221 ab->ab_retlen, count); 3222 } 3223 break; 3224 default: 3225 panic("Got a callback for a tcode that wasn't requested: %d\n", 3226 ab->ab_tcode); 3227 break; 3228 } 3229 ab->ab_csr = csr; 3230 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3231 return -1; 3232 } 3233
Indexes created Wed Sep 24 15:09:51 GMT 2025