fwohci.c revision 1.29
1 /* $NetBSD: fwohci.c,v 1.29 2001/05/11 06:10:44 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 115 116 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 117 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 119 120 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 121 struct fwohci_pkt *); 122 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 123 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 124 struct fwohci_pkt *); 125 126 static int fwohci_guidrom_init(struct fwohci_softc *); 127 static void fwohci_configrom_init(struct fwohci_softc *); 128 static int fwohci_configrom_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 static void fwohci_selfid_init(struct fwohci_softc *); 131 static int fwohci_selfid_input(struct fwohci_softc *); 132 133 static void fwohci_csr_init(struct fwohci_softc *); 134 static int fwohci_csr_input(struct fwohci_softc *, void *, 135 struct fwohci_pkt *); 136 137 static void fwohci_uid_collect(struct fwohci_softc *); 138 static int fwohci_uid_input(struct fwohci_softc *, void *, 139 struct fwohci_pkt *); 140 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 141 static void fwohci_check_nodes(struct fwohci_softc *); 142 143 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 144 void (*)(struct device *, struct mbuf *)); 145 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 146 static int fwohci_if_output(struct device *, struct mbuf *, 147 void (*)(struct device *, struct mbuf *)); 148 static int fwohci_read(struct ieee1394_abuf *); 149 static int fwohci_write(struct ieee1394_abuf *); 150 static int fwohci_extract_resp(struct fwohci_softc *, void *, 151 struct fwohci_pkt *); 152 static int fwohci_multi_resp(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_inreg(struct ieee1394_abuf *, int); 155 static int fwohci_parse_input(struct fwohci_softc *, void *, 156 struct fwohci_pkt *); 157 158 #ifdef FW_DEBUG 159 160 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 161 162 #define DPRINTF(x) if (fwdebug) printf x 163 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 164 int fwdebug = 3; 165 #else 166 #define DPRINTF(x) 167 #define DPRINTFN(n,x) 168 #endif 169 170 int 171 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 172 { 173 int i; 174 u_int32_t val; 175 #if 0 176 int error; 177 #endif 178 179 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 180 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 181 182 /* 183 * Wait for reset completion 184 */ 185 for (i = 0; i < OHCI_LOOP; i++) { 186 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 187 if ((val & OHCI_HCControl_SoftReset) == 0) 188 break; 189 } 190 191 /* What dialect of OHCI is this device? 192 */ 193 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 194 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 195 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 196 197 LIST_INIT(&sc->sc_nodelist); 198 199 if (fwohci_guidrom_init(sc) != 0) { 200 printf("\n%s: fatal: no global UID ROM\n", 201 sc->sc_sc1394.sc1394_dev.dv_xname); 202 return -1; 203 } 204 205 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 206 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 207 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 208 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 209 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 210 211 /* Get the maximum link speed and receive size 212 */ 213 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 214 sc->sc_sc1394.sc1394_link_speed = 215 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 216 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 217 printf(", %s", 218 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 219 } else { 220 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 221 } 222 223 /* MaxRec is encoded as log2(max_rec_octets)-1 224 */ 225 sc->sc_sc1394.sc1394_max_receive = 226 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 227 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 228 229 /* 230 * Count how many isochronous ctx we have. 231 */ 232 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 233 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 234 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 235 for (i = 0; val != 0; val >>= 1) { 236 if (val & 0x1) 237 i++; 238 } 239 sc->sc_isoctx = i; 240 printf(", %d iso_ctx", sc->sc_isoctx); 241 242 printf("\n"); 243 244 #if 0 245 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 246 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 247 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 248 return error; 249 #endif 250 251 sc->sc_dying = 0; 252 253 kthread_create(fwohci_create_event_thread, sc); 254 return 0; 255 } 256 257 int 258 fwohci_intr(void *arg) 259 { 260 struct fwohci_softc * const sc = arg; 261 int progress = 0; 262 u_int32_t intmask, iso; 263 264 for (;;) { 265 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 266 267 /* 268 * On a bus reset, everything except bus reset gets 269 * cleared. That can't get cleared until the selfid 270 * phase completes (which happens outside the 271 * interrupt routines). So if just a bus reset is left 272 * in the mask and it's already in the sc_intmask, 273 * just return. 274 */ 275 276 if ((intmask == 0) || 277 (progress && (intmask == OHCI_Int_BusReset) && 278 (sc->sc_intmask & OHCI_Int_BusReset))) { 279 if (progress) 280 wakeup(fwohci_event_thread); 281 return progress; 282 } 283 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 284 intmask & ~OHCI_Int_BusReset); 285 #ifdef FW_DEBUG 286 DPRINTFN(1, ("%s: intmask=0x%08x:", 287 sc->sc_sc1394.sc1394_dev.dv_xname, intmask)); 288 if (intmask & OHCI_Int_CycleTooLong) 289 DPRINTFN(1, (" CycleTooLong")); 290 if (intmask & OHCI_Int_UnrecoverableError) 291 DPRINTFN(1, (" UnrecoverableError")); 292 if (intmask & OHCI_Int_CycleInconsistent) 293 DPRINTFN(1, (" CycleInconsistent")); 294 if (intmask & OHCI_Int_BusReset) 295 DPRINTFN(1, (" BusReset")); 296 if (intmask & OHCI_Int_SelfIDComplete) 297 DPRINTFN(1, (" SelfIDComplete")); 298 if (intmask & OHCI_Int_LockRespErr) 299 DPRINTFN(1, (" LockRespErr")); 300 if (intmask & OHCI_Int_PostedWriteErr) 301 DPRINTFN(1, (" PostedWriteErr")); 302 if (intmask & OHCI_Int_ReqTxComplete) 303 DPRINTFN(1, (" ReqTxComplete(0x%04x)", 304 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 305 OHCI_SUBREG_ContextControlClear))); 306 if (intmask & OHCI_Int_RespTxComplete) 307 DPRINTFN(1, (" RespTxComplete(0x%04x)", 308 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 309 OHCI_SUBREG_ContextControlClear))); 310 if (intmask & OHCI_Int_ARRS) 311 DPRINTFN(1, (" ARRS(0x%04x)", 312 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 313 OHCI_SUBREG_ContextControlClear))); 314 if (intmask & OHCI_Int_ARRQ) 315 DPRINTFN(1, (" ARRQ(0x%04x)", 316 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 317 OHCI_SUBREG_ContextControlClear))); 318 if (intmask & OHCI_Int_IsochRx) 319 DPRINTFN(1, (" IsochRx(0x%08x)", 320 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear))); 321 if (intmask & OHCI_Int_IsochTx) 322 DPRINTFN(1, (" IsochTx(0x%08x)", 323 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear))); 324 if (intmask & OHCI_Int_RQPkt) 325 DPRINTFN(1, (" RQPkt(0x%04x)", 326 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 327 OHCI_SUBREG_ContextControlClear))); 328 if (intmask & OHCI_Int_RSPkt) 329 DPRINTFN(1, (" RSPkt(0x%04x)", 330 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 331 OHCI_SUBREG_ContextControlClear))); 332 DPRINTFN(1, ("\n")); 333 #endif /* FW_DEBUG */ 334 335 if (intmask & OHCI_Int_BusReset) { 336 /* 337 * According to OHCI spec 6.1.1 "busReset", 338 * All asynchronous transmit must be stopped before 339 * clearing BusReset. Moreover, the BusReset 340 * interrupt bit should not be cleared during the 341 * SelfID phase. Thus we turned off interrupt mask 342 * bit of BusReset instead until SelfID completion 343 * or SelfID timeout. 344 */ 345 intmask &= OHCI_Int_SelfIDComplete; 346 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 347 OHCI_Int_BusReset); 348 sc->sc_intmask = intmask; 349 sc->sc_intmask |= OHCI_Int_BusReset; 350 } 351 352 if (intmask & OHCI_Int_SelfIDComplete) 353 sc->sc_intmask |= OHCI_Int_SelfIDComplete; 354 355 if (intmask & OHCI_Int_ReqTxComplete) 356 sc->sc_intmask |= OHCI_Int_ReqTxComplete; 357 if (intmask & OHCI_Int_RespTxComplete) 358 sc->sc_intmask |= OHCI_Int_RespTxComplete; 359 if (intmask & OHCI_Int_RQPkt) 360 sc->sc_intmask |= OHCI_Int_RQPkt; 361 if (intmask & OHCI_Int_RSPkt) 362 sc->sc_intmask |= OHCI_Int_RSPkt; 363 if (intmask & OHCI_Int_IsochTx) { 364 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 365 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 366 sc->sc_intmask |= OHCI_Int_IsochTx; 367 } 368 if (intmask & OHCI_Int_IsochRx) { 369 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 370 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 371 sc->sc_iso |= iso; 372 sc->sc_intmask |= OHCI_Int_IsochRx; 373 } 374 375 if (!progress) { 376 sc->sc_intrcnt.ev_count++; 377 progress = 1; 378 } 379 } 380 } 381 382 static void 383 fwohci_create_event_thread(void *arg) 384 { 385 struct fwohci_softc *sc = arg; 386 387 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 388 sc->sc_sc1394.sc1394_dev.dv_xname)) { 389 printf("%s: unable to create event thread\n", 390 sc->sc_sc1394.sc1394_dev.dv_xname); 391 panic("fwohci_create_event_thread"); 392 } 393 } 394 395 static void 396 fwohci_thread_init(void *arg) 397 { 398 struct fwohci_softc *sc = arg; 399 int i; 400 401 /* 402 * Allocate descriptors 403 */ 404 if (fwohci_desc_alloc(sc)) { 405 printf("%s: not enabling interrupts\n", 406 sc->sc_sc1394.sc1394_dev.dv_xname); 407 kthread_exit(1); 408 } 409 410 /* 411 * Enable Link Power 412 */ 413 414 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 415 416 /* 417 * Allocate DMA Context 418 */ 419 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 420 OHCI_CTX_ASYNC_RX_REQUEST); 421 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 422 OHCI_CTX_ASYNC_RX_RESPONSE); 423 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 424 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 425 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 426 M_DEVBUF, M_WAITOK); 427 for (i = 0; i < sc->sc_isoctx; i++) 428 sc->sc_ctx_ir[i] = NULL; 429 430 /* 431 * Allocate buffer for configuration ROM and SelfID buffer 432 */ 433 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 434 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 435 436 callout_init(&sc->sc_selfid_callout); 437 438 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 439 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 440 441 /* 442 * establish hooks for shutdown and suspend/resume 443 */ 444 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 445 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 446 447 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 448 fwohci_print); 449 450 /* Main loop. It's not coming back normally. */ 451 452 fwohci_event_thread(sc); 453 454 kthread_exit(0); 455 } 456 457 static void 458 fwohci_event_thread(struct fwohci_softc *sc) 459 { 460 int i, s; 461 u_int32_t intmask, iso; 462 463 s = splbio(); 464 465 /* 466 * Initialize hardware registers. 467 */ 468 469 fwohci_hw_init(sc); 470 471 /* Initial Bus Reset */ 472 fwohci_phy_busreset(sc); 473 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 474 splx(s); 475 476 while (!sc->sc_dying) { 477 while (1) { 478 s = splbio(); 479 intmask = sc->sc_intmask; 480 if (intmask) { 481 splx(s); 482 if (intmask & OHCI_Int_BusReset) { 483 s = splbio(); 484 sc->sc_intmask &= ~OHCI_Int_BusReset; 485 splx(s); 486 fwohci_buf_stop(sc); 487 fwohci_buf_init(sc); 488 if (sc->sc_uidtbl != NULL) { 489 free(sc->sc_uidtbl, M_DEVBUF); 490 sc->sc_uidtbl = NULL; 491 } 492 493 callout_reset(&sc->sc_selfid_callout, 494 OHCI_SELFID_TIMEOUT, 495 (void (*)(void *)) 496 fwohci_phy_busreset, sc); 497 sc->sc_nodeid = 0xffff; /* indicate 498 invalid */ 499 sc->sc_rootid = 0; 500 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 501 } 502 if (intmask & OHCI_Int_SelfIDComplete) { 503 s = splbio(); 504 sc->sc_intmask &= 505 ~OHCI_Int_SelfIDComplete; 506 OHCI_CSR_WRITE(sc, 507 OHCI_REG_IntEventClear, 508 OHCI_Int_BusReset); 509 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 510 OHCI_Int_BusReset); 511 splx(s); 512 callout_stop(&sc->sc_selfid_callout); 513 if (fwohci_selfid_input(sc) == 0) { 514 fwohci_buf_start(sc); 515 fwohci_uid_collect(sc); 516 } 517 } 518 if (intmask & OHCI_Int_ReqTxComplete) { 519 s = splbio(); 520 sc->sc_intmask &= 521 ~OHCI_Int_ReqTxComplete; 522 splx(s); 523 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 524 } 525 if (intmask & OHCI_Int_RespTxComplete) { 526 s = splbio(); 527 sc->sc_intmask &= 528 ~OHCI_Int_RespTxComplete; 529 splx(s); 530 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 531 } 532 if (intmask & OHCI_Int_RQPkt) { 533 s = splbio(); 534 sc->sc_intmask &= ~OHCI_Int_RQPkt; 535 splx(s); 536 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 537 } 538 if (intmask & OHCI_Int_RSPkt) { 539 s = splbio(); 540 sc->sc_intmask &= ~OHCI_Int_RSPkt; 541 splx(s); 542 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 543 } 544 if (intmask & OHCI_Int_IsochTx) { 545 s = splbio(); 546 sc->sc_intmask &= ~OHCI_Int_IsochTx; 547 splx(s); 548 } 549 if (intmask & OHCI_Int_IsochRx) { 550 s = splbio(); 551 sc->sc_intmask &= ~OHCI_Int_IsochRx; 552 iso = sc->sc_iso; 553 sc->sc_iso = 0; 554 splx(s); 555 for (i = 0; i < sc->sc_isoctx; i++) { 556 if ((iso & (1 << i)) && 557 sc->sc_ctx_ir[i] != NULL) 558 fwohci_ir_input(sc, 559 sc->sc_ctx_ir[i]); 560 } 561 } 562 } else 563 break; 564 } 565 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 566 splx(s); 567 } 568 } 569 570 #if 0 571 static int 572 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 573 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 574 { 575 bus_dma_segment_t segs[1]; 576 int error, nsegs, steps; 577 578 steps = 0; 579 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 580 segs, 1, &nsegs, flags); 581 if (error) 582 goto cleanup; 583 584 steps = 1; 585 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 586 kvap, flags); 587 if (error) 588 goto cleanup; 589 590 if (error == 0) 591 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 592 size, flags, mapp); 593 if (error) 594 goto cleanup; 595 if (error == 0) 596 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 597 flags); 598 if (error) 599 goto cleanup; 600 601 cleanup: 602 switch (steps) { 603 case 1: 604 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 605 } 606 607 return error; 608 } 609 #endif 610 611 int 612 fwohci_print(void *aux, const char *pnp) 613 { 614 char *name = aux; 615 616 if (pnp) 617 printf("%s at %s", name, pnp); 618 619 return UNCONF; 620 } 621 622 static void 623 fwohci_hw_init(struct fwohci_softc *sc) 624 { 625 int i; 626 u_int32_t val; 627 628 /* 629 * Software Reset. 630 */ 631 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 632 for (i = 0; i < OHCI_LOOP; i++) { 633 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 634 if ((val & OHCI_HCControl_SoftReset) == 0) 635 break; 636 } 637 638 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 639 640 /* 641 * First, initilize CSRs with undefined value to default settings. 642 */ 643 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 644 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 645 #if 0 646 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 647 #else 648 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 649 #endif 650 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 651 for (i = 0; i < sc->sc_isoctx; i++) { 652 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 653 ~0); 654 } 655 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 656 657 fwohci_configrom_init(sc); 658 fwohci_selfid_init(sc); 659 fwohci_buf_init(sc); 660 fwohci_csr_init(sc); 661 662 /* 663 * Final CSR settings. 664 */ 665 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 666 OHCI_LinkControl_CycleTimerEnable | 667 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 668 669 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 670 671 /* clear receive filter */ 672 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 673 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 674 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 675 676 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 677 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 678 #if BYTE_ORDER == BIG_ENDIAN 679 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 680 OHCI_HCControl_NoByteSwapData); 681 #endif 682 683 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 684 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 685 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 686 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 687 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 688 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 689 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 690 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 691 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 692 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 693 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 694 695 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 696 697 /* 698 * Start the receivers 699 */ 700 fwohci_buf_start(sc); 701 } 702 703 static void 704 fwohci_power(int why, void *arg) 705 { 706 struct fwohci_softc *sc = arg; 707 int s; 708 709 s = splbio(); 710 switch (why) { 711 case PWR_SUSPEND: 712 case PWR_STANDBY: 713 fwohci_shutdown(sc); 714 break; 715 case PWR_RESUME: 716 fwohci_hw_init(sc); 717 fwohci_phy_busreset(sc); 718 break; 719 case PWR_SOFTSUSPEND: 720 case PWR_SOFTSTANDBY: 721 case PWR_SOFTRESUME: 722 break; 723 } 724 splx(s); 725 } 726 727 static void 728 fwohci_shutdown(void *arg) 729 { 730 struct fwohci_softc *sc = arg; 731 u_int32_t val; 732 733 callout_stop(&sc->sc_selfid_callout); 734 /* disable all interrupt */ 735 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 736 fwohci_buf_stop(sc); 737 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 738 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 739 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 740 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 741 fwohci_phy_busreset(sc); 742 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 743 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 744 } 745 746 /* 747 * COMMON FUNCTIONS 748 */ 749 750 /* 751 * read the PHY Register. 752 */ 753 static u_int8_t 754 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 755 { 756 int i; 757 u_int32_t val; 758 759 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 760 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 761 for (i = 0; i < OHCI_LOOP; i++) { 762 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 763 OHCI_PhyControl_RdDone) 764 break; 765 } 766 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 767 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 768 } 769 770 /* 771 * write the PHY Register. 772 */ 773 static void 774 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 775 { 776 int i; 777 778 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 779 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 780 (val << OHCI_PhyControl_WrData_BITPOS)); 781 for (i = 0; i < OHCI_LOOP; i++) { 782 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 783 OHCI_PhyControl_WrReg)) 784 break; 785 } 786 } 787 788 /* 789 * Initiate Bus Reset 790 */ 791 static void 792 fwohci_phy_busreset(struct fwohci_softc *sc) 793 { 794 int s; 795 u_int8_t val; 796 797 s = splbio(); 798 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 799 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 800 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 801 callout_stop(&sc->sc_selfid_callout); 802 val = fwohci_phy_read(sc, 1); 803 val = (val & 0x80) | /* preserve RHB (force root) */ 804 0x40 | /* Initiate Bus Reset */ 805 0x3f; /* default GAP count */ 806 fwohci_phy_write(sc, 1, val); 807 splx(s); 808 } 809 810 /* 811 * PHY Packet 812 */ 813 static void 814 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 815 { 816 u_int32_t val; 817 u_int8_t key, phyid; 818 819 val = pkt->fp_hdr[1]; 820 if (val != ~pkt->fp_hdr[2]) { 821 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 822 OHCI_CTXCTL_EVENT_BUS_RESET) { 823 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 824 pkt->fp_hdr[2])); 825 } else { 826 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 827 sc->sc_sc1394.sc1394_dev.dv_xname, val, 828 pkt->fp_hdr[2]); 829 } 830 return; 831 } 832 key = (val & 0xc0000000) >> 30; 833 phyid = (val & 0x3f000000) >> 24; 834 switch (key) { 835 case 0: 836 #ifdef FW_DEBUG 837 DPRINTFN(1, ("fwohci_phy_input: PHY Config from %d:", phyid)); 838 if (val & 0x00800000) 839 DPRINTFN(1, (" ForceRoot")); 840 if (val & 0x00400000) 841 DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16)); 842 printf("\n"); 843 #endif 844 break; 845 case 1: 846 DPRINTFN(1, ("fwohci_phy_input: Link-on from %d\n", phyid)); 847 break; 848 case 2: 849 #ifdef FW_DEBUG 850 DPRINTFN(1, ("fwohci_phy_input: SelfID from %d:", phyid)); 851 if (val & 0x00800000) { 852 DPRINTFN(1, (" #%d", (val & 0x00700000) >> 20)); 853 } else { 854 if (val & 0x00400000) 855 DPRINTFN(1, (" LinkActive")); 856 DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16)); 857 DPRINTFN(1, (" Spd=S%d", 858 100 << ((val & 0x0000c000) >> 14))); 859 if (val & 0x00000800) 860 DPRINTFN(1, (" Cont")); 861 if (val & 0x00000002) 862 DPRINTFN(1, (" InitiateBusReset")); 863 } 864 if (val & 0x00000001) 865 DPRINTFN(1, (" +")); 866 DPRINTFN(1, ("\n")); 867 #endif 868 break; 869 default: 870 printf("%s: unknown PHY packet: 0x%08x\n", 871 sc->sc_sc1394.sc1394_dev.dv_xname, val); 872 break; 873 } 874 } 875 876 /* 877 * Descriptor for context DMA. 878 */ 879 static int 880 fwohci_desc_alloc(struct fwohci_softc *sc) 881 { 882 int error, mapsize, dsize; 883 884 /* 885 * allocate descriptor buffer 886 */ 887 888 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 889 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 890 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 891 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 892 mapsize = howmany(sc->sc_descsize, NBBY); 893 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 894 memset(sc->sc_descmap, 0, mapsize); 895 896 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 897 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 898 printf("%s: unable to allocate descriptor buffer, error = %d\n", 899 sc->sc_sc1394.sc1394_dev.dv_xname, error); 900 goto fail_0; 901 } 902 903 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 904 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 905 != 0) { 906 printf("%s: unable to map descriptor buffer, error = %d\n", 907 sc->sc_sc1394.sc1394_dev.dv_xname, error); 908 goto fail_1; 909 } 910 911 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 912 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 913 printf("%s: unable to create descriptor buffer DMA map, " 914 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 915 goto fail_2; 916 } 917 918 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 919 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 920 printf("%s: unable to load descriptor buffer DMA map, " 921 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 922 goto fail_3; 923 } 924 925 return 0; 926 927 fail_3: 928 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 929 fail_2: 930 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 931 fail_1: 932 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 933 fail_0: 934 return error; 935 } 936 937 static struct fwohci_desc * 938 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 939 { 940 int i, n; 941 942 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 943 for (i = 0; ; i++) { 944 if (i == ndesc) { 945 for (i = 0; i < ndesc; i++) 946 setbit(sc->sc_descmap, n + i); 947 return sc->sc_desc + n; 948 } 949 if (isset(sc->sc_descmap, n + i)) 950 break; 951 } 952 } 953 return NULL; 954 } 955 956 static void 957 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 958 { 959 int i, n; 960 961 n = fd - sc->sc_desc; 962 for (i = 0; i < ndesc; i++, n++) { 963 #ifdef DIAGNOSTIC 964 if (isclr(sc->sc_descmap, n)) 965 panic("fwohci_desc_put: duplicated free"); 966 #endif 967 clrbit(sc->sc_descmap, n); 968 } 969 } 970 971 /* 972 * Asyncronous/Isochronous Transmit/Receive Context 973 */ 974 static int 975 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 976 int bufcnt, int ctx) 977 { 978 int i, error; 979 struct fwohci_ctx *fc; 980 struct fwohci_buf *fb; 981 struct fwohci_desc *fd; 982 983 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 984 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 985 LIST_INIT(&fc->fc_handler); 986 TAILQ_INIT(&fc->fc_buf); 987 fc->fc_ctx = ctx; 988 fc->fc_bufcnt = bufcnt; 989 fb = (struct fwohci_buf *)&fc[1]; 990 for (i = 0; i < bufcnt; i++, fb++) { 991 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 992 goto fail; 993 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 994 error = ENOBUFS; 995 goto fail; 996 } 997 fb->fb_desc = fd; 998 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 999 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1000 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1001 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1002 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1003 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1004 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1005 } 1006 *fcp = fc; 1007 return 0; 1008 1009 fail: 1010 while (i-- > 0) 1011 fwohci_buf_free(sc, --fb); 1012 free(fc, M_DEVBUF); 1013 return error; 1014 } 1015 1016 static void 1017 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1018 { 1019 struct fwohci_buf *fb; 1020 struct fwohci_handler *fh; 1021 1022 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1023 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1024 NULL, NULL); 1025 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1026 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1027 fwohci_buf_free(sc, fb); 1028 } 1029 free(fc, M_DEVBUF); 1030 } 1031 1032 static void 1033 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1034 { 1035 struct fwohci_buf *fb, *nfb; 1036 struct fwohci_desc *fd; 1037 struct fwohci_handler *fh; 1038 int n; 1039 1040 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1041 nfb = TAILQ_NEXT(fb, fb_list); 1042 fb->fb_off = 0; 1043 fd = fb->fb_desc; 1044 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1045 fd->fd_rescount = fd->fd_reqcount; 1046 } 1047 1048 n = fc->fc_ctx; 1049 fb = TAILQ_FIRST(&fc->fc_buf); 1050 if (fc->fc_isoch) { 1051 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1052 fb->fb_daddr | 1); 1053 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1054 OHCI_CTXCTL_RX_BUFFER_FILL | 1055 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1056 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1057 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1058 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1059 OHCI_CTXCTL_RX_ISOCH_HEADER); 1060 fh = LIST_FIRST(&fc->fc_handler); 1061 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1062 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1063 } else { 1064 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1065 fb->fb_daddr | 1); 1066 } 1067 } 1068 1069 /* 1070 * DMA data buffer 1071 */ 1072 static int 1073 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1074 { 1075 int error; 1076 1077 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1078 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1079 printf("%s: unable to allocate buffer, error = %d\n", 1080 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1081 goto fail_0; 1082 } 1083 1084 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1085 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1086 printf("%s: unable to map buffer, error = %d\n", 1087 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1088 goto fail_1; 1089 } 1090 1091 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1092 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1093 printf("%s: unable to create buffer DMA map, " 1094 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1095 error); 1096 goto fail_2; 1097 } 1098 1099 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1100 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1101 printf("%s: unable to load buffer DMA map, " 1102 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1103 error); 1104 goto fail_3; 1105 } 1106 1107 return 0; 1108 1109 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1110 fail_3: 1111 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1112 fail_2: 1113 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1114 fail_1: 1115 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1116 fail_0: 1117 return error; 1118 } 1119 1120 static void 1121 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1122 { 1123 1124 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1125 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1126 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1127 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1128 } 1129 1130 static void 1131 fwohci_buf_init(struct fwohci_softc *sc) 1132 { 1133 int i; 1134 1135 /* 1136 * Initialize for Asynchronous Transmit Queue. 1137 */ 1138 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1139 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1140 1141 /* 1142 * Initialize for Asynchronous Receive Queue. 1143 */ 1144 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1145 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1146 1147 /* 1148 * Initialize for Isochronous Receive Queue. 1149 */ 1150 for (i = 0; i < sc->sc_isoctx; i++) { 1151 if (sc->sc_ctx_ir[i] != NULL) 1152 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1153 } 1154 } 1155 1156 static void 1157 fwohci_buf_start(struct fwohci_softc *sc) 1158 { 1159 int i; 1160 1161 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1162 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1163 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1164 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1165 for (i = 0; i < sc->sc_isoctx; i++) { 1166 if (sc->sc_ctx_ir[i] != NULL && 1167 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1168 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1169 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1170 } 1171 } 1172 } 1173 1174 static void 1175 fwohci_buf_stop(struct fwohci_softc *sc) 1176 { 1177 int i, j; 1178 1179 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1180 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1181 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1182 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1183 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1184 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1185 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1186 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1187 for (i = 0; i < sc->sc_isoctx; i++) { 1188 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1189 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1190 } 1191 1192 /* 1193 * Make sure the transmitter is stopped. 1194 */ 1195 for (j = 0; j < OHCI_LOOP; j++) { 1196 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1197 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1198 continue; 1199 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1200 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1201 continue; 1202 break; 1203 } 1204 } 1205 1206 static void 1207 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1208 { 1209 struct fwohci_buf *fb, *tfb; 1210 1211 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1212 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1213 fb->fb_desc->fd_rescount != 0) 1214 break; 1215 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1216 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1217 fb->fb_off = 0; 1218 fb->fb_desc->fd_branch = 0; 1219 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1220 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1221 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1222 } 1223 } 1224 1225 static int 1226 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1227 int len) 1228 { 1229 struct fwohci_buf *fb; 1230 struct fwohci_desc *fd; 1231 int bufend; 1232 1233 fb = TAILQ_FIRST(&fc->fc_buf); 1234 again: 1235 fd = fb->fb_desc; 1236 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1237 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1238 fd->fd_reqcount, fd->fd_rescount, len, 1239 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1240 bufend = fd->fd_reqcount - fd->fd_rescount; 1241 if (fb->fb_off >= bufend) { 1242 if (fc->fc_isoch && fb->fb_off > 0) { 1243 fb->fb_off = fd->fd_reqcount; 1244 fd->fd_rescount = 0; 1245 } 1246 if (fd->fd_rescount == 0) { 1247 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1248 goto again; 1249 } 1250 return 0; 1251 } 1252 if (fb->fb_off + len > bufend) 1253 len = bufend - fb->fb_off; 1254 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1255 BUS_DMASYNC_POSTREAD); 1256 *pp = fb->fb_buf + fb->fb_off; 1257 fb->fb_off += roundup(len, 4); 1258 return len; 1259 } 1260 1261 static int 1262 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1263 struct fwohci_pkt *pkt) 1264 { 1265 caddr_t p; 1266 int len, count, i; 1267 1268 memset(pkt, 0, sizeof(*pkt)); 1269 pkt->fp_uio.uio_iov = pkt->fp_iov; 1270 pkt->fp_uio.uio_rw = UIO_WRITE; 1271 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1272 1273 /* get first quadlet */ 1274 count = 4; 1275 if (fc->fc_isoch) { 1276 /* 1277 * get trailer first, may be bogus data unless status update 1278 * in descriptor is set. 1279 */ 1280 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1281 sizeof(*pkt->fp_trail)); 1282 if (len <= 0) { 1283 DPRINTFN(1, ("fwohci_buf_input: no input for is#%d\n", 1284 fc->fc_ctx)); 1285 return 0; 1286 } 1287 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1288 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1289 } 1290 len = fwohci_buf_pktget(sc, fc, &p, count); 1291 if (len <= 0) { 1292 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1293 fc->fc_ctx)); 1294 return 0; 1295 } 1296 pkt->fp_hdr[0] = *(u_int32_t *)p; 1297 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1298 switch (pkt->fp_tcode) { 1299 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1300 case IEEE1394_TCODE_READ_RESP_QUAD: 1301 pkt->fp_hlen = 12; 1302 pkt->fp_dlen = 4; 1303 break; 1304 case IEEE1394_TCODE_READ_REQ_BLOCK: 1305 pkt->fp_hlen = 16; 1306 pkt->fp_dlen = 0; 1307 break; 1308 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1309 case IEEE1394_TCODE_READ_RESP_BLOCK: 1310 case IEEE1394_TCODE_LOCK_REQ: 1311 case IEEE1394_TCODE_LOCK_RESP: 1312 pkt->fp_hlen = 16; 1313 break; 1314 case IEEE1394_TCODE_STREAM_DATA: 1315 pkt->fp_hlen = 4; 1316 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1317 break; 1318 default: 1319 pkt->fp_hlen = 12; 1320 pkt->fp_dlen = 0; 1321 break; 1322 } 1323 1324 /* get header */ 1325 while (count < pkt->fp_hlen) { 1326 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1327 if (len == 0) { 1328 printf("fwohci_buf_input: malformed input 1: %d\n", 1329 pkt->fp_hlen - count); 1330 return 0; 1331 } 1332 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1333 count += len; 1334 } 1335 if ((pkt->fp_hlen == 16) && 1336 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1337 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1338 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1339 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1340 1341 /* get data */ 1342 count = 0; 1343 i = 0; 1344 while (count < pkt->fp_dlen) { 1345 len = fwohci_buf_pktget(sc, fc, 1346 (caddr_t *)&pkt->fp_iov[i].iov_base, 1347 pkt->fp_dlen - count); 1348 if (len == 0) { 1349 printf("fwohci_buf_input: malformed input 2: %d\n", 1350 pkt->fp_hlen - count); 1351 return 0; 1352 } 1353 pkt->fp_iov[i++].iov_len = len; 1354 count += len; 1355 } 1356 pkt->fp_uio.uio_iovcnt = i; 1357 pkt->fp_uio.uio_resid = count; 1358 1359 if (!fc->fc_isoch) { 1360 /* get trailer */ 1361 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1362 sizeof(*pkt->fp_trail)); 1363 if (len <= 0) { 1364 printf("fwohci_buf_input: malformed input 3: %d\n", 1365 pkt->fp_hlen - count); 1366 return 0; 1367 } 1368 } 1369 return 1; 1370 } 1371 1372 static int 1373 fwohci_handler_set(struct fwohci_softc *sc, 1374 int tcode, u_int32_t key1, u_int32_t key2, 1375 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1376 void *arg) 1377 { 1378 struct fwohci_ctx *fc; 1379 struct fwohci_handler *fh; 1380 int i, j; 1381 1382 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1383 j = sc->sc_isoctx; 1384 fh = NULL; 1385 for (i = 0; i < sc->sc_isoctx; i++) { 1386 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1387 if (j == sc->sc_isoctx) 1388 j = i; 1389 continue; 1390 } 1391 fh = LIST_FIRST(&fc->fc_handler); 1392 if (fh == NULL) { 1393 j = i; 1394 break; 1395 } 1396 if (fh->fh_tcode == tcode && 1397 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1398 break; 1399 fh = NULL; 1400 } 1401 if (fh == NULL) { 1402 if (handler == NULL) 1403 return 0; 1404 if (j == sc->sc_isoctx) { 1405 DPRINTF(("fwohci_handler_set: no more free " 1406 "context\n")); 1407 return ENOMEM; 1408 } 1409 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1410 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1411 fc->fc_isoch = 1; 1412 sc->sc_ctx_ir[j] = fc; 1413 } 1414 } 1415 } else { 1416 switch (tcode) { 1417 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1418 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1419 case IEEE1394_TCODE_READ_REQ_QUAD: 1420 case IEEE1394_TCODE_READ_REQ_BLOCK: 1421 case IEEE1394_TCODE_LOCK_REQ: 1422 fc = sc->sc_ctx_arrq; 1423 break; 1424 case IEEE1394_TCODE_WRITE_RESP: 1425 case IEEE1394_TCODE_READ_RESP_QUAD: 1426 case IEEE1394_TCODE_READ_RESP_BLOCK: 1427 case IEEE1394_TCODE_LOCK_RESP: 1428 fc = sc->sc_ctx_arrs; 1429 break; 1430 default: 1431 return EIO; 1432 } 1433 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1434 fh = LIST_NEXT(fh, fh_list)) { 1435 if (fh->fh_tcode == tcode && 1436 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1437 break; 1438 } 1439 } 1440 if (handler == NULL) { 1441 if (fh != NULL) { 1442 LIST_REMOVE(fh, fh_list); 1443 free(fh, M_DEVBUF); 1444 } 1445 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1446 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1447 fwohci_ctx_free(sc, fc); 1448 } 1449 return 0; 1450 } 1451 if (fh == NULL) { 1452 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1453 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1454 } 1455 fh->fh_tcode = tcode; 1456 fh->fh_key1 = key1; 1457 fh->fh_key2 = key2; 1458 fh->fh_handler = handler; 1459 fh->fh_handarg = arg; 1460 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1461 fc->fc_ctx, tcode, key1, key2)); 1462 1463 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1464 fwohci_ctx_init(sc, fc); 1465 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1466 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1467 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1468 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1469 } 1470 return 0; 1471 } 1472 1473 /* 1474 * Asyncronous Receive Requests input frontend. 1475 */ 1476 static void 1477 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1478 { 1479 int rcode; 1480 u_int32_t key1, key2; 1481 struct fwohci_handler *fh; 1482 struct fwohci_pkt pkt, res; 1483 1484 while (fwohci_buf_input(sc, fc, &pkt)) { 1485 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1486 fwohci_phy_input(sc, &pkt); 1487 return; 1488 } 1489 key1 = pkt.fp_hdr[1] & 0xffff; 1490 key2 = pkt.fp_hdr[2]; 1491 memset(&res, 0, sizeof(res)); 1492 res.fp_uio.uio_rw = UIO_WRITE; 1493 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1494 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1495 fh = LIST_NEXT(fh, fh_list)) { 1496 if (pkt.fp_tcode == fh->fh_tcode && 1497 key1 == fh->fh_key1 && 1498 key2 == fh->fh_key2) { 1499 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1500 &pkt); 1501 break; 1502 } 1503 } 1504 if (fh == NULL) { 1505 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1506 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1507 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1508 key2)); 1509 } 1510 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1511 OHCI_CTXCTL_EVENT_ACK_PENDING) 1512 return; 1513 if (rcode != -1) 1514 fwohci_atrs_output(sc, rcode, &pkt, &res); 1515 } 1516 fwohci_buf_next(sc, fc); 1517 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1518 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1519 } 1520 1521 1522 /* 1523 * Asynchronous Receive Response input frontend. 1524 */ 1525 static void 1526 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1527 { 1528 struct fwohci_pkt pkt; 1529 struct fwohci_handler *fh; 1530 u_int16_t srcid; 1531 int rcode, tlabel; 1532 1533 while (fwohci_buf_input(sc, fc, &pkt)) { 1534 srcid = pkt.fp_hdr[1] >> 16; 1535 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1536 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1537 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1538 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1539 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1540 pkt.fp_dlen)); 1541 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1542 fh = LIST_NEXT(fh, fh_list)) { 1543 if (pkt.fp_tcode == fh->fh_tcode && 1544 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1545 tlabel == fh->fh_key2) { 1546 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1547 LIST_REMOVE(fh, fh_list); 1548 free(fh, M_DEVBUF); 1549 break; 1550 } 1551 } 1552 #ifdef FW_DEBUG 1553 if (fh == NULL) { 1554 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1555 DPRINTFN(1, ("src: %d, rcode: %d, tlabel: %d, tcode: " 1556 "%d hdr[3]: 0x%08x, data: 0x%08lx\n", srcid, rcode, 1557 tlabel, pkt.fp_tcode, pkt.fp_hdr[3], 1558 (unsigned long)(*((int *)pkt.fp_iov[0].iov_base)))); 1559 } 1560 #endif 1561 } 1562 fwohci_buf_next(sc, fc); 1563 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1564 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1565 } 1566 1567 /* 1568 * Isochronous Receive input frontend. 1569 */ 1570 static void 1571 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1572 { 1573 int rcode, chan, tag; 1574 struct iovec *iov; 1575 struct fwohci_handler *fh; 1576 struct fwohci_pkt pkt; 1577 1578 while (fwohci_buf_input(sc, fc, &pkt)) { 1579 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1580 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1581 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1582 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1583 pkt.fp_dlen)); 1584 if (tag == IEEE1394_TAG_GASP) { 1585 /* 1586 * The pkt with tag=3 is GASP format. 1587 * Move GASP header to header part. 1588 */ 1589 if (pkt.fp_dlen < 8) 1590 continue; 1591 iov = pkt.fp_iov; 1592 /* assuming pkt per buffer mode */ 1593 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1594 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1595 iov->iov_base = (caddr_t)iov->iov_base + 8; 1596 iov->iov_len -= 8; 1597 pkt.fp_hlen += 8; 1598 pkt.fp_dlen -= 8; 1599 } 1600 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1601 fh = LIST_NEXT(fh, fh_list)) { 1602 if (pkt.fp_tcode == fh->fh_tcode && 1603 chan == fh->fh_key1 && tag == fh->fh_key2) { 1604 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1605 &pkt); 1606 break; 1607 } 1608 } 1609 #ifdef FW_DEBUG 1610 if (fh == NULL) { 1611 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1612 } else { 1613 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1614 } 1615 #endif 1616 } 1617 fwohci_buf_next(sc, fc); 1618 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1619 OHCI_CTXCTL_WAKE); 1620 } 1621 1622 /* 1623 * Asynchronous Transmit common routine. 1624 */ 1625 static int 1626 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1627 struct fwohci_pkt *pkt) 1628 { 1629 struct fwohci_buf *fb; 1630 struct fwohci_desc *fd; 1631 struct mbuf *m, *m0; 1632 int i, ndesc, error, off, len; 1633 u_int32_t val; 1634 #ifdef FW_DEBUG 1635 struct iovec *iov; 1636 #endif 1637 1638 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1639 /* We can't send anything during selfid duration */ 1640 return EAGAIN; 1641 1642 #ifdef FW_DEBUG 1643 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1644 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1645 for (i = 0; i < pkt->fp_hlen/4; i++) 1646 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 1647 DPRINTFN(2, ("$")); 1648 for (ndesc = 0, iov = pkt->fp_iov; 1649 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1650 for (i = 0; i < iov->iov_len; i++) 1651 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1652 ((u_int8_t *)iov->iov_base)[i])); 1653 DPRINTFN(2, ("$")); 1654 } 1655 DPRINTFN(1, ("\n")); 1656 #endif 1657 1658 if ((m = pkt->fp_m) != NULL) { 1659 for (ndesc = 2; m != NULL; m = m->m_next) 1660 ndesc++; 1661 if (ndesc > OHCI_DESC_MAX) { 1662 m0 = NULL; 1663 ndesc = 2; 1664 for (off = 0; off < pkt->fp_dlen; off += len) { 1665 if (m0 == NULL) { 1666 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1667 if (m0 != NULL) 1668 M_COPY_PKTHDR(m0, pkt->fp_m); 1669 m = m0; 1670 } else { 1671 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1672 m = m->m_next; 1673 } 1674 if (m != NULL) 1675 MCLGET(m, M_DONTWAIT); 1676 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1677 m_freem(m0); 1678 return ENOMEM; 1679 } 1680 len = pkt->fp_dlen - off; 1681 if (len > m->m_ext.ext_size) 1682 len = m->m_ext.ext_size; 1683 m_copydata(pkt->fp_m, off, len, 1684 mtod(m, caddr_t)); 1685 m->m_len = len; 1686 ndesc++; 1687 } 1688 m_freem(pkt->fp_m); 1689 pkt->fp_m = m0; 1690 } 1691 } else 1692 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1693 1694 if (ndesc > OHCI_DESC_MAX) 1695 return ENOBUFS; 1696 1697 if (fc->fc_bufcnt > 50) /*XXX*/ 1698 return ENOBUFS; 1699 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1700 fb->fb_nseg = ndesc; 1701 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1702 if (fb->fb_desc == NULL) { 1703 free(fb, M_DEVBUF); 1704 return ENOBUFS; 1705 } 1706 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1707 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1708 fb->fb_m = pkt->fp_m; 1709 fb->fb_callback = pkt->fp_callback; 1710 fb->fb_statuscb = pkt->fp_statuscb; 1711 fb->fb_statusarg = pkt->fp_statusarg; 1712 1713 if (ndesc > 2) { 1714 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1715 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1716 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1717 free(fb, M_DEVBUF); 1718 return error; 1719 } 1720 1721 if (pkt->fp_m != NULL) 1722 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1723 pkt->fp_m, BUS_DMA_WAITOK); 1724 else 1725 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1726 &pkt->fp_uio, BUS_DMA_WAITOK); 1727 if (error != 0) { 1728 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1729 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1730 free(fb, M_DEVBUF); 1731 return error; 1732 } 1733 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1734 BUS_DMASYNC_PREWRITE); 1735 } 1736 1737 fd = fb->fb_desc; 1738 fd->fd_flags = OHCI_DESC_IMMED; 1739 fd->fd_reqcount = pkt->fp_hlen; 1740 fd->fd_data = 0; 1741 fd->fd_branch = 0; 1742 fd->fd_status = 0; 1743 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1744 i = 3; /* XXX: 3 sec */ 1745 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1746 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1747 ((((val >> 25) + i) & 0x7) << 13); 1748 } else 1749 fd->fd_timestamp = 0; 1750 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1751 for (i = 0; i < ndesc - 2; i++) { 1752 fd = fb->fb_desc + 2 + i; 1753 fd->fd_flags = 0; 1754 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1755 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1756 fd->fd_branch = 0; 1757 fd->fd_status = 0; 1758 fd->fd_timestamp = 0; 1759 } 1760 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1761 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1762 1763 #ifdef FW_DEBUG 1764 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1765 (long)(fb->fb_desc - sc->sc_desc))); 1766 for (i = 0; i < ndesc * 4; i++) 1767 DPRINTFN(1, ("%s%08x", i&7?" ":"\n\t", 1768 ((u_int32_t *)fb->fb_desc)[i])); 1769 DPRINTFN(1, ("\n")); 1770 #endif 1771 1772 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1773 OHCI_SUBREG_ContextControlClear); 1774 1775 if (val & OHCI_CTXCTL_RUN) { 1776 if (fc->fc_branch == NULL) { 1777 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1778 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1779 goto run; 1780 } 1781 *fc->fc_branch = fb->fb_daddr | ndesc; 1782 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1783 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1784 } else { 1785 run: 1786 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1787 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1788 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1789 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1790 } 1791 fc->fc_branch = &fd->fd_branch; 1792 1793 fc->fc_bufcnt++; 1794 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1795 pkt->fp_m = NULL; 1796 return 0; 1797 } 1798 1799 static void 1800 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1801 { 1802 struct fwohci_buf *fb; 1803 struct fwohci_desc *fd; 1804 struct fwohci_pkt pkt; 1805 int i; 1806 1807 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1808 fd = fb->fb_desc; 1809 #ifdef FW_DEBUG 1810 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1811 force ? "force " : "", (long)(fd - sc->sc_desc), 1812 fb->fb_nseg)); 1813 for (i = 0; i < fb->fb_nseg * 4; i++) 1814 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", 1815 ((u_int32_t *)fd)[i])); 1816 DPRINTFN(1, ("\n")); 1817 #endif 1818 if (fb->fb_nseg > 2) 1819 fd += fb->fb_nseg - 1; 1820 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1821 break; 1822 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1823 if (fc->fc_branch == &fd->fd_branch) { 1824 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1825 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1826 fc->fc_branch = NULL; 1827 for (i = 0; i < OHCI_LOOP; i++) { 1828 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1829 OHCI_SUBREG_ContextControlClear) & 1830 OHCI_CTXCTL_ACTIVE)) 1831 break; 1832 } 1833 } 1834 1835 if (fb->fb_statuscb) { 1836 memset(&pkt, 0, sizeof(pkt)); 1837 pkt.fp_status = fd->fd_status; 1838 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1839 1840 /* Indicate this is just returning the status bits. */ 1841 pkt.fp_tcode = -1; 1842 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1843 fb->fb_statuscb = NULL; 1844 fb->fb_statusarg = NULL; 1845 } 1846 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1847 if (fb->fb_nseg > 2) 1848 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1849 fc->fc_bufcnt--; 1850 if (fb->fb_callback) { 1851 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1852 fb->fb_callback = NULL; 1853 } else if (fb->fb_m != NULL) 1854 m_freem(fb->fb_m); 1855 free(fb, M_DEVBUF); 1856 } 1857 } 1858 1859 /* 1860 * Asynchronous Transmit Reponse -- in response of request packet. 1861 */ 1862 static void 1863 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1864 struct fwohci_pkt *res) 1865 { 1866 1867 if (((*req->fp_trail & 0x001f0000) >> 16) != 1868 OHCI_CTXCTL_EVENT_ACK_PENDING) 1869 return; 1870 1871 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1872 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1873 switch (req->fp_tcode) { 1874 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1875 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1876 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1877 res->fp_hlen = 12; 1878 break; 1879 case IEEE1394_TCODE_READ_REQ_QUAD: 1880 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1881 res->fp_hlen = 16; 1882 res->fp_dlen = 0; 1883 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1884 res->fp_hdr[3] = 1885 *(u_int32_t *)res->fp_iov[0].iov_base; 1886 res->fp_uio.uio_iovcnt = 0; 1887 break; 1888 case IEEE1394_TCODE_READ_REQ_BLOCK: 1889 case IEEE1394_TCODE_LOCK_REQ: 1890 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1891 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1892 else 1893 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1894 res->fp_hlen = 16; 1895 res->fp_dlen = res->fp_uio.uio_resid; 1896 res->fp_hdr[3] = res->fp_dlen << 16; 1897 break; 1898 } 1899 res->fp_hdr[0] |= (res->fp_tcode << 4); 1900 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1901 } 1902 1903 /* 1904 * APPLICATION LAYER SERVICES 1905 */ 1906 1907 /* 1908 * Retrieve Global UID from GUID ROM 1909 */ 1910 static int 1911 fwohci_guidrom_init(struct fwohci_softc *sc) 1912 { 1913 int i, n, off; 1914 u_int32_t val1, val2; 1915 1916 /* Extract the Global UID 1917 */ 1918 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1919 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1920 1921 if (val1 != 0 || val2 != 0) { 1922 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1923 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1924 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1925 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1926 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1927 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1928 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1929 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1930 } else { 1931 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1932 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1933 return -1; 1934 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1935 for (i = 0; i < OHCI_LOOP; i++) { 1936 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1937 if (!(val1 & OHCI_Guid_AddrReset)) 1938 break; 1939 } 1940 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1941 val2 = 0; 1942 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1943 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1944 OHCI_Guid_RdStart); 1945 for (i = 0; i < OHCI_LOOP; i++) { 1946 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1947 if (!(val1 & OHCI_Guid_RdStart)) 1948 break; 1949 } 1950 if (n < off) 1951 continue; 1952 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1953 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1954 val2 |= val1; 1955 } 1956 if (val2 == 0) 1957 return -1; 1958 } 1959 return 0; 1960 } 1961 1962 /* 1963 * Initialization for Configuration ROM (no DMA context) 1964 */ 1965 1966 #define CFR_MAXUNIT 20 1967 1968 struct configromctx { 1969 u_int32_t *ptr; 1970 int curunit; 1971 struct { 1972 u_int32_t *start; 1973 int length; 1974 u_int32_t *refer; 1975 int refunit; 1976 } unit[CFR_MAXUNIT]; 1977 }; 1978 1979 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1980 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1981 1982 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1983 1984 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1985 1986 #define CFR_PUT_CRC(cfr, n) \ 1987 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1988 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1989 1990 #define CFR_START_UNIT(cfr, n) \ 1991 do { \ 1992 if ((cfr)->unit[n].refer != NULL) { \ 1993 *(cfr)->unit[n].refer |= \ 1994 (cfr)->ptr - (cfr)->unit[n].refer; \ 1995 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1996 } \ 1997 (cfr)->curunit = (n); \ 1998 (cfr)->unit[n].start = (cfr)->ptr++; \ 1999 } while (0 /* CONSTCOND */) 2000 2001 #define CFR_PUT_REFER(cfr, key, n) \ 2002 do { \ 2003 (cfr)->unit[n].refer = (cfr)->ptr; \ 2004 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2005 *(cfr)->ptr++ = (key) << 24; \ 2006 } while (0 /* CONSTCOND */) 2007 2008 #define CFR_END_UNIT(cfr) \ 2009 do { \ 2010 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2011 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2012 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2013 } while (0 /* CONSTCOND */) 2014 2015 static u_int16_t 2016 fwohci_crc16(u_int32_t *ptr, int len) 2017 { 2018 int shift; 2019 u_int32_t crc, sum, data; 2020 2021 crc = 0; 2022 while (len-- > 0) { 2023 data = *ptr++; 2024 for (shift = 28; shift >= 0; shift -= 4) { 2025 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2026 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2027 } 2028 crc &= 0xffff; 2029 } 2030 return crc; 2031 } 2032 2033 static void 2034 fwohci_configrom_init(struct fwohci_softc *sc) 2035 { 2036 int i, val; 2037 struct fwohci_buf *fb; 2038 u_int32_t *hdr; 2039 struct configromctx cfr; 2040 2041 fb = &sc->sc_buf_cnfrom; 2042 memset(&cfr, 0, sizeof(cfr)); 2043 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2044 2045 /* headers */ 2046 CFR_START_UNIT(&cfr, 0); 2047 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2048 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2049 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2050 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2051 CFR_END_UNIT(&cfr); 2052 /* copy info_length from crc_length */ 2053 *hdr |= (*hdr & 0x00ff0000) << 8; 2054 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2055 2056 /* root directory */ 2057 CFR_START_UNIT(&cfr, 1); 2058 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2059 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2060 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2061 /* spt,64,fix,lst,drq */ 2062 #ifdef INET 2063 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2064 #endif /* INET */ 2065 #ifdef INET6 2066 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2067 #endif /* INET6 */ 2068 CFR_END_UNIT(&cfr); 2069 2070 CFR_START_UNIT(&cfr, 2); 2071 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2072 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2073 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2074 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2075 CFR_END_UNIT(&cfr); 2076 2077 #ifdef INET 2078 /* IPv4 unit directory */ 2079 CFR_START_UNIT(&cfr, 3); 2080 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2081 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2082 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2083 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2084 CFR_END_UNIT(&cfr); 2085 2086 CFR_START_UNIT(&cfr, 6); 2087 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2088 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2089 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2090 CFR_END_UNIT(&cfr); 2091 2092 CFR_START_UNIT(&cfr, 7); 2093 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2094 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2095 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2096 CFR_END_UNIT(&cfr); 2097 #endif /* INET */ 2098 2099 #ifdef INET6 2100 /* IPv6 unit directory */ 2101 CFR_START_UNIT(&cfr, 4); 2102 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2103 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2104 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2105 /* XXX: TBA by IANA */ 2106 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2107 CFR_END_UNIT(&cfr); 2108 2109 CFR_START_UNIT(&cfr, 8); 2110 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2111 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2112 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2113 CFR_END_UNIT(&cfr); 2114 2115 CFR_START_UNIT(&cfr, 9); 2116 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2117 CFR_PUT_DATA1(&cfr, 0); 2118 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2119 CFR_END_UNIT(&cfr); 2120 #endif /* INET6 */ 2121 2122 fb->fb_off = cfr.ptr - hdr; 2123 #ifdef FW_DEBUG 2124 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2125 for (i = 0; i < fb->fb_off; i++) 2126 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2127 DPRINTFN(2, ("\n")); 2128 #endif /* FW_DEBUG */ 2129 2130 /* 2131 * Make network byte order for DMA 2132 */ 2133 for (i = 0; i < fb->fb_off; i++) 2134 HTONL(hdr[i]); 2135 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2136 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2137 2138 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2139 fb->fb_dmamap->dm_segs[0].ds_addr); 2140 2141 /* This register is only valid on OHCI 1.1. */ 2142 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2143 if ((OHCI_Version_GET_Version(val) == 1) && 2144 (OHCI_Version_GET_Revision(val) == 1)) 2145 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2146 OHCI_HCControl_BIBImageValid); 2147 2148 /* Just allow quad reads of the rom. */ 2149 for (i = 0; i < fb->fb_off; i++) 2150 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2151 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2152 fwohci_configrom_input, NULL); 2153 } 2154 2155 static int 2156 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2157 struct fwohci_pkt *pkt) 2158 { 2159 struct fwohci_pkt res; 2160 u_int32_t loc, *rom; 2161 2162 /* This will be used as an array index so size accordingly. */ 2163 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2164 if ((loc & 0x03) != 0) { 2165 /* alignment error */ 2166 return IEEE1394_RCODE_ADDRESS_ERROR; 2167 } 2168 else 2169 loc /= 4; 2170 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2171 2172 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2173 ntohl(rom[loc]))); 2174 2175 memset(&res, 0, sizeof(res)); 2176 res.fp_hdr[3] = rom[loc]; 2177 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2178 return -1; 2179 } 2180 2181 /* 2182 * SelfID buffer (no DMA context) 2183 */ 2184 static void 2185 fwohci_selfid_init(struct fwohci_softc *sc) 2186 { 2187 struct fwohci_buf *fb; 2188 2189 fb = &sc->sc_buf_selfid; 2190 #ifdef DIAGNOSTIC 2191 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2192 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2193 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2194 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2195 #endif 2196 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2197 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2198 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2199 2200 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2201 fb->fb_dmamap->dm_segs[0].ds_addr); 2202 } 2203 2204 static int 2205 fwohci_selfid_input(struct fwohci_softc *sc) 2206 { 2207 int i; 2208 u_int32_t count, val, gen; 2209 u_int32_t *buf; 2210 2211 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2212 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2213 again: 2214 if (val & OHCI_SelfID_Error) { 2215 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2216 return -1; 2217 } 2218 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2219 2220 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2221 0, count << 2, BUS_DMASYNC_POSTREAD); 2222 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2223 2224 #ifdef FW_DEBUG 2225 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2226 val)); 2227 for (i = 0; i < count; i++) 2228 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", buf[i])); 2229 DPRINTFN(1, ("\n")); 2230 #endif /* FW_DEBUG */ 2231 2232 for (i = 1; i < count; i += 2) { 2233 if (buf[i] != ~buf[i + 1]) 2234 break; 2235 if (buf[i] & 0x00000001) 2236 continue; /* more pkt */ 2237 if (buf[i] & 0x00800000) 2238 continue; /* external id */ 2239 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2240 if ((buf[i] & 0x00400800) == 0x00400800) 2241 sc->sc_irmid = sc->sc_rootid; 2242 } 2243 2244 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2245 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2246 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2247 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2248 goto again; 2249 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2250 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2251 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2252 return -1; 2253 } 2254 if (i != count) { 2255 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2256 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2257 #if 1 2258 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2259 /* 2260 * XXX: CXD3222 sometimes fails to DMA 2261 * selfid packet?? 2262 */ 2263 sc->sc_rootid = (count - 1) / 2 - 1; 2264 sc->sc_irmid = sc->sc_rootid; 2265 } else 2266 #endif 2267 return -1; 2268 } 2269 2270 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2271 if ((val & OHCI_NodeId_IDValid) == 0) { 2272 sc->sc_nodeid = 0xffff; /* invalid */ 2273 printf("%s: nodeid is invalid\n", 2274 sc->sc_sc1394.sc1394_dev.dv_xname); 2275 return -1; 2276 } 2277 sc->sc_nodeid = val & 0xffff; 2278 2279 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2280 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2281 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2282 sc->sc_irmid)); 2283 2284 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2285 return -1; 2286 2287 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2288 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2289 OHCI_LinkControl_CycleMaster); 2290 else 2291 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2292 OHCI_LinkControl_CycleMaster); 2293 return 0; 2294 } 2295 2296 /* 2297 * some CSRs are handled by driver. 2298 */ 2299 static void 2300 fwohci_csr_init(struct fwohci_softc *sc) 2301 { 2302 int i; 2303 static u_int32_t csr[] = { 2304 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2305 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2306 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2307 CSR_SB_BROADCAST_CHANNEL 2308 }; 2309 2310 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2311 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2312 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2313 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2314 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2315 } 2316 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2317 } 2318 2319 static int 2320 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2321 { 2322 struct fwohci_pkt res; 2323 u_int32_t reg; 2324 2325 /* 2326 * XXX need to do special functionality other than just r/w... 2327 */ 2328 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2329 2330 if ((reg & 0x03) != 0) { 2331 /* alignment error */ 2332 return IEEE1394_RCODE_ADDRESS_ERROR; 2333 } 2334 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2335 *(u_int32_t *)(&sc->sc_csr[reg]))); 2336 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2337 DPRINTFN(1, (" -> 0x%08x\n", 2338 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2339 *(u_int32_t *)&sc->sc_csr[reg] = 2340 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2341 } else { 2342 DPRINTFN(1, ("\n")); 2343 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2344 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2345 res.fp_iov[0].iov_len = 4; 2346 res.fp_uio.uio_resid = 4; 2347 res.fp_uio.uio_iovcnt = 1; 2348 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2349 return -1; 2350 } 2351 return IEEE1394_RCODE_COMPLETE; 2352 } 2353 2354 /* 2355 * Mapping between nodeid and unique ID (EUI-64). 2356 * 2357 * Track old mappings and simply update their devices with the new id's when 2358 * they match an existing EUI. This allows proper renumeration of the bus. 2359 */ 2360 static void 2361 fwohci_uid_collect(struct fwohci_softc *sc) 2362 { 2363 int i; 2364 struct fwohci_uidtbl *fu; 2365 struct fwohci_pkt pkt; 2366 struct ieee1394_softc *iea; 2367 2368 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2369 iea->sc1394_node_id = 0xffff; 2370 2371 if (sc->sc_uidtbl != NULL) 2372 free(sc->sc_uidtbl, M_DEVBUF); 2373 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2374 M_WAITOK); 2375 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2376 2377 memset(&pkt, 0, sizeof(pkt)); 2378 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2379 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2380 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2381 fu->fu_valid = 3; 2382 2383 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2384 if (iea) { 2385 iea->sc1394_node_id = i; 2386 DPRINTF(("%s: Updating nodeid to %d\n", 2387 iea->sc1394_dev.dv_xname, 2388 iea->sc1394_node_id)); 2389 } 2390 continue; 2391 } 2392 fu->fu_valid = 0; 2393 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2394 pkt.fp_hlen = 12; 2395 pkt.fp_dlen = 0; 2396 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2397 (pkt.fp_tcode << 4); 2398 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2399 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2400 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2401 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2402 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2403 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2404 2405 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2406 (pkt.fp_tcode << 4); 2407 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2408 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2409 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2410 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2411 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2412 2413 } 2414 if (sc->sc_rootid == 0) 2415 fwohci_check_nodes(sc); 2416 } 2417 2418 static int 2419 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2420 { 2421 struct fwohci_uidtbl *fu; 2422 struct ieee1394_softc *iea; 2423 struct ieee1394_attach_args fwa; 2424 int i, n, done, rcode, found; 2425 2426 found = 0; 2427 2428 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2429 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2430 if (rcode != IEEE1394_RCODE_COMPLETE || 2431 sc->sc_uidtbl == NULL || 2432 n > sc->sc_rootid) 2433 return 0; 2434 fu = &sc->sc_uidtbl[n]; 2435 if (arg == 0) { 2436 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2437 fu->fu_valid |= 0x1; 2438 } else { 2439 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2440 fu->fu_valid |= 0x2; 2441 } 2442 #ifdef FW_DEBUG 2443 if (fu->fu_valid == 0x3) 2444 DPRINTFN(1, ("fwohci_uid_input: " 2445 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2446 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2447 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2448 #endif 2449 if (fu->fu_valid == 0x3) { 2450 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2451 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2452 found = 1; 2453 iea->sc1394_node_id = n; 2454 DPRINTF(("%s: Updating nodeid to %d\n", 2455 iea->sc1394_dev.dv_xname, 2456 iea->sc1394_node_id)); 2457 break; 2458 } 2459 if (!found) { 2460 strcpy(fwa.name, "fwnode"); 2461 memcpy(fwa.uid, fu->fu_uid, 8); 2462 fwa.nodeid = n; 2463 fwa.read = fwohci_read; 2464 fwa.write = fwohci_write; 2465 fwa.inreg = fwohci_inreg; 2466 iea = (struct ieee1394_softc *) 2467 config_found(&sc->sc_sc1394.sc1394_dev, &fwa, 2468 fwohci_print); 2469 if (iea != NULL) 2470 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2471 sc1394_node); 2472 } 2473 } 2474 done = 1; 2475 2476 for (i = 0; i < sc->sc_rootid + 1; i++) { 2477 fu = &sc->sc_uidtbl[i]; 2478 if (fu->fu_valid != 0x3) { 2479 done = 0; 2480 break; 2481 } 2482 } 2483 if (done) 2484 fwohci_check_nodes(sc); 2485 2486 return 0; 2487 } 2488 2489 static void 2490 fwohci_check_nodes(struct fwohci_softc *sc) 2491 { 2492 struct device *detach = NULL; 2493 struct ieee1394_softc *iea; 2494 2495 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2496 2497 /* 2498 * Have to defer detachment until the next 2499 * loop iteration since config_detach 2500 * free's the softc and the loop iterator 2501 * needs data from the softc to move 2502 * forward. 2503 */ 2504 2505 if (detach) { 2506 config_detach(detach, 0); 2507 detach = NULL; 2508 } 2509 if (iea->sc1394_node_id == 0xffff) { 2510 detach = (struct device *)iea; 2511 LIST_REMOVE(iea, sc1394_node); 2512 } 2513 } 2514 if (detach) 2515 config_detach(detach, 0); 2516 } 2517 2518 static int 2519 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2520 { 2521 struct fwohci_uidtbl *fu; 2522 int n; 2523 static const u_int8_t bcast[] = 2524 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2525 2526 fu = sc->sc_uidtbl; 2527 if (fu == NULL) { 2528 notfound: 2529 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2530 return IEEE1394_BCAST_PHY_ID; 2531 fwohci_uid_collect(sc); /* try to get */ 2532 return -1; 2533 } 2534 for (n = 0; ; n++, fu++) { 2535 if (n > sc->sc_rootid) 2536 goto notfound; 2537 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2538 break; 2539 } 2540 return n; 2541 } 2542 2543 /* 2544 * functions to support network interface 2545 */ 2546 static int 2547 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2548 void (*handler)(struct device *, struct mbuf *)) 2549 { 2550 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2551 2552 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2553 fwohci_if_input, handler); 2554 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2555 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2556 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2557 return 0; 2558 } 2559 2560 static int 2561 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2562 { 2563 int n, len; 2564 struct mbuf *m; 2565 struct iovec *iov; 2566 void (*handler)(struct device *, struct mbuf *) = arg; 2567 2568 #ifdef FW_DEBUG 2569 int i; 2570 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2571 pkt->fp_dlen)); 2572 for (i = 0; i < pkt->fp_hlen/4; i++) 2573 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2574 DPRINTFN(2, ("$")); 2575 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2576 iov = &pkt->fp_iov[n]; 2577 for (i = 0; i < iov->iov_len; i++) 2578 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 2579 ((u_int8_t *)iov->iov_base)[i])); 2580 DPRINTFN(2, ("$")); 2581 } 2582 DPRINTFN(1, ("\n")); 2583 #endif /* FW_DEBUG */ 2584 len = pkt->fp_dlen; 2585 MGETHDR(m, M_DONTWAIT, MT_DATA); 2586 if (m == NULL) 2587 return IEEE1394_RCODE_COMPLETE; 2588 m->m_len = 16; 2589 if (len + m->m_len > MHLEN) { 2590 MCLGET(m, M_DONTWAIT); 2591 if ((m->m_flags & M_EXT) == 0) { 2592 m_freem(m); 2593 return IEEE1394_RCODE_COMPLETE; 2594 } 2595 } 2596 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2597 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2598 sc->sc_uidtbl[n].fu_valid != 0x3) { 2599 printf("%s: packet from unknown node: phy id %d\n", 2600 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2601 m_freem(m); 2602 return IEEE1394_RCODE_COMPLETE; 2603 } 2604 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2605 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2606 m->m_flags |= M_BCAST; 2607 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2608 } else { 2609 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2610 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2611 } 2612 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2613 mtod(m, u_int8_t *)[9] = 2614 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2615 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2616 2617 m->m_pkthdr.rcvif = NULL; /* set in child */ 2618 m->m_pkthdr.len = len + m->m_len; 2619 /* 2620 * We may use receive buffer by external mbuf instead of copy here. 2621 * But asynchronous receive buffer must be operate in buffer fill 2622 * mode, so that each receive buffer will shared by multiple mbufs. 2623 * If upper layer doesn't free mbuf soon, e.g. application program 2624 * is suspended, buffer must be reallocated. 2625 * Isochronous buffer must be operate in packet buffer mode, and 2626 * it is easy to map receive buffer to external mbuf. But it is 2627 * used for broadcast/multicast only, and is expected not so 2628 * performance sensitive for now. 2629 * XXX: The performance may be important for multicast case, 2630 * so we should revisit here later. 2631 * -- onoe 2632 */ 2633 n = 0; 2634 iov = pkt->fp_uio.uio_iov; 2635 while (len > 0) { 2636 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2637 iov->iov_len); 2638 m->m_len += iov->iov_len; 2639 len -= iov->iov_len; 2640 iov++; 2641 } 2642 (*handler)(sc->sc_sc1394.sc1394_if, m); 2643 return IEEE1394_RCODE_COMPLETE; 2644 } 2645 2646 static int 2647 fwohci_if_output(struct device *self, struct mbuf *m0, 2648 void (*callback)(struct device *, struct mbuf *)) 2649 { 2650 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2651 struct fwohci_pkt pkt; 2652 u_int8_t *p; 2653 int n, error, spd, hdrlen, maxrec; 2654 #ifdef FW_DEBUG 2655 struct mbuf *m; 2656 #endif 2657 2658 p = mtod(m0, u_int8_t *); 2659 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2660 spd = IEEE1394_SPD_S100; /*XXX*/ 2661 maxrec = 512; /*XXX*/ 2662 hdrlen = 8; 2663 } else { 2664 n = fwohci_uid_lookup(sc, p); 2665 if (n < 0) { 2666 printf("%s: nodeid unknown:" 2667 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2668 sc->sc_sc1394.sc1394_dev.dv_xname, 2669 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2670 error = EHOSTUNREACH; 2671 goto end; 2672 } 2673 if (n == IEEE1394_BCAST_PHY_ID) { 2674 printf("%s: broadcast with !M_MCAST\n", 2675 sc->sc_sc1394.sc1394_dev.dv_xname); 2676 #ifdef FW_DEBUG 2677 DPRINTFN(2, ("packet:")); 2678 for (m = m0; m != NULL; m = m->m_next) { 2679 for (n = 0; n < m->m_len; n++) 2680 DPRINTFN(2, ("%s%02x", (n%32)? 2681 ((n%4)?"":" "):"\n\t", 2682 mtod(m, u_int8_t *)[n])); 2683 DPRINTFN(2, ("$")); 2684 } 2685 DPRINTFN(2, ("\n")); 2686 #endif 2687 error = EHOSTUNREACH; 2688 goto end; 2689 } 2690 maxrec = 2 << p[8]; 2691 spd = p[9]; 2692 hdrlen = 0; 2693 } 2694 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2695 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2696 spd, sc->sc_sc1394.sc1394_link_speed)); 2697 spd = sc->sc_sc1394.sc1394_link_speed; 2698 } 2699 if (maxrec > (512 << spd)) { 2700 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2701 "\n", maxrec, spd)); 2702 maxrec = 512 << spd; 2703 } 2704 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2705 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2706 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2707 maxrec >>= 1; 2708 } 2709 if (maxrec < 512) { 2710 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2711 "minimum\n", maxrec)); 2712 maxrec = 512; 2713 } 2714 2715 m_adj(m0, 16 - hdrlen); 2716 if (m0->m_pkthdr.len > maxrec) { 2717 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2718 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2719 error = E2BIG; /*XXX*/ 2720 goto end; 2721 } 2722 2723 memset(&pkt, 0, sizeof(pkt)); 2724 pkt.fp_uio.uio_iov = pkt.fp_iov; 2725 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2726 pkt.fp_uio.uio_rw = UIO_WRITE; 2727 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2728 /* construct GASP header */ 2729 p = mtod(m0, u_int8_t *); 2730 p[0] = sc->sc_nodeid >> 8; 2731 p[1] = sc->sc_nodeid & 0xff; 2732 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2733 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2734 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2735 pkt.fp_hlen = 8; 2736 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2737 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2738 OHCI_NodeId_NodeNumber) << 8); 2739 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2740 } else { 2741 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2742 pkt.fp_hlen = 16; 2743 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2744 (spd << 16); 2745 pkt.fp_hdr[1] = 2746 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2747 (p[10] << 8) | p[11]; 2748 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2749 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2750 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2751 } 2752 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2753 pkt.fp_dlen = m0->m_pkthdr.len; 2754 pkt.fp_m = m0; 2755 pkt.fp_callback = callback; 2756 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2757 m0 = pkt.fp_m; 2758 end: 2759 if (m0 != NULL) { 2760 if (callback) 2761 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2762 else 2763 m_freem(m0); 2764 } 2765 return error; 2766 } 2767 2768 /* 2769 * High level routines to provide abstraction to attaching layers to 2770 * send/receive data. 2771 */ 2772 2773 static int 2774 fwohci_read(struct ieee1394_abuf *ab) 2775 { 2776 struct fwohci_pkt pkt; 2777 struct ieee1394_softc *sc = ab->ab_req; 2778 struct fwohci_softc *psc = 2779 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2780 u_int32_t high, lo; 2781 int rv, tcode; 2782 2783 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2784 lo = (ab->ab_csr & 0x00000000ffffffff); 2785 2786 memset(&pkt, 0, sizeof(pkt)); 2787 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2788 pkt.fp_hdr[2] = lo; 2789 pkt.fp_dlen = 0; 2790 2791 if (ab->ab_length == 4) { 2792 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2793 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2794 pkt.fp_hlen = 12; 2795 } else { 2796 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2797 pkt.fp_hlen = 16; 2798 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2799 pkt.fp_hdr[3] = (ab->ab_length << 16); 2800 } 2801 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2802 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2803 2804 pkt.fp_statusarg = ab; 2805 pkt.fp_statuscb = fwohci_extract_resp; 2806 2807 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2808 psc->sc_tlabel, fwohci_extract_resp, ab); 2809 if (rv) 2810 return rv; 2811 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2812 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2813 return rv; 2814 } 2815 2816 static int 2817 fwohci_write(struct ieee1394_abuf *ab) 2818 { 2819 struct fwohci_pkt pkt; 2820 struct ieee1394_softc *sc = ab->ab_req; 2821 struct fwohci_softc *psc = 2822 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2823 u_int32_t high, lo; 2824 int rv; 2825 2826 if (ab->ab_length > sc->sc1394_max_receive) { 2827 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2828 return E2BIG; 2829 } 2830 2831 memset(&pkt, 0, sizeof(pkt)); 2832 2833 pkt.fp_tcode = ab->ab_tcode; 2834 pkt.fp_uio.uio_iov = pkt.fp_iov; 2835 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2836 pkt.fp_uio.uio_rw = UIO_WRITE; 2837 2838 switch (ab->ab_tcode) { 2839 case IEEE1394_TCODE_WRITE_RESP: 2840 pkt.fp_hlen = 12; 2841 case IEEE1394_TCODE_READ_RESP_QUAD: 2842 case IEEE1394_TCODE_READ_RESP_BLOCK: 2843 if (!pkt.fp_hlen) 2844 pkt.fp_hlen = 16; 2845 high = ab->ab_retlen; 2846 ab->ab_retlen = 0; 2847 lo = 0; 2848 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2849 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2850 break; 2851 default: 2852 pkt.fp_hlen = 16; 2853 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2854 lo = (ab->ab_csr & 0x00000000ffffffff); 2855 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2856 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2857 break; 2858 } 2859 2860 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2861 pkt.fp_hdr[2] = lo; 2862 if (pkt.fp_hlen == 16) { 2863 if (ab->ab_length == 4) { 2864 pkt.fp_hdr[3] = ab->ab_data[0]; 2865 pkt.fp_dlen = 0; 2866 } else { 2867 pkt.fp_hdr[3] = (ab->ab_length << 16); 2868 pkt.fp_dlen = ab->ab_length; 2869 pkt.fp_uio.uio_iovcnt = 1; 2870 pkt.fp_uio.uio_resid = ab->ab_length; 2871 pkt.fp_iov[0].iov_base = ab->ab_data; 2872 pkt.fp_iov[0].iov_len = ab->ab_length; 2873 } 2874 } 2875 switch (ab->ab_tcode) { 2876 case IEEE1394_TCODE_WRITE_RESP: 2877 case IEEE1394_TCODE_READ_RESP_QUAD: 2878 case IEEE1394_TCODE_READ_RESP_BLOCK: 2879 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2880 break; 2881 default: 2882 rv = fwohci_handler_set(psc, IEEE1394_TCODE_WRITE_RESP, 2883 ab->ab_req->sc1394_node_id, psc->sc_tlabel, 2884 fwohci_extract_resp, ab); 2885 if (rv) 2886 return rv; 2887 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2888 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2889 break; 2890 } 2891 return rv; 2892 } 2893 2894 static int 2895 fwohci_extract_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2896 { 2897 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 2898 struct fwohci_pkt newpkt; 2899 u_int16_t status; 2900 u_int32_t *cur, high, lo; 2901 int i, rcode, rv; 2902 2903 status = 0; 2904 2905 /* 2906 * No callback just means we want to have something clean up the abuf. 2907 */ 2908 2909 if (ab->ab_cb == NULL) { 2910 if (ab->ab_data) 2911 free(ab->ab_data, M_1394DATA); 2912 if (ab) 2913 free(ab, M_1394DATA); 2914 return 0; 2915 } 2916 2917 /* Check for status packet. */ 2918 2919 if (pkt->fp_tcode == -1) { 2920 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2921 pkt->fp_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2922 2923 /* See below for this exception that's trapped internally. */ 2924 if (ab->ab_ackcb && 2925 !((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2926 (pkt->fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK))) { 2927 2928 /* 2929 * XXX: Deal with this better. Trap OHCI code and 2930 * translate/deal with the results. 2931 */ 2932 2933 if (status >= OHCI_CTXCTL_EVENT_RESERVED16) 2934 status = status & 0xf; 2935 else 2936 status = 0; 2937 ab->ab_ackcb(ab, status); 2938 return IEEE1394_RCODE_COMPLETE; 2939 } 2940 if (!((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2941 (pkt->fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK))) 2942 return IEEE1394_RCODE_COMPLETE; 2943 2944 } else 2945 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2946 2947 /* 2948 * Some area's (like the config rom want to be read as quadlets only. 2949 * 2950 * The current ideas to try are: 2951 * 2952 * Got an ACK_TYPE_ERROR on a block read 2953 * 2954 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a read block response 2955 * 2956 * If all cases construct a new packet for a quadlet read and let 2957 * mutli_resp handle the iteration over the space. 2958 */ 2959 2960 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2961 (pkt->fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2962 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2963 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2964 (pkt->fp_tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2965 2966 /* Read the area in quadlet chunks (internally track this). */ 2967 2968 memset(&newpkt, 0, sizeof(newpkt)); 2969 2970 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2971 lo = (ab->ab_csr & 0x00000000ffffffff); 2972 2973 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2974 newpkt.fp_hlen = 12; 2975 newpkt.fp_dlen = 0; 2976 newpkt.fp_hdr[1] = 2977 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2978 newpkt.fp_hdr[2] = lo; 2979 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2980 (newpkt.fp_tcode << 4); 2981 2982 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2983 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2984 fwohci_multi_resp, ab); 2985 if (rv) 2986 return rv; 2987 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2988 if (ab->ab_ackcb) { 2989 newpkt.fp_statusarg = ab; 2990 newpkt.fp_statuscb = fwohci_extract_resp; 2991 } 2992 fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 2993 } else { 2994 2995 /* 2996 * Recombine all the iov data into 1 chunk for higher 2997 * level code. 2998 */ 2999 3000 cur = ab->ab_data; 3001 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3002 /* 3003 * Make sure and don't exceed the buffer 3004 * allocated for return. 3005 */ 3006 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3007 ab->ab_length) { 3008 memcpy(cur, pkt->fp_iov[i].iov_base, 3009 (ab->ab_length - ab->ab_retlen)); 3010 ab->ab_retlen = ab->ab_length; 3011 break; 3012 } 3013 memcpy(cur, pkt->fp_iov[i].iov_base, 3014 pkt->fp_iov[i].iov_len); 3015 cur += pkt->fp_iov[i].iov_len; 3016 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3017 } 3018 (*ab->ab_cb)(ab, rcode); 3019 } 3020 return IEEE1394_RCODE_COMPLETE; 3021 } 3022 3023 static int 3024 fwohci_multi_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3025 { 3026 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3027 struct fwohci_pkt newpkt; 3028 u_int32_t high, lo; 3029 int rcode, rv; 3030 3031 /* 3032 * Bad return codes from the wire, just return what's already in the 3033 * buf. 3034 */ 3035 3036 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3037 3038 if (rcode) { 3039 (*ab->ab_cb)(ab, rcode); 3040 return rcode; 3041 } 3042 3043 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3044 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3045 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3046 ab->ab_retlen = ab->ab_length; 3047 } else { 3048 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3049 pkt->fp_iov[0].iov_base, 4); 3050 ab->ab_retlen += 4; 3051 } 3052 /* Still more, loop and read 4 more bytes. */ 3053 if (ab->ab_retlen < ab->ab_length) { 3054 memset(&newpkt, 0, sizeof(newpkt)); 3055 3056 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3057 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3058 3059 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3060 newpkt.fp_hlen = 12; 3061 newpkt.fp_dlen = 0; 3062 newpkt.fp_hdr[1] = 3063 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3064 newpkt.fp_hdr[2] = lo; 3065 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3066 (newpkt.fp_tcode << 4); 3067 3068 /* 3069 * Bad return code. Just give up and return what's 3070 * come in now. 3071 */ 3072 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3073 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3074 fwohci_multi_resp, ab); 3075 if (rv) { 3076 (*ab->ab_cb)(ab, rcode); 3077 return IEEE1394_RCODE_DATA_ERROR; 3078 } 3079 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3080 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3081 if (rv) { 3082 (*ab->ab_cb)(ab, rcode); 3083 return IEEE1394_RCODE_DATA_ERROR; 3084 } 3085 } else 3086 (*ab->ab_cb)(ab, rcode); 3087 return IEEE1394_RCODE_COMPLETE; 3088 } 3089 3090 static int 3091 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3092 { 3093 struct ieee1394_softc *sc = ab->ab_req; 3094 struct fwohci_softc *psc = 3095 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3096 u_int32_t high, lo; 3097 int i, rv; 3098 3099 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3100 lo = (ab->ab_csr & 0x00000000ffffffff); 3101 3102 switch (ab->ab_tcode) { 3103 case IEEE1394_TCODE_READ_REQ_QUAD: 3104 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3105 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3106 fwohci_parse_input, ab); 3107 break; 3108 case IEEE1394_TCODE_READ_REQ_BLOCK: 3109 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3110 if (allow) { 3111 for (i = 0; i < (ab->ab_length / 4); i++) { 3112 rv = fwohci_handler_set(psc, ab->ab_tcode, 3113 high, lo + (i * 4), 3114 fwohci_parse_input, ab); 3115 if (rv) 3116 return rv; 3117 } 3118 ab->ab_data = (void *)1; 3119 } else 3120 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3121 fwohci_parse_input, ab); 3122 break; 3123 default: 3124 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3125 return -1; 3126 break; 3127 } 3128 return rv; 3129 } 3130 3131 static int 3132 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3133 { 3134 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3135 u_int64_t csr; 3136 u_int32_t *cur; 3137 int i, count; 3138 3139 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3140 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3141 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3142 3143 switch (ab->ab_tcode) { 3144 case IEEE1394_TCODE_READ_REQ_QUAD: 3145 ab->ab_retlen = 4; 3146 break; 3147 case IEEE1394_TCODE_READ_REQ_BLOCK: 3148 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3149 if (ab->ab_data) { 3150 if ((csr + ab->ab_retlen) > 3151 (ab->ab_csr + ab->ab_length)) 3152 return IEEE1394_RCODE_ADDRESS_ERROR; 3153 ab->ab_data = NULL; 3154 } else 3155 if (ab->ab_retlen != ab->ab_length) 3156 return IEEE1394_RCODE_ADDRESS_ERROR; 3157 break; 3158 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3159 ab->ab_retlen = 4; 3160 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3161 if (!ab->ab_retlen) 3162 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3163 if (ab->ab_data) { 3164 if ((csr + ab->ab_retlen) > 3165 (ab->ab_csr + ab->ab_length)) 3166 return IEEE1394_RCODE_ADDRESS_ERROR; 3167 ab->ab_data = NULL; 3168 } else 3169 if (ab->ab_retlen != ab->ab_length) 3170 return IEEE1394_RCODE_ADDRESS_ERROR; 3171 3172 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3173 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3174 ab->ab_data[0] = pkt->fp_hdr[3]; 3175 else { 3176 count = 0; 3177 cur = ab->ab_data; 3178 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3179 memcpy(cur, pkt->fp_iov[i].iov_base, 3180 pkt->fp_iov[i].iov_len); 3181 cur += pkt->fp_iov[i].iov_len; 3182 count += pkt->fp_iov[i].iov_len; 3183 } 3184 if (ab->ab_retlen != count) 3185 panic("Packet claims %d length " 3186 "but only %d bytes returned\n", 3187 ab->ab_retlen, count); 3188 } 3189 break; 3190 default: 3191 panic("Got a callback for a tcode that wasn't requested: %d\n", 3192 ab->ab_tcode); 3193 break; 3194 } 3195 ab->ab_csr = csr; 3196 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3197 return -1; 3198 } 3199
Indexes created Wed Sep 24 15:09:51 GMT 2025