fwohci.c revision 1.30
1 /* $NetBSD: fwohci.c,v 1.30 2001/05/13 05:01:42 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 115 116 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 117 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 119 120 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 121 struct fwohci_pkt *); 122 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 123 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 124 struct fwohci_pkt *); 125 126 static int fwohci_guidrom_init(struct fwohci_softc *); 127 static void fwohci_configrom_init(struct fwohci_softc *); 128 static int fwohci_configrom_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 static void fwohci_selfid_init(struct fwohci_softc *); 131 static int fwohci_selfid_input(struct fwohci_softc *); 132 133 static void fwohci_csr_init(struct fwohci_softc *); 134 static int fwohci_csr_input(struct fwohci_softc *, void *, 135 struct fwohci_pkt *); 136 137 static void fwohci_uid_collect(struct fwohci_softc *); 138 static int fwohci_uid_input(struct fwohci_softc *, void *, 139 struct fwohci_pkt *); 140 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 141 static void fwohci_check_nodes(struct fwohci_softc *); 142 143 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 144 void (*)(struct device *, struct mbuf *)); 145 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 146 static int fwohci_if_output(struct device *, struct mbuf *, 147 void (*)(struct device *, struct mbuf *)); 148 static int fwohci_read(struct ieee1394_abuf *); 149 static int fwohci_write(struct ieee1394_abuf *); 150 static int fwohci_extract_resp(struct fwohci_softc *, void *, 151 struct fwohci_pkt *); 152 static int fwohci_multi_resp(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_inreg(struct ieee1394_abuf *, int); 155 static int fwohci_parse_input(struct fwohci_softc *, void *, 156 struct fwohci_pkt *); 157 static int fwohci_submatch(struct device *, struct cfdata *, void *); 158 159 #ifdef FW_DEBUG 160 161 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 162 163 #define DPRINTF(x) if (fwdebug) printf x 164 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 165 int fwdebug = 0; 166 #else 167 #define DPRINTF(x) 168 #define DPRINTFN(n,x) 169 #endif 170 171 int 172 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 173 { 174 int i; 175 u_int32_t val; 176 #if 0 177 int error; 178 #endif 179 180 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 181 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 182 183 /* 184 * Wait for reset completion 185 */ 186 for (i = 0; i < OHCI_LOOP; i++) { 187 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 188 if ((val & OHCI_HCControl_SoftReset) == 0) 189 break; 190 } 191 192 /* What dialect of OHCI is this device? 193 */ 194 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 195 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 196 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 197 198 LIST_INIT(&sc->sc_nodelist); 199 200 if (fwohci_guidrom_init(sc) != 0) { 201 printf("\n%s: fatal: no global UID ROM\n", 202 sc->sc_sc1394.sc1394_dev.dv_xname); 203 return -1; 204 } 205 206 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 207 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 208 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 209 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 210 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 211 212 /* Get the maximum link speed and receive size 213 */ 214 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 215 sc->sc_sc1394.sc1394_link_speed = 216 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 217 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 218 printf(", %s", 219 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 220 } else { 221 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 222 } 223 224 /* MaxRec is encoded as log2(max_rec_octets)-1 225 */ 226 sc->sc_sc1394.sc1394_max_receive = 227 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 228 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 229 230 /* 231 * Count how many isochronous ctx we have. 232 */ 233 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 234 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 235 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 236 for (i = 0; val != 0; val >>= 1) { 237 if (val & 0x1) 238 i++; 239 } 240 sc->sc_isoctx = i; 241 printf(", %d iso_ctx", sc->sc_isoctx); 242 243 printf("\n"); 244 245 #if 0 246 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 247 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 248 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 249 return error; 250 #endif 251 252 sc->sc_dying = 0; 253 254 kthread_create(fwohci_create_event_thread, sc); 255 return 0; 256 } 257 258 int 259 fwohci_intr(void *arg) 260 { 261 struct fwohci_softc * const sc = arg; 262 int progress = 0; 263 u_int32_t intmask, iso; 264 265 for (;;) { 266 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 267 268 /* 269 * On a bus reset, everything except bus reset gets 270 * cleared. That can't get cleared until the selfid 271 * phase completes (which happens outside the 272 * interrupt routines). So if just a bus reset is left 273 * in the mask and it's already in the sc_intmask, 274 * just return. 275 */ 276 277 if ((intmask == 0) || 278 (progress && (intmask == OHCI_Int_BusReset) && 279 (sc->sc_intmask & OHCI_Int_BusReset))) { 280 if (progress) 281 wakeup(fwohci_event_thread); 282 return progress; 283 } 284 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 285 intmask & ~OHCI_Int_BusReset); 286 #ifdef FW_DEBUG 287 DPRINTFN(1, ("%s: intmask=0x%08x:", 288 sc->sc_sc1394.sc1394_dev.dv_xname, intmask)); 289 if (intmask & OHCI_Int_CycleTooLong) 290 DPRINTFN(1, (" CycleTooLong")); 291 if (intmask & OHCI_Int_UnrecoverableError) 292 DPRINTFN(1, (" UnrecoverableError")); 293 if (intmask & OHCI_Int_CycleInconsistent) 294 DPRINTFN(1, (" CycleInconsistent")); 295 if (intmask & OHCI_Int_BusReset) 296 DPRINTFN(1, (" BusReset")); 297 if (intmask & OHCI_Int_SelfIDComplete) 298 DPRINTFN(1, (" SelfIDComplete")); 299 if (intmask & OHCI_Int_LockRespErr) 300 DPRINTFN(1, (" LockRespErr")); 301 if (intmask & OHCI_Int_PostedWriteErr) 302 DPRINTFN(1, (" PostedWriteErr")); 303 if (intmask & OHCI_Int_ReqTxComplete) 304 DPRINTFN(1, (" ReqTxComplete(0x%04x)", 305 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 306 OHCI_SUBREG_ContextControlClear))); 307 if (intmask & OHCI_Int_RespTxComplete) 308 DPRINTFN(1, (" RespTxComplete(0x%04x)", 309 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 310 OHCI_SUBREG_ContextControlClear))); 311 if (intmask & OHCI_Int_ARRS) 312 DPRINTFN(1, (" ARRS(0x%04x)", 313 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 314 OHCI_SUBREG_ContextControlClear))); 315 if (intmask & OHCI_Int_ARRQ) 316 DPRINTFN(1, (" ARRQ(0x%04x)", 317 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 318 OHCI_SUBREG_ContextControlClear))); 319 if (intmask & OHCI_Int_IsochRx) 320 DPRINTFN(1, (" IsochRx(0x%08x)", 321 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear))); 322 if (intmask & OHCI_Int_IsochTx) 323 DPRINTFN(1, (" IsochTx(0x%08x)", 324 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear))); 325 if (intmask & OHCI_Int_RQPkt) 326 DPRINTFN(1, (" RQPkt(0x%04x)", 327 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 328 OHCI_SUBREG_ContextControlClear))); 329 if (intmask & OHCI_Int_RSPkt) 330 DPRINTFN(1, (" RSPkt(0x%04x)", 331 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 332 OHCI_SUBREG_ContextControlClear))); 333 DPRINTFN(1, ("\n")); 334 #endif /* FW_DEBUG */ 335 336 if (intmask & OHCI_Int_BusReset) { 337 /* 338 * According to OHCI spec 6.1.1 "busReset", 339 * All asynchronous transmit must be stopped before 340 * clearing BusReset. Moreover, the BusReset 341 * interrupt bit should not be cleared during the 342 * SelfID phase. Thus we turned off interrupt mask 343 * bit of BusReset instead until SelfID completion 344 * or SelfID timeout. 345 */ 346 intmask &= OHCI_Int_SelfIDComplete; 347 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 348 OHCI_Int_BusReset); 349 sc->sc_intmask = intmask; 350 sc->sc_intmask |= OHCI_Int_BusReset; 351 } 352 353 if (intmask & OHCI_Int_SelfIDComplete) 354 sc->sc_intmask |= OHCI_Int_SelfIDComplete; 355 356 if (intmask & OHCI_Int_ReqTxComplete) 357 sc->sc_intmask |= OHCI_Int_ReqTxComplete; 358 if (intmask & OHCI_Int_RespTxComplete) 359 sc->sc_intmask |= OHCI_Int_RespTxComplete; 360 if (intmask & OHCI_Int_RQPkt) 361 sc->sc_intmask |= OHCI_Int_RQPkt; 362 if (intmask & OHCI_Int_RSPkt) 363 sc->sc_intmask |= OHCI_Int_RSPkt; 364 if (intmask & OHCI_Int_IsochTx) { 365 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 366 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 367 sc->sc_intmask |= OHCI_Int_IsochTx; 368 } 369 if (intmask & OHCI_Int_IsochRx) { 370 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 371 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 372 sc->sc_iso |= iso; 373 sc->sc_intmask |= OHCI_Int_IsochRx; 374 } 375 376 if (!progress) { 377 sc->sc_intrcnt.ev_count++; 378 progress = 1; 379 } 380 } 381 } 382 383 static void 384 fwohci_create_event_thread(void *arg) 385 { 386 struct fwohci_softc *sc = arg; 387 388 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 389 sc->sc_sc1394.sc1394_dev.dv_xname)) { 390 printf("%s: unable to create event thread\n", 391 sc->sc_sc1394.sc1394_dev.dv_xname); 392 panic("fwohci_create_event_thread"); 393 } 394 } 395 396 static void 397 fwohci_thread_init(void *arg) 398 { 399 struct fwohci_softc *sc = arg; 400 int i; 401 402 /* 403 * Allocate descriptors 404 */ 405 if (fwohci_desc_alloc(sc)) { 406 printf("%s: not enabling interrupts\n", 407 sc->sc_sc1394.sc1394_dev.dv_xname); 408 kthread_exit(1); 409 } 410 411 /* 412 * Enable Link Power 413 */ 414 415 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 416 417 /* 418 * Allocate DMA Context 419 */ 420 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 421 OHCI_CTX_ASYNC_RX_REQUEST); 422 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 423 OHCI_CTX_ASYNC_RX_RESPONSE); 424 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 425 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 426 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 427 M_DEVBUF, M_WAITOK); 428 for (i = 0; i < sc->sc_isoctx; i++) 429 sc->sc_ctx_ir[i] = NULL; 430 431 /* 432 * Allocate buffer for configuration ROM and SelfID buffer 433 */ 434 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 435 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 436 437 callout_init(&sc->sc_selfid_callout); 438 439 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 440 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 441 442 /* 443 * establish hooks for shutdown and suspend/resume 444 */ 445 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 446 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 447 448 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 449 fwohci_print); 450 451 /* Main loop. It's not coming back normally. */ 452 453 fwohci_event_thread(sc); 454 455 kthread_exit(0); 456 } 457 458 static void 459 fwohci_event_thread(struct fwohci_softc *sc) 460 { 461 int i, s; 462 u_int32_t intmask, iso; 463 464 s = splbio(); 465 466 /* 467 * Initialize hardware registers. 468 */ 469 470 fwohci_hw_init(sc); 471 472 /* Initial Bus Reset */ 473 fwohci_phy_busreset(sc); 474 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 475 splx(s); 476 477 while (!sc->sc_dying) { 478 while (1) { 479 s = splbio(); 480 intmask = sc->sc_intmask; 481 if (intmask) { 482 splx(s); 483 if (intmask & OHCI_Int_BusReset) { 484 s = splbio(); 485 sc->sc_intmask &= ~OHCI_Int_BusReset; 486 splx(s); 487 fwohci_buf_stop(sc); 488 fwohci_buf_init(sc); 489 if (sc->sc_uidtbl != NULL) { 490 free(sc->sc_uidtbl, M_DEVBUF); 491 sc->sc_uidtbl = NULL; 492 } 493 494 callout_reset(&sc->sc_selfid_callout, 495 OHCI_SELFID_TIMEOUT, 496 (void (*)(void *)) 497 fwohci_phy_busreset, sc); 498 sc->sc_nodeid = 0xffff; /* indicate 499 invalid */ 500 sc->sc_rootid = 0; 501 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 502 } 503 if (intmask & OHCI_Int_SelfIDComplete) { 504 s = splbio(); 505 sc->sc_intmask &= 506 ~OHCI_Int_SelfIDComplete; 507 OHCI_CSR_WRITE(sc, 508 OHCI_REG_IntEventClear, 509 OHCI_Int_BusReset); 510 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 511 OHCI_Int_BusReset); 512 splx(s); 513 callout_stop(&sc->sc_selfid_callout); 514 if (fwohci_selfid_input(sc) == 0) { 515 fwohci_buf_start(sc); 516 fwohci_uid_collect(sc); 517 } 518 } 519 if (intmask & OHCI_Int_ReqTxComplete) { 520 s = splbio(); 521 sc->sc_intmask &= 522 ~OHCI_Int_ReqTxComplete; 523 splx(s); 524 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 525 } 526 if (intmask & OHCI_Int_RespTxComplete) { 527 s = splbio(); 528 sc->sc_intmask &= 529 ~OHCI_Int_RespTxComplete; 530 splx(s); 531 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 532 } 533 if (intmask & OHCI_Int_RQPkt) { 534 s = splbio(); 535 sc->sc_intmask &= ~OHCI_Int_RQPkt; 536 splx(s); 537 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 538 } 539 if (intmask & OHCI_Int_RSPkt) { 540 s = splbio(); 541 sc->sc_intmask &= ~OHCI_Int_RSPkt; 542 splx(s); 543 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 544 } 545 if (intmask & OHCI_Int_IsochTx) { 546 s = splbio(); 547 sc->sc_intmask &= ~OHCI_Int_IsochTx; 548 splx(s); 549 } 550 if (intmask & OHCI_Int_IsochRx) { 551 s = splbio(); 552 sc->sc_intmask &= ~OHCI_Int_IsochRx; 553 iso = sc->sc_iso; 554 sc->sc_iso = 0; 555 splx(s); 556 for (i = 0; i < sc->sc_isoctx; i++) { 557 if ((iso & (1 << i)) && 558 sc->sc_ctx_ir[i] != NULL) 559 fwohci_ir_input(sc, 560 sc->sc_ctx_ir[i]); 561 } 562 } 563 } else 564 break; 565 } 566 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 567 splx(s); 568 } 569 } 570 571 #if 0 572 static int 573 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 574 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 575 { 576 bus_dma_segment_t segs[1]; 577 int error, nsegs, steps; 578 579 steps = 0; 580 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 581 segs, 1, &nsegs, flags); 582 if (error) 583 goto cleanup; 584 585 steps = 1; 586 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 587 kvap, flags); 588 if (error) 589 goto cleanup; 590 591 if (error == 0) 592 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 593 size, flags, mapp); 594 if (error) 595 goto cleanup; 596 if (error == 0) 597 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 598 flags); 599 if (error) 600 goto cleanup; 601 602 cleanup: 603 switch (steps) { 604 case 1: 605 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 606 } 607 608 return error; 609 } 610 #endif 611 612 int 613 fwohci_print(void *aux, const char *pnp) 614 { 615 char *name = aux; 616 617 if (pnp) 618 printf("%s at %s", name, pnp); 619 620 return QUIET; 621 } 622 623 static void 624 fwohci_hw_init(struct fwohci_softc *sc) 625 { 626 int i; 627 u_int32_t val; 628 629 /* 630 * Software Reset. 631 */ 632 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 633 for (i = 0; i < OHCI_LOOP; i++) { 634 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 635 if ((val & OHCI_HCControl_SoftReset) == 0) 636 break; 637 } 638 639 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 640 641 /* 642 * First, initilize CSRs with undefined value to default settings. 643 */ 644 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 645 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 646 #if 0 647 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 648 #else 649 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 650 #endif 651 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 652 for (i = 0; i < sc->sc_isoctx; i++) { 653 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 654 ~0); 655 } 656 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 657 658 fwohci_configrom_init(sc); 659 fwohci_selfid_init(sc); 660 fwohci_buf_init(sc); 661 fwohci_csr_init(sc); 662 663 /* 664 * Final CSR settings. 665 */ 666 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 667 OHCI_LinkControl_CycleTimerEnable | 668 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 669 670 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 671 672 /* clear receive filter */ 673 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 674 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 675 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 676 677 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 678 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 679 #if BYTE_ORDER == BIG_ENDIAN 680 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 681 OHCI_HCControl_NoByteSwapData); 682 #endif 683 684 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 685 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 686 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 687 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 688 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 689 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 690 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 691 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 692 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 693 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 694 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 695 696 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 697 698 /* 699 * Start the receivers 700 */ 701 fwohci_buf_start(sc); 702 } 703 704 static void 705 fwohci_power(int why, void *arg) 706 { 707 struct fwohci_softc *sc = arg; 708 int s; 709 710 s = splbio(); 711 switch (why) { 712 case PWR_SUSPEND: 713 case PWR_STANDBY: 714 fwohci_shutdown(sc); 715 break; 716 case PWR_RESUME: 717 fwohci_hw_init(sc); 718 fwohci_phy_busreset(sc); 719 break; 720 case PWR_SOFTSUSPEND: 721 case PWR_SOFTSTANDBY: 722 case PWR_SOFTRESUME: 723 break; 724 } 725 splx(s); 726 } 727 728 static void 729 fwohci_shutdown(void *arg) 730 { 731 struct fwohci_softc *sc = arg; 732 u_int32_t val; 733 734 callout_stop(&sc->sc_selfid_callout); 735 /* disable all interrupt */ 736 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 737 fwohci_buf_stop(sc); 738 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 739 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 740 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 741 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 742 fwohci_phy_busreset(sc); 743 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 744 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 745 } 746 747 /* 748 * COMMON FUNCTIONS 749 */ 750 751 /* 752 * read the PHY Register. 753 */ 754 static u_int8_t 755 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 756 { 757 int i; 758 u_int32_t val; 759 760 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 761 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 762 for (i = 0; i < OHCI_LOOP; i++) { 763 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 764 OHCI_PhyControl_RdDone) 765 break; 766 } 767 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 768 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 769 } 770 771 /* 772 * write the PHY Register. 773 */ 774 static void 775 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 776 { 777 int i; 778 779 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 780 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 781 (val << OHCI_PhyControl_WrData_BITPOS)); 782 for (i = 0; i < OHCI_LOOP; i++) { 783 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 784 OHCI_PhyControl_WrReg)) 785 break; 786 } 787 } 788 789 /* 790 * Initiate Bus Reset 791 */ 792 static void 793 fwohci_phy_busreset(struct fwohci_softc *sc) 794 { 795 int s; 796 u_int8_t val; 797 798 s = splbio(); 799 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 800 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 801 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 802 callout_stop(&sc->sc_selfid_callout); 803 val = fwohci_phy_read(sc, 1); 804 val = (val & 0x80) | /* preserve RHB (force root) */ 805 0x40 | /* Initiate Bus Reset */ 806 0x3f; /* default GAP count */ 807 fwohci_phy_write(sc, 1, val); 808 splx(s); 809 } 810 811 /* 812 * PHY Packet 813 */ 814 static void 815 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 816 { 817 u_int32_t val; 818 u_int8_t key, phyid; 819 820 val = pkt->fp_hdr[1]; 821 if (val != ~pkt->fp_hdr[2]) { 822 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 823 OHCI_CTXCTL_EVENT_BUS_RESET) { 824 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 825 pkt->fp_hdr[2])); 826 } else { 827 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 828 sc->sc_sc1394.sc1394_dev.dv_xname, val, 829 pkt->fp_hdr[2]); 830 } 831 return; 832 } 833 key = (val & 0xc0000000) >> 30; 834 phyid = (val & 0x3f000000) >> 24; 835 switch (key) { 836 case 0: 837 #ifdef FW_DEBUG 838 DPRINTFN(1, ("fwohci_phy_input: PHY Config from %d:", phyid)); 839 if (val & 0x00800000) 840 DPRINTFN(1, (" ForceRoot")); 841 if (val & 0x00400000) 842 DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16)); 843 printf("\n"); 844 #endif 845 break; 846 case 1: 847 DPRINTFN(1, ("fwohci_phy_input: Link-on from %d\n", phyid)); 848 break; 849 case 2: 850 #ifdef FW_DEBUG 851 DPRINTFN(1, ("fwohci_phy_input: SelfID from %d:", phyid)); 852 if (val & 0x00800000) { 853 DPRINTFN(1, (" #%d", (val & 0x00700000) >> 20)); 854 } else { 855 if (val & 0x00400000) 856 DPRINTFN(1, (" LinkActive")); 857 DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16)); 858 DPRINTFN(1, (" Spd=S%d", 859 100 << ((val & 0x0000c000) >> 14))); 860 if (val & 0x00000800) 861 DPRINTFN(1, (" Cont")); 862 if (val & 0x00000002) 863 DPRINTFN(1, (" InitiateBusReset")); 864 } 865 if (val & 0x00000001) 866 DPRINTFN(1, (" +")); 867 DPRINTFN(1, ("\n")); 868 #endif 869 break; 870 default: 871 printf("%s: unknown PHY packet: 0x%08x\n", 872 sc->sc_sc1394.sc1394_dev.dv_xname, val); 873 break; 874 } 875 } 876 877 /* 878 * Descriptor for context DMA. 879 */ 880 static int 881 fwohci_desc_alloc(struct fwohci_softc *sc) 882 { 883 int error, mapsize, dsize; 884 885 /* 886 * allocate descriptor buffer 887 */ 888 889 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 890 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 891 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 892 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 893 mapsize = howmany(sc->sc_descsize, NBBY); 894 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 895 memset(sc->sc_descmap, 0, mapsize); 896 897 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 898 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 899 printf("%s: unable to allocate descriptor buffer, error = %d\n", 900 sc->sc_sc1394.sc1394_dev.dv_xname, error); 901 goto fail_0; 902 } 903 904 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 905 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 906 != 0) { 907 printf("%s: unable to map descriptor buffer, error = %d\n", 908 sc->sc_sc1394.sc1394_dev.dv_xname, error); 909 goto fail_1; 910 } 911 912 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 913 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 914 printf("%s: unable to create descriptor buffer DMA map, " 915 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 916 goto fail_2; 917 } 918 919 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 920 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 921 printf("%s: unable to load descriptor buffer DMA map, " 922 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 923 goto fail_3; 924 } 925 926 return 0; 927 928 fail_3: 929 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 930 fail_2: 931 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 932 fail_1: 933 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 934 fail_0: 935 return error; 936 } 937 938 static struct fwohci_desc * 939 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 940 { 941 int i, n; 942 943 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 944 for (i = 0; ; i++) { 945 if (i == ndesc) { 946 for (i = 0; i < ndesc; i++) 947 setbit(sc->sc_descmap, n + i); 948 return sc->sc_desc + n; 949 } 950 if (isset(sc->sc_descmap, n + i)) 951 break; 952 } 953 } 954 return NULL; 955 } 956 957 static void 958 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 959 { 960 int i, n; 961 962 n = fd - sc->sc_desc; 963 for (i = 0; i < ndesc; i++, n++) { 964 #ifdef DIAGNOSTIC 965 if (isclr(sc->sc_descmap, n)) 966 panic("fwohci_desc_put: duplicated free"); 967 #endif 968 clrbit(sc->sc_descmap, n); 969 } 970 } 971 972 /* 973 * Asyncronous/Isochronous Transmit/Receive Context 974 */ 975 static int 976 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 977 int bufcnt, int ctx) 978 { 979 int i, error; 980 struct fwohci_ctx *fc; 981 struct fwohci_buf *fb; 982 struct fwohci_desc *fd; 983 984 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 985 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 986 LIST_INIT(&fc->fc_handler); 987 TAILQ_INIT(&fc->fc_buf); 988 fc->fc_ctx = ctx; 989 fc->fc_bufcnt = bufcnt; 990 fb = (struct fwohci_buf *)&fc[1]; 991 for (i = 0; i < bufcnt; i++, fb++) { 992 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 993 goto fail; 994 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 995 error = ENOBUFS; 996 goto fail; 997 } 998 fb->fb_desc = fd; 999 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1000 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1001 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1002 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1003 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1004 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1005 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1006 } 1007 *fcp = fc; 1008 return 0; 1009 1010 fail: 1011 while (i-- > 0) 1012 fwohci_buf_free(sc, --fb); 1013 free(fc, M_DEVBUF); 1014 return error; 1015 } 1016 1017 static void 1018 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1019 { 1020 struct fwohci_buf *fb; 1021 struct fwohci_handler *fh; 1022 1023 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1024 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1025 NULL, NULL); 1026 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1027 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1028 fwohci_buf_free(sc, fb); 1029 } 1030 free(fc, M_DEVBUF); 1031 } 1032 1033 static void 1034 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1035 { 1036 struct fwohci_buf *fb, *nfb; 1037 struct fwohci_desc *fd; 1038 struct fwohci_handler *fh; 1039 int n; 1040 1041 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1042 nfb = TAILQ_NEXT(fb, fb_list); 1043 fb->fb_off = 0; 1044 fd = fb->fb_desc; 1045 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1046 fd->fd_rescount = fd->fd_reqcount; 1047 } 1048 1049 n = fc->fc_ctx; 1050 fb = TAILQ_FIRST(&fc->fc_buf); 1051 if (fc->fc_isoch) { 1052 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1053 fb->fb_daddr | 1); 1054 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1055 OHCI_CTXCTL_RX_BUFFER_FILL | 1056 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1057 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1058 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1059 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1060 OHCI_CTXCTL_RX_ISOCH_HEADER); 1061 fh = LIST_FIRST(&fc->fc_handler); 1062 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1063 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1064 } else { 1065 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1066 fb->fb_daddr | 1); 1067 } 1068 } 1069 1070 /* 1071 * DMA data buffer 1072 */ 1073 static int 1074 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1075 { 1076 int error; 1077 1078 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1079 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1080 printf("%s: unable to allocate buffer, error = %d\n", 1081 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1082 goto fail_0; 1083 } 1084 1085 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1086 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1087 printf("%s: unable to map buffer, error = %d\n", 1088 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1089 goto fail_1; 1090 } 1091 1092 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1093 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1094 printf("%s: unable to create buffer DMA map, " 1095 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1096 error); 1097 goto fail_2; 1098 } 1099 1100 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1101 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1102 printf("%s: unable to load buffer DMA map, " 1103 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1104 error); 1105 goto fail_3; 1106 } 1107 1108 return 0; 1109 1110 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1111 fail_3: 1112 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1113 fail_2: 1114 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1115 fail_1: 1116 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1117 fail_0: 1118 return error; 1119 } 1120 1121 static void 1122 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1123 { 1124 1125 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1126 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1127 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1128 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1129 } 1130 1131 static void 1132 fwohci_buf_init(struct fwohci_softc *sc) 1133 { 1134 int i; 1135 1136 /* 1137 * Initialize for Asynchronous Transmit Queue. 1138 */ 1139 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1140 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1141 1142 /* 1143 * Initialize for Asynchronous Receive Queue. 1144 */ 1145 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1146 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1147 1148 /* 1149 * Initialize for Isochronous Receive Queue. 1150 */ 1151 for (i = 0; i < sc->sc_isoctx; i++) { 1152 if (sc->sc_ctx_ir[i] != NULL) 1153 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1154 } 1155 } 1156 1157 static void 1158 fwohci_buf_start(struct fwohci_softc *sc) 1159 { 1160 int i; 1161 1162 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1163 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1164 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1165 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1166 for (i = 0; i < sc->sc_isoctx; i++) { 1167 if (sc->sc_ctx_ir[i] != NULL && 1168 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1169 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1170 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1171 } 1172 } 1173 } 1174 1175 static void 1176 fwohci_buf_stop(struct fwohci_softc *sc) 1177 { 1178 int i, j; 1179 1180 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1181 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1182 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1183 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1184 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1185 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1186 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1187 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1188 for (i = 0; i < sc->sc_isoctx; i++) { 1189 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1190 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1191 } 1192 1193 /* 1194 * Make sure the transmitter is stopped. 1195 */ 1196 for (j = 0; j < OHCI_LOOP; j++) { 1197 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1198 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1199 continue; 1200 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1201 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1202 continue; 1203 break; 1204 } 1205 } 1206 1207 static void 1208 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1209 { 1210 struct fwohci_buf *fb, *tfb; 1211 1212 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1213 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1214 fb->fb_desc->fd_rescount != 0) 1215 break; 1216 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1217 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1218 fb->fb_off = 0; 1219 fb->fb_desc->fd_branch = 0; 1220 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1221 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1222 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1223 } 1224 } 1225 1226 static int 1227 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1228 int len) 1229 { 1230 struct fwohci_buf *fb; 1231 struct fwohci_desc *fd; 1232 int bufend; 1233 1234 fb = TAILQ_FIRST(&fc->fc_buf); 1235 again: 1236 fd = fb->fb_desc; 1237 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1238 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1239 fd->fd_reqcount, fd->fd_rescount, len, 1240 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1241 bufend = fd->fd_reqcount - fd->fd_rescount; 1242 if (fb->fb_off >= bufend) { 1243 if (fc->fc_isoch && fb->fb_off > 0) { 1244 fb->fb_off = fd->fd_reqcount; 1245 fd->fd_rescount = 0; 1246 } 1247 if (fd->fd_rescount == 0) { 1248 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1249 goto again; 1250 } 1251 return 0; 1252 } 1253 if (fb->fb_off + len > bufend) 1254 len = bufend - fb->fb_off; 1255 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1256 BUS_DMASYNC_POSTREAD); 1257 *pp = fb->fb_buf + fb->fb_off; 1258 fb->fb_off += roundup(len, 4); 1259 return len; 1260 } 1261 1262 static int 1263 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1264 struct fwohci_pkt *pkt) 1265 { 1266 caddr_t p; 1267 int len, count, i; 1268 1269 memset(pkt, 0, sizeof(*pkt)); 1270 pkt->fp_uio.uio_iov = pkt->fp_iov; 1271 pkt->fp_uio.uio_rw = UIO_WRITE; 1272 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1273 1274 /* get first quadlet */ 1275 count = 4; 1276 if (fc->fc_isoch) { 1277 /* 1278 * get trailer first, may be bogus data unless status update 1279 * in descriptor is set. 1280 */ 1281 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1282 sizeof(*pkt->fp_trail)); 1283 if (len <= 0) { 1284 DPRINTFN(1, ("fwohci_buf_input: no input for is#%d\n", 1285 fc->fc_ctx)); 1286 return 0; 1287 } 1288 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1289 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1290 } 1291 len = fwohci_buf_pktget(sc, fc, &p, count); 1292 if (len <= 0) { 1293 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1294 fc->fc_ctx)); 1295 return 0; 1296 } 1297 pkt->fp_hdr[0] = *(u_int32_t *)p; 1298 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1299 switch (pkt->fp_tcode) { 1300 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1301 case IEEE1394_TCODE_READ_RESP_QUAD: 1302 pkt->fp_hlen = 12; 1303 pkt->fp_dlen = 4; 1304 break; 1305 case IEEE1394_TCODE_READ_REQ_BLOCK: 1306 pkt->fp_hlen = 16; 1307 pkt->fp_dlen = 0; 1308 break; 1309 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1310 case IEEE1394_TCODE_READ_RESP_BLOCK: 1311 case IEEE1394_TCODE_LOCK_REQ: 1312 case IEEE1394_TCODE_LOCK_RESP: 1313 pkt->fp_hlen = 16; 1314 break; 1315 case IEEE1394_TCODE_STREAM_DATA: 1316 pkt->fp_hlen = 4; 1317 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1318 break; 1319 default: 1320 pkt->fp_hlen = 12; 1321 pkt->fp_dlen = 0; 1322 break; 1323 } 1324 1325 /* get header */ 1326 while (count < pkt->fp_hlen) { 1327 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1328 if (len == 0) { 1329 printf("fwohci_buf_input: malformed input 1: %d\n", 1330 pkt->fp_hlen - count); 1331 return 0; 1332 } 1333 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1334 count += len; 1335 } 1336 if ((pkt->fp_hlen == 16) && 1337 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1338 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1339 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1340 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1341 1342 /* get data */ 1343 count = 0; 1344 i = 0; 1345 while (count < pkt->fp_dlen) { 1346 len = fwohci_buf_pktget(sc, fc, 1347 (caddr_t *)&pkt->fp_iov[i].iov_base, 1348 pkt->fp_dlen - count); 1349 if (len == 0) { 1350 printf("fwohci_buf_input: malformed input 2: %d\n", 1351 pkt->fp_hlen - count); 1352 return 0; 1353 } 1354 pkt->fp_iov[i++].iov_len = len; 1355 count += len; 1356 } 1357 pkt->fp_uio.uio_iovcnt = i; 1358 pkt->fp_uio.uio_resid = count; 1359 1360 if (!fc->fc_isoch) { 1361 /* get trailer */ 1362 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1363 sizeof(*pkt->fp_trail)); 1364 if (len <= 0) { 1365 printf("fwohci_buf_input: malformed input 3: %d\n", 1366 pkt->fp_hlen - count); 1367 return 0; 1368 } 1369 } 1370 return 1; 1371 } 1372 1373 static int 1374 fwohci_handler_set(struct fwohci_softc *sc, 1375 int tcode, u_int32_t key1, u_int32_t key2, 1376 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1377 void *arg) 1378 { 1379 struct fwohci_ctx *fc; 1380 struct fwohci_handler *fh; 1381 int i, j; 1382 1383 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1384 j = sc->sc_isoctx; 1385 fh = NULL; 1386 for (i = 0; i < sc->sc_isoctx; i++) { 1387 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1388 if (j == sc->sc_isoctx) 1389 j = i; 1390 continue; 1391 } 1392 fh = LIST_FIRST(&fc->fc_handler); 1393 if (fh == NULL) { 1394 j = i; 1395 break; 1396 } 1397 if (fh->fh_tcode == tcode && 1398 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1399 break; 1400 fh = NULL; 1401 } 1402 if (fh == NULL) { 1403 if (handler == NULL) 1404 return 0; 1405 if (j == sc->sc_isoctx) { 1406 DPRINTF(("fwohci_handler_set: no more free " 1407 "context\n")); 1408 return ENOMEM; 1409 } 1410 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1411 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1412 fc->fc_isoch = 1; 1413 sc->sc_ctx_ir[j] = fc; 1414 } 1415 } 1416 } else { 1417 switch (tcode) { 1418 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1419 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1420 case IEEE1394_TCODE_READ_REQ_QUAD: 1421 case IEEE1394_TCODE_READ_REQ_BLOCK: 1422 case IEEE1394_TCODE_LOCK_REQ: 1423 fc = sc->sc_ctx_arrq; 1424 break; 1425 case IEEE1394_TCODE_WRITE_RESP: 1426 case IEEE1394_TCODE_READ_RESP_QUAD: 1427 case IEEE1394_TCODE_READ_RESP_BLOCK: 1428 case IEEE1394_TCODE_LOCK_RESP: 1429 fc = sc->sc_ctx_arrs; 1430 break; 1431 default: 1432 return EIO; 1433 } 1434 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1435 fh = LIST_NEXT(fh, fh_list)) { 1436 if (fh->fh_tcode == tcode && 1437 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1438 break; 1439 } 1440 } 1441 if (handler == NULL) { 1442 if (fh != NULL) { 1443 LIST_REMOVE(fh, fh_list); 1444 free(fh, M_DEVBUF); 1445 } 1446 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1447 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1448 fwohci_ctx_free(sc, fc); 1449 } 1450 return 0; 1451 } 1452 if (fh == NULL) { 1453 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1454 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1455 } 1456 fh->fh_tcode = tcode; 1457 fh->fh_key1 = key1; 1458 fh->fh_key2 = key2; 1459 fh->fh_handler = handler; 1460 fh->fh_handarg = arg; 1461 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1462 fc->fc_ctx, tcode, key1, key2)); 1463 1464 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1465 fwohci_ctx_init(sc, fc); 1466 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1467 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1468 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1469 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1470 } 1471 return 0; 1472 } 1473 1474 /* 1475 * Asyncronous Receive Requests input frontend. 1476 */ 1477 static void 1478 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1479 { 1480 int rcode; 1481 u_int32_t key1, key2; 1482 struct fwohci_handler *fh; 1483 struct fwohci_pkt pkt, res; 1484 1485 while (fwohci_buf_input(sc, fc, &pkt)) { 1486 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1487 fwohci_phy_input(sc, &pkt); 1488 return; 1489 } 1490 key1 = pkt.fp_hdr[1] & 0xffff; 1491 key2 = pkt.fp_hdr[2]; 1492 memset(&res, 0, sizeof(res)); 1493 res.fp_uio.uio_rw = UIO_WRITE; 1494 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1495 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1496 fh = LIST_NEXT(fh, fh_list)) { 1497 if (pkt.fp_tcode == fh->fh_tcode && 1498 key1 == fh->fh_key1 && 1499 key2 == fh->fh_key2) { 1500 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1501 &pkt); 1502 break; 1503 } 1504 } 1505 if (fh == NULL) { 1506 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1507 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1508 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1509 key2)); 1510 } 1511 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1512 OHCI_CTXCTL_EVENT_ACK_PENDING) 1513 return; 1514 if (rcode != -1) 1515 fwohci_atrs_output(sc, rcode, &pkt, &res); 1516 } 1517 fwohci_buf_next(sc, fc); 1518 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1519 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1520 } 1521 1522 1523 /* 1524 * Asynchronous Receive Response input frontend. 1525 */ 1526 static void 1527 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1528 { 1529 struct fwohci_pkt pkt; 1530 struct fwohci_handler *fh; 1531 u_int16_t srcid; 1532 int rcode, tlabel; 1533 1534 while (fwohci_buf_input(sc, fc, &pkt)) { 1535 srcid = pkt.fp_hdr[1] >> 16; 1536 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1537 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1538 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1539 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1540 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1541 pkt.fp_dlen)); 1542 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1543 fh = LIST_NEXT(fh, fh_list)) { 1544 if (pkt.fp_tcode == fh->fh_tcode && 1545 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1546 tlabel == fh->fh_key2) { 1547 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1548 LIST_REMOVE(fh, fh_list); 1549 free(fh, M_DEVBUF); 1550 break; 1551 } 1552 } 1553 #ifdef FW_DEBUG 1554 if (fh == NULL) { 1555 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1556 DPRINTFN(1, ("src: %d, rcode: %d, tlabel: %d, tcode: " 1557 "%d hdr[3]: 0x%08x, data: 0x%08lx\n", srcid, rcode, 1558 tlabel, pkt.fp_tcode, pkt.fp_hdr[3], 1559 (unsigned long)(*((int *)pkt.fp_iov[0].iov_base)))); 1560 } 1561 #endif 1562 } 1563 fwohci_buf_next(sc, fc); 1564 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1565 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1566 } 1567 1568 /* 1569 * Isochronous Receive input frontend. 1570 */ 1571 static void 1572 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1573 { 1574 int rcode, chan, tag; 1575 struct iovec *iov; 1576 struct fwohci_handler *fh; 1577 struct fwohci_pkt pkt; 1578 1579 while (fwohci_buf_input(sc, fc, &pkt)) { 1580 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1581 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1582 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1583 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1584 pkt.fp_dlen)); 1585 if (tag == IEEE1394_TAG_GASP) { 1586 /* 1587 * The pkt with tag=3 is GASP format. 1588 * Move GASP header to header part. 1589 */ 1590 if (pkt.fp_dlen < 8) 1591 continue; 1592 iov = pkt.fp_iov; 1593 /* assuming pkt per buffer mode */ 1594 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1595 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1596 iov->iov_base = (caddr_t)iov->iov_base + 8; 1597 iov->iov_len -= 8; 1598 pkt.fp_hlen += 8; 1599 pkt.fp_dlen -= 8; 1600 } 1601 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1602 fh = LIST_NEXT(fh, fh_list)) { 1603 if (pkt.fp_tcode == fh->fh_tcode && 1604 chan == fh->fh_key1 && tag == fh->fh_key2) { 1605 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1606 &pkt); 1607 break; 1608 } 1609 } 1610 #ifdef FW_DEBUG 1611 if (fh == NULL) { 1612 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1613 } else { 1614 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1615 } 1616 #endif 1617 } 1618 fwohci_buf_next(sc, fc); 1619 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1620 OHCI_CTXCTL_WAKE); 1621 } 1622 1623 /* 1624 * Asynchronous Transmit common routine. 1625 */ 1626 static int 1627 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1628 struct fwohci_pkt *pkt) 1629 { 1630 struct fwohci_buf *fb; 1631 struct fwohci_desc *fd; 1632 struct mbuf *m, *m0; 1633 int i, ndesc, error, off, len; 1634 u_int32_t val; 1635 #ifdef FW_DEBUG 1636 struct iovec *iov; 1637 #endif 1638 1639 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1640 /* We can't send anything during selfid duration */ 1641 return EAGAIN; 1642 1643 #ifdef FW_DEBUG 1644 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1645 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1646 for (i = 0; i < pkt->fp_hlen/4; i++) 1647 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 1648 DPRINTFN(2, ("$")); 1649 for (ndesc = 0, iov = pkt->fp_iov; 1650 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1651 for (i = 0; i < iov->iov_len; i++) 1652 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1653 ((u_int8_t *)iov->iov_base)[i])); 1654 DPRINTFN(2, ("$")); 1655 } 1656 DPRINTFN(1, ("\n")); 1657 #endif 1658 1659 if ((m = pkt->fp_m) != NULL) { 1660 for (ndesc = 2; m != NULL; m = m->m_next) 1661 ndesc++; 1662 if (ndesc > OHCI_DESC_MAX) { 1663 m0 = NULL; 1664 ndesc = 2; 1665 for (off = 0; off < pkt->fp_dlen; off += len) { 1666 if (m0 == NULL) { 1667 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1668 if (m0 != NULL) 1669 M_COPY_PKTHDR(m0, pkt->fp_m); 1670 m = m0; 1671 } else { 1672 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1673 m = m->m_next; 1674 } 1675 if (m != NULL) 1676 MCLGET(m, M_DONTWAIT); 1677 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1678 m_freem(m0); 1679 return ENOMEM; 1680 } 1681 len = pkt->fp_dlen - off; 1682 if (len > m->m_ext.ext_size) 1683 len = m->m_ext.ext_size; 1684 m_copydata(pkt->fp_m, off, len, 1685 mtod(m, caddr_t)); 1686 m->m_len = len; 1687 ndesc++; 1688 } 1689 m_freem(pkt->fp_m); 1690 pkt->fp_m = m0; 1691 } 1692 } else 1693 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1694 1695 if (ndesc > OHCI_DESC_MAX) 1696 return ENOBUFS; 1697 1698 if (fc->fc_bufcnt > 50) /*XXX*/ 1699 return ENOBUFS; 1700 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1701 fb->fb_nseg = ndesc; 1702 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1703 if (fb->fb_desc == NULL) { 1704 free(fb, M_DEVBUF); 1705 return ENOBUFS; 1706 } 1707 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1708 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1709 fb->fb_m = pkt->fp_m; 1710 fb->fb_callback = pkt->fp_callback; 1711 fb->fb_statuscb = pkt->fp_statuscb; 1712 fb->fb_statusarg = pkt->fp_statusarg; 1713 1714 if (ndesc > 2) { 1715 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1716 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1717 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1718 free(fb, M_DEVBUF); 1719 return error; 1720 } 1721 1722 if (pkt->fp_m != NULL) 1723 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1724 pkt->fp_m, BUS_DMA_WAITOK); 1725 else 1726 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1727 &pkt->fp_uio, BUS_DMA_WAITOK); 1728 if (error != 0) { 1729 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1730 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1731 free(fb, M_DEVBUF); 1732 return error; 1733 } 1734 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1735 BUS_DMASYNC_PREWRITE); 1736 } 1737 1738 fd = fb->fb_desc; 1739 fd->fd_flags = OHCI_DESC_IMMED; 1740 fd->fd_reqcount = pkt->fp_hlen; 1741 fd->fd_data = 0; 1742 fd->fd_branch = 0; 1743 fd->fd_status = 0; 1744 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1745 i = 3; /* XXX: 3 sec */ 1746 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1747 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1748 ((((val >> 25) + i) & 0x7) << 13); 1749 } else 1750 fd->fd_timestamp = 0; 1751 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1752 for (i = 0; i < ndesc - 2; i++) { 1753 fd = fb->fb_desc + 2 + i; 1754 fd->fd_flags = 0; 1755 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1756 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1757 fd->fd_branch = 0; 1758 fd->fd_status = 0; 1759 fd->fd_timestamp = 0; 1760 } 1761 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1762 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1763 1764 #ifdef FW_DEBUG 1765 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1766 (long)(fb->fb_desc - sc->sc_desc))); 1767 for (i = 0; i < ndesc * 4; i++) 1768 DPRINTFN(1, ("%s%08x", i&7?" ":"\n\t", 1769 ((u_int32_t *)fb->fb_desc)[i])); 1770 DPRINTFN(1, ("\n")); 1771 #endif 1772 1773 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1774 OHCI_SUBREG_ContextControlClear); 1775 1776 if (val & OHCI_CTXCTL_RUN) { 1777 if (fc->fc_branch == NULL) { 1778 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1779 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1780 goto run; 1781 } 1782 *fc->fc_branch = fb->fb_daddr | ndesc; 1783 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1784 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1785 } else { 1786 run: 1787 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1788 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1789 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1790 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1791 } 1792 fc->fc_branch = &fd->fd_branch; 1793 1794 fc->fc_bufcnt++; 1795 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1796 pkt->fp_m = NULL; 1797 return 0; 1798 } 1799 1800 static void 1801 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1802 { 1803 struct fwohci_buf *fb; 1804 struct fwohci_desc *fd; 1805 struct fwohci_pkt pkt; 1806 int i; 1807 1808 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1809 fd = fb->fb_desc; 1810 #ifdef FW_DEBUG 1811 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1812 force ? "force " : "", (long)(fd - sc->sc_desc), 1813 fb->fb_nseg)); 1814 for (i = 0; i < fb->fb_nseg * 4; i++) 1815 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", 1816 ((u_int32_t *)fd)[i])); 1817 DPRINTFN(1, ("\n")); 1818 #endif 1819 if (fb->fb_nseg > 2) 1820 fd += fb->fb_nseg - 1; 1821 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1822 break; 1823 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1824 if (fc->fc_branch == &fd->fd_branch) { 1825 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1826 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1827 fc->fc_branch = NULL; 1828 for (i = 0; i < OHCI_LOOP; i++) { 1829 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1830 OHCI_SUBREG_ContextControlClear) & 1831 OHCI_CTXCTL_ACTIVE)) 1832 break; 1833 } 1834 } 1835 1836 if (fb->fb_statuscb) { 1837 memset(&pkt, 0, sizeof(pkt)); 1838 pkt.fp_status = fd->fd_status; 1839 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1840 1841 /* Indicate this is just returning the status bits. */ 1842 pkt.fp_tcode = -1; 1843 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1844 fb->fb_statuscb = NULL; 1845 fb->fb_statusarg = NULL; 1846 } 1847 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1848 if (fb->fb_nseg > 2) 1849 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1850 fc->fc_bufcnt--; 1851 if (fb->fb_callback) { 1852 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1853 fb->fb_callback = NULL; 1854 } else if (fb->fb_m != NULL) 1855 m_freem(fb->fb_m); 1856 free(fb, M_DEVBUF); 1857 } 1858 } 1859 1860 /* 1861 * Asynchronous Transmit Reponse -- in response of request packet. 1862 */ 1863 static void 1864 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1865 struct fwohci_pkt *res) 1866 { 1867 1868 if (((*req->fp_trail & 0x001f0000) >> 16) != 1869 OHCI_CTXCTL_EVENT_ACK_PENDING) 1870 return; 1871 1872 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1873 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1874 switch (req->fp_tcode) { 1875 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1876 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1877 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1878 res->fp_hlen = 12; 1879 break; 1880 case IEEE1394_TCODE_READ_REQ_QUAD: 1881 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1882 res->fp_hlen = 16; 1883 res->fp_dlen = 0; 1884 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1885 res->fp_hdr[3] = 1886 *(u_int32_t *)res->fp_iov[0].iov_base; 1887 res->fp_uio.uio_iovcnt = 0; 1888 break; 1889 case IEEE1394_TCODE_READ_REQ_BLOCK: 1890 case IEEE1394_TCODE_LOCK_REQ: 1891 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1892 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1893 else 1894 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1895 res->fp_hlen = 16; 1896 res->fp_dlen = res->fp_uio.uio_resid; 1897 res->fp_hdr[3] = res->fp_dlen << 16; 1898 break; 1899 } 1900 res->fp_hdr[0] |= (res->fp_tcode << 4); 1901 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1902 } 1903 1904 /* 1905 * APPLICATION LAYER SERVICES 1906 */ 1907 1908 /* 1909 * Retrieve Global UID from GUID ROM 1910 */ 1911 static int 1912 fwohci_guidrom_init(struct fwohci_softc *sc) 1913 { 1914 int i, n, off; 1915 u_int32_t val1, val2; 1916 1917 /* Extract the Global UID 1918 */ 1919 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1920 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1921 1922 if (val1 != 0 || val2 != 0) { 1923 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1924 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1925 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1926 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1927 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1928 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1929 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1930 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1931 } else { 1932 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1933 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1934 return -1; 1935 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1936 for (i = 0; i < OHCI_LOOP; i++) { 1937 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1938 if (!(val1 & OHCI_Guid_AddrReset)) 1939 break; 1940 } 1941 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1942 val2 = 0; 1943 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1944 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1945 OHCI_Guid_RdStart); 1946 for (i = 0; i < OHCI_LOOP; i++) { 1947 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1948 if (!(val1 & OHCI_Guid_RdStart)) 1949 break; 1950 } 1951 if (n < off) 1952 continue; 1953 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1954 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1955 val2 |= val1; 1956 } 1957 if (val2 == 0) 1958 return -1; 1959 } 1960 return 0; 1961 } 1962 1963 /* 1964 * Initialization for Configuration ROM (no DMA context) 1965 */ 1966 1967 #define CFR_MAXUNIT 20 1968 1969 struct configromctx { 1970 u_int32_t *ptr; 1971 int curunit; 1972 struct { 1973 u_int32_t *start; 1974 int length; 1975 u_int32_t *refer; 1976 int refunit; 1977 } unit[CFR_MAXUNIT]; 1978 }; 1979 1980 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1981 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1982 1983 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1984 1985 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1986 1987 #define CFR_PUT_CRC(cfr, n) \ 1988 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1989 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1990 1991 #define CFR_START_UNIT(cfr, n) \ 1992 do { \ 1993 if ((cfr)->unit[n].refer != NULL) { \ 1994 *(cfr)->unit[n].refer |= \ 1995 (cfr)->ptr - (cfr)->unit[n].refer; \ 1996 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1997 } \ 1998 (cfr)->curunit = (n); \ 1999 (cfr)->unit[n].start = (cfr)->ptr++; \ 2000 } while (0 /* CONSTCOND */) 2001 2002 #define CFR_PUT_REFER(cfr, key, n) \ 2003 do { \ 2004 (cfr)->unit[n].refer = (cfr)->ptr; \ 2005 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2006 *(cfr)->ptr++ = (key) << 24; \ 2007 } while (0 /* CONSTCOND */) 2008 2009 #define CFR_END_UNIT(cfr) \ 2010 do { \ 2011 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2012 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2013 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2014 } while (0 /* CONSTCOND */) 2015 2016 static u_int16_t 2017 fwohci_crc16(u_int32_t *ptr, int len) 2018 { 2019 int shift; 2020 u_int32_t crc, sum, data; 2021 2022 crc = 0; 2023 while (len-- > 0) { 2024 data = *ptr++; 2025 for (shift = 28; shift >= 0; shift -= 4) { 2026 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2027 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2028 } 2029 crc &= 0xffff; 2030 } 2031 return crc; 2032 } 2033 2034 static void 2035 fwohci_configrom_init(struct fwohci_softc *sc) 2036 { 2037 int i, val; 2038 struct fwohci_buf *fb; 2039 u_int32_t *hdr; 2040 struct configromctx cfr; 2041 2042 fb = &sc->sc_buf_cnfrom; 2043 memset(&cfr, 0, sizeof(cfr)); 2044 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2045 2046 /* headers */ 2047 CFR_START_UNIT(&cfr, 0); 2048 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2049 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2050 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2051 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2052 CFR_END_UNIT(&cfr); 2053 /* copy info_length from crc_length */ 2054 *hdr |= (*hdr & 0x00ff0000) << 8; 2055 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2056 2057 /* root directory */ 2058 CFR_START_UNIT(&cfr, 1); 2059 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2060 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2061 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2062 /* spt,64,fix,lst,drq */ 2063 #ifdef INET 2064 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2065 #endif /* INET */ 2066 #ifdef INET6 2067 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2068 #endif /* INET6 */ 2069 CFR_END_UNIT(&cfr); 2070 2071 CFR_START_UNIT(&cfr, 2); 2072 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2073 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2074 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2075 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2076 CFR_END_UNIT(&cfr); 2077 2078 #ifdef INET 2079 /* IPv4 unit directory */ 2080 CFR_START_UNIT(&cfr, 3); 2081 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2082 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2083 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2084 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2085 CFR_END_UNIT(&cfr); 2086 2087 CFR_START_UNIT(&cfr, 6); 2088 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2089 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2090 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2091 CFR_END_UNIT(&cfr); 2092 2093 CFR_START_UNIT(&cfr, 7); 2094 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2095 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2096 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2097 CFR_END_UNIT(&cfr); 2098 #endif /* INET */ 2099 2100 #ifdef INET6 2101 /* IPv6 unit directory */ 2102 CFR_START_UNIT(&cfr, 4); 2103 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2104 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2105 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2106 /* XXX: TBA by IANA */ 2107 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2108 CFR_END_UNIT(&cfr); 2109 2110 CFR_START_UNIT(&cfr, 8); 2111 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2112 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2113 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2114 CFR_END_UNIT(&cfr); 2115 2116 CFR_START_UNIT(&cfr, 9); 2117 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2118 CFR_PUT_DATA1(&cfr, 0); 2119 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2120 CFR_END_UNIT(&cfr); 2121 #endif /* INET6 */ 2122 2123 fb->fb_off = cfr.ptr - hdr; 2124 #ifdef FW_DEBUG 2125 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2126 for (i = 0; i < fb->fb_off; i++) 2127 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2128 DPRINTFN(2, ("\n")); 2129 #endif /* FW_DEBUG */ 2130 2131 /* 2132 * Make network byte order for DMA 2133 */ 2134 for (i = 0; i < fb->fb_off; i++) 2135 HTONL(hdr[i]); 2136 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2137 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2138 2139 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2140 fb->fb_dmamap->dm_segs[0].ds_addr); 2141 2142 /* This register is only valid on OHCI 1.1. */ 2143 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2144 if ((OHCI_Version_GET_Version(val) == 1) && 2145 (OHCI_Version_GET_Revision(val) == 1)) 2146 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2147 OHCI_HCControl_BIBImageValid); 2148 2149 /* Just allow quad reads of the rom. */ 2150 for (i = 0; i < fb->fb_off; i++) 2151 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2152 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2153 fwohci_configrom_input, NULL); 2154 } 2155 2156 static int 2157 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2158 struct fwohci_pkt *pkt) 2159 { 2160 struct fwohci_pkt res; 2161 u_int32_t loc, *rom; 2162 2163 /* This will be used as an array index so size accordingly. */ 2164 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2165 if ((loc & 0x03) != 0) { 2166 /* alignment error */ 2167 return IEEE1394_RCODE_ADDRESS_ERROR; 2168 } 2169 else 2170 loc /= 4; 2171 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2172 2173 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2174 ntohl(rom[loc]))); 2175 2176 memset(&res, 0, sizeof(res)); 2177 res.fp_hdr[3] = rom[loc]; 2178 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2179 return -1; 2180 } 2181 2182 /* 2183 * SelfID buffer (no DMA context) 2184 */ 2185 static void 2186 fwohci_selfid_init(struct fwohci_softc *sc) 2187 { 2188 struct fwohci_buf *fb; 2189 2190 fb = &sc->sc_buf_selfid; 2191 #ifdef DIAGNOSTIC 2192 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2193 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2194 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2195 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2196 #endif 2197 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2198 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2199 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2200 2201 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2202 fb->fb_dmamap->dm_segs[0].ds_addr); 2203 } 2204 2205 static int 2206 fwohci_selfid_input(struct fwohci_softc *sc) 2207 { 2208 int i; 2209 u_int32_t count, val, gen; 2210 u_int32_t *buf; 2211 2212 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2213 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2214 again: 2215 if (val & OHCI_SelfID_Error) { 2216 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2217 return -1; 2218 } 2219 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2220 2221 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2222 0, count << 2, BUS_DMASYNC_POSTREAD); 2223 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2224 2225 #ifdef FW_DEBUG 2226 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2227 val)); 2228 for (i = 0; i < count; i++) 2229 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", buf[i])); 2230 DPRINTFN(1, ("\n")); 2231 #endif /* FW_DEBUG */ 2232 2233 for (i = 1; i < count; i += 2) { 2234 if (buf[i] != ~buf[i + 1]) 2235 break; 2236 if (buf[i] & 0x00000001) 2237 continue; /* more pkt */ 2238 if (buf[i] & 0x00800000) 2239 continue; /* external id */ 2240 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2241 if ((buf[i] & 0x00400800) == 0x00400800) 2242 sc->sc_irmid = sc->sc_rootid; 2243 } 2244 2245 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2246 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2247 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2248 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2249 goto again; 2250 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2251 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2252 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2253 return -1; 2254 } 2255 if (i != count) { 2256 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2257 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2258 #if 1 2259 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2260 /* 2261 * XXX: CXD3222 sometimes fails to DMA 2262 * selfid packet?? 2263 */ 2264 sc->sc_rootid = (count - 1) / 2 - 1; 2265 sc->sc_irmid = sc->sc_rootid; 2266 } else 2267 #endif 2268 return -1; 2269 } 2270 2271 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2272 if ((val & OHCI_NodeId_IDValid) == 0) { 2273 sc->sc_nodeid = 0xffff; /* invalid */ 2274 printf("%s: nodeid is invalid\n", 2275 sc->sc_sc1394.sc1394_dev.dv_xname); 2276 return -1; 2277 } 2278 sc->sc_nodeid = val & 0xffff; 2279 2280 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2281 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2282 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2283 sc->sc_irmid)); 2284 2285 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2286 return -1; 2287 2288 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2289 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2290 OHCI_LinkControl_CycleMaster); 2291 else 2292 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2293 OHCI_LinkControl_CycleMaster); 2294 return 0; 2295 } 2296 2297 /* 2298 * some CSRs are handled by driver. 2299 */ 2300 static void 2301 fwohci_csr_init(struct fwohci_softc *sc) 2302 { 2303 int i; 2304 static u_int32_t csr[] = { 2305 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2306 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2307 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2308 CSR_SB_BROADCAST_CHANNEL 2309 }; 2310 2311 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2312 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2313 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2314 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2315 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2316 } 2317 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2318 } 2319 2320 static int 2321 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2322 { 2323 struct fwohci_pkt res; 2324 u_int32_t reg; 2325 2326 /* 2327 * XXX need to do special functionality other than just r/w... 2328 */ 2329 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2330 2331 if ((reg & 0x03) != 0) { 2332 /* alignment error */ 2333 return IEEE1394_RCODE_ADDRESS_ERROR; 2334 } 2335 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2336 *(u_int32_t *)(&sc->sc_csr[reg]))); 2337 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2338 DPRINTFN(1, (" -> 0x%08x\n", 2339 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2340 *(u_int32_t *)&sc->sc_csr[reg] = 2341 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2342 } else { 2343 DPRINTFN(1, ("\n")); 2344 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2345 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2346 res.fp_iov[0].iov_len = 4; 2347 res.fp_uio.uio_resid = 4; 2348 res.fp_uio.uio_iovcnt = 1; 2349 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2350 return -1; 2351 } 2352 return IEEE1394_RCODE_COMPLETE; 2353 } 2354 2355 /* 2356 * Mapping between nodeid and unique ID (EUI-64). 2357 * 2358 * Track old mappings and simply update their devices with the new id's when 2359 * they match an existing EUI. This allows proper renumeration of the bus. 2360 */ 2361 static void 2362 fwohci_uid_collect(struct fwohci_softc *sc) 2363 { 2364 int i; 2365 struct fwohci_uidtbl *fu; 2366 struct fwohci_pkt pkt; 2367 struct ieee1394_softc *iea; 2368 2369 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2370 iea->sc1394_node_id = 0xffff; 2371 2372 if (sc->sc_uidtbl != NULL) 2373 free(sc->sc_uidtbl, M_DEVBUF); 2374 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2375 M_WAITOK); 2376 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2377 2378 memset(&pkt, 0, sizeof(pkt)); 2379 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2380 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2381 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2382 fu->fu_valid = 3; 2383 2384 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2385 if (iea) { 2386 iea->sc1394_node_id = i; 2387 DPRINTF(("%s: Updating nodeid to %d\n", 2388 iea->sc1394_dev.dv_xname, 2389 iea->sc1394_node_id)); 2390 } 2391 continue; 2392 } 2393 fu->fu_valid = 0; 2394 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2395 pkt.fp_hlen = 12; 2396 pkt.fp_dlen = 0; 2397 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2398 (pkt.fp_tcode << 4); 2399 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2400 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2401 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2402 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2403 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2404 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2405 2406 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2407 (pkt.fp_tcode << 4); 2408 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2409 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2410 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2411 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2412 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2413 2414 } 2415 if (sc->sc_rootid == 0) 2416 fwohci_check_nodes(sc); 2417 } 2418 2419 static int 2420 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2421 { 2422 struct fwohci_uidtbl *fu; 2423 struct ieee1394_softc *iea; 2424 struct ieee1394_attach_args fwa; 2425 int i, n, done, rcode, found; 2426 2427 found = 0; 2428 2429 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2430 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2431 if (rcode != IEEE1394_RCODE_COMPLETE || 2432 sc->sc_uidtbl == NULL || 2433 n > sc->sc_rootid) 2434 return 0; 2435 fu = &sc->sc_uidtbl[n]; 2436 if (arg == 0) { 2437 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2438 fu->fu_valid |= 0x1; 2439 } else { 2440 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2441 fu->fu_valid |= 0x2; 2442 } 2443 #ifdef FW_DEBUG 2444 if (fu->fu_valid == 0x3) 2445 DPRINTFN(1, ("fwohci_uid_input: " 2446 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2447 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2448 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2449 #endif 2450 if (fu->fu_valid == 0x3) { 2451 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2452 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2453 found = 1; 2454 iea->sc1394_node_id = n; 2455 DPRINTF(("%s: Updating nodeid to %d\n", 2456 iea->sc1394_dev.dv_xname, 2457 iea->sc1394_node_id)); 2458 break; 2459 } 2460 if (!found) { 2461 strcpy(fwa.name, "fwnode"); 2462 memcpy(fwa.uid, fu->fu_uid, 8); 2463 fwa.nodeid = n; 2464 fwa.read = fwohci_read; 2465 fwa.write = fwohci_write; 2466 fwa.inreg = fwohci_inreg; 2467 iea = (struct ieee1394_softc *) 2468 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2469 fwohci_print, fwohci_submatch); 2470 if (iea != NULL) 2471 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2472 sc1394_node); 2473 } 2474 } 2475 done = 1; 2476 2477 for (i = 0; i < sc->sc_rootid + 1; i++) { 2478 fu = &sc->sc_uidtbl[i]; 2479 if (fu->fu_valid != 0x3) { 2480 done = 0; 2481 break; 2482 } 2483 } 2484 if (done) 2485 fwohci_check_nodes(sc); 2486 2487 return 0; 2488 } 2489 2490 static void 2491 fwohci_check_nodes(struct fwohci_softc *sc) 2492 { 2493 struct device *detach = NULL; 2494 struct ieee1394_softc *iea; 2495 2496 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2497 2498 /* 2499 * Have to defer detachment until the next 2500 * loop iteration since config_detach 2501 * free's the softc and the loop iterator 2502 * needs data from the softc to move 2503 * forward. 2504 */ 2505 2506 if (detach) { 2507 config_detach(detach, 0); 2508 detach = NULL; 2509 } 2510 if (iea->sc1394_node_id == 0xffff) { 2511 detach = (struct device *)iea; 2512 LIST_REMOVE(iea, sc1394_node); 2513 } 2514 } 2515 if (detach) 2516 config_detach(detach, 0); 2517 } 2518 2519 static int 2520 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2521 { 2522 struct fwohci_uidtbl *fu; 2523 int n; 2524 static const u_int8_t bcast[] = 2525 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2526 2527 fu = sc->sc_uidtbl; 2528 if (fu == NULL) { 2529 notfound: 2530 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2531 return IEEE1394_BCAST_PHY_ID; 2532 fwohci_uid_collect(sc); /* try to get */ 2533 return -1; 2534 } 2535 for (n = 0; ; n++, fu++) { 2536 if (n > sc->sc_rootid) 2537 goto notfound; 2538 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2539 break; 2540 } 2541 return n; 2542 } 2543 2544 /* 2545 * functions to support network interface 2546 */ 2547 static int 2548 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2549 void (*handler)(struct device *, struct mbuf *)) 2550 { 2551 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2552 2553 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2554 fwohci_if_input, handler); 2555 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2556 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2557 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2558 return 0; 2559 } 2560 2561 static int 2562 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2563 { 2564 int n, len; 2565 struct mbuf *m; 2566 struct iovec *iov; 2567 void (*handler)(struct device *, struct mbuf *) = arg; 2568 2569 #ifdef FW_DEBUG 2570 int i; 2571 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2572 pkt->fp_dlen)); 2573 for (i = 0; i < pkt->fp_hlen/4; i++) 2574 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2575 DPRINTFN(2, ("$")); 2576 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2577 iov = &pkt->fp_iov[n]; 2578 for (i = 0; i < iov->iov_len; i++) 2579 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 2580 ((u_int8_t *)iov->iov_base)[i])); 2581 DPRINTFN(2, ("$")); 2582 } 2583 DPRINTFN(1, ("\n")); 2584 #endif /* FW_DEBUG */ 2585 len = pkt->fp_dlen; 2586 MGETHDR(m, M_DONTWAIT, MT_DATA); 2587 if (m == NULL) 2588 return IEEE1394_RCODE_COMPLETE; 2589 m->m_len = 16; 2590 if (len + m->m_len > MHLEN) { 2591 MCLGET(m, M_DONTWAIT); 2592 if ((m->m_flags & M_EXT) == 0) { 2593 m_freem(m); 2594 return IEEE1394_RCODE_COMPLETE; 2595 } 2596 } 2597 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2598 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2599 sc->sc_uidtbl[n].fu_valid != 0x3) { 2600 printf("%s: packet from unknown node: phy id %d\n", 2601 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2602 m_freem(m); 2603 return IEEE1394_RCODE_COMPLETE; 2604 } 2605 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2606 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2607 m->m_flags |= M_BCAST; 2608 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2609 } else { 2610 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2611 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2612 } 2613 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2614 mtod(m, u_int8_t *)[9] = 2615 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2616 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2617 2618 m->m_pkthdr.rcvif = NULL; /* set in child */ 2619 m->m_pkthdr.len = len + m->m_len; 2620 /* 2621 * We may use receive buffer by external mbuf instead of copy here. 2622 * But asynchronous receive buffer must be operate in buffer fill 2623 * mode, so that each receive buffer will shared by multiple mbufs. 2624 * If upper layer doesn't free mbuf soon, e.g. application program 2625 * is suspended, buffer must be reallocated. 2626 * Isochronous buffer must be operate in packet buffer mode, and 2627 * it is easy to map receive buffer to external mbuf. But it is 2628 * used for broadcast/multicast only, and is expected not so 2629 * performance sensitive for now. 2630 * XXX: The performance may be important for multicast case, 2631 * so we should revisit here later. 2632 * -- onoe 2633 */ 2634 n = 0; 2635 iov = pkt->fp_uio.uio_iov; 2636 while (len > 0) { 2637 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2638 iov->iov_len); 2639 m->m_len += iov->iov_len; 2640 len -= iov->iov_len; 2641 iov++; 2642 } 2643 (*handler)(sc->sc_sc1394.sc1394_if, m); 2644 return IEEE1394_RCODE_COMPLETE; 2645 } 2646 2647 static int 2648 fwohci_if_output(struct device *self, struct mbuf *m0, 2649 void (*callback)(struct device *, struct mbuf *)) 2650 { 2651 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2652 struct fwohci_pkt pkt; 2653 u_int8_t *p; 2654 int n, error, spd, hdrlen, maxrec; 2655 #ifdef FW_DEBUG 2656 struct mbuf *m; 2657 #endif 2658 2659 p = mtod(m0, u_int8_t *); 2660 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2661 spd = IEEE1394_SPD_S100; /*XXX*/ 2662 maxrec = 512; /*XXX*/ 2663 hdrlen = 8; 2664 } else { 2665 n = fwohci_uid_lookup(sc, p); 2666 if (n < 0) { 2667 printf("%s: nodeid unknown:" 2668 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2669 sc->sc_sc1394.sc1394_dev.dv_xname, 2670 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2671 error = EHOSTUNREACH; 2672 goto end; 2673 } 2674 if (n == IEEE1394_BCAST_PHY_ID) { 2675 printf("%s: broadcast with !M_MCAST\n", 2676 sc->sc_sc1394.sc1394_dev.dv_xname); 2677 #ifdef FW_DEBUG 2678 DPRINTFN(2, ("packet:")); 2679 for (m = m0; m != NULL; m = m->m_next) { 2680 for (n = 0; n < m->m_len; n++) 2681 DPRINTFN(2, ("%s%02x", (n%32)? 2682 ((n%4)?"":" "):"\n\t", 2683 mtod(m, u_int8_t *)[n])); 2684 DPRINTFN(2, ("$")); 2685 } 2686 DPRINTFN(2, ("\n")); 2687 #endif 2688 error = EHOSTUNREACH; 2689 goto end; 2690 } 2691 maxrec = 2 << p[8]; 2692 spd = p[9]; 2693 hdrlen = 0; 2694 } 2695 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2696 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2697 spd, sc->sc_sc1394.sc1394_link_speed)); 2698 spd = sc->sc_sc1394.sc1394_link_speed; 2699 } 2700 if (maxrec > (512 << spd)) { 2701 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2702 "\n", maxrec, spd)); 2703 maxrec = 512 << spd; 2704 } 2705 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2706 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2707 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2708 maxrec >>= 1; 2709 } 2710 if (maxrec < 512) { 2711 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2712 "minimum\n", maxrec)); 2713 maxrec = 512; 2714 } 2715 2716 m_adj(m0, 16 - hdrlen); 2717 if (m0->m_pkthdr.len > maxrec) { 2718 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2719 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2720 error = E2BIG; /*XXX*/ 2721 goto end; 2722 } 2723 2724 memset(&pkt, 0, sizeof(pkt)); 2725 pkt.fp_uio.uio_iov = pkt.fp_iov; 2726 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2727 pkt.fp_uio.uio_rw = UIO_WRITE; 2728 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2729 /* construct GASP header */ 2730 p = mtod(m0, u_int8_t *); 2731 p[0] = sc->sc_nodeid >> 8; 2732 p[1] = sc->sc_nodeid & 0xff; 2733 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2734 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2735 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2736 pkt.fp_hlen = 8; 2737 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2738 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2739 OHCI_NodeId_NodeNumber) << 8); 2740 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2741 } else { 2742 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2743 pkt.fp_hlen = 16; 2744 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2745 (spd << 16); 2746 pkt.fp_hdr[1] = 2747 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2748 (p[10] << 8) | p[11]; 2749 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2750 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2751 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2752 } 2753 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2754 pkt.fp_dlen = m0->m_pkthdr.len; 2755 pkt.fp_m = m0; 2756 pkt.fp_callback = callback; 2757 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2758 m0 = pkt.fp_m; 2759 end: 2760 if (m0 != NULL) { 2761 if (callback) 2762 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2763 else 2764 m_freem(m0); 2765 } 2766 return error; 2767 } 2768 2769 /* 2770 * High level routines to provide abstraction to attaching layers to 2771 * send/receive data. 2772 */ 2773 2774 static int 2775 fwohci_read(struct ieee1394_abuf *ab) 2776 { 2777 struct fwohci_pkt pkt; 2778 struct ieee1394_softc *sc = ab->ab_req; 2779 struct fwohci_softc *psc = 2780 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2781 u_int32_t high, lo; 2782 int rv, tcode; 2783 2784 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2785 lo = (ab->ab_csr & 0x00000000ffffffff); 2786 2787 memset(&pkt, 0, sizeof(pkt)); 2788 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2789 pkt.fp_hdr[2] = lo; 2790 pkt.fp_dlen = 0; 2791 2792 if (ab->ab_length == 4) { 2793 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2794 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2795 pkt.fp_hlen = 12; 2796 } else { 2797 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2798 pkt.fp_hlen = 16; 2799 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2800 pkt.fp_hdr[3] = (ab->ab_length << 16); 2801 } 2802 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2803 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2804 2805 pkt.fp_statusarg = ab; 2806 pkt.fp_statuscb = fwohci_extract_resp; 2807 2808 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2809 psc->sc_tlabel, fwohci_extract_resp, ab); 2810 if (rv) 2811 return rv; 2812 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2813 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2814 return rv; 2815 } 2816 2817 static int 2818 fwohci_write(struct ieee1394_abuf *ab) 2819 { 2820 struct fwohci_pkt pkt; 2821 struct ieee1394_softc *sc = ab->ab_req; 2822 struct fwohci_softc *psc = 2823 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2824 u_int32_t high, lo; 2825 int rv; 2826 2827 if (ab->ab_length > sc->sc1394_max_receive) { 2828 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2829 return E2BIG; 2830 } 2831 2832 memset(&pkt, 0, sizeof(pkt)); 2833 2834 pkt.fp_tcode = ab->ab_tcode; 2835 pkt.fp_uio.uio_iov = pkt.fp_iov; 2836 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2837 pkt.fp_uio.uio_rw = UIO_WRITE; 2838 2839 switch (ab->ab_tcode) { 2840 case IEEE1394_TCODE_WRITE_RESP: 2841 pkt.fp_hlen = 12; 2842 case IEEE1394_TCODE_READ_RESP_QUAD: 2843 case IEEE1394_TCODE_READ_RESP_BLOCK: 2844 if (!pkt.fp_hlen) 2845 pkt.fp_hlen = 16; 2846 high = ab->ab_retlen; 2847 ab->ab_retlen = 0; 2848 lo = 0; 2849 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2850 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2851 break; 2852 default: 2853 pkt.fp_hlen = 16; 2854 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2855 lo = (ab->ab_csr & 0x00000000ffffffff); 2856 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2857 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2858 break; 2859 } 2860 2861 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2862 pkt.fp_hdr[2] = lo; 2863 if (pkt.fp_hlen == 16) { 2864 if (ab->ab_length == 4) { 2865 pkt.fp_hdr[3] = ab->ab_data[0]; 2866 pkt.fp_dlen = 0; 2867 } else { 2868 pkt.fp_hdr[3] = (ab->ab_length << 16); 2869 pkt.fp_dlen = ab->ab_length; 2870 pkt.fp_uio.uio_iovcnt = 1; 2871 pkt.fp_uio.uio_resid = ab->ab_length; 2872 pkt.fp_iov[0].iov_base = ab->ab_data; 2873 pkt.fp_iov[0].iov_len = ab->ab_length; 2874 } 2875 } 2876 switch (ab->ab_tcode) { 2877 case IEEE1394_TCODE_WRITE_RESP: 2878 case IEEE1394_TCODE_READ_RESP_QUAD: 2879 case IEEE1394_TCODE_READ_RESP_BLOCK: 2880 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2881 break; 2882 default: 2883 rv = fwohci_handler_set(psc, IEEE1394_TCODE_WRITE_RESP, 2884 ab->ab_req->sc1394_node_id, psc->sc_tlabel, 2885 fwohci_extract_resp, ab); 2886 if (rv) 2887 return rv; 2888 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2889 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2890 break; 2891 } 2892 return rv; 2893 } 2894 2895 static int 2896 fwohci_extract_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2897 { 2898 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 2899 struct fwohci_pkt newpkt; 2900 u_int16_t status; 2901 u_int32_t *cur, high, lo; 2902 int i, rcode, rv; 2903 2904 status = 0; 2905 2906 /* 2907 * No callback just means we want to have something clean up the abuf. 2908 */ 2909 2910 if (ab->ab_cb == NULL) { 2911 if (ab->ab_data) 2912 free(ab->ab_data, M_1394DATA); 2913 if (ab) 2914 free(ab, M_1394DATA); 2915 return 0; 2916 } 2917 2918 /* Check for status packet. */ 2919 2920 if (pkt->fp_tcode == -1) { 2921 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2922 pkt->fp_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2923 2924 /* See below for this exception that's trapped internally. */ 2925 if (ab->ab_ackcb && 2926 !((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2927 (pkt->fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK))) { 2928 2929 /* 2930 * XXX: Deal with this better. Trap OHCI code and 2931 * translate/deal with the results. 2932 */ 2933 2934 if (status >= OHCI_CTXCTL_EVENT_RESERVED16) 2935 status = status & 0xf; 2936 else 2937 status = 0; 2938 ab->ab_ackcb(ab, status); 2939 return IEEE1394_RCODE_COMPLETE; 2940 } 2941 if (!((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2942 (pkt->fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK))) 2943 return IEEE1394_RCODE_COMPLETE; 2944 2945 } else 2946 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2947 2948 /* 2949 * Some area's (like the config rom want to be read as quadlets only. 2950 * 2951 * The current ideas to try are: 2952 * 2953 * Got an ACK_TYPE_ERROR on a block read 2954 * 2955 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a read block response 2956 * 2957 * If all cases construct a new packet for a quadlet read and let 2958 * mutli_resp handle the iteration over the space. 2959 */ 2960 2961 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2962 (pkt->fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2963 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2964 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2965 (pkt->fp_tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2966 2967 /* Read the area in quadlet chunks (internally track this). */ 2968 2969 memset(&newpkt, 0, sizeof(newpkt)); 2970 2971 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2972 lo = (ab->ab_csr & 0x00000000ffffffff); 2973 2974 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2975 newpkt.fp_hlen = 12; 2976 newpkt.fp_dlen = 0; 2977 newpkt.fp_hdr[1] = 2978 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2979 newpkt.fp_hdr[2] = lo; 2980 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2981 (newpkt.fp_tcode << 4); 2982 2983 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2984 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2985 fwohci_multi_resp, ab); 2986 if (rv) 2987 return rv; 2988 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2989 if (ab->ab_ackcb) { 2990 newpkt.fp_statusarg = ab; 2991 newpkt.fp_statuscb = fwohci_extract_resp; 2992 } 2993 fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 2994 } else { 2995 2996 /* 2997 * Recombine all the iov data into 1 chunk for higher 2998 * level code. 2999 */ 3000 3001 cur = ab->ab_data; 3002 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3003 /* 3004 * Make sure and don't exceed the buffer 3005 * allocated for return. 3006 */ 3007 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3008 ab->ab_length) { 3009 memcpy(cur, pkt->fp_iov[i].iov_base, 3010 (ab->ab_length - ab->ab_retlen)); 3011 ab->ab_retlen = ab->ab_length; 3012 break; 3013 } 3014 memcpy(cur, pkt->fp_iov[i].iov_base, 3015 pkt->fp_iov[i].iov_len); 3016 cur += pkt->fp_iov[i].iov_len; 3017 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3018 } 3019 (*ab->ab_cb)(ab, rcode); 3020 } 3021 return IEEE1394_RCODE_COMPLETE; 3022 } 3023 3024 static int 3025 fwohci_multi_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3026 { 3027 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3028 struct fwohci_pkt newpkt; 3029 u_int32_t high, lo; 3030 int rcode, rv; 3031 3032 /* 3033 * Bad return codes from the wire, just return what's already in the 3034 * buf. 3035 */ 3036 3037 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3038 3039 if (rcode) { 3040 (*ab->ab_cb)(ab, rcode); 3041 return rcode; 3042 } 3043 3044 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3045 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3046 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3047 ab->ab_retlen = ab->ab_length; 3048 } else { 3049 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3050 pkt->fp_iov[0].iov_base, 4); 3051 ab->ab_retlen += 4; 3052 } 3053 /* Still more, loop and read 4 more bytes. */ 3054 if (ab->ab_retlen < ab->ab_length) { 3055 memset(&newpkt, 0, sizeof(newpkt)); 3056 3057 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3058 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3059 3060 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3061 newpkt.fp_hlen = 12; 3062 newpkt.fp_dlen = 0; 3063 newpkt.fp_hdr[1] = 3064 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3065 newpkt.fp_hdr[2] = lo; 3066 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3067 (newpkt.fp_tcode << 4); 3068 3069 /* 3070 * Bad return code. Just give up and return what's 3071 * come in now. 3072 */ 3073 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3074 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3075 fwohci_multi_resp, ab); 3076 if (rv) { 3077 (*ab->ab_cb)(ab, rcode); 3078 return IEEE1394_RCODE_DATA_ERROR; 3079 } 3080 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3081 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3082 if (rv) { 3083 (*ab->ab_cb)(ab, rcode); 3084 return IEEE1394_RCODE_DATA_ERROR; 3085 } 3086 } else 3087 (*ab->ab_cb)(ab, rcode); 3088 return IEEE1394_RCODE_COMPLETE; 3089 } 3090 3091 static int 3092 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3093 { 3094 struct ieee1394_softc *sc = ab->ab_req; 3095 struct fwohci_softc *psc = 3096 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3097 u_int32_t high, lo; 3098 int i, rv; 3099 3100 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3101 lo = (ab->ab_csr & 0x00000000ffffffff); 3102 3103 switch (ab->ab_tcode) { 3104 case IEEE1394_TCODE_READ_REQ_QUAD: 3105 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3106 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3107 fwohci_parse_input, ab); 3108 break; 3109 case IEEE1394_TCODE_READ_REQ_BLOCK: 3110 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3111 if (allow) { 3112 for (i = 0; i < (ab->ab_length / 4); i++) { 3113 rv = fwohci_handler_set(psc, ab->ab_tcode, 3114 high, lo + (i * 4), 3115 fwohci_parse_input, ab); 3116 if (rv) 3117 return rv; 3118 } 3119 ab->ab_data = (void *)1; 3120 } else 3121 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3122 fwohci_parse_input, ab); 3123 break; 3124 default: 3125 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3126 return -1; 3127 break; 3128 } 3129 return rv; 3130 } 3131 3132 static int 3133 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3134 { 3135 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3136 u_int64_t csr; 3137 u_int32_t *cur; 3138 int i, count; 3139 3140 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3141 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3142 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3143 3144 switch (ab->ab_tcode) { 3145 case IEEE1394_TCODE_READ_REQ_QUAD: 3146 ab->ab_retlen = 4; 3147 break; 3148 case IEEE1394_TCODE_READ_REQ_BLOCK: 3149 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3150 if (ab->ab_data) { 3151 if ((csr + ab->ab_retlen) > 3152 (ab->ab_csr + ab->ab_length)) 3153 return IEEE1394_RCODE_ADDRESS_ERROR; 3154 ab->ab_data = NULL; 3155 } else 3156 if (ab->ab_retlen != ab->ab_length) 3157 return IEEE1394_RCODE_ADDRESS_ERROR; 3158 break; 3159 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3160 ab->ab_retlen = 4; 3161 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3162 if (!ab->ab_retlen) 3163 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3164 if (ab->ab_data) { 3165 if ((csr + ab->ab_retlen) > 3166 (ab->ab_csr + ab->ab_length)) 3167 return IEEE1394_RCODE_ADDRESS_ERROR; 3168 ab->ab_data = NULL; 3169 } else 3170 if (ab->ab_retlen != ab->ab_length) 3171 return IEEE1394_RCODE_ADDRESS_ERROR; 3172 3173 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3174 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3175 ab->ab_data[0] = pkt->fp_hdr[3]; 3176 else { 3177 count = 0; 3178 cur = ab->ab_data; 3179 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3180 memcpy(cur, pkt->fp_iov[i].iov_base, 3181 pkt->fp_iov[i].iov_len); 3182 cur += pkt->fp_iov[i].iov_len; 3183 count += pkt->fp_iov[i].iov_len; 3184 } 3185 if (ab->ab_retlen != count) 3186 panic("Packet claims %d length " 3187 "but only %d bytes returned\n", 3188 ab->ab_retlen, count); 3189 } 3190 break; 3191 default: 3192 panic("Got a callback for a tcode that wasn't requested: %d\n", 3193 ab->ab_tcode); 3194 break; 3195 } 3196 ab->ab_csr = csr; 3197 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3198 return -1; 3199 } 3200 3201 static int 3202 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3203 { 3204 struct ieee1394_attach_args *fwa = aux; 3205 3206 /* Both halves must be filled in for a match. */ 3207 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3208 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3209 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3210 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3211 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3212 return 0; 3213 } 3214
Indexes created Fri Sep 26 20:09:58 GMT 2025