fwohci.c revision 1.31
1 /* $NetBSD: fwohci.c,v 1.31 2001/05/15 06:52:30 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 115 116 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 117 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 119 120 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 121 struct fwohci_pkt *); 122 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 123 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 124 struct fwohci_pkt *); 125 126 static int fwohci_guidrom_init(struct fwohci_softc *); 127 static void fwohci_configrom_init(struct fwohci_softc *); 128 static int fwohci_configrom_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 static void fwohci_selfid_init(struct fwohci_softc *); 131 static int fwohci_selfid_input(struct fwohci_softc *); 132 133 static void fwohci_csr_init(struct fwohci_softc *); 134 static int fwohci_csr_input(struct fwohci_softc *, void *, 135 struct fwohci_pkt *); 136 137 static void fwohci_uid_collect(struct fwohci_softc *); 138 static int fwohci_uid_input(struct fwohci_softc *, void *, 139 struct fwohci_pkt *); 140 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 141 static void fwohci_check_nodes(struct fwohci_softc *); 142 143 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 144 void (*)(struct device *, struct mbuf *)); 145 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 146 static int fwohci_if_output(struct device *, struct mbuf *, 147 void (*)(struct device *, struct mbuf *)); 148 static int fwohci_read(struct ieee1394_abuf *); 149 static int fwohci_write(struct ieee1394_abuf *); 150 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 151 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 152 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_inreg(struct ieee1394_abuf *, int); 155 static int fwohci_parse_input(struct fwohci_softc *, void *, 156 struct fwohci_pkt *); 157 static int fwohci_submatch(struct device *, struct cfdata *, void *); 158 159 #ifdef FW_DEBUG 160 161 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 162 163 #define DPRINTF(x) if (fwdebug) printf x 164 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 165 int fwdebug = 0; 166 #else 167 #define DPRINTF(x) 168 #define DPRINTFN(n,x) 169 #endif 170 171 int 172 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 173 { 174 int i; 175 u_int32_t val; 176 #if 0 177 int error; 178 #endif 179 180 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 181 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 182 183 /* 184 * Wait for reset completion 185 */ 186 for (i = 0; i < OHCI_LOOP; i++) { 187 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 188 if ((val & OHCI_HCControl_SoftReset) == 0) 189 break; 190 } 191 192 /* What dialect of OHCI is this device? 193 */ 194 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 195 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 196 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 197 198 LIST_INIT(&sc->sc_nodelist); 199 200 if (fwohci_guidrom_init(sc) != 0) { 201 printf("\n%s: fatal: no global UID ROM\n", 202 sc->sc_sc1394.sc1394_dev.dv_xname); 203 return -1; 204 } 205 206 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 207 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 208 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 209 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 210 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 211 212 /* Get the maximum link speed and receive size 213 */ 214 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 215 sc->sc_sc1394.sc1394_link_speed = 216 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 217 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 218 printf(", %s", 219 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 220 } else { 221 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 222 } 223 224 /* MaxRec is encoded as log2(max_rec_octets)-1 225 */ 226 sc->sc_sc1394.sc1394_max_receive = 227 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 228 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 229 230 /* 231 * Count how many isochronous ctx we have. 232 */ 233 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 234 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 235 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 236 for (i = 0; val != 0; val >>= 1) { 237 if (val & 0x1) 238 i++; 239 } 240 sc->sc_isoctx = i; 241 printf(", %d iso_ctx", sc->sc_isoctx); 242 243 printf("\n"); 244 245 #if 0 246 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 247 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 248 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 249 return error; 250 #endif 251 252 sc->sc_dying = 0; 253 254 kthread_create(fwohci_create_event_thread, sc); 255 return 0; 256 } 257 258 int 259 fwohci_intr(void *arg) 260 { 261 struct fwohci_softc * const sc = arg; 262 int progress = 0; 263 u_int32_t intmask, iso; 264 265 for (;;) { 266 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 267 268 /* 269 * On a bus reset, everything except bus reset gets 270 * cleared. That can't get cleared until the selfid 271 * phase completes (which happens outside the 272 * interrupt routines). So if just a bus reset is left 273 * in the mask and it's already in the sc_intmask, 274 * just return. 275 */ 276 277 if ((intmask == 0) || 278 (progress && (intmask == OHCI_Int_BusReset) && 279 (sc->sc_intmask & OHCI_Int_BusReset))) { 280 if (progress) 281 wakeup(fwohci_event_thread); 282 return progress; 283 } 284 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 285 intmask & ~OHCI_Int_BusReset); 286 #ifdef FW_DEBUG 287 DPRINTFN(1, ("%s: intmask=0x%08x:", 288 sc->sc_sc1394.sc1394_dev.dv_xname, intmask)); 289 if (intmask & OHCI_Int_CycleTooLong) 290 DPRINTFN(1, (" CycleTooLong")); 291 if (intmask & OHCI_Int_UnrecoverableError) 292 DPRINTFN(1, (" UnrecoverableError")); 293 if (intmask & OHCI_Int_CycleInconsistent) 294 DPRINTFN(1, (" CycleInconsistent")); 295 if (intmask & OHCI_Int_BusReset) 296 DPRINTFN(1, (" BusReset")); 297 if (intmask & OHCI_Int_SelfIDComplete) 298 DPRINTFN(1, (" SelfIDComplete")); 299 if (intmask & OHCI_Int_LockRespErr) 300 DPRINTFN(1, (" LockRespErr")); 301 if (intmask & OHCI_Int_PostedWriteErr) 302 DPRINTFN(1, (" PostedWriteErr")); 303 if (intmask & OHCI_Int_ReqTxComplete) 304 DPRINTFN(1, (" ReqTxComplete(0x%04x)", 305 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 306 OHCI_SUBREG_ContextControlClear))); 307 if (intmask & OHCI_Int_RespTxComplete) 308 DPRINTFN(1, (" RespTxComplete(0x%04x)", 309 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 310 OHCI_SUBREG_ContextControlClear))); 311 if (intmask & OHCI_Int_ARRS) 312 DPRINTFN(1, (" ARRS(0x%04x)", 313 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 314 OHCI_SUBREG_ContextControlClear))); 315 if (intmask & OHCI_Int_ARRQ) 316 DPRINTFN(1, (" ARRQ(0x%04x)", 317 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 318 OHCI_SUBREG_ContextControlClear))); 319 if (intmask & OHCI_Int_IsochRx) 320 DPRINTFN(1, (" IsochRx(0x%08x)", 321 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear))); 322 if (intmask & OHCI_Int_IsochTx) 323 DPRINTFN(1, (" IsochTx(0x%08x)", 324 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear))); 325 if (intmask & OHCI_Int_RQPkt) 326 DPRINTFN(1, (" RQPkt(0x%04x)", 327 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 328 OHCI_SUBREG_ContextControlClear))); 329 if (intmask & OHCI_Int_RSPkt) 330 DPRINTFN(1, (" RSPkt(0x%04x)", 331 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 332 OHCI_SUBREG_ContextControlClear))); 333 DPRINTFN(1, ("\n")); 334 #endif /* FW_DEBUG */ 335 336 if (intmask & OHCI_Int_BusReset) { 337 /* 338 * According to OHCI spec 6.1.1 "busReset", 339 * All asynchronous transmit must be stopped before 340 * clearing BusReset. Moreover, the BusReset 341 * interrupt bit should not be cleared during the 342 * SelfID phase. Thus we turned off interrupt mask 343 * bit of BusReset instead until SelfID completion 344 * or SelfID timeout. 345 */ 346 intmask &= OHCI_Int_SelfIDComplete; 347 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 348 OHCI_Int_BusReset); 349 sc->sc_intmask = intmask; 350 sc->sc_intmask |= OHCI_Int_BusReset; 351 } 352 353 if (intmask & OHCI_Int_SelfIDComplete) 354 sc->sc_intmask |= OHCI_Int_SelfIDComplete; 355 356 if (intmask & OHCI_Int_ReqTxComplete) 357 sc->sc_intmask |= OHCI_Int_ReqTxComplete; 358 if (intmask & OHCI_Int_RespTxComplete) 359 sc->sc_intmask |= OHCI_Int_RespTxComplete; 360 if (intmask & OHCI_Int_RQPkt) 361 sc->sc_intmask |= OHCI_Int_RQPkt; 362 if (intmask & OHCI_Int_RSPkt) 363 sc->sc_intmask |= OHCI_Int_RSPkt; 364 if (intmask & OHCI_Int_IsochTx) { 365 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 366 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 367 sc->sc_intmask |= OHCI_Int_IsochTx; 368 } 369 if (intmask & OHCI_Int_IsochRx) { 370 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 371 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 372 sc->sc_iso |= iso; 373 sc->sc_intmask |= OHCI_Int_IsochRx; 374 } 375 376 if (!progress) { 377 sc->sc_intrcnt.ev_count++; 378 progress = 1; 379 } 380 } 381 } 382 383 static void 384 fwohci_create_event_thread(void *arg) 385 { 386 struct fwohci_softc *sc = arg; 387 388 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 389 sc->sc_sc1394.sc1394_dev.dv_xname)) { 390 printf("%s: unable to create event thread\n", 391 sc->sc_sc1394.sc1394_dev.dv_xname); 392 panic("fwohci_create_event_thread"); 393 } 394 } 395 396 static void 397 fwohci_thread_init(void *arg) 398 { 399 struct fwohci_softc *sc = arg; 400 int i; 401 402 /* 403 * Allocate descriptors 404 */ 405 if (fwohci_desc_alloc(sc)) { 406 printf("%s: not enabling interrupts\n", 407 sc->sc_sc1394.sc1394_dev.dv_xname); 408 kthread_exit(1); 409 } 410 411 /* 412 * Enable Link Power 413 */ 414 415 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 416 417 /* 418 * Allocate DMA Context 419 */ 420 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 421 OHCI_CTX_ASYNC_RX_REQUEST); 422 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 423 OHCI_CTX_ASYNC_RX_RESPONSE); 424 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 425 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 426 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 427 M_DEVBUF, M_WAITOK); 428 for (i = 0; i < sc->sc_isoctx; i++) 429 sc->sc_ctx_ir[i] = NULL; 430 431 /* 432 * Allocate buffer for configuration ROM and SelfID buffer 433 */ 434 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 435 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 436 437 callout_init(&sc->sc_selfid_callout); 438 439 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 440 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 441 442 /* 443 * establish hooks for shutdown and suspend/resume 444 */ 445 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 446 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 447 448 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 449 fwohci_print); 450 451 /* Main loop. It's not coming back normally. */ 452 453 fwohci_event_thread(sc); 454 455 kthread_exit(0); 456 } 457 458 static void 459 fwohci_event_thread(struct fwohci_softc *sc) 460 { 461 int i, s; 462 u_int32_t intmask, iso; 463 464 s = splbio(); 465 466 /* 467 * Initialize hardware registers. 468 */ 469 470 fwohci_hw_init(sc); 471 472 /* Initial Bus Reset */ 473 fwohci_phy_busreset(sc); 474 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 475 splx(s); 476 477 while (!sc->sc_dying) { 478 while (1) { 479 s = splbio(); 480 intmask = sc->sc_intmask; 481 if (intmask) { 482 splx(s); 483 if (intmask & OHCI_Int_BusReset) { 484 s = splbio(); 485 sc->sc_intmask &= ~OHCI_Int_BusReset; 486 splx(s); 487 fwohci_buf_stop(sc); 488 fwohci_buf_init(sc); 489 if (sc->sc_uidtbl != NULL) { 490 free(sc->sc_uidtbl, M_DEVBUF); 491 sc->sc_uidtbl = NULL; 492 } 493 494 callout_reset(&sc->sc_selfid_callout, 495 OHCI_SELFID_TIMEOUT, 496 (void (*)(void *)) 497 fwohci_phy_busreset, sc); 498 sc->sc_nodeid = 0xffff; /* indicate 499 invalid */ 500 sc->sc_rootid = 0; 501 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 502 } 503 if (intmask & OHCI_Int_SelfIDComplete) { 504 s = splbio(); 505 sc->sc_intmask &= 506 ~OHCI_Int_SelfIDComplete; 507 OHCI_CSR_WRITE(sc, 508 OHCI_REG_IntEventClear, 509 OHCI_Int_BusReset); 510 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 511 OHCI_Int_BusReset); 512 splx(s); 513 callout_stop(&sc->sc_selfid_callout); 514 if (fwohci_selfid_input(sc) == 0) { 515 fwohci_buf_start(sc); 516 fwohci_uid_collect(sc); 517 } 518 } 519 if (intmask & OHCI_Int_ReqTxComplete) { 520 s = splbio(); 521 sc->sc_intmask &= 522 ~OHCI_Int_ReqTxComplete; 523 splx(s); 524 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 525 } 526 if (intmask & OHCI_Int_RespTxComplete) { 527 s = splbio(); 528 sc->sc_intmask &= 529 ~OHCI_Int_RespTxComplete; 530 splx(s); 531 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 532 } 533 if (intmask & OHCI_Int_RQPkt) { 534 s = splbio(); 535 sc->sc_intmask &= ~OHCI_Int_RQPkt; 536 splx(s); 537 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 538 } 539 if (intmask & OHCI_Int_RSPkt) { 540 s = splbio(); 541 sc->sc_intmask &= ~OHCI_Int_RSPkt; 542 splx(s); 543 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 544 } 545 if (intmask & OHCI_Int_IsochTx) { 546 s = splbio(); 547 sc->sc_intmask &= ~OHCI_Int_IsochTx; 548 splx(s); 549 } 550 if (intmask & OHCI_Int_IsochRx) { 551 s = splbio(); 552 sc->sc_intmask &= ~OHCI_Int_IsochRx; 553 iso = sc->sc_iso; 554 sc->sc_iso = 0; 555 splx(s); 556 for (i = 0; i < sc->sc_isoctx; i++) { 557 if ((iso & (1 << i)) && 558 sc->sc_ctx_ir[i] != NULL) 559 fwohci_ir_input(sc, 560 sc->sc_ctx_ir[i]); 561 } 562 } 563 } else 564 break; 565 } 566 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 567 splx(s); 568 } 569 } 570 571 #if 0 572 static int 573 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 574 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 575 { 576 bus_dma_segment_t segs[1]; 577 int error, nsegs, steps; 578 579 steps = 0; 580 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 581 segs, 1, &nsegs, flags); 582 if (error) 583 goto cleanup; 584 585 steps = 1; 586 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 587 kvap, flags); 588 if (error) 589 goto cleanup; 590 591 if (error == 0) 592 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 593 size, flags, mapp); 594 if (error) 595 goto cleanup; 596 if (error == 0) 597 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 598 flags); 599 if (error) 600 goto cleanup; 601 602 cleanup: 603 switch (steps) { 604 case 1: 605 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 606 } 607 608 return error; 609 } 610 #endif 611 612 int 613 fwohci_print(void *aux, const char *pnp) 614 { 615 char *name = aux; 616 617 if (pnp) 618 printf("%s at %s", name, pnp); 619 620 return QUIET; 621 } 622 623 static void 624 fwohci_hw_init(struct fwohci_softc *sc) 625 { 626 int i; 627 u_int32_t val; 628 629 /* 630 * Software Reset. 631 */ 632 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 633 for (i = 0; i < OHCI_LOOP; i++) { 634 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 635 if ((val & OHCI_HCControl_SoftReset) == 0) 636 break; 637 } 638 639 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 640 641 /* 642 * First, initilize CSRs with undefined value to default settings. 643 */ 644 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 645 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 646 #if 0 647 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 648 #else 649 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 650 #endif 651 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 652 for (i = 0; i < sc->sc_isoctx; i++) { 653 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 654 ~0); 655 } 656 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 657 658 fwohci_configrom_init(sc); 659 fwohci_selfid_init(sc); 660 fwohci_buf_init(sc); 661 fwohci_csr_init(sc); 662 663 /* 664 * Final CSR settings. 665 */ 666 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 667 OHCI_LinkControl_CycleTimerEnable | 668 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 669 670 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 671 672 /* clear receive filter */ 673 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 674 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 675 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 676 677 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 678 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 679 #if BYTE_ORDER == BIG_ENDIAN 680 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 681 OHCI_HCControl_NoByteSwapData); 682 #endif 683 684 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 685 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 686 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 687 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 688 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 689 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 690 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 691 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 692 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 693 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 694 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 695 696 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 697 698 /* 699 * Start the receivers 700 */ 701 fwohci_buf_start(sc); 702 } 703 704 static void 705 fwohci_power(int why, void *arg) 706 { 707 struct fwohci_softc *sc = arg; 708 int s; 709 710 s = splbio(); 711 switch (why) { 712 case PWR_SUSPEND: 713 case PWR_STANDBY: 714 fwohci_shutdown(sc); 715 break; 716 case PWR_RESUME: 717 fwohci_hw_init(sc); 718 fwohci_phy_busreset(sc); 719 break; 720 case PWR_SOFTSUSPEND: 721 case PWR_SOFTSTANDBY: 722 case PWR_SOFTRESUME: 723 break; 724 } 725 splx(s); 726 } 727 728 static void 729 fwohci_shutdown(void *arg) 730 { 731 struct fwohci_softc *sc = arg; 732 u_int32_t val; 733 734 callout_stop(&sc->sc_selfid_callout); 735 /* disable all interrupt */ 736 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 737 fwohci_buf_stop(sc); 738 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 739 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 740 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 741 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 742 fwohci_phy_busreset(sc); 743 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 744 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 745 } 746 747 /* 748 * COMMON FUNCTIONS 749 */ 750 751 /* 752 * read the PHY Register. 753 */ 754 static u_int8_t 755 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 756 { 757 int i; 758 u_int32_t val; 759 760 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 761 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 762 for (i = 0; i < OHCI_LOOP; i++) { 763 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 764 OHCI_PhyControl_RdDone) 765 break; 766 } 767 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 768 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 769 } 770 771 /* 772 * write the PHY Register. 773 */ 774 static void 775 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 776 { 777 int i; 778 779 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 780 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 781 (val << OHCI_PhyControl_WrData_BITPOS)); 782 for (i = 0; i < OHCI_LOOP; i++) { 783 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 784 OHCI_PhyControl_WrReg)) 785 break; 786 } 787 } 788 789 /* 790 * Initiate Bus Reset 791 */ 792 static void 793 fwohci_phy_busreset(struct fwohci_softc *sc) 794 { 795 int s; 796 u_int8_t val; 797 798 s = splbio(); 799 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 800 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 801 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 802 callout_stop(&sc->sc_selfid_callout); 803 val = fwohci_phy_read(sc, 1); 804 val = (val & 0x80) | /* preserve RHB (force root) */ 805 0x40 | /* Initiate Bus Reset */ 806 0x3f; /* default GAP count */ 807 fwohci_phy_write(sc, 1, val); 808 splx(s); 809 } 810 811 /* 812 * PHY Packet 813 */ 814 static void 815 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 816 { 817 u_int32_t val; 818 u_int8_t key, phyid; 819 820 val = pkt->fp_hdr[1]; 821 if (val != ~pkt->fp_hdr[2]) { 822 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 823 OHCI_CTXCTL_EVENT_BUS_RESET) { 824 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 825 pkt->fp_hdr[2])); 826 } else { 827 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 828 sc->sc_sc1394.sc1394_dev.dv_xname, val, 829 pkt->fp_hdr[2]); 830 } 831 return; 832 } 833 key = (val & 0xc0000000) >> 30; 834 phyid = (val & 0x3f000000) >> 24; 835 switch (key) { 836 case 0: 837 #ifdef FW_DEBUG 838 DPRINTFN(1, ("fwohci_phy_input: PHY Config from %d:", phyid)); 839 if (val & 0x00800000) 840 DPRINTFN(1, (" ForceRoot")); 841 if (val & 0x00400000) 842 DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16)); 843 printf("\n"); 844 #endif 845 break; 846 case 1: 847 DPRINTFN(1, ("fwohci_phy_input: Link-on from %d\n", phyid)); 848 break; 849 case 2: 850 #ifdef FW_DEBUG 851 DPRINTFN(1, ("fwohci_phy_input: SelfID from %d:", phyid)); 852 if (val & 0x00800000) { 853 DPRINTFN(1, (" #%d", (val & 0x00700000) >> 20)); 854 } else { 855 if (val & 0x00400000) 856 DPRINTFN(1, (" LinkActive")); 857 DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16)); 858 DPRINTFN(1, (" Spd=S%d", 859 100 << ((val & 0x0000c000) >> 14))); 860 if (val & 0x00000800) 861 DPRINTFN(1, (" Cont")); 862 if (val & 0x00000002) 863 DPRINTFN(1, (" InitiateBusReset")); 864 } 865 if (val & 0x00000001) 866 DPRINTFN(1, (" +")); 867 DPRINTFN(1, ("\n")); 868 #endif 869 break; 870 default: 871 printf("%s: unknown PHY packet: 0x%08x\n", 872 sc->sc_sc1394.sc1394_dev.dv_xname, val); 873 break; 874 } 875 } 876 877 /* 878 * Descriptor for context DMA. 879 */ 880 static int 881 fwohci_desc_alloc(struct fwohci_softc *sc) 882 { 883 int error, mapsize, dsize; 884 885 /* 886 * allocate descriptor buffer 887 */ 888 889 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 890 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 891 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 892 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 893 mapsize = howmany(sc->sc_descsize, NBBY); 894 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 895 memset(sc->sc_descmap, 0, mapsize); 896 897 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 898 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 899 printf("%s: unable to allocate descriptor buffer, error = %d\n", 900 sc->sc_sc1394.sc1394_dev.dv_xname, error); 901 goto fail_0; 902 } 903 904 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 905 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 906 != 0) { 907 printf("%s: unable to map descriptor buffer, error = %d\n", 908 sc->sc_sc1394.sc1394_dev.dv_xname, error); 909 goto fail_1; 910 } 911 912 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 913 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 914 printf("%s: unable to create descriptor buffer DMA map, " 915 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 916 goto fail_2; 917 } 918 919 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 920 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 921 printf("%s: unable to load descriptor buffer DMA map, " 922 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 923 goto fail_3; 924 } 925 926 return 0; 927 928 fail_3: 929 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 930 fail_2: 931 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 932 fail_1: 933 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 934 fail_0: 935 return error; 936 } 937 938 static struct fwohci_desc * 939 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 940 { 941 int i, n; 942 943 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 944 for (i = 0; ; i++) { 945 if (i == ndesc) { 946 for (i = 0; i < ndesc; i++) 947 setbit(sc->sc_descmap, n + i); 948 return sc->sc_desc + n; 949 } 950 if (isset(sc->sc_descmap, n + i)) 951 break; 952 } 953 } 954 return NULL; 955 } 956 957 static void 958 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 959 { 960 int i, n; 961 962 n = fd - sc->sc_desc; 963 for (i = 0; i < ndesc; i++, n++) { 964 #ifdef DIAGNOSTIC 965 if (isclr(sc->sc_descmap, n)) 966 panic("fwohci_desc_put: duplicated free"); 967 #endif 968 clrbit(sc->sc_descmap, n); 969 } 970 } 971 972 /* 973 * Asyncronous/Isochronous Transmit/Receive Context 974 */ 975 static int 976 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 977 int bufcnt, int ctx) 978 { 979 int i, error; 980 struct fwohci_ctx *fc; 981 struct fwohci_buf *fb; 982 struct fwohci_desc *fd; 983 984 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 985 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 986 LIST_INIT(&fc->fc_handler); 987 TAILQ_INIT(&fc->fc_buf); 988 fc->fc_ctx = ctx; 989 fc->fc_bufcnt = bufcnt; 990 fb = (struct fwohci_buf *)&fc[1]; 991 for (i = 0; i < bufcnt; i++, fb++) { 992 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 993 goto fail; 994 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 995 error = ENOBUFS; 996 goto fail; 997 } 998 fb->fb_desc = fd; 999 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1000 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1001 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1002 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1003 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1004 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1005 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1006 } 1007 *fcp = fc; 1008 return 0; 1009 1010 fail: 1011 while (i-- > 0) 1012 fwohci_buf_free(sc, --fb); 1013 free(fc, M_DEVBUF); 1014 return error; 1015 } 1016 1017 static void 1018 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1019 { 1020 struct fwohci_buf *fb; 1021 struct fwohci_handler *fh; 1022 1023 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1024 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1025 NULL, NULL); 1026 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1027 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1028 fwohci_buf_free(sc, fb); 1029 } 1030 free(fc, M_DEVBUF); 1031 } 1032 1033 static void 1034 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1035 { 1036 struct fwohci_buf *fb, *nfb; 1037 struct fwohci_desc *fd; 1038 struct fwohci_handler *fh; 1039 int n; 1040 1041 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1042 nfb = TAILQ_NEXT(fb, fb_list); 1043 fb->fb_off = 0; 1044 fd = fb->fb_desc; 1045 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1046 fd->fd_rescount = fd->fd_reqcount; 1047 } 1048 1049 n = fc->fc_ctx; 1050 fb = TAILQ_FIRST(&fc->fc_buf); 1051 if (fc->fc_isoch) { 1052 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1053 fb->fb_daddr | 1); 1054 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1055 OHCI_CTXCTL_RX_BUFFER_FILL | 1056 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1057 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1058 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1059 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1060 OHCI_CTXCTL_RX_ISOCH_HEADER); 1061 fh = LIST_FIRST(&fc->fc_handler); 1062 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1063 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1064 } else { 1065 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1066 fb->fb_daddr | 1); 1067 } 1068 } 1069 1070 /* 1071 * DMA data buffer 1072 */ 1073 static int 1074 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1075 { 1076 int error; 1077 1078 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1079 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1080 printf("%s: unable to allocate buffer, error = %d\n", 1081 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1082 goto fail_0; 1083 } 1084 1085 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1086 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1087 printf("%s: unable to map buffer, error = %d\n", 1088 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1089 goto fail_1; 1090 } 1091 1092 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1093 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1094 printf("%s: unable to create buffer DMA map, " 1095 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1096 error); 1097 goto fail_2; 1098 } 1099 1100 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1101 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1102 printf("%s: unable to load buffer DMA map, " 1103 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1104 error); 1105 goto fail_3; 1106 } 1107 1108 return 0; 1109 1110 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1111 fail_3: 1112 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1113 fail_2: 1114 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1115 fail_1: 1116 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1117 fail_0: 1118 return error; 1119 } 1120 1121 static void 1122 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1123 { 1124 1125 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1126 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1127 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1128 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1129 } 1130 1131 static void 1132 fwohci_buf_init(struct fwohci_softc *sc) 1133 { 1134 int i; 1135 1136 /* 1137 * Initialize for Asynchronous Transmit Queue. 1138 */ 1139 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1140 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1141 1142 /* 1143 * Initialize for Asynchronous Receive Queue. 1144 */ 1145 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1146 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1147 1148 /* 1149 * Initialize for Isochronous Receive Queue. 1150 */ 1151 for (i = 0; i < sc->sc_isoctx; i++) { 1152 if (sc->sc_ctx_ir[i] != NULL) 1153 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1154 } 1155 } 1156 1157 static void 1158 fwohci_buf_start(struct fwohci_softc *sc) 1159 { 1160 int i; 1161 1162 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1163 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1164 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1165 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1166 for (i = 0; i < sc->sc_isoctx; i++) { 1167 if (sc->sc_ctx_ir[i] != NULL && 1168 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1169 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1170 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1171 } 1172 } 1173 } 1174 1175 static void 1176 fwohci_buf_stop(struct fwohci_softc *sc) 1177 { 1178 int i, j; 1179 1180 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1181 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1182 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1183 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1184 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1185 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1186 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1187 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1188 for (i = 0; i < sc->sc_isoctx; i++) { 1189 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1190 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1191 } 1192 1193 /* 1194 * Make sure the transmitter is stopped. 1195 */ 1196 for (j = 0; j < OHCI_LOOP; j++) { 1197 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1198 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1199 continue; 1200 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1201 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1202 continue; 1203 break; 1204 } 1205 } 1206 1207 static void 1208 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1209 { 1210 struct fwohci_buf *fb, *tfb; 1211 1212 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1213 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1214 fb->fb_desc->fd_rescount != 0) 1215 break; 1216 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1217 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1218 fb->fb_off = 0; 1219 fb->fb_desc->fd_branch = 0; 1220 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1221 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1222 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1223 } 1224 } 1225 1226 static int 1227 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1228 int len) 1229 { 1230 struct fwohci_buf *fb; 1231 struct fwohci_desc *fd; 1232 int bufend; 1233 1234 fb = TAILQ_FIRST(&fc->fc_buf); 1235 again: 1236 fd = fb->fb_desc; 1237 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1238 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1239 fd->fd_reqcount, fd->fd_rescount, len, 1240 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1241 bufend = fd->fd_reqcount - fd->fd_rescount; 1242 if (fb->fb_off >= bufend) { 1243 if (fc->fc_isoch && fb->fb_off > 0) { 1244 fb->fb_off = fd->fd_reqcount; 1245 fd->fd_rescount = 0; 1246 } 1247 if (fd->fd_rescount == 0) { 1248 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1249 goto again; 1250 } 1251 return 0; 1252 } 1253 if (fb->fb_off + len > bufend) 1254 len = bufend - fb->fb_off; 1255 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1256 BUS_DMASYNC_POSTREAD); 1257 *pp = fb->fb_buf + fb->fb_off; 1258 fb->fb_off += roundup(len, 4); 1259 return len; 1260 } 1261 1262 static int 1263 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1264 struct fwohci_pkt *pkt) 1265 { 1266 caddr_t p; 1267 int len, count, i; 1268 1269 memset(pkt, 0, sizeof(*pkt)); 1270 pkt->fp_uio.uio_iov = pkt->fp_iov; 1271 pkt->fp_uio.uio_rw = UIO_WRITE; 1272 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1273 1274 /* get first quadlet */ 1275 count = 4; 1276 if (fc->fc_isoch) { 1277 /* 1278 * get trailer first, may be bogus data unless status update 1279 * in descriptor is set. 1280 */ 1281 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1282 sizeof(*pkt->fp_trail)); 1283 if (len <= 0) { 1284 DPRINTFN(1, ("fwohci_buf_input: no input for is#%d\n", 1285 fc->fc_ctx)); 1286 return 0; 1287 } 1288 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1289 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1290 } 1291 len = fwohci_buf_pktget(sc, fc, &p, count); 1292 if (len <= 0) { 1293 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1294 fc->fc_ctx)); 1295 return 0; 1296 } 1297 pkt->fp_hdr[0] = *(u_int32_t *)p; 1298 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1299 switch (pkt->fp_tcode) { 1300 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1301 case IEEE1394_TCODE_READ_RESP_QUAD: 1302 pkt->fp_hlen = 12; 1303 pkt->fp_dlen = 4; 1304 break; 1305 case IEEE1394_TCODE_READ_REQ_BLOCK: 1306 pkt->fp_hlen = 16; 1307 pkt->fp_dlen = 0; 1308 break; 1309 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1310 case IEEE1394_TCODE_READ_RESP_BLOCK: 1311 case IEEE1394_TCODE_LOCK_REQ: 1312 case IEEE1394_TCODE_LOCK_RESP: 1313 pkt->fp_hlen = 16; 1314 break; 1315 case IEEE1394_TCODE_STREAM_DATA: 1316 pkt->fp_hlen = 4; 1317 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1318 break; 1319 default: 1320 pkt->fp_hlen = 12; 1321 pkt->fp_dlen = 0; 1322 break; 1323 } 1324 1325 /* get header */ 1326 while (count < pkt->fp_hlen) { 1327 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1328 if (len == 0) { 1329 printf("fwohci_buf_input: malformed input 1: %d\n", 1330 pkt->fp_hlen - count); 1331 return 0; 1332 } 1333 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1334 count += len; 1335 } 1336 if ((pkt->fp_hlen == 16) && 1337 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1338 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1339 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1340 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1341 1342 /* get data */ 1343 count = 0; 1344 i = 0; 1345 while (count < pkt->fp_dlen) { 1346 len = fwohci_buf_pktget(sc, fc, 1347 (caddr_t *)&pkt->fp_iov[i].iov_base, 1348 pkt->fp_dlen - count); 1349 if (len == 0) { 1350 printf("fwohci_buf_input: malformed input 2: %d\n", 1351 pkt->fp_hlen - count); 1352 return 0; 1353 } 1354 pkt->fp_iov[i++].iov_len = len; 1355 count += len; 1356 } 1357 pkt->fp_uio.uio_iovcnt = i; 1358 pkt->fp_uio.uio_resid = count; 1359 1360 if (!fc->fc_isoch) { 1361 /* get trailer */ 1362 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1363 sizeof(*pkt->fp_trail)); 1364 if (len <= 0) { 1365 printf("fwohci_buf_input: malformed input 3: %d\n", 1366 pkt->fp_hlen - count); 1367 return 0; 1368 } 1369 } 1370 return 1; 1371 } 1372 1373 static int 1374 fwohci_handler_set(struct fwohci_softc *sc, 1375 int tcode, u_int32_t key1, u_int32_t key2, 1376 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1377 void *arg) 1378 { 1379 struct fwohci_ctx *fc; 1380 struct fwohci_handler *fh; 1381 int i, j; 1382 1383 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1384 j = sc->sc_isoctx; 1385 fh = NULL; 1386 for (i = 0; i < sc->sc_isoctx; i++) { 1387 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1388 if (j == sc->sc_isoctx) 1389 j = i; 1390 continue; 1391 } 1392 fh = LIST_FIRST(&fc->fc_handler); 1393 if (fh == NULL) { 1394 j = i; 1395 break; 1396 } 1397 if (fh->fh_tcode == tcode && 1398 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1399 break; 1400 fh = NULL; 1401 } 1402 if (fh == NULL) { 1403 if (handler == NULL) 1404 return 0; 1405 if (j == sc->sc_isoctx) { 1406 DPRINTF(("fwohci_handler_set: no more free " 1407 "context\n")); 1408 return ENOMEM; 1409 } 1410 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1411 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1412 fc->fc_isoch = 1; 1413 sc->sc_ctx_ir[j] = fc; 1414 } 1415 } 1416 } else { 1417 switch (tcode) { 1418 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1419 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1420 case IEEE1394_TCODE_READ_REQ_QUAD: 1421 case IEEE1394_TCODE_READ_REQ_BLOCK: 1422 case IEEE1394_TCODE_LOCK_REQ: 1423 fc = sc->sc_ctx_arrq; 1424 break; 1425 case IEEE1394_TCODE_WRITE_RESP: 1426 case IEEE1394_TCODE_READ_RESP_QUAD: 1427 case IEEE1394_TCODE_READ_RESP_BLOCK: 1428 case IEEE1394_TCODE_LOCK_RESP: 1429 fc = sc->sc_ctx_arrs; 1430 break; 1431 default: 1432 return EIO; 1433 } 1434 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1435 fh = LIST_NEXT(fh, fh_list)) { 1436 if (fh->fh_tcode == tcode && 1437 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1438 break; 1439 } 1440 } 1441 if (handler == NULL) { 1442 if (fh != NULL) { 1443 LIST_REMOVE(fh, fh_list); 1444 free(fh, M_DEVBUF); 1445 } 1446 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1447 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1448 fwohci_ctx_free(sc, fc); 1449 } 1450 return 0; 1451 } 1452 if (fh == NULL) { 1453 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1454 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1455 } 1456 fh->fh_tcode = tcode; 1457 fh->fh_key1 = key1; 1458 fh->fh_key2 = key2; 1459 fh->fh_handler = handler; 1460 fh->fh_handarg = arg; 1461 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1462 fc->fc_ctx, tcode, key1, key2)); 1463 1464 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1465 fwohci_ctx_init(sc, fc); 1466 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1467 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1468 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1469 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1470 } 1471 return 0; 1472 } 1473 1474 /* 1475 * Asyncronous Receive Requests input frontend. 1476 */ 1477 static void 1478 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1479 { 1480 int rcode; 1481 u_int32_t key1, key2; 1482 struct fwohci_handler *fh; 1483 struct fwohci_pkt pkt, res; 1484 1485 while (fwohci_buf_input(sc, fc, &pkt)) { 1486 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1487 fwohci_phy_input(sc, &pkt); 1488 return; 1489 } 1490 key1 = pkt.fp_hdr[1] & 0xffff; 1491 key2 = pkt.fp_hdr[2]; 1492 memset(&res, 0, sizeof(res)); 1493 res.fp_uio.uio_rw = UIO_WRITE; 1494 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1495 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1496 fh = LIST_NEXT(fh, fh_list)) { 1497 if (pkt.fp_tcode == fh->fh_tcode && 1498 key1 == fh->fh_key1 && 1499 key2 == fh->fh_key2) { 1500 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1501 &pkt); 1502 break; 1503 } 1504 } 1505 if (fh == NULL) { 1506 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1507 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1508 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1509 key2)); 1510 } 1511 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1512 OHCI_CTXCTL_EVENT_ACK_PENDING) 1513 return; 1514 if (rcode != -1) 1515 fwohci_atrs_output(sc, rcode, &pkt, &res); 1516 } 1517 fwohci_buf_next(sc, fc); 1518 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1519 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1520 } 1521 1522 1523 /* 1524 * Asynchronous Receive Response input frontend. 1525 */ 1526 static void 1527 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1528 { 1529 struct fwohci_pkt pkt; 1530 struct fwohci_handler *fh; 1531 u_int16_t srcid; 1532 int rcode, tlabel; 1533 1534 while (fwohci_buf_input(sc, fc, &pkt)) { 1535 srcid = pkt.fp_hdr[1] >> 16; 1536 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1537 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1538 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1539 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1540 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1541 pkt.fp_dlen)); 1542 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1543 fh = LIST_NEXT(fh, fh_list)) { 1544 if (pkt.fp_tcode == fh->fh_tcode && 1545 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1546 tlabel == fh->fh_key2) { 1547 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1548 LIST_REMOVE(fh, fh_list); 1549 free(fh, M_DEVBUF); 1550 break; 1551 } 1552 } 1553 if (fh == NULL) 1554 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1555 } 1556 fwohci_buf_next(sc, fc); 1557 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1558 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1559 } 1560 1561 /* 1562 * Isochronous Receive input frontend. 1563 */ 1564 static void 1565 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1566 { 1567 int rcode, chan, tag; 1568 struct iovec *iov; 1569 struct fwohci_handler *fh; 1570 struct fwohci_pkt pkt; 1571 1572 while (fwohci_buf_input(sc, fc, &pkt)) { 1573 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1574 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1575 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1576 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1577 pkt.fp_dlen)); 1578 if (tag == IEEE1394_TAG_GASP) { 1579 /* 1580 * The pkt with tag=3 is GASP format. 1581 * Move GASP header to header part. 1582 */ 1583 if (pkt.fp_dlen < 8) 1584 continue; 1585 iov = pkt.fp_iov; 1586 /* assuming pkt per buffer mode */ 1587 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1588 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1589 iov->iov_base = (caddr_t)iov->iov_base + 8; 1590 iov->iov_len -= 8; 1591 pkt.fp_hlen += 8; 1592 pkt.fp_dlen -= 8; 1593 } 1594 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1595 fh = LIST_NEXT(fh, fh_list)) { 1596 if (pkt.fp_tcode == fh->fh_tcode && 1597 chan == fh->fh_key1 && tag == fh->fh_key2) { 1598 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1599 &pkt); 1600 break; 1601 } 1602 } 1603 #ifdef FW_DEBUG 1604 if (fh == NULL) { 1605 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1606 } else { 1607 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1608 } 1609 #endif 1610 } 1611 fwohci_buf_next(sc, fc); 1612 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1613 OHCI_CTXCTL_WAKE); 1614 } 1615 1616 /* 1617 * Asynchronous Transmit common routine. 1618 */ 1619 static int 1620 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1621 struct fwohci_pkt *pkt) 1622 { 1623 struct fwohci_buf *fb; 1624 struct fwohci_desc *fd; 1625 struct mbuf *m, *m0; 1626 int i, ndesc, error, off, len; 1627 u_int32_t val; 1628 #ifdef FW_DEBUG 1629 struct iovec *iov; 1630 #endif 1631 1632 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1633 /* We can't send anything during selfid duration */ 1634 return EAGAIN; 1635 1636 #ifdef FW_DEBUG 1637 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1638 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1639 for (i = 0; i < pkt->fp_hlen/4; i++) 1640 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 1641 DPRINTFN(2, ("$")); 1642 for (ndesc = 0, iov = pkt->fp_iov; 1643 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1644 for (i = 0; i < iov->iov_len; i++) 1645 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1646 ((u_int8_t *)iov->iov_base)[i])); 1647 DPRINTFN(2, ("$")); 1648 } 1649 DPRINTFN(1, ("\n")); 1650 #endif 1651 1652 if ((m = pkt->fp_m) != NULL) { 1653 for (ndesc = 2; m != NULL; m = m->m_next) 1654 ndesc++; 1655 if (ndesc > OHCI_DESC_MAX) { 1656 m0 = NULL; 1657 ndesc = 2; 1658 for (off = 0; off < pkt->fp_dlen; off += len) { 1659 if (m0 == NULL) { 1660 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1661 if (m0 != NULL) 1662 M_COPY_PKTHDR(m0, pkt->fp_m); 1663 m = m0; 1664 } else { 1665 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1666 m = m->m_next; 1667 } 1668 if (m != NULL) 1669 MCLGET(m, M_DONTWAIT); 1670 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1671 m_freem(m0); 1672 return ENOMEM; 1673 } 1674 len = pkt->fp_dlen - off; 1675 if (len > m->m_ext.ext_size) 1676 len = m->m_ext.ext_size; 1677 m_copydata(pkt->fp_m, off, len, 1678 mtod(m, caddr_t)); 1679 m->m_len = len; 1680 ndesc++; 1681 } 1682 m_freem(pkt->fp_m); 1683 pkt->fp_m = m0; 1684 } 1685 } else 1686 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1687 1688 if (ndesc > OHCI_DESC_MAX) 1689 return ENOBUFS; 1690 1691 if (fc->fc_bufcnt > 50) /*XXX*/ 1692 return ENOBUFS; 1693 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1694 fb->fb_nseg = ndesc; 1695 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1696 if (fb->fb_desc == NULL) { 1697 free(fb, M_DEVBUF); 1698 return ENOBUFS; 1699 } 1700 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1701 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1702 fb->fb_m = pkt->fp_m; 1703 fb->fb_callback = pkt->fp_callback; 1704 fb->fb_statuscb = pkt->fp_statuscb; 1705 fb->fb_statusarg = pkt->fp_statusarg; 1706 1707 if (ndesc > 2) { 1708 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1709 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1710 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1711 free(fb, M_DEVBUF); 1712 return error; 1713 } 1714 1715 if (pkt->fp_m != NULL) 1716 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1717 pkt->fp_m, BUS_DMA_WAITOK); 1718 else 1719 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1720 &pkt->fp_uio, BUS_DMA_WAITOK); 1721 if (error != 0) { 1722 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1723 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1724 free(fb, M_DEVBUF); 1725 return error; 1726 } 1727 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1728 BUS_DMASYNC_PREWRITE); 1729 } 1730 1731 fd = fb->fb_desc; 1732 fd->fd_flags = OHCI_DESC_IMMED; 1733 fd->fd_reqcount = pkt->fp_hlen; 1734 fd->fd_data = 0; 1735 fd->fd_branch = 0; 1736 fd->fd_status = 0; 1737 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1738 i = 3; /* XXX: 3 sec */ 1739 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1740 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1741 ((((val >> 25) + i) & 0x7) << 13); 1742 } else 1743 fd->fd_timestamp = 0; 1744 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1745 for (i = 0; i < ndesc - 2; i++) { 1746 fd = fb->fb_desc + 2 + i; 1747 fd->fd_flags = 0; 1748 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1749 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1750 fd->fd_branch = 0; 1751 fd->fd_status = 0; 1752 fd->fd_timestamp = 0; 1753 } 1754 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1755 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1756 1757 #ifdef FW_DEBUG 1758 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1759 (long)(fb->fb_desc - sc->sc_desc))); 1760 for (i = 0; i < ndesc * 4; i++) 1761 DPRINTFN(1, ("%s%08x", i&7?" ":"\n\t", 1762 ((u_int32_t *)fb->fb_desc)[i])); 1763 DPRINTFN(1, ("\n")); 1764 #endif 1765 1766 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1767 OHCI_SUBREG_ContextControlClear); 1768 1769 if (val & OHCI_CTXCTL_RUN) { 1770 if (fc->fc_branch == NULL) { 1771 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1772 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1773 goto run; 1774 } 1775 *fc->fc_branch = fb->fb_daddr | ndesc; 1776 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1777 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1778 } else { 1779 run: 1780 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1781 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1782 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1783 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1784 } 1785 fc->fc_branch = &fd->fd_branch; 1786 1787 fc->fc_bufcnt++; 1788 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1789 pkt->fp_m = NULL; 1790 return 0; 1791 } 1792 1793 static void 1794 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1795 { 1796 struct fwohci_buf *fb; 1797 struct fwohci_desc *fd; 1798 struct fwohci_pkt pkt; 1799 int i; 1800 1801 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1802 fd = fb->fb_desc; 1803 #ifdef FW_DEBUG 1804 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1805 force ? "force " : "", (long)(fd - sc->sc_desc), 1806 fb->fb_nseg)); 1807 for (i = 0; i < fb->fb_nseg * 4; i++) 1808 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", 1809 ((u_int32_t *)fd)[i])); 1810 DPRINTFN(1, ("\n")); 1811 #endif 1812 if (fb->fb_nseg > 2) 1813 fd += fb->fb_nseg - 1; 1814 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1815 break; 1816 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1817 if (fc->fc_branch == &fd->fd_branch) { 1818 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1819 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1820 fc->fc_branch = NULL; 1821 for (i = 0; i < OHCI_LOOP; i++) { 1822 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1823 OHCI_SUBREG_ContextControlClear) & 1824 OHCI_CTXCTL_ACTIVE)) 1825 break; 1826 } 1827 } 1828 1829 if (fb->fb_statuscb) { 1830 memset(&pkt, 0, sizeof(pkt)); 1831 pkt.fp_status = fd->fd_status; 1832 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1833 1834 /* Indicate this is just returning the status bits. */ 1835 pkt.fp_tcode = -1; 1836 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1837 fb->fb_statuscb = NULL; 1838 fb->fb_statusarg = NULL; 1839 } 1840 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1841 if (fb->fb_nseg > 2) 1842 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1843 fc->fc_bufcnt--; 1844 if (fb->fb_callback) { 1845 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1846 fb->fb_callback = NULL; 1847 } else if (fb->fb_m != NULL) 1848 m_freem(fb->fb_m); 1849 free(fb, M_DEVBUF); 1850 } 1851 } 1852 1853 /* 1854 * Asynchronous Transmit Reponse -- in response of request packet. 1855 */ 1856 static void 1857 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1858 struct fwohci_pkt *res) 1859 { 1860 1861 if (((*req->fp_trail & 0x001f0000) >> 16) != 1862 OHCI_CTXCTL_EVENT_ACK_PENDING) 1863 return; 1864 1865 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1866 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1867 switch (req->fp_tcode) { 1868 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1869 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1870 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1871 res->fp_hlen = 12; 1872 break; 1873 case IEEE1394_TCODE_READ_REQ_QUAD: 1874 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1875 res->fp_hlen = 16; 1876 res->fp_dlen = 0; 1877 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1878 res->fp_hdr[3] = 1879 *(u_int32_t *)res->fp_iov[0].iov_base; 1880 res->fp_uio.uio_iovcnt = 0; 1881 break; 1882 case IEEE1394_TCODE_READ_REQ_BLOCK: 1883 case IEEE1394_TCODE_LOCK_REQ: 1884 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1885 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1886 else 1887 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1888 res->fp_hlen = 16; 1889 res->fp_dlen = res->fp_uio.uio_resid; 1890 res->fp_hdr[3] = res->fp_dlen << 16; 1891 break; 1892 } 1893 res->fp_hdr[0] |= (res->fp_tcode << 4); 1894 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1895 } 1896 1897 /* 1898 * APPLICATION LAYER SERVICES 1899 */ 1900 1901 /* 1902 * Retrieve Global UID from GUID ROM 1903 */ 1904 static int 1905 fwohci_guidrom_init(struct fwohci_softc *sc) 1906 { 1907 int i, n, off; 1908 u_int32_t val1, val2; 1909 1910 /* Extract the Global UID 1911 */ 1912 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1913 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1914 1915 if (val1 != 0 || val2 != 0) { 1916 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1917 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1918 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1919 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1920 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1921 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1922 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1923 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1924 } else { 1925 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1926 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1927 return -1; 1928 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1929 for (i = 0; i < OHCI_LOOP; i++) { 1930 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1931 if (!(val1 & OHCI_Guid_AddrReset)) 1932 break; 1933 } 1934 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1935 val2 = 0; 1936 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1937 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1938 OHCI_Guid_RdStart); 1939 for (i = 0; i < OHCI_LOOP; i++) { 1940 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1941 if (!(val1 & OHCI_Guid_RdStart)) 1942 break; 1943 } 1944 if (n < off) 1945 continue; 1946 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1947 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1948 val2 |= val1; 1949 } 1950 if (val2 == 0) 1951 return -1; 1952 } 1953 return 0; 1954 } 1955 1956 /* 1957 * Initialization for Configuration ROM (no DMA context) 1958 */ 1959 1960 #define CFR_MAXUNIT 20 1961 1962 struct configromctx { 1963 u_int32_t *ptr; 1964 int curunit; 1965 struct { 1966 u_int32_t *start; 1967 int length; 1968 u_int32_t *refer; 1969 int refunit; 1970 } unit[CFR_MAXUNIT]; 1971 }; 1972 1973 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1974 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1975 1976 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1977 1978 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1979 1980 #define CFR_PUT_CRC(cfr, n) \ 1981 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1982 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1983 1984 #define CFR_START_UNIT(cfr, n) \ 1985 do { \ 1986 if ((cfr)->unit[n].refer != NULL) { \ 1987 *(cfr)->unit[n].refer |= \ 1988 (cfr)->ptr - (cfr)->unit[n].refer; \ 1989 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1990 } \ 1991 (cfr)->curunit = (n); \ 1992 (cfr)->unit[n].start = (cfr)->ptr++; \ 1993 } while (0 /* CONSTCOND */) 1994 1995 #define CFR_PUT_REFER(cfr, key, n) \ 1996 do { \ 1997 (cfr)->unit[n].refer = (cfr)->ptr; \ 1998 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1999 *(cfr)->ptr++ = (key) << 24; \ 2000 } while (0 /* CONSTCOND */) 2001 2002 #define CFR_END_UNIT(cfr) \ 2003 do { \ 2004 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2005 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2006 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2007 } while (0 /* CONSTCOND */) 2008 2009 static u_int16_t 2010 fwohci_crc16(u_int32_t *ptr, int len) 2011 { 2012 int shift; 2013 u_int32_t crc, sum, data; 2014 2015 crc = 0; 2016 while (len-- > 0) { 2017 data = *ptr++; 2018 for (shift = 28; shift >= 0; shift -= 4) { 2019 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2020 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2021 } 2022 crc &= 0xffff; 2023 } 2024 return crc; 2025 } 2026 2027 static void 2028 fwohci_configrom_init(struct fwohci_softc *sc) 2029 { 2030 int i, val; 2031 struct fwohci_buf *fb; 2032 u_int32_t *hdr; 2033 struct configromctx cfr; 2034 2035 fb = &sc->sc_buf_cnfrom; 2036 memset(&cfr, 0, sizeof(cfr)); 2037 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2038 2039 /* headers */ 2040 CFR_START_UNIT(&cfr, 0); 2041 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2042 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2043 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2044 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2045 CFR_END_UNIT(&cfr); 2046 /* copy info_length from crc_length */ 2047 *hdr |= (*hdr & 0x00ff0000) << 8; 2048 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2049 2050 /* root directory */ 2051 CFR_START_UNIT(&cfr, 1); 2052 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2053 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2054 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2055 /* spt,64,fix,lst,drq */ 2056 #ifdef INET 2057 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2058 #endif /* INET */ 2059 #ifdef INET6 2060 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2061 #endif /* INET6 */ 2062 CFR_END_UNIT(&cfr); 2063 2064 CFR_START_UNIT(&cfr, 2); 2065 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2066 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2067 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2068 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2069 CFR_END_UNIT(&cfr); 2070 2071 #ifdef INET 2072 /* IPv4 unit directory */ 2073 CFR_START_UNIT(&cfr, 3); 2074 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2075 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2076 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2077 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2078 CFR_END_UNIT(&cfr); 2079 2080 CFR_START_UNIT(&cfr, 6); 2081 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2082 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2083 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2084 CFR_END_UNIT(&cfr); 2085 2086 CFR_START_UNIT(&cfr, 7); 2087 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2088 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2089 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2090 CFR_END_UNIT(&cfr); 2091 #endif /* INET */ 2092 2093 #ifdef INET6 2094 /* IPv6 unit directory */ 2095 CFR_START_UNIT(&cfr, 4); 2096 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2097 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2098 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2099 /* XXX: TBA by IANA */ 2100 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2101 CFR_END_UNIT(&cfr); 2102 2103 CFR_START_UNIT(&cfr, 8); 2104 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2105 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2106 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2107 CFR_END_UNIT(&cfr); 2108 2109 CFR_START_UNIT(&cfr, 9); 2110 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2111 CFR_PUT_DATA1(&cfr, 0); 2112 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2113 CFR_END_UNIT(&cfr); 2114 #endif /* INET6 */ 2115 2116 fb->fb_off = cfr.ptr - hdr; 2117 #ifdef FW_DEBUG 2118 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2119 for (i = 0; i < fb->fb_off; i++) 2120 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2121 DPRINTFN(2, ("\n")); 2122 #endif /* FW_DEBUG */ 2123 2124 /* 2125 * Make network byte order for DMA 2126 */ 2127 for (i = 0; i < fb->fb_off; i++) 2128 HTONL(hdr[i]); 2129 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2130 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2131 2132 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2133 fb->fb_dmamap->dm_segs[0].ds_addr); 2134 2135 /* This register is only valid on OHCI 1.1. */ 2136 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2137 if ((OHCI_Version_GET_Version(val) == 1) && 2138 (OHCI_Version_GET_Revision(val) == 1)) 2139 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2140 OHCI_HCControl_BIBImageValid); 2141 2142 /* Just allow quad reads of the rom. */ 2143 for (i = 0; i < fb->fb_off; i++) 2144 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2145 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2146 fwohci_configrom_input, NULL); 2147 } 2148 2149 static int 2150 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2151 struct fwohci_pkt *pkt) 2152 { 2153 struct fwohci_pkt res; 2154 u_int32_t loc, *rom; 2155 2156 /* This will be used as an array index so size accordingly. */ 2157 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2158 if ((loc & 0x03) != 0) { 2159 /* alignment error */ 2160 return IEEE1394_RCODE_ADDRESS_ERROR; 2161 } 2162 else 2163 loc /= 4; 2164 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2165 2166 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2167 ntohl(rom[loc]))); 2168 2169 memset(&res, 0, sizeof(res)); 2170 res.fp_hdr[3] = rom[loc]; 2171 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2172 return -1; 2173 } 2174 2175 /* 2176 * SelfID buffer (no DMA context) 2177 */ 2178 static void 2179 fwohci_selfid_init(struct fwohci_softc *sc) 2180 { 2181 struct fwohci_buf *fb; 2182 2183 fb = &sc->sc_buf_selfid; 2184 #ifdef DIAGNOSTIC 2185 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2186 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2187 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2188 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2189 #endif 2190 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2191 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2192 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2193 2194 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2195 fb->fb_dmamap->dm_segs[0].ds_addr); 2196 } 2197 2198 static int 2199 fwohci_selfid_input(struct fwohci_softc *sc) 2200 { 2201 int i; 2202 u_int32_t count, val, gen; 2203 u_int32_t *buf; 2204 2205 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2206 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2207 again: 2208 if (val & OHCI_SelfID_Error) { 2209 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2210 return -1; 2211 } 2212 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2213 2214 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2215 0, count << 2, BUS_DMASYNC_POSTREAD); 2216 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2217 2218 #ifdef FW_DEBUG 2219 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2220 val)); 2221 for (i = 0; i < count; i++) 2222 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", buf[i])); 2223 DPRINTFN(1, ("\n")); 2224 #endif /* FW_DEBUG */ 2225 2226 for (i = 1; i < count; i += 2) { 2227 if (buf[i] != ~buf[i + 1]) 2228 break; 2229 if (buf[i] & 0x00000001) 2230 continue; /* more pkt */ 2231 if (buf[i] & 0x00800000) 2232 continue; /* external id */ 2233 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2234 if ((buf[i] & 0x00400800) == 0x00400800) 2235 sc->sc_irmid = sc->sc_rootid; 2236 } 2237 2238 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2239 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2240 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2241 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2242 goto again; 2243 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2244 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2245 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2246 return -1; 2247 } 2248 if (i != count) { 2249 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2250 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2251 #if 1 2252 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2253 /* 2254 * XXX: CXD3222 sometimes fails to DMA 2255 * selfid packet?? 2256 */ 2257 sc->sc_rootid = (count - 1) / 2 - 1; 2258 sc->sc_irmid = sc->sc_rootid; 2259 } else 2260 #endif 2261 return -1; 2262 } 2263 2264 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2265 if ((val & OHCI_NodeId_IDValid) == 0) { 2266 sc->sc_nodeid = 0xffff; /* invalid */ 2267 printf("%s: nodeid is invalid\n", 2268 sc->sc_sc1394.sc1394_dev.dv_xname); 2269 return -1; 2270 } 2271 sc->sc_nodeid = val & 0xffff; 2272 2273 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2274 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2275 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2276 sc->sc_irmid)); 2277 2278 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2279 return -1; 2280 2281 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2282 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2283 OHCI_LinkControl_CycleMaster); 2284 else 2285 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2286 OHCI_LinkControl_CycleMaster); 2287 return 0; 2288 } 2289 2290 /* 2291 * some CSRs are handled by driver. 2292 */ 2293 static void 2294 fwohci_csr_init(struct fwohci_softc *sc) 2295 { 2296 int i; 2297 static u_int32_t csr[] = { 2298 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2299 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2300 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2301 CSR_SB_BROADCAST_CHANNEL 2302 }; 2303 2304 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2305 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2306 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2307 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2308 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2309 } 2310 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2311 } 2312 2313 static int 2314 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2315 { 2316 struct fwohci_pkt res; 2317 u_int32_t reg; 2318 2319 /* 2320 * XXX need to do special functionality other than just r/w... 2321 */ 2322 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2323 2324 if ((reg & 0x03) != 0) { 2325 /* alignment error */ 2326 return IEEE1394_RCODE_ADDRESS_ERROR; 2327 } 2328 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2329 *(u_int32_t *)(&sc->sc_csr[reg]))); 2330 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2331 DPRINTFN(1, (" -> 0x%08x\n", 2332 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2333 *(u_int32_t *)&sc->sc_csr[reg] = 2334 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2335 } else { 2336 DPRINTFN(1, ("\n")); 2337 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2338 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2339 res.fp_iov[0].iov_len = 4; 2340 res.fp_uio.uio_resid = 4; 2341 res.fp_uio.uio_iovcnt = 1; 2342 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2343 return -1; 2344 } 2345 return IEEE1394_RCODE_COMPLETE; 2346 } 2347 2348 /* 2349 * Mapping between nodeid and unique ID (EUI-64). 2350 * 2351 * Track old mappings and simply update their devices with the new id's when 2352 * they match an existing EUI. This allows proper renumeration of the bus. 2353 */ 2354 static void 2355 fwohci_uid_collect(struct fwohci_softc *sc) 2356 { 2357 int i; 2358 struct fwohci_uidtbl *fu; 2359 struct fwohci_pkt pkt; 2360 struct ieee1394_softc *iea; 2361 2362 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2363 iea->sc1394_node_id = 0xffff; 2364 2365 if (sc->sc_uidtbl != NULL) 2366 free(sc->sc_uidtbl, M_DEVBUF); 2367 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2368 M_WAITOK); 2369 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2370 2371 memset(&pkt, 0, sizeof(pkt)); 2372 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2373 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2374 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2375 fu->fu_valid = 3; 2376 2377 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2378 if (iea) { 2379 iea->sc1394_node_id = i; 2380 DPRINTF(("%s: Updating nodeid to %d\n", 2381 iea->sc1394_dev.dv_xname, 2382 iea->sc1394_node_id)); 2383 } 2384 continue; 2385 } 2386 fu->fu_valid = 0; 2387 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2388 pkt.fp_hlen = 12; 2389 pkt.fp_dlen = 0; 2390 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2391 (pkt.fp_tcode << 4); 2392 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2393 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2394 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2395 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2396 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2397 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2398 2399 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2400 (pkt.fp_tcode << 4); 2401 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2402 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2403 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2404 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2405 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2406 2407 } 2408 if (sc->sc_rootid == 0) 2409 fwohci_check_nodes(sc); 2410 } 2411 2412 static int 2413 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2414 { 2415 struct fwohci_uidtbl *fu; 2416 struct ieee1394_softc *iea; 2417 struct ieee1394_attach_args fwa; 2418 int i, n, done, rcode, found; 2419 2420 found = 0; 2421 2422 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2423 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2424 if (rcode != IEEE1394_RCODE_COMPLETE || 2425 sc->sc_uidtbl == NULL || 2426 n > sc->sc_rootid) 2427 return 0; 2428 fu = &sc->sc_uidtbl[n]; 2429 if (arg == 0) { 2430 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2431 fu->fu_valid |= 0x1; 2432 } else { 2433 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2434 fu->fu_valid |= 0x2; 2435 } 2436 #ifdef FW_DEBUG 2437 if (fu->fu_valid == 0x3) 2438 DPRINTFN(1, ("fwohci_uid_input: " 2439 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2440 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2441 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2442 #endif 2443 if (fu->fu_valid == 0x3) { 2444 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2445 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2446 found = 1; 2447 iea->sc1394_node_id = n; 2448 DPRINTF(("%s: Updating nodeid to %d\n", 2449 iea->sc1394_dev.dv_xname, 2450 iea->sc1394_node_id)); 2451 break; 2452 } 2453 if (!found) { 2454 strcpy(fwa.name, "fwnode"); 2455 memcpy(fwa.uid, fu->fu_uid, 8); 2456 fwa.nodeid = n; 2457 fwa.read = fwohci_read; 2458 fwa.write = fwohci_write; 2459 fwa.inreg = fwohci_inreg; 2460 iea = (struct ieee1394_softc *) 2461 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2462 fwohci_print, fwohci_submatch); 2463 if (iea != NULL) 2464 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2465 sc1394_node); 2466 } 2467 } 2468 done = 1; 2469 2470 for (i = 0; i < sc->sc_rootid + 1; i++) { 2471 fu = &sc->sc_uidtbl[i]; 2472 if (fu->fu_valid != 0x3) { 2473 done = 0; 2474 break; 2475 } 2476 } 2477 if (done) 2478 fwohci_check_nodes(sc); 2479 2480 return 0; 2481 } 2482 2483 static void 2484 fwohci_check_nodes(struct fwohci_softc *sc) 2485 { 2486 struct device *detach = NULL; 2487 struct ieee1394_softc *iea; 2488 2489 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2490 2491 /* 2492 * Have to defer detachment until the next 2493 * loop iteration since config_detach 2494 * free's the softc and the loop iterator 2495 * needs data from the softc to move 2496 * forward. 2497 */ 2498 2499 if (detach) { 2500 config_detach(detach, 0); 2501 detach = NULL; 2502 } 2503 if (iea->sc1394_node_id == 0xffff) { 2504 detach = (struct device *)iea; 2505 LIST_REMOVE(iea, sc1394_node); 2506 } 2507 } 2508 if (detach) 2509 config_detach(detach, 0); 2510 } 2511 2512 static int 2513 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2514 { 2515 struct fwohci_uidtbl *fu; 2516 int n; 2517 static const u_int8_t bcast[] = 2518 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2519 2520 fu = sc->sc_uidtbl; 2521 if (fu == NULL) { 2522 notfound: 2523 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2524 return IEEE1394_BCAST_PHY_ID; 2525 fwohci_uid_collect(sc); /* try to get */ 2526 return -1; 2527 } 2528 for (n = 0; ; n++, fu++) { 2529 if (n > sc->sc_rootid) 2530 goto notfound; 2531 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2532 break; 2533 } 2534 return n; 2535 } 2536 2537 /* 2538 * functions to support network interface 2539 */ 2540 static int 2541 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2542 void (*handler)(struct device *, struct mbuf *)) 2543 { 2544 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2545 2546 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2547 fwohci_if_input, handler); 2548 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2549 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2550 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2551 return 0; 2552 } 2553 2554 static int 2555 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2556 { 2557 int n, len; 2558 struct mbuf *m; 2559 struct iovec *iov; 2560 void (*handler)(struct device *, struct mbuf *) = arg; 2561 2562 #ifdef FW_DEBUG 2563 int i; 2564 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2565 pkt->fp_dlen)); 2566 for (i = 0; i < pkt->fp_hlen/4; i++) 2567 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2568 DPRINTFN(2, ("$")); 2569 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2570 iov = &pkt->fp_iov[n]; 2571 for (i = 0; i < iov->iov_len; i++) 2572 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 2573 ((u_int8_t *)iov->iov_base)[i])); 2574 DPRINTFN(2, ("$")); 2575 } 2576 DPRINTFN(1, ("\n")); 2577 #endif /* FW_DEBUG */ 2578 len = pkt->fp_dlen; 2579 MGETHDR(m, M_DONTWAIT, MT_DATA); 2580 if (m == NULL) 2581 return IEEE1394_RCODE_COMPLETE; 2582 m->m_len = 16; 2583 if (len + m->m_len > MHLEN) { 2584 MCLGET(m, M_DONTWAIT); 2585 if ((m->m_flags & M_EXT) == 0) { 2586 m_freem(m); 2587 return IEEE1394_RCODE_COMPLETE; 2588 } 2589 } 2590 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2591 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2592 sc->sc_uidtbl[n].fu_valid != 0x3) { 2593 printf("%s: packet from unknown node: phy id %d\n", 2594 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2595 m_freem(m); 2596 return IEEE1394_RCODE_COMPLETE; 2597 } 2598 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2599 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2600 m->m_flags |= M_BCAST; 2601 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2602 } else { 2603 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2604 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2605 } 2606 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2607 mtod(m, u_int8_t *)[9] = 2608 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2609 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2610 2611 m->m_pkthdr.rcvif = NULL; /* set in child */ 2612 m->m_pkthdr.len = len + m->m_len; 2613 /* 2614 * We may use receive buffer by external mbuf instead of copy here. 2615 * But asynchronous receive buffer must be operate in buffer fill 2616 * mode, so that each receive buffer will shared by multiple mbufs. 2617 * If upper layer doesn't free mbuf soon, e.g. application program 2618 * is suspended, buffer must be reallocated. 2619 * Isochronous buffer must be operate in packet buffer mode, and 2620 * it is easy to map receive buffer to external mbuf. But it is 2621 * used for broadcast/multicast only, and is expected not so 2622 * performance sensitive for now. 2623 * XXX: The performance may be important for multicast case, 2624 * so we should revisit here later. 2625 * -- onoe 2626 */ 2627 n = 0; 2628 iov = pkt->fp_uio.uio_iov; 2629 while (len > 0) { 2630 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2631 iov->iov_len); 2632 m->m_len += iov->iov_len; 2633 len -= iov->iov_len; 2634 iov++; 2635 } 2636 (*handler)(sc->sc_sc1394.sc1394_if, m); 2637 return IEEE1394_RCODE_COMPLETE; 2638 } 2639 2640 static int 2641 fwohci_if_output(struct device *self, struct mbuf *m0, 2642 void (*callback)(struct device *, struct mbuf *)) 2643 { 2644 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2645 struct fwohci_pkt pkt; 2646 u_int8_t *p; 2647 int n, error, spd, hdrlen, maxrec; 2648 #ifdef FW_DEBUG 2649 struct mbuf *m; 2650 #endif 2651 2652 p = mtod(m0, u_int8_t *); 2653 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2654 spd = IEEE1394_SPD_S100; /*XXX*/ 2655 maxrec = 512; /*XXX*/ 2656 hdrlen = 8; 2657 } else { 2658 n = fwohci_uid_lookup(sc, p); 2659 if (n < 0) { 2660 printf("%s: nodeid unknown:" 2661 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2662 sc->sc_sc1394.sc1394_dev.dv_xname, 2663 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2664 error = EHOSTUNREACH; 2665 goto end; 2666 } 2667 if (n == IEEE1394_BCAST_PHY_ID) { 2668 printf("%s: broadcast with !M_MCAST\n", 2669 sc->sc_sc1394.sc1394_dev.dv_xname); 2670 #ifdef FW_DEBUG 2671 DPRINTFN(2, ("packet:")); 2672 for (m = m0; m != NULL; m = m->m_next) { 2673 for (n = 0; n < m->m_len; n++) 2674 DPRINTFN(2, ("%s%02x", (n%32)? 2675 ((n%4)?"":" "):"\n\t", 2676 mtod(m, u_int8_t *)[n])); 2677 DPRINTFN(2, ("$")); 2678 } 2679 DPRINTFN(2, ("\n")); 2680 #endif 2681 error = EHOSTUNREACH; 2682 goto end; 2683 } 2684 maxrec = 2 << p[8]; 2685 spd = p[9]; 2686 hdrlen = 0; 2687 } 2688 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2689 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2690 spd, sc->sc_sc1394.sc1394_link_speed)); 2691 spd = sc->sc_sc1394.sc1394_link_speed; 2692 } 2693 if (maxrec > (512 << spd)) { 2694 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2695 "\n", maxrec, spd)); 2696 maxrec = 512 << spd; 2697 } 2698 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2699 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2700 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2701 maxrec >>= 1; 2702 } 2703 if (maxrec < 512) { 2704 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2705 "minimum\n", maxrec)); 2706 maxrec = 512; 2707 } 2708 2709 m_adj(m0, 16 - hdrlen); 2710 if (m0->m_pkthdr.len > maxrec) { 2711 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2712 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2713 error = E2BIG; /*XXX*/ 2714 goto end; 2715 } 2716 2717 memset(&pkt, 0, sizeof(pkt)); 2718 pkt.fp_uio.uio_iov = pkt.fp_iov; 2719 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2720 pkt.fp_uio.uio_rw = UIO_WRITE; 2721 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2722 /* construct GASP header */ 2723 p = mtod(m0, u_int8_t *); 2724 p[0] = sc->sc_nodeid >> 8; 2725 p[1] = sc->sc_nodeid & 0xff; 2726 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2727 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2728 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2729 pkt.fp_hlen = 8; 2730 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2731 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2732 OHCI_NodeId_NodeNumber) << 8); 2733 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2734 } else { 2735 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2736 pkt.fp_hlen = 16; 2737 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2738 (spd << 16); 2739 pkt.fp_hdr[1] = 2740 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2741 (p[10] << 8) | p[11]; 2742 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2743 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2744 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2745 } 2746 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2747 pkt.fp_dlen = m0->m_pkthdr.len; 2748 pkt.fp_m = m0; 2749 pkt.fp_callback = callback; 2750 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2751 m0 = pkt.fp_m; 2752 end: 2753 if (m0 != NULL) { 2754 if (callback) 2755 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2756 else 2757 m_freem(m0); 2758 } 2759 return error; 2760 } 2761 2762 /* 2763 * High level routines to provide abstraction to attaching layers to 2764 * send/receive data. 2765 */ 2766 2767 /* 2768 * These break down into 4 routines as follows: 2769 * 2770 * int fwohci_read(struct ieee1394_abuf *) 2771 * 2772 * This routine will attempt to read a region from the requested node. 2773 * A callback must be provided which will be called when either the completed 2774 * read is done or an unrecoverable error occurs. This is mainly a convenience 2775 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2776 * and recombining all the returned data. This could also be done with a series 2777 * of write/inreg's for each packet sent. 2778 * 2779 * int fwohci_write(struct ieee1394_abuf *) 2780 * 2781 * The work horse main entry point for putting packets on the bus. This is the 2782 * generalized interface for fwnode/etc code to put packets out onto the bus. 2783 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2784 * will callback via a func pointer to the calling code with the resulting ACK 2785 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2786 * write routine will take care of free'ing the abuf since the fwnode/etc code 2787 * won't have any knowledge of when to do this. This allows for simple one-off 2788 * packets to be sent from the upper-level code without worrying about a callback 2789 * for cleanup. 2790 * 2791 * int fwohci_inreg(struct ieee1394_abuf *, int) 2792 * 2793 * This is very simple. It evals the abuf passed in and registers an internal 2794 * handler as the callback for packets received for that operation. 2795 * The integer argument specifies whether on a block read/write operation to 2796 * allow sub-regions to be read/written (in block form) as well. 2797 * 2798 * XXX: This whole structure needs to be redone as a list of regions and 2799 * operations allowed on those regions. 2800 * 2801 * int fwohci_unreg(struct ieee1394_abuf *, int) 2802 * 2803 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2804 * routine will simply verify ab_cb is NULL and call inreg. 2805 * 2806 * This simply unregisters the respective callback done via inreg for items 2807 * which only need to register an area for a one-time operation (like a status 2808 * buffer a remote node will write to when the current operation is done). The 2809 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2810 * it unregisters). 2811 */ 2812 2813 static int 2814 fwohci_read(struct ieee1394_abuf *ab) 2815 { 2816 struct fwohci_pkt pkt; 2817 struct ieee1394_softc *sc = ab->ab_req; 2818 struct fwohci_softc *psc = 2819 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2820 struct fwohci_cb *fcb; 2821 u_int32_t high, lo; 2822 int rv, tcode; 2823 2824 /* Have to have a callback when reading. */ 2825 if (ab->ab_cb == NULL) 2826 return -1; 2827 2828 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2829 fcb->ab = ab; 2830 fcb->count = 0; 2831 fcb->abuf_valid = 1; 2832 2833 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2834 lo = (ab->ab_csr & 0x00000000ffffffff); 2835 2836 memset(&pkt, 0, sizeof(pkt)); 2837 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2838 pkt.fp_hdr[2] = lo; 2839 pkt.fp_dlen = 0; 2840 2841 if (ab->ab_length == 4) { 2842 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2843 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2844 pkt.fp_hlen = 12; 2845 } else { 2846 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2847 pkt.fp_hlen = 16; 2848 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2849 pkt.fp_hdr[3] = (ab->ab_length << 16); 2850 } 2851 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2852 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2853 2854 pkt.fp_statusarg = fcb; 2855 pkt.fp_statuscb = fwohci_read_resp; 2856 2857 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2858 psc->sc_tlabel, fwohci_read_resp, fcb); 2859 if (rv) 2860 return rv; 2861 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2862 if (rv) 2863 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2864 psc->sc_tlabel, NULL, NULL); 2865 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2866 fcb->count = 1; 2867 return rv; 2868 } 2869 2870 static int 2871 fwohci_write(struct ieee1394_abuf *ab) 2872 { 2873 struct fwohci_pkt pkt; 2874 struct ieee1394_softc *sc = ab->ab_req; 2875 struct fwohci_softc *psc = 2876 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2877 u_int32_t high, lo; 2878 int rv; 2879 2880 if (ab->ab_length > sc->sc1394_max_receive) { 2881 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2882 return E2BIG; 2883 } 2884 2885 memset(&pkt, 0, sizeof(pkt)); 2886 2887 pkt.fp_tcode = ab->ab_tcode; 2888 pkt.fp_uio.uio_iov = pkt.fp_iov; 2889 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2890 pkt.fp_uio.uio_rw = UIO_WRITE; 2891 2892 pkt.fp_statusarg = ab; 2893 pkt.fp_statuscb = fwohci_write_ack; 2894 2895 switch (ab->ab_tcode) { 2896 case IEEE1394_TCODE_WRITE_RESP: 2897 pkt.fp_hlen = 12; 2898 case IEEE1394_TCODE_READ_RESP_QUAD: 2899 case IEEE1394_TCODE_READ_RESP_BLOCK: 2900 if (!pkt.fp_hlen) 2901 pkt.fp_hlen = 16; 2902 high = ab->ab_retlen; 2903 ab->ab_retlen = 0; 2904 lo = 0; 2905 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2906 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2907 break; 2908 default: 2909 pkt.fp_hlen = 16; 2910 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2911 lo = (ab->ab_csr & 0x00000000ffffffff); 2912 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2913 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2914 break; 2915 } 2916 2917 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2918 pkt.fp_hdr[2] = lo; 2919 if (pkt.fp_hlen == 16) { 2920 if (ab->ab_length == 4) { 2921 pkt.fp_hdr[3] = ab->ab_data[0]; 2922 pkt.fp_dlen = 0; 2923 } else { 2924 pkt.fp_hdr[3] = (ab->ab_length << 16); 2925 pkt.fp_dlen = ab->ab_length; 2926 pkt.fp_uio.uio_iovcnt = 1; 2927 pkt.fp_uio.uio_resid = ab->ab_length; 2928 pkt.fp_iov[0].iov_base = ab->ab_data; 2929 pkt.fp_iov[0].iov_len = ab->ab_length; 2930 } 2931 } 2932 switch (ab->ab_tcode) { 2933 case IEEE1394_TCODE_WRITE_RESP: 2934 case IEEE1394_TCODE_READ_RESP_QUAD: 2935 case IEEE1394_TCODE_READ_RESP_BLOCK: 2936 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2937 break; 2938 default: 2939 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2940 break; 2941 } 2942 return rv; 2943 } 2944 2945 static int 2946 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2947 { 2948 struct fwohci_cb *fcb = arg; 2949 struct ieee1394_abuf *ab = fcb->ab; 2950 struct fwohci_pkt newpkt; 2951 u_int32_t *cur, high, lo; 2952 int i, tcode, rcode, status, rv; 2953 2954 /* 2955 * Both the ACK handling and normal response callbacks are handled here. 2956 * The main reason for this is the various error conditions that can 2957 * occur trying to block read some areas and the ways that gets reported 2958 * back to calling station. This is a variety of ACK codes, responses, 2959 * etc which makes it much more difficult to process if both aren't 2960 * handled here. 2961 */ 2962 2963 /* Check for status packet. */ 2964 2965 if (pkt->fp_tcode == -1) { 2966 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2967 rcode = -1; 2968 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2969 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2970 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2971 DPRINTF(("Got status packet: 0x%02x\n", 2972 (unsigned int)status)); 2973 fcb->count--; 2974 2975 /* 2976 * Got all the ack's back and the buffer is invalid (i.e. the 2977 * callback has been called. Clean up. 2978 */ 2979 2980 if (fcb->abuf_valid == 0) { 2981 if (fcb->count == 0) 2982 free(fcb, M_DEVBUF); 2983 return IEEE1394_RCODE_COMPLETE; 2984 } 2985 } else { 2986 status = -1; 2987 tcode = pkt->fp_tcode; 2988 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2989 } 2990 2991 /* 2992 * Some area's (like the config rom want to be read as quadlets only. 2993 * 2994 * The current ideas to try are: 2995 * 2996 * Got an ACK_TYPE_ERROR on a block read. 2997 * 2998 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2999 * response. 3000 * 3001 * In all cases construct a new packet for a quadlet read and let 3002 * mutli_resp handle the iteration over the space. 3003 */ 3004 3005 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 3006 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 3007 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 3008 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 3009 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 3010 3011 /* Read the area in quadlet chunks (internally track this). */ 3012 3013 memset(&newpkt, 0, sizeof(newpkt)); 3014 3015 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3016 lo = (ab->ab_csr & 0x00000000ffffffff); 3017 3018 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3019 newpkt.fp_hlen = 12; 3020 newpkt.fp_dlen = 0; 3021 newpkt.fp_hdr[1] = 3022 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3023 newpkt.fp_hdr[2] = lo; 3024 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3025 (newpkt.fp_tcode << 4); 3026 3027 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3028 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3029 fwohci_read_multi_resp, fcb); 3030 if (rv) { 3031 (*ab->ab_cb)(ab, -1); 3032 goto cleanup; 3033 } 3034 newpkt.fp_statusarg = fcb; 3035 newpkt.fp_statuscb = fwohci_read_resp; 3036 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3037 if (rv) { 3038 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3039 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3040 NULL); 3041 (*ab->ab_cb)(ab, -1); 3042 goto cleanup; 3043 } 3044 fcb->count++; 3045 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3046 return IEEE1394_RCODE_COMPLETE; 3047 } else if ((rcode != -1) || ((status != -1) && 3048 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3049 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3050 3051 /* 3052 * Recombine all the iov data into 1 chunk for higher 3053 * level code. 3054 */ 3055 3056 if (rcode != -1) { 3057 cur = ab->ab_data; 3058 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3059 /* 3060 * Make sure and don't exceed the buffer 3061 * allocated for return. 3062 */ 3063 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3064 ab->ab_length) { 3065 memcpy(cur, pkt->fp_iov[i].iov_base, 3066 (ab->ab_length - ab->ab_retlen)); 3067 ab->ab_retlen = ab->ab_length; 3068 break; 3069 } 3070 memcpy(cur, pkt->fp_iov[i].iov_base, 3071 pkt->fp_iov[i].iov_len); 3072 cur += pkt->fp_iov[i].iov_len; 3073 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3074 } 3075 } 3076 if (status != -1) 3077 /* XXX: Need a complete tlabel interface. */ 3078 for (i = 0; i < 64; i++) 3079 fwohci_handler_set(sc, 3080 IEEE1394_TCODE_READ_RESP_QUAD, 3081 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3082 (*ab->ab_cb)(ab, rcode); 3083 goto cleanup; 3084 } else 3085 /* Good ack packet. */ 3086 return IEEE1394_RCODE_COMPLETE; 3087 3088 /* Can't get here unless ab->ab_cb has been called. */ 3089 3090 cleanup: 3091 fcb->abuf_valid = 0; 3092 if (fcb->count == 0) 3093 free(fcb, M_DEVBUF); 3094 return IEEE1394_RCODE_COMPLETE; 3095 } 3096 3097 static int 3098 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3099 struct fwohci_pkt *pkt) 3100 { 3101 struct fwohci_cb *fcb = arg; 3102 struct ieee1394_abuf *ab = fcb->ab; 3103 struct fwohci_pkt newpkt; 3104 u_int32_t high, lo; 3105 int rcode, rv; 3106 3107 /* 3108 * Bad return codes from the wire, just return what's already in the 3109 * buf. 3110 */ 3111 3112 /* Make sure a response packet didn't arrive after a bad ACK. */ 3113 if (fcb->abuf_valid == 0) 3114 return IEEE1394_RCODE_COMPLETE; 3115 3116 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3117 3118 if (rcode) { 3119 (*ab->ab_cb)(ab, rcode); 3120 goto cleanup; 3121 } 3122 3123 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3124 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3125 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3126 ab->ab_retlen = ab->ab_length; 3127 } else { 3128 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3129 pkt->fp_iov[0].iov_base, 4); 3130 ab->ab_retlen += 4; 3131 } 3132 /* Still more, loop and read 4 more bytes. */ 3133 if (ab->ab_retlen < ab->ab_length) { 3134 memset(&newpkt, 0, sizeof(newpkt)); 3135 3136 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3137 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3138 3139 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3140 newpkt.fp_hlen = 12; 3141 newpkt.fp_dlen = 0; 3142 newpkt.fp_hdr[1] = 3143 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3144 newpkt.fp_hdr[2] = lo; 3145 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3146 (newpkt.fp_tcode << 4); 3147 3148 newpkt.fp_statusarg = fcb; 3149 newpkt.fp_statuscb = fwohci_read_resp; 3150 3151 /* 3152 * Bad return code. Just give up and return what's 3153 * come in now. 3154 */ 3155 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3156 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3157 fwohci_read_multi_resp, fcb); 3158 if (rv) 3159 (*ab->ab_cb)(ab, -1); 3160 else { 3161 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3162 if (rv) { 3163 fwohci_handler_set(sc, 3164 IEEE1394_TCODE_READ_RESP_QUAD, 3165 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3166 NULL, NULL); 3167 (*ab->ab_cb)(ab, -1); 3168 } else { 3169 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3170 fcb->count++; 3171 return IEEE1394_RCODE_COMPLETE; 3172 } 3173 } 3174 } else 3175 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3176 3177 cleanup: 3178 /* Can't get here unless ab_cb has been called. */ 3179 fcb->abuf_valid = 0; 3180 if (fcb->count == 0) 3181 free(fcb, M_DEVBUF); 3182 return IEEE1394_RCODE_COMPLETE; 3183 } 3184 3185 static int 3186 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3187 { 3188 struct ieee1394_abuf *ab = arg; 3189 u_int16_t status; 3190 3191 3192 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3193 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3194 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3195 DPRINTF(("Got status packet: 0x%02x\n", 3196 (unsigned int)status)); 3197 3198 /* No callback means this level should free the buffers. */ 3199 if (ab->ab_cb) 3200 (*ab->ab_cb)(ab, status); 3201 else { 3202 if (ab->ab_data) 3203 free(ab->ab_data, M_1394DATA); 3204 free(ab, M_1394DATA); 3205 } 3206 return IEEE1394_RCODE_COMPLETE; 3207 } 3208 3209 static int 3210 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3211 { 3212 struct ieee1394_softc *sc = ab->ab_req; 3213 struct fwohci_softc *psc = 3214 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3215 u_int32_t high, lo; 3216 int i, j, rv; 3217 3218 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3219 lo = (ab->ab_csr & 0x00000000ffffffff); 3220 3221 rv = 0; 3222 switch (ab->ab_tcode) { 3223 case IEEE1394_TCODE_READ_REQ_QUAD: 3224 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3225 if (ab->ab_cb) 3226 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3227 fwohci_parse_input, ab); 3228 else 3229 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3230 NULL); 3231 break; 3232 case IEEE1394_TCODE_READ_REQ_BLOCK: 3233 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3234 if (allow) { 3235 for (i = 0; i < (ab->ab_length / 4); i++) { 3236 if (ab->ab_cb) { 3237 rv = fwohci_handler_set(psc, 3238 ab->ab_tcode, high, lo + (i * 4), 3239 fwohci_parse_input, ab); 3240 if (rv) 3241 break; 3242 } else 3243 fwohci_handler_set(psc, ab->ab_tcode, 3244 high, lo + (i * 4), NULL, NULL); 3245 } 3246 if (i != (ab->ab_length / 4)) { 3247 j = i + 1; 3248 for (i = 0; i < j; i++) 3249 fwohci_handler_set(psc, ab->ab_tcode, 3250 high, lo + (i * 4), NULL, NULL); 3251 } else 3252 ab->ab_data = (void *)1; 3253 } else { 3254 if (ab->ab_cb) 3255 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3256 lo, fwohci_parse_input, ab); 3257 else 3258 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3259 NULL, NULL); 3260 } 3261 break; 3262 default: 3263 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3264 return -1; 3265 break; 3266 } 3267 return rv; 3268 } 3269 3270 static int 3271 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3272 { 3273 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3274 u_int64_t csr; 3275 u_int32_t *cur; 3276 int i, count; 3277 3278 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3279 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3280 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3281 3282 switch (ab->ab_tcode) { 3283 case IEEE1394_TCODE_READ_REQ_QUAD: 3284 ab->ab_retlen = 4; 3285 break; 3286 case IEEE1394_TCODE_READ_REQ_BLOCK: 3287 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3288 if (ab->ab_data) { 3289 if ((csr + ab->ab_retlen) > 3290 (ab->ab_csr + ab->ab_length)) 3291 return IEEE1394_RCODE_ADDRESS_ERROR; 3292 ab->ab_data = NULL; 3293 } else 3294 if (ab->ab_retlen != ab->ab_length) 3295 return IEEE1394_RCODE_ADDRESS_ERROR; 3296 break; 3297 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3298 ab->ab_retlen = 4; 3299 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3300 if (!ab->ab_retlen) 3301 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3302 if (ab->ab_data) { 3303 if ((csr + ab->ab_retlen) > 3304 (ab->ab_csr + ab->ab_length)) 3305 return IEEE1394_RCODE_ADDRESS_ERROR; 3306 ab->ab_data = NULL; 3307 } else 3308 if (ab->ab_retlen != ab->ab_length) 3309 return IEEE1394_RCODE_ADDRESS_ERROR; 3310 3311 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3312 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3313 ab->ab_data[0] = pkt->fp_hdr[3]; 3314 else { 3315 count = 0; 3316 cur = ab->ab_data; 3317 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3318 memcpy(cur, pkt->fp_iov[i].iov_base, 3319 pkt->fp_iov[i].iov_len); 3320 cur += pkt->fp_iov[i].iov_len; 3321 count += pkt->fp_iov[i].iov_len; 3322 } 3323 if (ab->ab_retlen != count) 3324 panic("Packet claims %d length " 3325 "but only %d bytes returned\n", 3326 ab->ab_retlen, count); 3327 } 3328 break; 3329 default: 3330 panic("Got a callback for a tcode that wasn't requested: %d\n", 3331 ab->ab_tcode); 3332 break; 3333 } 3334 ab->ab_csr = csr; 3335 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3336 return -1; 3337 } 3338 3339 static int 3340 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3341 { 3342 struct ieee1394_attach_args *fwa = aux; 3343 3344 /* Both halves must be filled in for a match. */ 3345 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3346 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3347 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3348 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3349 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3350 return 0; 3351 } 3352
Indexes created Thu Sep 25 16:09:42 GMT 2025