fwohci.c revision 1.33
1 /* $NetBSD: fwohci.c,v 1.33 2001/06/28 14:37:56 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 115 116 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 117 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 119 120 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 121 struct fwohci_pkt *); 122 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 123 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 124 struct fwohci_pkt *); 125 126 static int fwohci_guidrom_init(struct fwohci_softc *); 127 static void fwohci_configrom_init(struct fwohci_softc *); 128 static int fwohci_configrom_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 static void fwohci_selfid_init(struct fwohci_softc *); 131 static int fwohci_selfid_input(struct fwohci_softc *); 132 133 static void fwohci_csr_init(struct fwohci_softc *); 134 static int fwohci_csr_input(struct fwohci_softc *, void *, 135 struct fwohci_pkt *); 136 137 static void fwohci_uid_collect(struct fwohci_softc *); 138 static int fwohci_uid_input(struct fwohci_softc *, void *, 139 struct fwohci_pkt *); 140 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 141 static void fwohci_check_nodes(struct fwohci_softc *); 142 143 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 144 void (*)(struct device *, struct mbuf *)); 145 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 146 static int fwohci_if_output(struct device *, struct mbuf *, 147 void (*)(struct device *, struct mbuf *)); 148 static int fwohci_read(struct ieee1394_abuf *); 149 static int fwohci_write(struct ieee1394_abuf *); 150 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 151 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 152 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_inreg(struct ieee1394_abuf *, int); 155 static int fwohci_parse_input(struct fwohci_softc *, void *, 156 struct fwohci_pkt *); 157 static int fwohci_submatch(struct device *, struct cfdata *, void *); 158 159 #ifdef FW_DEBUG 160 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 161 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 162 163 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 164 165 #define DPRINTF(x) if (fwdebug) printf x 166 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 167 int fwdebug = 0; 168 #else 169 #define DPRINTF(x) 170 #define DPRINTFN(n,x) 171 #endif 172 173 int 174 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 175 { 176 int i; 177 u_int32_t val; 178 #if 0 179 int error; 180 #endif 181 182 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 183 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 184 185 /* 186 * Wait for reset completion 187 */ 188 for (i = 0; i < OHCI_LOOP; i++) { 189 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 190 if ((val & OHCI_HCControl_SoftReset) == 0) 191 break; 192 } 193 194 /* What dialect of OHCI is this device? 195 */ 196 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 197 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 198 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 199 200 LIST_INIT(&sc->sc_nodelist); 201 202 if (fwohci_guidrom_init(sc) != 0) { 203 printf("\n%s: fatal: no global UID ROM\n", 204 sc->sc_sc1394.sc1394_dev.dv_xname); 205 return -1; 206 } 207 208 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 209 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 210 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 211 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 212 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 213 214 /* Get the maximum link speed and receive size 215 */ 216 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 217 sc->sc_sc1394.sc1394_link_speed = 218 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 219 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 220 printf(", %s", 221 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 222 } else { 223 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 224 } 225 226 /* MaxRec is encoded as log2(max_rec_octets)-1 227 */ 228 sc->sc_sc1394.sc1394_max_receive = 229 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 230 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 231 232 /* 233 * Count how many isochronous ctx we have. 234 */ 235 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 236 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 237 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 238 for (i = 0; val != 0; val >>= 1) { 239 if (val & 0x1) 240 i++; 241 } 242 sc->sc_isoctx = i; 243 printf(", %d iso_ctx", sc->sc_isoctx); 244 245 printf("\n"); 246 247 #if 0 248 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 249 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 250 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 251 return error; 252 #endif 253 254 sc->sc_dying = 0; 255 256 kthread_create(fwohci_create_event_thread, sc); 257 return 0; 258 } 259 260 int 261 fwohci_intr(void *arg) 262 { 263 struct fwohci_softc * const sc = arg; 264 int progress = 0; 265 u_int32_t intmask, iso; 266 267 for (;;) { 268 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 269 270 /* 271 * On a bus reset, everything except bus reset gets 272 * cleared. That can't get cleared until the selfid 273 * phase completes (which happens outside the 274 * interrupt routines). So if just a bus reset is left 275 * in the mask and it's already in the sc_intmask, 276 * just return. 277 */ 278 279 if ((intmask == 0) || 280 (progress && (intmask == OHCI_Int_BusReset) && 281 (sc->sc_intmask & OHCI_Int_BusReset))) { 282 if (progress) 283 wakeup(fwohci_event_thread); 284 return progress; 285 } 286 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 287 intmask & ~OHCI_Int_BusReset); 288 #ifdef FW_DEBUG 289 if (fwdebug > 1) 290 fwohci_show_intr(sc, intmask); 291 #endif 292 293 if (intmask & OHCI_Int_BusReset) { 294 /* 295 * According to OHCI spec 6.1.1 "busReset", 296 * All asynchronous transmit must be stopped before 297 * clearing BusReset. Moreover, the BusReset 298 * interrupt bit should not be cleared during the 299 * SelfID phase. Thus we turned off interrupt mask 300 * bit of BusReset instead until SelfID completion 301 * or SelfID timeout. 302 */ 303 intmask &= OHCI_Int_SelfIDComplete; 304 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 305 OHCI_Int_BusReset); 306 sc->sc_intmask = intmask; 307 sc->sc_intmask |= OHCI_Int_BusReset; 308 } 309 310 if (intmask & OHCI_Int_SelfIDComplete) 311 sc->sc_intmask |= OHCI_Int_SelfIDComplete; 312 313 if (intmask & OHCI_Int_ReqTxComplete) 314 sc->sc_intmask |= OHCI_Int_ReqTxComplete; 315 if (intmask & OHCI_Int_RespTxComplete) 316 sc->sc_intmask |= OHCI_Int_RespTxComplete; 317 if (intmask & OHCI_Int_RQPkt) 318 sc->sc_intmask |= OHCI_Int_RQPkt; 319 if (intmask & OHCI_Int_RSPkt) 320 sc->sc_intmask |= OHCI_Int_RSPkt; 321 if (intmask & OHCI_Int_IsochTx) { 322 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 323 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 324 sc->sc_intmask |= OHCI_Int_IsochTx; 325 } 326 if (intmask & OHCI_Int_IsochRx) { 327 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 328 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 329 sc->sc_iso |= iso; 330 sc->sc_intmask |= OHCI_Int_IsochRx; 331 } 332 333 if (!progress) { 334 sc->sc_intrcnt.ev_count++; 335 progress = 1; 336 } 337 } 338 } 339 340 static void 341 fwohci_create_event_thread(void *arg) 342 { 343 struct fwohci_softc *sc = arg; 344 345 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 346 sc->sc_sc1394.sc1394_dev.dv_xname)) { 347 printf("%s: unable to create event thread\n", 348 sc->sc_sc1394.sc1394_dev.dv_xname); 349 panic("fwohci_create_event_thread"); 350 } 351 } 352 353 static void 354 fwohci_thread_init(void *arg) 355 { 356 struct fwohci_softc *sc = arg; 357 int i; 358 359 /* 360 * Allocate descriptors 361 */ 362 if (fwohci_desc_alloc(sc)) { 363 printf("%s: not enabling interrupts\n", 364 sc->sc_sc1394.sc1394_dev.dv_xname); 365 kthread_exit(1); 366 } 367 368 /* 369 * Enable Link Power 370 */ 371 372 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 373 374 /* 375 * Allocate DMA Context 376 */ 377 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 378 OHCI_CTX_ASYNC_RX_REQUEST); 379 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 380 OHCI_CTX_ASYNC_RX_RESPONSE); 381 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 382 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 383 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 384 M_DEVBUF, M_WAITOK); 385 for (i = 0; i < sc->sc_isoctx; i++) 386 sc->sc_ctx_ir[i] = NULL; 387 388 /* 389 * Allocate buffer for configuration ROM and SelfID buffer 390 */ 391 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 392 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 393 394 callout_init(&sc->sc_selfid_callout); 395 396 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 397 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 398 399 /* 400 * establish hooks for shutdown and suspend/resume 401 */ 402 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 403 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 404 405 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 406 fwohci_print); 407 408 /* Main loop. It's not coming back normally. */ 409 410 fwohci_event_thread(sc); 411 412 kthread_exit(0); 413 } 414 415 static void 416 fwohci_event_thread(struct fwohci_softc *sc) 417 { 418 int i, s; 419 u_int32_t intmask, iso; 420 421 s = splbio(); 422 423 /* 424 * Initialize hardware registers. 425 */ 426 427 fwohci_hw_init(sc); 428 429 /* Initial Bus Reset */ 430 fwohci_phy_busreset(sc); 431 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 432 splx(s); 433 434 while (!sc->sc_dying) { 435 while (1) { 436 s = splbio(); 437 intmask = sc->sc_intmask; 438 if (intmask) { 439 splx(s); 440 if (intmask & OHCI_Int_BusReset) { 441 s = splbio(); 442 sc->sc_intmask &= ~OHCI_Int_BusReset; 443 splx(s); 444 fwohci_buf_stop(sc); 445 fwohci_buf_init(sc); 446 if (sc->sc_uidtbl != NULL) { 447 free(sc->sc_uidtbl, M_DEVBUF); 448 sc->sc_uidtbl = NULL; 449 } 450 451 callout_reset(&sc->sc_selfid_callout, 452 OHCI_SELFID_TIMEOUT, 453 (void (*)(void *)) 454 fwohci_phy_busreset, sc); 455 sc->sc_nodeid = 0xffff; /* indicate 456 invalid */ 457 sc->sc_rootid = 0; 458 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 459 } 460 if (intmask & OHCI_Int_SelfIDComplete) { 461 s = splbio(); 462 sc->sc_intmask &= 463 ~OHCI_Int_SelfIDComplete; 464 OHCI_CSR_WRITE(sc, 465 OHCI_REG_IntEventClear, 466 OHCI_Int_BusReset); 467 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 468 OHCI_Int_BusReset); 469 splx(s); 470 callout_stop(&sc->sc_selfid_callout); 471 if (fwohci_selfid_input(sc) == 0) { 472 fwohci_buf_start(sc); 473 fwohci_uid_collect(sc); 474 } 475 } 476 if (intmask & OHCI_Int_ReqTxComplete) { 477 s = splbio(); 478 sc->sc_intmask &= 479 ~OHCI_Int_ReqTxComplete; 480 splx(s); 481 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 482 } 483 if (intmask & OHCI_Int_RespTxComplete) { 484 s = splbio(); 485 sc->sc_intmask &= 486 ~OHCI_Int_RespTxComplete; 487 splx(s); 488 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 489 } 490 if (intmask & OHCI_Int_RQPkt) { 491 s = splbio(); 492 sc->sc_intmask &= ~OHCI_Int_RQPkt; 493 splx(s); 494 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 495 } 496 if (intmask & OHCI_Int_RSPkt) { 497 s = splbio(); 498 sc->sc_intmask &= ~OHCI_Int_RSPkt; 499 splx(s); 500 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 501 } 502 if (intmask & OHCI_Int_IsochTx) { 503 s = splbio(); 504 sc->sc_intmask &= ~OHCI_Int_IsochTx; 505 splx(s); 506 } 507 if (intmask & OHCI_Int_IsochRx) { 508 s = splbio(); 509 sc->sc_intmask &= ~OHCI_Int_IsochRx; 510 iso = sc->sc_iso; 511 sc->sc_iso = 0; 512 splx(s); 513 for (i = 0; i < sc->sc_isoctx; i++) { 514 if ((iso & (1 << i)) && 515 sc->sc_ctx_ir[i] != NULL) 516 fwohci_ir_input(sc, 517 sc->sc_ctx_ir[i]); 518 } 519 } 520 } else 521 break; 522 } 523 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 524 splx(s); 525 } 526 } 527 528 #if 0 529 static int 530 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 531 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 532 { 533 bus_dma_segment_t segs[1]; 534 int error, nsegs, steps; 535 536 steps = 0; 537 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 538 segs, 1, &nsegs, flags); 539 if (error) 540 goto cleanup; 541 542 steps = 1; 543 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 544 kvap, flags); 545 if (error) 546 goto cleanup; 547 548 if (error == 0) 549 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 550 size, flags, mapp); 551 if (error) 552 goto cleanup; 553 if (error == 0) 554 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 555 flags); 556 if (error) 557 goto cleanup; 558 559 cleanup: 560 switch (steps) { 561 case 1: 562 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 563 } 564 565 return error; 566 } 567 #endif 568 569 int 570 fwohci_print(void *aux, const char *pnp) 571 { 572 char *name = aux; 573 574 if (pnp) 575 printf("%s at %s", name, pnp); 576 577 return QUIET; 578 } 579 580 static void 581 fwohci_hw_init(struct fwohci_softc *sc) 582 { 583 int i; 584 u_int32_t val; 585 586 /* 587 * Software Reset. 588 */ 589 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 590 for (i = 0; i < OHCI_LOOP; i++) { 591 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 592 if ((val & OHCI_HCControl_SoftReset) == 0) 593 break; 594 } 595 596 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 597 598 /* 599 * First, initilize CSRs with undefined value to default settings. 600 */ 601 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 602 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 603 #if 0 604 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 605 #else 606 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 607 #endif 608 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 609 for (i = 0; i < sc->sc_isoctx; i++) { 610 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 611 ~0); 612 } 613 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 614 615 fwohci_configrom_init(sc); 616 fwohci_selfid_init(sc); 617 fwohci_buf_init(sc); 618 fwohci_csr_init(sc); 619 620 /* 621 * Final CSR settings. 622 */ 623 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 624 OHCI_LinkControl_CycleTimerEnable | 625 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 626 627 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 628 629 /* clear receive filter */ 630 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 631 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 632 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 633 634 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 635 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 636 #if BYTE_ORDER == BIG_ENDIAN 637 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 638 OHCI_HCControl_NoByteSwapData); 639 #endif 640 641 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 642 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 643 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 644 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 645 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 646 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 647 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 648 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 649 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 650 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 651 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 652 653 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 654 655 /* 656 * Start the receivers 657 */ 658 fwohci_buf_start(sc); 659 } 660 661 static void 662 fwohci_power(int why, void *arg) 663 { 664 struct fwohci_softc *sc = arg; 665 int s; 666 667 s = splbio(); 668 switch (why) { 669 case PWR_SUSPEND: 670 case PWR_STANDBY: 671 fwohci_shutdown(sc); 672 break; 673 case PWR_RESUME: 674 fwohci_hw_init(sc); 675 fwohci_phy_busreset(sc); 676 break; 677 case PWR_SOFTSUSPEND: 678 case PWR_SOFTSTANDBY: 679 case PWR_SOFTRESUME: 680 break; 681 } 682 splx(s); 683 } 684 685 static void 686 fwohci_shutdown(void *arg) 687 { 688 struct fwohci_softc *sc = arg; 689 u_int32_t val; 690 691 callout_stop(&sc->sc_selfid_callout); 692 /* disable all interrupt */ 693 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 694 fwohci_buf_stop(sc); 695 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 696 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 697 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 698 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 699 fwohci_phy_busreset(sc); 700 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 701 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 702 } 703 704 /* 705 * COMMON FUNCTIONS 706 */ 707 708 /* 709 * read the PHY Register. 710 */ 711 static u_int8_t 712 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 713 { 714 int i; 715 u_int32_t val; 716 717 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 718 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 719 for (i = 0; i < OHCI_LOOP; i++) { 720 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 721 OHCI_PhyControl_RdDone) 722 break; 723 } 724 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 725 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 726 } 727 728 /* 729 * write the PHY Register. 730 */ 731 static void 732 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 733 { 734 int i; 735 736 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 737 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 738 (val << OHCI_PhyControl_WrData_BITPOS)); 739 for (i = 0; i < OHCI_LOOP; i++) { 740 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 741 OHCI_PhyControl_WrReg)) 742 break; 743 } 744 } 745 746 /* 747 * Initiate Bus Reset 748 */ 749 static void 750 fwohci_phy_busreset(struct fwohci_softc *sc) 751 { 752 int s; 753 u_int8_t val; 754 755 s = splbio(); 756 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 757 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 758 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 759 callout_stop(&sc->sc_selfid_callout); 760 val = fwohci_phy_read(sc, 1); 761 val = (val & 0x80) | /* preserve RHB (force root) */ 762 0x40 | /* Initiate Bus Reset */ 763 0x3f; /* default GAP count */ 764 fwohci_phy_write(sc, 1, val); 765 splx(s); 766 } 767 768 /* 769 * PHY Packet 770 */ 771 static void 772 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 773 { 774 u_int32_t val; 775 776 val = pkt->fp_hdr[1]; 777 if (val != ~pkt->fp_hdr[2]) { 778 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 779 OHCI_CTXCTL_EVENT_BUS_RESET) { 780 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 781 pkt->fp_hdr[2])); 782 } else { 783 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 784 sc->sc_sc1394.sc1394_dev.dv_xname, val, 785 pkt->fp_hdr[2]); 786 } 787 return; 788 } 789 #ifdef FW_DEBUG 790 if (fwdebug > 1) 791 fwohci_show_phypkt(sc, val); 792 #endif 793 } 794 795 /* 796 * Descriptor for context DMA. 797 */ 798 static int 799 fwohci_desc_alloc(struct fwohci_softc *sc) 800 { 801 int error, mapsize, dsize; 802 803 /* 804 * allocate descriptor buffer 805 */ 806 807 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 808 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 809 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 810 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 811 mapsize = howmany(sc->sc_descsize, NBBY); 812 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 813 memset(sc->sc_descmap, 0, mapsize); 814 815 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 816 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 817 printf("%s: unable to allocate descriptor buffer, error = %d\n", 818 sc->sc_sc1394.sc1394_dev.dv_xname, error); 819 goto fail_0; 820 } 821 822 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 823 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 824 != 0) { 825 printf("%s: unable to map descriptor buffer, error = %d\n", 826 sc->sc_sc1394.sc1394_dev.dv_xname, error); 827 goto fail_1; 828 } 829 830 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 831 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 832 printf("%s: unable to create descriptor buffer DMA map, " 833 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 834 goto fail_2; 835 } 836 837 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 838 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 839 printf("%s: unable to load descriptor buffer DMA map, " 840 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 841 goto fail_3; 842 } 843 844 return 0; 845 846 fail_3: 847 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 848 fail_2: 849 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 850 fail_1: 851 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 852 fail_0: 853 return error; 854 } 855 856 static struct fwohci_desc * 857 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 858 { 859 int i, n; 860 861 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 862 for (i = 0; ; i++) { 863 if (i == ndesc) { 864 for (i = 0; i < ndesc; i++) 865 setbit(sc->sc_descmap, n + i); 866 return sc->sc_desc + n; 867 } 868 if (isset(sc->sc_descmap, n + i)) 869 break; 870 } 871 } 872 return NULL; 873 } 874 875 static void 876 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 877 { 878 int i, n; 879 880 n = fd - sc->sc_desc; 881 for (i = 0; i < ndesc; i++, n++) { 882 #ifdef DIAGNOSTIC 883 if (isclr(sc->sc_descmap, n)) 884 panic("fwohci_desc_put: duplicated free"); 885 #endif 886 clrbit(sc->sc_descmap, n); 887 } 888 } 889 890 /* 891 * Asyncronous/Isochronous Transmit/Receive Context 892 */ 893 static int 894 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 895 int bufcnt, int ctx) 896 { 897 int i, error; 898 struct fwohci_ctx *fc; 899 struct fwohci_buf *fb; 900 struct fwohci_desc *fd; 901 902 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 903 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 904 LIST_INIT(&fc->fc_handler); 905 TAILQ_INIT(&fc->fc_buf); 906 fc->fc_ctx = ctx; 907 fc->fc_bufcnt = bufcnt; 908 fb = (struct fwohci_buf *)&fc[1]; 909 for (i = 0; i < bufcnt; i++, fb++) { 910 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 911 goto fail; 912 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 913 error = ENOBUFS; 914 goto fail; 915 } 916 fb->fb_desc = fd; 917 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 918 ((caddr_t)fd - (caddr_t)sc->sc_desc); 919 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 920 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 921 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 922 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 923 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 924 } 925 *fcp = fc; 926 return 0; 927 928 fail: 929 while (i-- > 0) 930 fwohci_buf_free(sc, --fb); 931 free(fc, M_DEVBUF); 932 return error; 933 } 934 935 static void 936 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 937 { 938 struct fwohci_buf *fb; 939 struct fwohci_handler *fh; 940 941 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 942 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 943 NULL, NULL); 944 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 945 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 946 fwohci_buf_free(sc, fb); 947 } 948 free(fc, M_DEVBUF); 949 } 950 951 static void 952 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 953 { 954 struct fwohci_buf *fb, *nfb; 955 struct fwohci_desc *fd; 956 struct fwohci_handler *fh; 957 int n; 958 959 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 960 nfb = TAILQ_NEXT(fb, fb_list); 961 fb->fb_off = 0; 962 fd = fb->fb_desc; 963 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 964 fd->fd_rescount = fd->fd_reqcount; 965 } 966 967 n = fc->fc_ctx; 968 fb = TAILQ_FIRST(&fc->fc_buf); 969 if (fc->fc_isoch) { 970 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 971 fb->fb_daddr | 1); 972 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 973 OHCI_CTXCTL_RX_BUFFER_FILL | 974 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 975 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 976 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 977 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 978 OHCI_CTXCTL_RX_ISOCH_HEADER); 979 fh = LIST_FIRST(&fc->fc_handler); 980 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 981 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 982 } else { 983 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 984 fb->fb_daddr | 1); 985 } 986 } 987 988 /* 989 * DMA data buffer 990 */ 991 static int 992 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 993 { 994 int error; 995 996 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 997 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 998 printf("%s: unable to allocate buffer, error = %d\n", 999 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1000 goto fail_0; 1001 } 1002 1003 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1004 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1005 printf("%s: unable to map buffer, error = %d\n", 1006 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1007 goto fail_1; 1008 } 1009 1010 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1011 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1012 printf("%s: unable to create buffer DMA map, " 1013 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1014 error); 1015 goto fail_2; 1016 } 1017 1018 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1019 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1020 printf("%s: unable to load buffer DMA map, " 1021 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1022 error); 1023 goto fail_3; 1024 } 1025 1026 return 0; 1027 1028 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1029 fail_3: 1030 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1031 fail_2: 1032 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1033 fail_1: 1034 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1035 fail_0: 1036 return error; 1037 } 1038 1039 static void 1040 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1041 { 1042 1043 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1044 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1045 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1046 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1047 } 1048 1049 static void 1050 fwohci_buf_init(struct fwohci_softc *sc) 1051 { 1052 int i; 1053 1054 /* 1055 * Initialize for Asynchronous Transmit Queue. 1056 */ 1057 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1058 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1059 1060 /* 1061 * Initialize for Asynchronous Receive Queue. 1062 */ 1063 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1064 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1065 1066 /* 1067 * Initialize for Isochronous Receive Queue. 1068 */ 1069 for (i = 0; i < sc->sc_isoctx; i++) { 1070 if (sc->sc_ctx_ir[i] != NULL) 1071 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1072 } 1073 } 1074 1075 static void 1076 fwohci_buf_start(struct fwohci_softc *sc) 1077 { 1078 int i; 1079 1080 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1081 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1082 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1083 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1084 for (i = 0; i < sc->sc_isoctx; i++) { 1085 if (sc->sc_ctx_ir[i] != NULL && 1086 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1087 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1088 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1089 } 1090 } 1091 } 1092 1093 static void 1094 fwohci_buf_stop(struct fwohci_softc *sc) 1095 { 1096 int i, j; 1097 1098 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1099 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1100 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1101 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1102 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1103 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1104 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1105 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1106 for (i = 0; i < sc->sc_isoctx; i++) { 1107 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1108 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1109 } 1110 1111 /* 1112 * Make sure the transmitter is stopped. 1113 */ 1114 for (j = 0; j < OHCI_LOOP; j++) { 1115 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1116 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1117 continue; 1118 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1119 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1120 continue; 1121 break; 1122 } 1123 } 1124 1125 static void 1126 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1127 { 1128 struct fwohci_buf *fb, *tfb; 1129 1130 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1131 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1132 fb->fb_desc->fd_rescount != 0) 1133 break; 1134 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1135 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1136 fb->fb_off = 0; 1137 fb->fb_desc->fd_branch = 0; 1138 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1139 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1140 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1141 } 1142 } 1143 1144 static int 1145 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1146 int len) 1147 { 1148 struct fwohci_buf *fb; 1149 struct fwohci_desc *fd; 1150 int bufend; 1151 1152 fb = TAILQ_FIRST(&fc->fc_buf); 1153 again: 1154 fd = fb->fb_desc; 1155 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1156 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1157 fd->fd_reqcount, fd->fd_rescount, len, 1158 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1159 bufend = fd->fd_reqcount - fd->fd_rescount; 1160 if (fb->fb_off >= bufend) { 1161 if (fc->fc_isoch && fb->fb_off > 0) { 1162 fb->fb_off = fd->fd_reqcount; 1163 fd->fd_rescount = 0; 1164 } 1165 if (fd->fd_rescount == 0) { 1166 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1167 goto again; 1168 } 1169 return 0; 1170 } 1171 if (fb->fb_off + len > bufend) 1172 len = bufend - fb->fb_off; 1173 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1174 BUS_DMASYNC_POSTREAD); 1175 *pp = fb->fb_buf + fb->fb_off; 1176 fb->fb_off += roundup(len, 4); 1177 return len; 1178 } 1179 1180 static int 1181 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1182 struct fwohci_pkt *pkt) 1183 { 1184 caddr_t p; 1185 int len, count, i; 1186 1187 memset(pkt, 0, sizeof(*pkt)); 1188 pkt->fp_uio.uio_iov = pkt->fp_iov; 1189 pkt->fp_uio.uio_rw = UIO_WRITE; 1190 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1191 1192 /* get first quadlet */ 1193 count = 4; 1194 if (fc->fc_isoch) { 1195 /* 1196 * get trailer first, may be bogus data unless status update 1197 * in descriptor is set. 1198 */ 1199 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1200 sizeof(*pkt->fp_trail)); 1201 if (len <= 0) { 1202 DPRINTFN(1, ("fwohci_buf_input: no input for is#%d\n", 1203 fc->fc_ctx)); 1204 return 0; 1205 } 1206 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1207 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1208 } 1209 len = fwohci_buf_pktget(sc, fc, &p, count); 1210 if (len <= 0) { 1211 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1212 fc->fc_ctx)); 1213 return 0; 1214 } 1215 pkt->fp_hdr[0] = *(u_int32_t *)p; 1216 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1217 switch (pkt->fp_tcode) { 1218 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1219 case IEEE1394_TCODE_READ_RESP_QUAD: 1220 pkt->fp_hlen = 12; 1221 pkt->fp_dlen = 4; 1222 break; 1223 case IEEE1394_TCODE_READ_REQ_BLOCK: 1224 pkt->fp_hlen = 16; 1225 pkt->fp_dlen = 0; 1226 break; 1227 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1228 case IEEE1394_TCODE_READ_RESP_BLOCK: 1229 case IEEE1394_TCODE_LOCK_REQ: 1230 case IEEE1394_TCODE_LOCK_RESP: 1231 pkt->fp_hlen = 16; 1232 break; 1233 case IEEE1394_TCODE_STREAM_DATA: 1234 pkt->fp_hlen = 4; 1235 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1236 break; 1237 default: 1238 pkt->fp_hlen = 12; 1239 pkt->fp_dlen = 0; 1240 break; 1241 } 1242 1243 /* get header */ 1244 while (count < pkt->fp_hlen) { 1245 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1246 if (len == 0) { 1247 printf("fwohci_buf_input: malformed input 1: %d\n", 1248 pkt->fp_hlen - count); 1249 return 0; 1250 } 1251 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1252 count += len; 1253 } 1254 if ((pkt->fp_hlen == 16) && 1255 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1256 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1257 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1258 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1259 1260 /* get data */ 1261 count = 0; 1262 i = 0; 1263 while (count < pkt->fp_dlen) { 1264 len = fwohci_buf_pktget(sc, fc, 1265 (caddr_t *)&pkt->fp_iov[i].iov_base, 1266 pkt->fp_dlen - count); 1267 if (len == 0) { 1268 printf("fwohci_buf_input: malformed input 2: %d\n", 1269 pkt->fp_hlen - count); 1270 return 0; 1271 } 1272 pkt->fp_iov[i++].iov_len = len; 1273 count += len; 1274 } 1275 pkt->fp_uio.uio_iovcnt = i; 1276 pkt->fp_uio.uio_resid = count; 1277 1278 if (!fc->fc_isoch) { 1279 /* get trailer */ 1280 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1281 sizeof(*pkt->fp_trail)); 1282 if (len <= 0) { 1283 printf("fwohci_buf_input: malformed input 3: %d\n", 1284 pkt->fp_hlen - count); 1285 return 0; 1286 } 1287 } 1288 return 1; 1289 } 1290 1291 static int 1292 fwohci_handler_set(struct fwohci_softc *sc, 1293 int tcode, u_int32_t key1, u_int32_t key2, 1294 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1295 void *arg) 1296 { 1297 struct fwohci_ctx *fc; 1298 struct fwohci_handler *fh; 1299 int i, j; 1300 1301 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1302 j = sc->sc_isoctx; 1303 fh = NULL; 1304 for (i = 0; i < sc->sc_isoctx; i++) { 1305 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1306 if (j == sc->sc_isoctx) 1307 j = i; 1308 continue; 1309 } 1310 fh = LIST_FIRST(&fc->fc_handler); 1311 if (fh == NULL) { 1312 j = i; 1313 break; 1314 } 1315 if (fh->fh_tcode == tcode && 1316 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1317 break; 1318 fh = NULL; 1319 } 1320 if (fh == NULL) { 1321 if (handler == NULL) 1322 return 0; 1323 if (j == sc->sc_isoctx) { 1324 DPRINTF(("fwohci_handler_set: no more free " 1325 "context\n")); 1326 return ENOMEM; 1327 } 1328 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1329 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1330 fc->fc_isoch = 1; 1331 sc->sc_ctx_ir[j] = fc; 1332 } 1333 } 1334 } else { 1335 switch (tcode) { 1336 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1337 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1338 case IEEE1394_TCODE_READ_REQ_QUAD: 1339 case IEEE1394_TCODE_READ_REQ_BLOCK: 1340 case IEEE1394_TCODE_LOCK_REQ: 1341 fc = sc->sc_ctx_arrq; 1342 break; 1343 case IEEE1394_TCODE_WRITE_RESP: 1344 case IEEE1394_TCODE_READ_RESP_QUAD: 1345 case IEEE1394_TCODE_READ_RESP_BLOCK: 1346 case IEEE1394_TCODE_LOCK_RESP: 1347 fc = sc->sc_ctx_arrs; 1348 break; 1349 default: 1350 return EIO; 1351 } 1352 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1353 fh = LIST_NEXT(fh, fh_list)) { 1354 if (fh->fh_tcode == tcode && 1355 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1356 break; 1357 } 1358 } 1359 if (handler == NULL) { 1360 if (fh != NULL) { 1361 LIST_REMOVE(fh, fh_list); 1362 free(fh, M_DEVBUF); 1363 } 1364 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1365 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1366 fwohci_ctx_free(sc, fc); 1367 } 1368 return 0; 1369 } 1370 if (fh == NULL) { 1371 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1372 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1373 } 1374 fh->fh_tcode = tcode; 1375 fh->fh_key1 = key1; 1376 fh->fh_key2 = key2; 1377 fh->fh_handler = handler; 1378 fh->fh_handarg = arg; 1379 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1380 fc->fc_ctx, tcode, key1, key2)); 1381 1382 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1383 fwohci_ctx_init(sc, fc); 1384 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1385 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1386 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1387 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1388 } 1389 return 0; 1390 } 1391 1392 /* 1393 * Asyncronous Receive Requests input frontend. 1394 */ 1395 static void 1396 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1397 { 1398 int rcode; 1399 u_int32_t key1, key2; 1400 struct fwohci_handler *fh; 1401 struct fwohci_pkt pkt, res; 1402 1403 while (fwohci_buf_input(sc, fc, &pkt)) { 1404 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1405 fwohci_phy_input(sc, &pkt); 1406 return; 1407 } 1408 key1 = pkt.fp_hdr[1] & 0xffff; 1409 key2 = pkt.fp_hdr[2]; 1410 memset(&res, 0, sizeof(res)); 1411 res.fp_uio.uio_rw = UIO_WRITE; 1412 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1413 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1414 fh = LIST_NEXT(fh, fh_list)) { 1415 if (pkt.fp_tcode == fh->fh_tcode && 1416 key1 == fh->fh_key1 && 1417 key2 == fh->fh_key2) { 1418 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1419 &pkt); 1420 break; 1421 } 1422 } 1423 if (fh == NULL) { 1424 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1425 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1426 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1427 key2)); 1428 } 1429 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1430 OHCI_CTXCTL_EVENT_ACK_PENDING) 1431 return; 1432 if (rcode != -1) 1433 fwohci_atrs_output(sc, rcode, &pkt, &res); 1434 } 1435 fwohci_buf_next(sc, fc); 1436 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1437 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1438 } 1439 1440 1441 /* 1442 * Asynchronous Receive Response input frontend. 1443 */ 1444 static void 1445 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1446 { 1447 struct fwohci_pkt pkt; 1448 struct fwohci_handler *fh; 1449 u_int16_t srcid; 1450 int rcode, tlabel; 1451 1452 while (fwohci_buf_input(sc, fc, &pkt)) { 1453 srcid = pkt.fp_hdr[1] >> 16; 1454 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1455 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1456 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1457 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1458 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1459 pkt.fp_dlen)); 1460 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1461 fh = LIST_NEXT(fh, fh_list)) { 1462 if (pkt.fp_tcode == fh->fh_tcode && 1463 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1464 tlabel == fh->fh_key2) { 1465 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1466 LIST_REMOVE(fh, fh_list); 1467 free(fh, M_DEVBUF); 1468 break; 1469 } 1470 } 1471 if (fh == NULL) 1472 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1473 } 1474 fwohci_buf_next(sc, fc); 1475 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1476 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1477 } 1478 1479 /* 1480 * Isochronous Receive input frontend. 1481 */ 1482 static void 1483 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1484 { 1485 int rcode, chan, tag; 1486 struct iovec *iov; 1487 struct fwohci_handler *fh; 1488 struct fwohci_pkt pkt; 1489 1490 while (fwohci_buf_input(sc, fc, &pkt)) { 1491 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1492 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1493 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1494 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1495 pkt.fp_dlen)); 1496 if (tag == IEEE1394_TAG_GASP) { 1497 /* 1498 * The pkt with tag=3 is GASP format. 1499 * Move GASP header to header part. 1500 */ 1501 if (pkt.fp_dlen < 8) 1502 continue; 1503 iov = pkt.fp_iov; 1504 /* assuming pkt per buffer mode */ 1505 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1506 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1507 iov->iov_base = (caddr_t)iov->iov_base + 8; 1508 iov->iov_len -= 8; 1509 pkt.fp_hlen += 8; 1510 pkt.fp_dlen -= 8; 1511 } 1512 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1513 fh = LIST_NEXT(fh, fh_list)) { 1514 if (pkt.fp_tcode == fh->fh_tcode && 1515 chan == fh->fh_key1 && tag == fh->fh_key2) { 1516 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1517 &pkt); 1518 break; 1519 } 1520 } 1521 #ifdef FW_DEBUG 1522 if (fh == NULL) { 1523 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1524 } else { 1525 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1526 } 1527 #endif 1528 } 1529 fwohci_buf_next(sc, fc); 1530 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1531 OHCI_CTXCTL_WAKE); 1532 } 1533 1534 /* 1535 * Asynchronous Transmit common routine. 1536 */ 1537 static int 1538 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1539 struct fwohci_pkt *pkt) 1540 { 1541 struct fwohci_buf *fb; 1542 struct fwohci_desc *fd; 1543 struct mbuf *m, *m0; 1544 int i, ndesc, error, off, len; 1545 u_int32_t val; 1546 #ifdef FW_DEBUG 1547 struct iovec *iov; 1548 #endif 1549 1550 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1551 /* We can't send anything during selfid duration */ 1552 return EAGAIN; 1553 1554 #ifdef FW_DEBUG 1555 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1556 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1557 for (i = 0; i < pkt->fp_hlen/4; i++) 1558 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 1559 DPRINTFN(2, ("$")); 1560 for (ndesc = 0, iov = pkt->fp_iov; 1561 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1562 for (i = 0; i < iov->iov_len; i++) 1563 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1564 ((u_int8_t *)iov->iov_base)[i])); 1565 DPRINTFN(2, ("$")); 1566 } 1567 DPRINTFN(1, ("\n")); 1568 #endif 1569 1570 if ((m = pkt->fp_m) != NULL) { 1571 for (ndesc = 2; m != NULL; m = m->m_next) 1572 ndesc++; 1573 if (ndesc > OHCI_DESC_MAX) { 1574 m0 = NULL; 1575 ndesc = 2; 1576 for (off = 0; off < pkt->fp_dlen; off += len) { 1577 if (m0 == NULL) { 1578 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1579 if (m0 != NULL) 1580 M_COPY_PKTHDR(m0, pkt->fp_m); 1581 m = m0; 1582 } else { 1583 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1584 m = m->m_next; 1585 } 1586 if (m != NULL) 1587 MCLGET(m, M_DONTWAIT); 1588 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1589 m_freem(m0); 1590 return ENOMEM; 1591 } 1592 len = pkt->fp_dlen - off; 1593 if (len > m->m_ext.ext_size) 1594 len = m->m_ext.ext_size; 1595 m_copydata(pkt->fp_m, off, len, 1596 mtod(m, caddr_t)); 1597 m->m_len = len; 1598 ndesc++; 1599 } 1600 m_freem(pkt->fp_m); 1601 pkt->fp_m = m0; 1602 } 1603 } else 1604 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1605 1606 if (ndesc > OHCI_DESC_MAX) 1607 return ENOBUFS; 1608 1609 if (fc->fc_bufcnt > 50) /*XXX*/ 1610 return ENOBUFS; 1611 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1612 fb->fb_nseg = ndesc; 1613 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1614 if (fb->fb_desc == NULL) { 1615 free(fb, M_DEVBUF); 1616 return ENOBUFS; 1617 } 1618 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1619 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1620 fb->fb_m = pkt->fp_m; 1621 fb->fb_callback = pkt->fp_callback; 1622 fb->fb_statuscb = pkt->fp_statuscb; 1623 fb->fb_statusarg = pkt->fp_statusarg; 1624 1625 if (ndesc > 2) { 1626 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1627 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1628 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1629 free(fb, M_DEVBUF); 1630 return error; 1631 } 1632 1633 if (pkt->fp_m != NULL) 1634 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1635 pkt->fp_m, BUS_DMA_WAITOK); 1636 else 1637 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1638 &pkt->fp_uio, BUS_DMA_WAITOK); 1639 if (error != 0) { 1640 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1641 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1642 free(fb, M_DEVBUF); 1643 return error; 1644 } 1645 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1646 BUS_DMASYNC_PREWRITE); 1647 } 1648 1649 fd = fb->fb_desc; 1650 fd->fd_flags = OHCI_DESC_IMMED; 1651 fd->fd_reqcount = pkt->fp_hlen; 1652 fd->fd_data = 0; 1653 fd->fd_branch = 0; 1654 fd->fd_status = 0; 1655 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1656 i = 3; /* XXX: 3 sec */ 1657 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1658 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1659 ((((val >> 25) + i) & 0x7) << 13); 1660 } else 1661 fd->fd_timestamp = 0; 1662 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1663 for (i = 0; i < ndesc - 2; i++) { 1664 fd = fb->fb_desc + 2 + i; 1665 fd->fd_flags = 0; 1666 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1667 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1668 fd->fd_branch = 0; 1669 fd->fd_status = 0; 1670 fd->fd_timestamp = 0; 1671 } 1672 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1673 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1674 1675 #ifdef FW_DEBUG 1676 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1677 (long)(fb->fb_desc - sc->sc_desc))); 1678 for (i = 0; i < ndesc * 4; i++) 1679 DPRINTFN(1, ("%s%08x", i&7?" ":"\n\t", 1680 ((u_int32_t *)fb->fb_desc)[i])); 1681 DPRINTFN(1, ("\n")); 1682 #endif 1683 1684 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1685 OHCI_SUBREG_ContextControlClear); 1686 1687 if (val & OHCI_CTXCTL_RUN) { 1688 if (fc->fc_branch == NULL) { 1689 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1690 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1691 goto run; 1692 } 1693 *fc->fc_branch = fb->fb_daddr | ndesc; 1694 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1695 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1696 } else { 1697 run: 1698 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1699 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1700 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1701 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1702 } 1703 fc->fc_branch = &fd->fd_branch; 1704 1705 fc->fc_bufcnt++; 1706 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1707 pkt->fp_m = NULL; 1708 return 0; 1709 } 1710 1711 static void 1712 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1713 { 1714 struct fwohci_buf *fb; 1715 struct fwohci_desc *fd; 1716 struct fwohci_pkt pkt; 1717 int i; 1718 1719 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1720 fd = fb->fb_desc; 1721 #ifdef FW_DEBUG 1722 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1723 force ? "force " : "", (long)(fd - sc->sc_desc), 1724 fb->fb_nseg)); 1725 for (i = 0; i < fb->fb_nseg * 4; i++) 1726 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", 1727 ((u_int32_t *)fd)[i])); 1728 DPRINTFN(1, ("\n")); 1729 #endif 1730 if (fb->fb_nseg > 2) 1731 fd += fb->fb_nseg - 1; 1732 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1733 break; 1734 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1735 if (fc->fc_branch == &fd->fd_branch) { 1736 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1737 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1738 fc->fc_branch = NULL; 1739 for (i = 0; i < OHCI_LOOP; i++) { 1740 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1741 OHCI_SUBREG_ContextControlClear) & 1742 OHCI_CTXCTL_ACTIVE)) 1743 break; 1744 } 1745 } 1746 1747 if (fb->fb_statuscb) { 1748 memset(&pkt, 0, sizeof(pkt)); 1749 pkt.fp_status = fd->fd_status; 1750 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1751 1752 /* Indicate this is just returning the status bits. */ 1753 pkt.fp_tcode = -1; 1754 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1755 fb->fb_statuscb = NULL; 1756 fb->fb_statusarg = NULL; 1757 } 1758 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1759 if (fb->fb_nseg > 2) 1760 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1761 fc->fc_bufcnt--; 1762 if (fb->fb_callback) { 1763 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1764 fb->fb_callback = NULL; 1765 } else if (fb->fb_m != NULL) 1766 m_freem(fb->fb_m); 1767 free(fb, M_DEVBUF); 1768 } 1769 } 1770 1771 /* 1772 * Asynchronous Transmit Reponse -- in response of request packet. 1773 */ 1774 static void 1775 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1776 struct fwohci_pkt *res) 1777 { 1778 1779 if (((*req->fp_trail & 0x001f0000) >> 16) != 1780 OHCI_CTXCTL_EVENT_ACK_PENDING) 1781 return; 1782 1783 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1784 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1785 switch (req->fp_tcode) { 1786 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1787 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1788 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1789 res->fp_hlen = 12; 1790 break; 1791 case IEEE1394_TCODE_READ_REQ_QUAD: 1792 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1793 res->fp_hlen = 16; 1794 res->fp_dlen = 0; 1795 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1796 res->fp_hdr[3] = 1797 *(u_int32_t *)res->fp_iov[0].iov_base; 1798 res->fp_uio.uio_iovcnt = 0; 1799 break; 1800 case IEEE1394_TCODE_READ_REQ_BLOCK: 1801 case IEEE1394_TCODE_LOCK_REQ: 1802 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1803 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1804 else 1805 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1806 res->fp_hlen = 16; 1807 res->fp_dlen = res->fp_uio.uio_resid; 1808 res->fp_hdr[3] = res->fp_dlen << 16; 1809 break; 1810 } 1811 res->fp_hdr[0] |= (res->fp_tcode << 4); 1812 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1813 } 1814 1815 /* 1816 * APPLICATION LAYER SERVICES 1817 */ 1818 1819 /* 1820 * Retrieve Global UID from GUID ROM 1821 */ 1822 static int 1823 fwohci_guidrom_init(struct fwohci_softc *sc) 1824 { 1825 int i, n, off; 1826 u_int32_t val1, val2; 1827 1828 /* Extract the Global UID 1829 */ 1830 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1831 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1832 1833 if (val1 != 0 || val2 != 0) { 1834 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1835 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1836 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1837 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1838 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1839 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1840 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1841 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1842 } else { 1843 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1844 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1845 return -1; 1846 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1847 for (i = 0; i < OHCI_LOOP; i++) { 1848 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1849 if (!(val1 & OHCI_Guid_AddrReset)) 1850 break; 1851 } 1852 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1853 val2 = 0; 1854 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1855 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1856 OHCI_Guid_RdStart); 1857 for (i = 0; i < OHCI_LOOP; i++) { 1858 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1859 if (!(val1 & OHCI_Guid_RdStart)) 1860 break; 1861 } 1862 if (n < off) 1863 continue; 1864 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1865 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1866 val2 |= val1; 1867 } 1868 if (val2 == 0) 1869 return -1; 1870 } 1871 return 0; 1872 } 1873 1874 /* 1875 * Initialization for Configuration ROM (no DMA context) 1876 */ 1877 1878 #define CFR_MAXUNIT 20 1879 1880 struct configromctx { 1881 u_int32_t *ptr; 1882 int curunit; 1883 struct { 1884 u_int32_t *start; 1885 int length; 1886 u_int32_t *refer; 1887 int refunit; 1888 } unit[CFR_MAXUNIT]; 1889 }; 1890 1891 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1892 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1893 1894 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1895 1896 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1897 1898 #define CFR_PUT_CRC(cfr, n) \ 1899 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1900 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1901 1902 #define CFR_START_UNIT(cfr, n) \ 1903 do { \ 1904 if ((cfr)->unit[n].refer != NULL) { \ 1905 *(cfr)->unit[n].refer |= \ 1906 (cfr)->ptr - (cfr)->unit[n].refer; \ 1907 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1908 } \ 1909 (cfr)->curunit = (n); \ 1910 (cfr)->unit[n].start = (cfr)->ptr++; \ 1911 } while (0 /* CONSTCOND */) 1912 1913 #define CFR_PUT_REFER(cfr, key, n) \ 1914 do { \ 1915 (cfr)->unit[n].refer = (cfr)->ptr; \ 1916 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1917 *(cfr)->ptr++ = (key) << 24; \ 1918 } while (0 /* CONSTCOND */) 1919 1920 #define CFR_END_UNIT(cfr) \ 1921 do { \ 1922 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1923 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1924 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1925 } while (0 /* CONSTCOND */) 1926 1927 static u_int16_t 1928 fwohci_crc16(u_int32_t *ptr, int len) 1929 { 1930 int shift; 1931 u_int32_t crc, sum, data; 1932 1933 crc = 0; 1934 while (len-- > 0) { 1935 data = *ptr++; 1936 for (shift = 28; shift >= 0; shift -= 4) { 1937 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1938 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1939 } 1940 crc &= 0xffff; 1941 } 1942 return crc; 1943 } 1944 1945 static void 1946 fwohci_configrom_init(struct fwohci_softc *sc) 1947 { 1948 int i, val; 1949 struct fwohci_buf *fb; 1950 u_int32_t *hdr; 1951 struct configromctx cfr; 1952 1953 fb = &sc->sc_buf_cnfrom; 1954 memset(&cfr, 0, sizeof(cfr)); 1955 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1956 1957 /* headers */ 1958 CFR_START_UNIT(&cfr, 0); 1959 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1960 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1961 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1962 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1963 CFR_END_UNIT(&cfr); 1964 /* copy info_length from crc_length */ 1965 *hdr |= (*hdr & 0x00ff0000) << 8; 1966 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1967 1968 /* root directory */ 1969 CFR_START_UNIT(&cfr, 1); 1970 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1971 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1972 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1973 /* spt,64,fix,lst,drq */ 1974 #ifdef INET 1975 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1976 #endif /* INET */ 1977 #ifdef INET6 1978 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1979 #endif /* INET6 */ 1980 CFR_END_UNIT(&cfr); 1981 1982 CFR_START_UNIT(&cfr, 2); 1983 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1984 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1985 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1986 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1987 CFR_END_UNIT(&cfr); 1988 1989 #ifdef INET 1990 /* IPv4 unit directory */ 1991 CFR_START_UNIT(&cfr, 3); 1992 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1993 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1994 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1995 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1996 CFR_END_UNIT(&cfr); 1997 1998 CFR_START_UNIT(&cfr, 6); 1999 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2000 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2001 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2002 CFR_END_UNIT(&cfr); 2003 2004 CFR_START_UNIT(&cfr, 7); 2005 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2006 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2007 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2008 CFR_END_UNIT(&cfr); 2009 #endif /* INET */ 2010 2011 #ifdef INET6 2012 /* IPv6 unit directory */ 2013 CFR_START_UNIT(&cfr, 4); 2014 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2015 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2016 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2017 /* XXX: TBA by IANA */ 2018 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2019 CFR_END_UNIT(&cfr); 2020 2021 CFR_START_UNIT(&cfr, 8); 2022 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2023 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2024 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2025 CFR_END_UNIT(&cfr); 2026 2027 CFR_START_UNIT(&cfr, 9); 2028 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2029 CFR_PUT_DATA1(&cfr, 0); 2030 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2031 CFR_END_UNIT(&cfr); 2032 #endif /* INET6 */ 2033 2034 fb->fb_off = cfr.ptr - hdr; 2035 #ifdef FW_DEBUG 2036 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2037 for (i = 0; i < fb->fb_off; i++) 2038 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2039 DPRINTFN(2, ("\n")); 2040 #endif /* FW_DEBUG */ 2041 2042 /* 2043 * Make network byte order for DMA 2044 */ 2045 for (i = 0; i < fb->fb_off; i++) 2046 HTONL(hdr[i]); 2047 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2048 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2049 2050 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2051 fb->fb_dmamap->dm_segs[0].ds_addr); 2052 2053 /* This register is only valid on OHCI 1.1. */ 2054 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2055 if ((OHCI_Version_GET_Version(val) == 1) && 2056 (OHCI_Version_GET_Revision(val) == 1)) 2057 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2058 OHCI_HCControl_BIBImageValid); 2059 2060 /* Just allow quad reads of the rom. */ 2061 for (i = 0; i < fb->fb_off; i++) 2062 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2063 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2064 fwohci_configrom_input, NULL); 2065 } 2066 2067 static int 2068 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2069 struct fwohci_pkt *pkt) 2070 { 2071 struct fwohci_pkt res; 2072 u_int32_t loc, *rom; 2073 2074 /* This will be used as an array index so size accordingly. */ 2075 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2076 if ((loc & 0x03) != 0) { 2077 /* alignment error */ 2078 return IEEE1394_RCODE_ADDRESS_ERROR; 2079 } 2080 else 2081 loc /= 4; 2082 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2083 2084 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2085 ntohl(rom[loc]))); 2086 2087 memset(&res, 0, sizeof(res)); 2088 res.fp_hdr[3] = rom[loc]; 2089 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2090 return -1; 2091 } 2092 2093 /* 2094 * SelfID buffer (no DMA context) 2095 */ 2096 static void 2097 fwohci_selfid_init(struct fwohci_softc *sc) 2098 { 2099 struct fwohci_buf *fb; 2100 2101 fb = &sc->sc_buf_selfid; 2102 #ifdef DIAGNOSTIC 2103 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2104 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2105 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2106 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2107 #endif 2108 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2109 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2110 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2111 2112 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2113 fb->fb_dmamap->dm_segs[0].ds_addr); 2114 } 2115 2116 static int 2117 fwohci_selfid_input(struct fwohci_softc *sc) 2118 { 2119 int i; 2120 u_int32_t count, val, gen; 2121 u_int32_t *buf; 2122 2123 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2124 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2125 again: 2126 if (val & OHCI_SelfID_Error) { 2127 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2128 return -1; 2129 } 2130 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2131 2132 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2133 0, count << 2, BUS_DMASYNC_POSTREAD); 2134 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2135 2136 #ifdef FW_DEBUG 2137 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2138 val)); 2139 for (i = 0; i < count; i++) 2140 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", buf[i])); 2141 DPRINTFN(1, ("\n")); 2142 #endif /* FW_DEBUG */ 2143 2144 for (i = 1; i < count; i += 2) { 2145 if (buf[i] != ~buf[i + 1]) 2146 break; 2147 if (buf[i] & 0x00000001) 2148 continue; /* more pkt */ 2149 if (buf[i] & 0x00800000) 2150 continue; /* external id */ 2151 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2152 if ((buf[i] & 0x00400800) == 0x00400800) 2153 sc->sc_irmid = sc->sc_rootid; 2154 } 2155 2156 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2157 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2158 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2159 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2160 goto again; 2161 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2162 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2163 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2164 return -1; 2165 } 2166 if (i != count) { 2167 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2168 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2169 #if 1 2170 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2171 /* 2172 * XXX: CXD3222 sometimes fails to DMA 2173 * selfid packet?? 2174 */ 2175 sc->sc_rootid = (count - 1) / 2 - 1; 2176 sc->sc_irmid = sc->sc_rootid; 2177 } else 2178 #endif 2179 return -1; 2180 } 2181 2182 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2183 if ((val & OHCI_NodeId_IDValid) == 0) { 2184 sc->sc_nodeid = 0xffff; /* invalid */ 2185 printf("%s: nodeid is invalid\n", 2186 sc->sc_sc1394.sc1394_dev.dv_xname); 2187 return -1; 2188 } 2189 sc->sc_nodeid = val & 0xffff; 2190 2191 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2192 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2193 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2194 sc->sc_irmid)); 2195 2196 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2197 return -1; 2198 2199 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2200 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2201 OHCI_LinkControl_CycleMaster); 2202 else 2203 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2204 OHCI_LinkControl_CycleMaster); 2205 return 0; 2206 } 2207 2208 /* 2209 * some CSRs are handled by driver. 2210 */ 2211 static void 2212 fwohci_csr_init(struct fwohci_softc *sc) 2213 { 2214 int i; 2215 static u_int32_t csr[] = { 2216 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2217 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2218 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2219 CSR_SB_BROADCAST_CHANNEL 2220 }; 2221 2222 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2223 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2224 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2225 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2226 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2227 } 2228 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2229 } 2230 2231 static int 2232 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2233 { 2234 struct fwohci_pkt res; 2235 u_int32_t reg; 2236 2237 /* 2238 * XXX need to do special functionality other than just r/w... 2239 */ 2240 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2241 2242 if ((reg & 0x03) != 0) { 2243 /* alignment error */ 2244 return IEEE1394_RCODE_ADDRESS_ERROR; 2245 } 2246 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2247 *(u_int32_t *)(&sc->sc_csr[reg]))); 2248 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2249 DPRINTFN(1, (" -> 0x%08x\n", 2250 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2251 *(u_int32_t *)&sc->sc_csr[reg] = 2252 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2253 } else { 2254 DPRINTFN(1, ("\n")); 2255 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2256 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2257 res.fp_iov[0].iov_len = 4; 2258 res.fp_uio.uio_resid = 4; 2259 res.fp_uio.uio_iovcnt = 1; 2260 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2261 return -1; 2262 } 2263 return IEEE1394_RCODE_COMPLETE; 2264 } 2265 2266 /* 2267 * Mapping between nodeid and unique ID (EUI-64). 2268 * 2269 * Track old mappings and simply update their devices with the new id's when 2270 * they match an existing EUI. This allows proper renumeration of the bus. 2271 */ 2272 static void 2273 fwohci_uid_collect(struct fwohci_softc *sc) 2274 { 2275 int i; 2276 struct fwohci_uidtbl *fu; 2277 struct fwohci_pkt pkt; 2278 struct ieee1394_softc *iea; 2279 2280 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2281 iea->sc1394_node_id = 0xffff; 2282 2283 if (sc->sc_uidtbl != NULL) 2284 free(sc->sc_uidtbl, M_DEVBUF); 2285 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2286 M_WAITOK); 2287 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2288 2289 memset(&pkt, 0, sizeof(pkt)); 2290 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2291 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2292 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2293 fu->fu_valid = 3; 2294 2295 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2296 if (iea) { 2297 iea->sc1394_node_id = i; 2298 DPRINTF(("%s: Updating nodeid to %d\n", 2299 iea->sc1394_dev.dv_xname, 2300 iea->sc1394_node_id)); 2301 } 2302 continue; 2303 } 2304 fu->fu_valid = 0; 2305 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2306 pkt.fp_hlen = 12; 2307 pkt.fp_dlen = 0; 2308 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2309 (pkt.fp_tcode << 4); 2310 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2311 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2312 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2313 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2314 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2315 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2316 2317 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2318 (pkt.fp_tcode << 4); 2319 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2320 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2321 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2322 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2323 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2324 2325 } 2326 if (sc->sc_rootid == 0) 2327 fwohci_check_nodes(sc); 2328 } 2329 2330 static int 2331 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2332 { 2333 struct fwohci_uidtbl *fu; 2334 struct ieee1394_softc *iea; 2335 struct ieee1394_attach_args fwa; 2336 int i, n, done, rcode, found; 2337 2338 found = 0; 2339 2340 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2341 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2342 if (rcode != IEEE1394_RCODE_COMPLETE || 2343 sc->sc_uidtbl == NULL || 2344 n > sc->sc_rootid) 2345 return 0; 2346 fu = &sc->sc_uidtbl[n]; 2347 if (arg == 0) { 2348 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2349 fu->fu_valid |= 0x1; 2350 } else { 2351 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2352 fu->fu_valid |= 0x2; 2353 } 2354 #ifdef FW_DEBUG 2355 if (fu->fu_valid == 0x3) 2356 DPRINTFN(1, ("fwohci_uid_input: " 2357 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2358 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2359 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2360 #endif 2361 if (fu->fu_valid == 0x3) { 2362 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2363 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2364 found = 1; 2365 iea->sc1394_node_id = n; 2366 DPRINTF(("%s: Updating nodeid to %d\n", 2367 iea->sc1394_dev.dv_xname, 2368 iea->sc1394_node_id)); 2369 break; 2370 } 2371 if (!found) { 2372 strcpy(fwa.name, "fwnode"); 2373 memcpy(fwa.uid, fu->fu_uid, 8); 2374 fwa.nodeid = n; 2375 fwa.read = fwohci_read; 2376 fwa.write = fwohci_write; 2377 fwa.inreg = fwohci_inreg; 2378 iea = (struct ieee1394_softc *) 2379 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2380 fwohci_print, fwohci_submatch); 2381 if (iea != NULL) 2382 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2383 sc1394_node); 2384 } 2385 } 2386 done = 1; 2387 2388 for (i = 0; i < sc->sc_rootid + 1; i++) { 2389 fu = &sc->sc_uidtbl[i]; 2390 if (fu->fu_valid != 0x3) { 2391 done = 0; 2392 break; 2393 } 2394 } 2395 if (done) 2396 fwohci_check_nodes(sc); 2397 2398 return 0; 2399 } 2400 2401 static void 2402 fwohci_check_nodes(struct fwohci_softc *sc) 2403 { 2404 struct device *detach = NULL; 2405 struct ieee1394_softc *iea; 2406 2407 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2408 2409 /* 2410 * Have to defer detachment until the next 2411 * loop iteration since config_detach 2412 * free's the softc and the loop iterator 2413 * needs data from the softc to move 2414 * forward. 2415 */ 2416 2417 if (detach) { 2418 config_detach(detach, 0); 2419 detach = NULL; 2420 } 2421 if (iea->sc1394_node_id == 0xffff) { 2422 detach = (struct device *)iea; 2423 LIST_REMOVE(iea, sc1394_node); 2424 } 2425 } 2426 if (detach) 2427 config_detach(detach, 0); 2428 } 2429 2430 static int 2431 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2432 { 2433 struct fwohci_uidtbl *fu; 2434 int n; 2435 static const u_int8_t bcast[] = 2436 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2437 2438 fu = sc->sc_uidtbl; 2439 if (fu == NULL) { 2440 notfound: 2441 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2442 return IEEE1394_BCAST_PHY_ID; 2443 fwohci_uid_collect(sc); /* try to get */ 2444 return -1; 2445 } 2446 for (n = 0; ; n++, fu++) { 2447 if (n > sc->sc_rootid) 2448 goto notfound; 2449 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2450 break; 2451 } 2452 return n; 2453 } 2454 2455 /* 2456 * functions to support network interface 2457 */ 2458 static int 2459 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2460 void (*handler)(struct device *, struct mbuf *)) 2461 { 2462 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2463 2464 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2465 fwohci_if_input, handler); 2466 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2467 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2468 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2469 return 0; 2470 } 2471 2472 static int 2473 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2474 { 2475 int n, len; 2476 struct mbuf *m; 2477 struct iovec *iov; 2478 void (*handler)(struct device *, struct mbuf *) = arg; 2479 2480 #ifdef FW_DEBUG 2481 int i; 2482 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2483 pkt->fp_dlen)); 2484 for (i = 0; i < pkt->fp_hlen/4; i++) 2485 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2486 DPRINTFN(2, ("$")); 2487 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2488 iov = &pkt->fp_iov[n]; 2489 for (i = 0; i < iov->iov_len; i++) 2490 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 2491 ((u_int8_t *)iov->iov_base)[i])); 2492 DPRINTFN(2, ("$")); 2493 } 2494 DPRINTFN(1, ("\n")); 2495 #endif /* FW_DEBUG */ 2496 len = pkt->fp_dlen; 2497 MGETHDR(m, M_DONTWAIT, MT_DATA); 2498 if (m == NULL) 2499 return IEEE1394_RCODE_COMPLETE; 2500 m->m_len = 16; 2501 if (len + m->m_len > MHLEN) { 2502 MCLGET(m, M_DONTWAIT); 2503 if ((m->m_flags & M_EXT) == 0) { 2504 m_freem(m); 2505 return IEEE1394_RCODE_COMPLETE; 2506 } 2507 } 2508 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2509 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2510 sc->sc_uidtbl[n].fu_valid != 0x3) { 2511 printf("%s: packet from unknown node: phy id %d\n", 2512 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2513 m_freem(m); 2514 return IEEE1394_RCODE_COMPLETE; 2515 } 2516 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2517 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2518 m->m_flags |= M_BCAST; 2519 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2520 } else { 2521 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2522 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2523 } 2524 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2525 mtod(m, u_int8_t *)[9] = 2526 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2527 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2528 2529 m->m_pkthdr.rcvif = NULL; /* set in child */ 2530 m->m_pkthdr.len = len + m->m_len; 2531 /* 2532 * We may use receive buffer by external mbuf instead of copy here. 2533 * But asynchronous receive buffer must be operate in buffer fill 2534 * mode, so that each receive buffer will shared by multiple mbufs. 2535 * If upper layer doesn't free mbuf soon, e.g. application program 2536 * is suspended, buffer must be reallocated. 2537 * Isochronous buffer must be operate in packet buffer mode, and 2538 * it is easy to map receive buffer to external mbuf. But it is 2539 * used for broadcast/multicast only, and is expected not so 2540 * performance sensitive for now. 2541 * XXX: The performance may be important for multicast case, 2542 * so we should revisit here later. 2543 * -- onoe 2544 */ 2545 n = 0; 2546 iov = pkt->fp_uio.uio_iov; 2547 while (len > 0) { 2548 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2549 iov->iov_len); 2550 m->m_len += iov->iov_len; 2551 len -= iov->iov_len; 2552 iov++; 2553 } 2554 (*handler)(sc->sc_sc1394.sc1394_if, m); 2555 return IEEE1394_RCODE_COMPLETE; 2556 } 2557 2558 static int 2559 fwohci_if_output(struct device *self, struct mbuf *m0, 2560 void (*callback)(struct device *, struct mbuf *)) 2561 { 2562 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2563 struct fwohci_pkt pkt; 2564 u_int8_t *p; 2565 int n, error, spd, hdrlen, maxrec; 2566 #ifdef FW_DEBUG 2567 struct mbuf *m; 2568 #endif 2569 2570 p = mtod(m0, u_int8_t *); 2571 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2572 spd = IEEE1394_SPD_S100; /*XXX*/ 2573 maxrec = 512; /*XXX*/ 2574 hdrlen = 8; 2575 } else { 2576 n = fwohci_uid_lookup(sc, p); 2577 if (n < 0) { 2578 printf("%s: nodeid unknown:" 2579 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2580 sc->sc_sc1394.sc1394_dev.dv_xname, 2581 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2582 error = EHOSTUNREACH; 2583 goto end; 2584 } 2585 if (n == IEEE1394_BCAST_PHY_ID) { 2586 printf("%s: broadcast with !M_MCAST\n", 2587 sc->sc_sc1394.sc1394_dev.dv_xname); 2588 #ifdef FW_DEBUG 2589 DPRINTFN(2, ("packet:")); 2590 for (m = m0; m != NULL; m = m->m_next) { 2591 for (n = 0; n < m->m_len; n++) 2592 DPRINTFN(2, ("%s%02x", (n%32)? 2593 ((n%4)?"":" "):"\n\t", 2594 mtod(m, u_int8_t *)[n])); 2595 DPRINTFN(2, ("$")); 2596 } 2597 DPRINTFN(2, ("\n")); 2598 #endif 2599 error = EHOSTUNREACH; 2600 goto end; 2601 } 2602 maxrec = 2 << p[8]; 2603 spd = p[9]; 2604 hdrlen = 0; 2605 } 2606 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2607 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2608 spd, sc->sc_sc1394.sc1394_link_speed)); 2609 spd = sc->sc_sc1394.sc1394_link_speed; 2610 } 2611 if (maxrec > (512 << spd)) { 2612 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2613 "\n", maxrec, spd)); 2614 maxrec = 512 << spd; 2615 } 2616 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2617 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2618 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2619 maxrec >>= 1; 2620 } 2621 if (maxrec < 512) { 2622 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2623 "minimum\n", maxrec)); 2624 maxrec = 512; 2625 } 2626 2627 m_adj(m0, 16 - hdrlen); 2628 if (m0->m_pkthdr.len > maxrec) { 2629 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2630 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2631 error = E2BIG; /*XXX*/ 2632 goto end; 2633 } 2634 2635 memset(&pkt, 0, sizeof(pkt)); 2636 pkt.fp_uio.uio_iov = pkt.fp_iov; 2637 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2638 pkt.fp_uio.uio_rw = UIO_WRITE; 2639 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2640 /* construct GASP header */ 2641 p = mtod(m0, u_int8_t *); 2642 p[0] = sc->sc_nodeid >> 8; 2643 p[1] = sc->sc_nodeid & 0xff; 2644 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2645 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2646 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2647 pkt.fp_hlen = 8; 2648 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2649 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2650 OHCI_NodeId_NodeNumber) << 8); 2651 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2652 } else { 2653 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2654 pkt.fp_hlen = 16; 2655 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2656 (spd << 16); 2657 pkt.fp_hdr[1] = 2658 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2659 (p[10] << 8) | p[11]; 2660 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2661 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2662 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2663 } 2664 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2665 pkt.fp_dlen = m0->m_pkthdr.len; 2666 pkt.fp_m = m0; 2667 pkt.fp_callback = callback; 2668 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2669 m0 = pkt.fp_m; 2670 end: 2671 if (m0 != NULL) { 2672 if (callback) 2673 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2674 else 2675 m_freem(m0); 2676 } 2677 return error; 2678 } 2679 2680 /* 2681 * High level routines to provide abstraction to attaching layers to 2682 * send/receive data. 2683 */ 2684 2685 /* 2686 * These break down into 4 routines as follows: 2687 * 2688 * int fwohci_read(struct ieee1394_abuf *) 2689 * 2690 * This routine will attempt to read a region from the requested node. 2691 * A callback must be provided which will be called when either the completed 2692 * read is done or an unrecoverable error occurs. This is mainly a convenience 2693 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2694 * and recombining all the returned data. This could also be done with a series 2695 * of write/inreg's for each packet sent. 2696 * 2697 * int fwohci_write(struct ieee1394_abuf *) 2698 * 2699 * The work horse main entry point for putting packets on the bus. This is the 2700 * generalized interface for fwnode/etc code to put packets out onto the bus. 2701 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2702 * will callback via a func pointer to the calling code with the resulting ACK 2703 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2704 * write routine will take care of free'ing the abuf since the fwnode/etc code 2705 * won't have any knowledge of when to do this. This allows for simple one-off 2706 * packets to be sent from the upper-level code without worrying about a callback 2707 * for cleanup. 2708 * 2709 * int fwohci_inreg(struct ieee1394_abuf *, int) 2710 * 2711 * This is very simple. It evals the abuf passed in and registers an internal 2712 * handler as the callback for packets received for that operation. 2713 * The integer argument specifies whether on a block read/write operation to 2714 * allow sub-regions to be read/written (in block form) as well. 2715 * 2716 * XXX: This whole structure needs to be redone as a list of regions and 2717 * operations allowed on those regions. 2718 * 2719 * int fwohci_unreg(struct ieee1394_abuf *, int) 2720 * 2721 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2722 * routine will simply verify ab_cb is NULL and call inreg. 2723 * 2724 * This simply unregisters the respective callback done via inreg for items 2725 * which only need to register an area for a one-time operation (like a status 2726 * buffer a remote node will write to when the current operation is done). The 2727 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2728 * it unregisters). 2729 */ 2730 2731 static int 2732 fwohci_read(struct ieee1394_abuf *ab) 2733 { 2734 struct fwohci_pkt pkt; 2735 struct ieee1394_softc *sc = ab->ab_req; 2736 struct fwohci_softc *psc = 2737 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2738 struct fwohci_cb *fcb; 2739 u_int32_t high, lo; 2740 int rv, tcode; 2741 2742 /* Have to have a callback when reading. */ 2743 if (ab->ab_cb == NULL) 2744 return -1; 2745 2746 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2747 fcb->ab = ab; 2748 fcb->count = 0; 2749 fcb->abuf_valid = 1; 2750 2751 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2752 lo = (ab->ab_csr & 0x00000000ffffffff); 2753 2754 memset(&pkt, 0, sizeof(pkt)); 2755 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2756 pkt.fp_hdr[2] = lo; 2757 pkt.fp_dlen = 0; 2758 2759 if (ab->ab_length == 4) { 2760 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2761 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2762 pkt.fp_hlen = 12; 2763 } else { 2764 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2765 pkt.fp_hlen = 16; 2766 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2767 pkt.fp_hdr[3] = (ab->ab_length << 16); 2768 } 2769 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2770 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2771 2772 pkt.fp_statusarg = fcb; 2773 pkt.fp_statuscb = fwohci_read_resp; 2774 2775 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2776 psc->sc_tlabel, fwohci_read_resp, fcb); 2777 if (rv) 2778 return rv; 2779 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2780 if (rv) 2781 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2782 psc->sc_tlabel, NULL, NULL); 2783 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2784 fcb->count = 1; 2785 return rv; 2786 } 2787 2788 static int 2789 fwohci_write(struct ieee1394_abuf *ab) 2790 { 2791 struct fwohci_pkt pkt; 2792 struct ieee1394_softc *sc = ab->ab_req; 2793 struct fwohci_softc *psc = 2794 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2795 u_int32_t high, lo; 2796 int rv; 2797 2798 if (ab->ab_length > sc->sc1394_max_receive) { 2799 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2800 return E2BIG; 2801 } 2802 2803 memset(&pkt, 0, sizeof(pkt)); 2804 2805 pkt.fp_tcode = ab->ab_tcode; 2806 pkt.fp_uio.uio_iov = pkt.fp_iov; 2807 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2808 pkt.fp_uio.uio_rw = UIO_WRITE; 2809 2810 pkt.fp_statusarg = ab; 2811 pkt.fp_statuscb = fwohci_write_ack; 2812 2813 switch (ab->ab_tcode) { 2814 case IEEE1394_TCODE_WRITE_RESP: 2815 pkt.fp_hlen = 12; 2816 case IEEE1394_TCODE_READ_RESP_QUAD: 2817 case IEEE1394_TCODE_READ_RESP_BLOCK: 2818 if (!pkt.fp_hlen) 2819 pkt.fp_hlen = 16; 2820 high = ab->ab_retlen; 2821 ab->ab_retlen = 0; 2822 lo = 0; 2823 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2824 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2825 break; 2826 default: 2827 pkt.fp_hlen = 16; 2828 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2829 lo = (ab->ab_csr & 0x00000000ffffffff); 2830 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2831 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2832 break; 2833 } 2834 2835 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2836 pkt.fp_hdr[2] = lo; 2837 if (pkt.fp_hlen == 16) { 2838 if (ab->ab_length == 4) { 2839 pkt.fp_hdr[3] = ab->ab_data[0]; 2840 pkt.fp_dlen = 0; 2841 } else { 2842 pkt.fp_hdr[3] = (ab->ab_length << 16); 2843 pkt.fp_dlen = ab->ab_length; 2844 pkt.fp_uio.uio_iovcnt = 1; 2845 pkt.fp_uio.uio_resid = ab->ab_length; 2846 pkt.fp_iov[0].iov_base = ab->ab_data; 2847 pkt.fp_iov[0].iov_len = ab->ab_length; 2848 } 2849 } 2850 switch (ab->ab_tcode) { 2851 case IEEE1394_TCODE_WRITE_RESP: 2852 case IEEE1394_TCODE_READ_RESP_QUAD: 2853 case IEEE1394_TCODE_READ_RESP_BLOCK: 2854 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2855 break; 2856 default: 2857 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2858 break; 2859 } 2860 return rv; 2861 } 2862 2863 static int 2864 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2865 { 2866 struct fwohci_cb *fcb = arg; 2867 struct ieee1394_abuf *ab = fcb->ab; 2868 struct fwohci_pkt newpkt; 2869 u_int32_t *cur, high, lo; 2870 int i, tcode, rcode, status, rv; 2871 2872 /* 2873 * Both the ACK handling and normal response callbacks are handled here. 2874 * The main reason for this is the various error conditions that can 2875 * occur trying to block read some areas and the ways that gets reported 2876 * back to calling station. This is a variety of ACK codes, responses, 2877 * etc which makes it much more difficult to process if both aren't 2878 * handled here. 2879 */ 2880 2881 /* Check for status packet. */ 2882 2883 if (pkt->fp_tcode == -1) { 2884 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2885 rcode = -1; 2886 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2887 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2888 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2889 DPRINTF(("Got status packet: 0x%02x\n", 2890 (unsigned int)status)); 2891 fcb->count--; 2892 2893 /* 2894 * Got all the ack's back and the buffer is invalid (i.e. the 2895 * callback has been called. Clean up. 2896 */ 2897 2898 if (fcb->abuf_valid == 0) { 2899 if (fcb->count == 0) 2900 free(fcb, M_DEVBUF); 2901 return IEEE1394_RCODE_COMPLETE; 2902 } 2903 } else { 2904 status = -1; 2905 tcode = pkt->fp_tcode; 2906 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2907 } 2908 2909 /* 2910 * Some area's (like the config rom want to be read as quadlets only. 2911 * 2912 * The current ideas to try are: 2913 * 2914 * Got an ACK_TYPE_ERROR on a block read. 2915 * 2916 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2917 * response. 2918 * 2919 * In all cases construct a new packet for a quadlet read and let 2920 * mutli_resp handle the iteration over the space. 2921 */ 2922 2923 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2924 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2925 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2926 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2927 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2928 2929 /* Read the area in quadlet chunks (internally track this). */ 2930 2931 memset(&newpkt, 0, sizeof(newpkt)); 2932 2933 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2934 lo = (ab->ab_csr & 0x00000000ffffffff); 2935 2936 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2937 newpkt.fp_hlen = 12; 2938 newpkt.fp_dlen = 0; 2939 newpkt.fp_hdr[1] = 2940 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2941 newpkt.fp_hdr[2] = lo; 2942 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2943 (newpkt.fp_tcode << 4); 2944 2945 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2946 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2947 fwohci_read_multi_resp, fcb); 2948 if (rv) { 2949 (*ab->ab_cb)(ab, -1); 2950 goto cleanup; 2951 } 2952 newpkt.fp_statusarg = fcb; 2953 newpkt.fp_statuscb = fwohci_read_resp; 2954 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 2955 if (rv) { 2956 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2957 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 2958 NULL); 2959 (*ab->ab_cb)(ab, -1); 2960 goto cleanup; 2961 } 2962 fcb->count++; 2963 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2964 return IEEE1394_RCODE_COMPLETE; 2965 } else if ((rcode != -1) || ((status != -1) && 2966 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2967 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 2968 2969 /* 2970 * Recombine all the iov data into 1 chunk for higher 2971 * level code. 2972 */ 2973 2974 if (rcode != -1) { 2975 cur = ab->ab_data; 2976 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 2977 /* 2978 * Make sure and don't exceed the buffer 2979 * allocated for return. 2980 */ 2981 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 2982 ab->ab_length) { 2983 memcpy(cur, pkt->fp_iov[i].iov_base, 2984 (ab->ab_length - ab->ab_retlen)); 2985 ab->ab_retlen = ab->ab_length; 2986 break; 2987 } 2988 memcpy(cur, pkt->fp_iov[i].iov_base, 2989 pkt->fp_iov[i].iov_len); 2990 cur += pkt->fp_iov[i].iov_len; 2991 ab->ab_retlen += pkt->fp_iov[i].iov_len; 2992 } 2993 } 2994 if (status != -1) 2995 /* XXX: Need a complete tlabel interface. */ 2996 for (i = 0; i < 64; i++) 2997 fwohci_handler_set(sc, 2998 IEEE1394_TCODE_READ_RESP_QUAD, 2999 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3000 (*ab->ab_cb)(ab, rcode); 3001 goto cleanup; 3002 } else 3003 /* Good ack packet. */ 3004 return IEEE1394_RCODE_COMPLETE; 3005 3006 /* Can't get here unless ab->ab_cb has been called. */ 3007 3008 cleanup: 3009 fcb->abuf_valid = 0; 3010 if (fcb->count == 0) 3011 free(fcb, M_DEVBUF); 3012 return IEEE1394_RCODE_COMPLETE; 3013 } 3014 3015 static int 3016 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3017 struct fwohci_pkt *pkt) 3018 { 3019 struct fwohci_cb *fcb = arg; 3020 struct ieee1394_abuf *ab = fcb->ab; 3021 struct fwohci_pkt newpkt; 3022 u_int32_t high, lo; 3023 int rcode, rv; 3024 3025 /* 3026 * Bad return codes from the wire, just return what's already in the 3027 * buf. 3028 */ 3029 3030 /* Make sure a response packet didn't arrive after a bad ACK. */ 3031 if (fcb->abuf_valid == 0) 3032 return IEEE1394_RCODE_COMPLETE; 3033 3034 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3035 3036 if (rcode) { 3037 (*ab->ab_cb)(ab, rcode); 3038 goto cleanup; 3039 } 3040 3041 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3042 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3043 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3044 ab->ab_retlen = ab->ab_length; 3045 } else { 3046 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3047 pkt->fp_iov[0].iov_base, 4); 3048 ab->ab_retlen += 4; 3049 } 3050 /* Still more, loop and read 4 more bytes. */ 3051 if (ab->ab_retlen < ab->ab_length) { 3052 memset(&newpkt, 0, sizeof(newpkt)); 3053 3054 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3055 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3056 3057 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3058 newpkt.fp_hlen = 12; 3059 newpkt.fp_dlen = 0; 3060 newpkt.fp_hdr[1] = 3061 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3062 newpkt.fp_hdr[2] = lo; 3063 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3064 (newpkt.fp_tcode << 4); 3065 3066 newpkt.fp_statusarg = fcb; 3067 newpkt.fp_statuscb = fwohci_read_resp; 3068 3069 /* 3070 * Bad return code. Just give up and return what's 3071 * come in now. 3072 */ 3073 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3074 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3075 fwohci_read_multi_resp, fcb); 3076 if (rv) 3077 (*ab->ab_cb)(ab, -1); 3078 else { 3079 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3080 if (rv) { 3081 fwohci_handler_set(sc, 3082 IEEE1394_TCODE_READ_RESP_QUAD, 3083 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3084 NULL, NULL); 3085 (*ab->ab_cb)(ab, -1); 3086 } else { 3087 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3088 fcb->count++; 3089 return IEEE1394_RCODE_COMPLETE; 3090 } 3091 } 3092 } else 3093 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3094 3095 cleanup: 3096 /* Can't get here unless ab_cb has been called. */ 3097 fcb->abuf_valid = 0; 3098 if (fcb->count == 0) 3099 free(fcb, M_DEVBUF); 3100 return IEEE1394_RCODE_COMPLETE; 3101 } 3102 3103 static int 3104 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3105 { 3106 struct ieee1394_abuf *ab = arg; 3107 u_int16_t status; 3108 3109 3110 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3111 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3112 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3113 DPRINTF(("Got status packet: 0x%02x\n", 3114 (unsigned int)status)); 3115 3116 /* No callback means this level should free the buffers. */ 3117 if (ab->ab_cb) 3118 (*ab->ab_cb)(ab, status); 3119 else { 3120 if (ab->ab_data) 3121 free(ab->ab_data, M_1394DATA); 3122 free(ab, M_1394DATA); 3123 } 3124 return IEEE1394_RCODE_COMPLETE; 3125 } 3126 3127 static int 3128 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3129 { 3130 struct ieee1394_softc *sc = ab->ab_req; 3131 struct fwohci_softc *psc = 3132 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3133 u_int32_t high, lo; 3134 int i, j, rv; 3135 3136 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3137 lo = (ab->ab_csr & 0x00000000ffffffff); 3138 3139 rv = 0; 3140 switch (ab->ab_tcode) { 3141 case IEEE1394_TCODE_READ_REQ_QUAD: 3142 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3143 if (ab->ab_cb) 3144 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3145 fwohci_parse_input, ab); 3146 else 3147 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3148 NULL); 3149 break; 3150 case IEEE1394_TCODE_READ_REQ_BLOCK: 3151 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3152 if (allow) { 3153 for (i = 0; i < (ab->ab_length / 4); i++) { 3154 if (ab->ab_cb) { 3155 rv = fwohci_handler_set(psc, 3156 ab->ab_tcode, high, lo + (i * 4), 3157 fwohci_parse_input, ab); 3158 if (rv) 3159 break; 3160 } else 3161 fwohci_handler_set(psc, ab->ab_tcode, 3162 high, lo + (i * 4), NULL, NULL); 3163 } 3164 if (i != (ab->ab_length / 4)) { 3165 j = i + 1; 3166 for (i = 0; i < j; i++) 3167 fwohci_handler_set(psc, ab->ab_tcode, 3168 high, lo + (i * 4), NULL, NULL); 3169 } else 3170 ab->ab_data = (void *)1; 3171 } else { 3172 if (ab->ab_cb) 3173 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3174 lo, fwohci_parse_input, ab); 3175 else 3176 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3177 NULL, NULL); 3178 } 3179 break; 3180 default: 3181 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3182 return -1; 3183 break; 3184 } 3185 return rv; 3186 } 3187 3188 static int 3189 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3190 { 3191 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3192 u_int64_t csr; 3193 u_int32_t *cur; 3194 int i, count; 3195 3196 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3197 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3198 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3199 3200 switch (ab->ab_tcode) { 3201 case IEEE1394_TCODE_READ_REQ_QUAD: 3202 ab->ab_retlen = 4; 3203 break; 3204 case IEEE1394_TCODE_READ_REQ_BLOCK: 3205 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3206 if (ab->ab_data) { 3207 if ((csr + ab->ab_retlen) > 3208 (ab->ab_csr + ab->ab_length)) 3209 return IEEE1394_RCODE_ADDRESS_ERROR; 3210 ab->ab_data = NULL; 3211 } else 3212 if (ab->ab_retlen != ab->ab_length) 3213 return IEEE1394_RCODE_ADDRESS_ERROR; 3214 break; 3215 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3216 ab->ab_retlen = 4; 3217 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3218 if (!ab->ab_retlen) 3219 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3220 if (ab->ab_data) { 3221 if ((csr + ab->ab_retlen) > 3222 (ab->ab_csr + ab->ab_length)) 3223 return IEEE1394_RCODE_ADDRESS_ERROR; 3224 ab->ab_data = NULL; 3225 } else 3226 if (ab->ab_retlen != ab->ab_length) 3227 return IEEE1394_RCODE_ADDRESS_ERROR; 3228 3229 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3230 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3231 ab->ab_data[0] = pkt->fp_hdr[3]; 3232 else { 3233 count = 0; 3234 cur = ab->ab_data; 3235 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3236 memcpy(cur, pkt->fp_iov[i].iov_base, 3237 pkt->fp_iov[i].iov_len); 3238 cur += pkt->fp_iov[i].iov_len; 3239 count += pkt->fp_iov[i].iov_len; 3240 } 3241 if (ab->ab_retlen != count) 3242 panic("Packet claims %d length " 3243 "but only %d bytes returned\n", 3244 ab->ab_retlen, count); 3245 } 3246 break; 3247 default: 3248 panic("Got a callback for a tcode that wasn't requested: %d\n", 3249 ab->ab_tcode); 3250 break; 3251 } 3252 ab->ab_csr = csr; 3253 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3254 return -1; 3255 } 3256 3257 static int 3258 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3259 { 3260 struct ieee1394_attach_args *fwa = aux; 3261 3262 /* Both halves must be filled in for a match. */ 3263 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3264 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3265 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3266 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3267 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3268 return 0; 3269 } 3270 3271 #ifdef FW_DEBUG 3272 static void 3273 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3274 { 3275 3276 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3277 intmask); 3278 if (intmask & OHCI_Int_CycleTooLong) 3279 printf(" CycleTooLong"); 3280 if (intmask & OHCI_Int_UnrecoverableError) 3281 printf(" UnrecoverableError"); 3282 if (intmask & OHCI_Int_CycleInconsistent) 3283 printf(" CycleInconsistent"); 3284 if (intmask & OHCI_Int_BusReset) 3285 printf(" BusReset"); 3286 if (intmask & OHCI_Int_SelfIDComplete) 3287 printf(" SelfIDComplete"); 3288 if (intmask & OHCI_Int_LockRespErr) 3289 printf(" LockRespErr"); 3290 if (intmask & OHCI_Int_PostedWriteErr) 3291 printf(" PostedWriteErr"); 3292 if (intmask & OHCI_Int_ReqTxComplete) 3293 printf(" ReqTxComplete(0x%04x)", 3294 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3295 OHCI_SUBREG_ContextControlClear)); 3296 if (intmask & OHCI_Int_RespTxComplete) 3297 printf(" RespTxComplete(0x%04x)", 3298 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3299 OHCI_SUBREG_ContextControlClear)); 3300 if (intmask & OHCI_Int_ARRS) 3301 printf(" ARRS(0x%04x)", 3302 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3303 OHCI_SUBREG_ContextControlClear)); 3304 if (intmask & OHCI_Int_ARRQ) 3305 printf(" ARRQ(0x%04x)", 3306 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3307 OHCI_SUBREG_ContextControlClear)); 3308 if (intmask & OHCI_Int_IsochRx) 3309 printf(" IsochRx(0x%08x)", 3310 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3311 if (intmask & OHCI_Int_IsochTx) 3312 printf(" IsochTx(0x%08x)", 3313 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3314 if (intmask & OHCI_Int_RQPkt) 3315 printf(" RQPkt(0x%04x)", 3316 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3317 OHCI_SUBREG_ContextControlClear)); 3318 if (intmask & OHCI_Int_RSPkt) 3319 printf(" RSPkt(0x%04x)", 3320 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3321 OHCI_SUBREG_ContextControlClear)); 3322 printf("\n"); 3323 } 3324 3325 static void 3326 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3327 { 3328 u_int8_t key, phyid; 3329 3330 key = (val & 0xc0000000) >> 30; 3331 phyid = (val & 0x3f000000) >> 24; 3332 printf("%s: PHY packet from %d: ", 3333 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3334 switch (key) { 3335 case 0: 3336 printf("PHY Config:"); 3337 if (val & 0x00800000) 3338 printf(" ForceRoot"); 3339 if (val & 0x00400000) 3340 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3341 printf("\n"); 3342 break; 3343 case 1: 3344 printf("Link-on\n"); 3345 break; 3346 case 2: 3347 printf("SelfID:"); 3348 if (val & 0x00800000) { 3349 printf(" #%d", (val & 0x00700000) >> 20); 3350 } else { 3351 if (val & 0x00400000) 3352 printf(" LinkActive"); 3353 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3354 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3355 if (val & 0x00000800) 3356 printf(" Cont"); 3357 if (val & 0x00000002) 3358 printf(" InitiateBusReset"); 3359 } 3360 if (val & 0x00000001) 3361 printf(" +"); 3362 printf("\n"); 3363 break; 3364 default: 3365 printf("unknown: 0x%08x\n", val); 3366 break; 3367 } 3368 } 3369 #endif /* FW_DEBUG */ 3370
Indexes created Fri Sep 26 20:09:58 GMT 2025