fwohci.c revision 1.34
1 /* $NetBSD: fwohci.c,v 1.34 2001/06/28 14:38:56 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 115 116 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 117 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 119 120 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 121 struct fwohci_pkt *); 122 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 123 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 124 struct fwohci_pkt *); 125 126 static int fwohci_guidrom_init(struct fwohci_softc *); 127 static void fwohci_configrom_init(struct fwohci_softc *); 128 static int fwohci_configrom_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 static void fwohci_selfid_init(struct fwohci_softc *); 131 static int fwohci_selfid_input(struct fwohci_softc *); 132 133 static void fwohci_csr_init(struct fwohci_softc *); 134 static int fwohci_csr_input(struct fwohci_softc *, void *, 135 struct fwohci_pkt *); 136 137 static void fwohci_uid_collect(struct fwohci_softc *); 138 static int fwohci_uid_input(struct fwohci_softc *, void *, 139 struct fwohci_pkt *); 140 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 141 static void fwohci_check_nodes(struct fwohci_softc *); 142 143 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 144 void (*)(struct device *, struct mbuf *)); 145 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 146 static int fwohci_if_output(struct device *, struct mbuf *, 147 void (*)(struct device *, struct mbuf *)); 148 static int fwohci_read(struct ieee1394_abuf *); 149 static int fwohci_write(struct ieee1394_abuf *); 150 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 151 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 152 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_inreg(struct ieee1394_abuf *, int); 155 static int fwohci_parse_input(struct fwohci_softc *, void *, 156 struct fwohci_pkt *); 157 static int fwohci_submatch(struct device *, struct cfdata *, void *); 158 159 #ifdef FW_DEBUG 160 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 161 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 162 163 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 164 165 #define DPRINTF(x) if (fwdebug) printf x 166 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 167 int fwdebug = 0; 168 #else 169 #define DPRINTF(x) 170 #define DPRINTFN(n,x) 171 #endif 172 173 int 174 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 175 { 176 int i; 177 u_int32_t val; 178 #if 0 179 int error; 180 #endif 181 182 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 183 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 184 185 /* 186 * Wait for reset completion 187 */ 188 for (i = 0; i < OHCI_LOOP; i++) { 189 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 190 if ((val & OHCI_HCControl_SoftReset) == 0) 191 break; 192 } 193 194 /* What dialect of OHCI is this device? 195 */ 196 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 197 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 198 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 199 200 LIST_INIT(&sc->sc_nodelist); 201 202 if (fwohci_guidrom_init(sc) != 0) { 203 printf("\n%s: fatal: no global UID ROM\n", 204 sc->sc_sc1394.sc1394_dev.dv_xname); 205 return -1; 206 } 207 208 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 209 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 210 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 211 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 212 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 213 214 /* Get the maximum link speed and receive size 215 */ 216 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 217 sc->sc_sc1394.sc1394_link_speed = 218 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 219 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 220 printf(", %s", 221 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 222 } else { 223 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 224 } 225 226 /* MaxRec is encoded as log2(max_rec_octets)-1 227 */ 228 sc->sc_sc1394.sc1394_max_receive = 229 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 230 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 231 232 /* 233 * Count how many isochronous ctx we have. 234 */ 235 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 236 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 237 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 238 for (i = 0; val != 0; val >>= 1) { 239 if (val & 0x1) 240 i++; 241 } 242 sc->sc_isoctx = i; 243 printf(", %d iso_ctx", sc->sc_isoctx); 244 245 printf("\n"); 246 247 #if 0 248 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 249 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 250 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 251 return error; 252 #endif 253 254 sc->sc_dying = 0; 255 256 kthread_create(fwohci_create_event_thread, sc); 257 return 0; 258 } 259 260 int 261 fwohci_intr(void *arg) 262 { 263 struct fwohci_softc * const sc = arg; 264 int progress = 0; 265 u_int32_t intmask, iso; 266 267 for (;;) { 268 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 269 270 /* 271 * On a bus reset, everything except bus reset gets 272 * cleared. That can't get cleared until the selfid 273 * phase completes (which happens outside the 274 * interrupt routines). So if just a bus reset is left 275 * in the mask and it's already in the sc_intmask, 276 * just return. 277 */ 278 279 if ((intmask == 0) || 280 (progress && (intmask == OHCI_Int_BusReset) && 281 (sc->sc_intmask & OHCI_Int_BusReset))) { 282 if (progress) 283 wakeup(fwohci_event_thread); 284 return progress; 285 } 286 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 287 intmask & ~OHCI_Int_BusReset); 288 #ifdef FW_DEBUG 289 if (fwdebug > 1) 290 fwohci_show_intr(sc, intmask); 291 #endif 292 293 if (intmask & OHCI_Int_BusReset) { 294 /* 295 * According to OHCI spec 6.1.1 "busReset", 296 * All asynchronous transmit must be stopped before 297 * clearing BusReset. Moreover, the BusReset 298 * interrupt bit should not be cleared during the 299 * SelfID phase. Thus we turned off interrupt mask 300 * bit of BusReset instead until SelfID completion 301 * or SelfID timeout. 302 */ 303 intmask &= OHCI_Int_SelfIDComplete; 304 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 305 OHCI_Int_BusReset); 306 sc->sc_intmask = OHCI_Int_BusReset; 307 } 308 sc->sc_intmask |= intmask; 309 310 if (intmask & OHCI_Int_IsochTx) { 311 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 312 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 313 } 314 if (intmask & OHCI_Int_IsochRx) { 315 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 316 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 317 sc->sc_iso |= iso; 318 } 319 320 if (!progress) { 321 sc->sc_intrcnt.ev_count++; 322 progress = 1; 323 } 324 } 325 } 326 327 static void 328 fwohci_create_event_thread(void *arg) 329 { 330 struct fwohci_softc *sc = arg; 331 332 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 333 sc->sc_sc1394.sc1394_dev.dv_xname)) { 334 printf("%s: unable to create event thread\n", 335 sc->sc_sc1394.sc1394_dev.dv_xname); 336 panic("fwohci_create_event_thread"); 337 } 338 } 339 340 static void 341 fwohci_thread_init(void *arg) 342 { 343 struct fwohci_softc *sc = arg; 344 int i; 345 346 /* 347 * Allocate descriptors 348 */ 349 if (fwohci_desc_alloc(sc)) { 350 printf("%s: not enabling interrupts\n", 351 sc->sc_sc1394.sc1394_dev.dv_xname); 352 kthread_exit(1); 353 } 354 355 /* 356 * Enable Link Power 357 */ 358 359 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 360 361 /* 362 * Allocate DMA Context 363 */ 364 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 365 OHCI_CTX_ASYNC_RX_REQUEST); 366 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 367 OHCI_CTX_ASYNC_RX_RESPONSE); 368 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 369 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 370 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 371 M_DEVBUF, M_WAITOK); 372 for (i = 0; i < sc->sc_isoctx; i++) 373 sc->sc_ctx_ir[i] = NULL; 374 375 /* 376 * Allocate buffer for configuration ROM and SelfID buffer 377 */ 378 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 379 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 380 381 callout_init(&sc->sc_selfid_callout); 382 383 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 384 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 385 386 /* 387 * establish hooks for shutdown and suspend/resume 388 */ 389 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 390 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 391 392 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 393 fwohci_print); 394 395 /* Main loop. It's not coming back normally. */ 396 397 fwohci_event_thread(sc); 398 399 kthread_exit(0); 400 } 401 402 static void 403 fwohci_event_thread(struct fwohci_softc *sc) 404 { 405 int i, s; 406 u_int32_t intmask, iso; 407 408 s = splbio(); 409 410 /* 411 * Initialize hardware registers. 412 */ 413 414 fwohci_hw_init(sc); 415 416 /* Initial Bus Reset */ 417 fwohci_phy_busreset(sc); 418 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 419 splx(s); 420 421 while (!sc->sc_dying) { 422 while (1) { 423 s = splbio(); 424 intmask = sc->sc_intmask; 425 if (intmask) { 426 splx(s); 427 if (intmask & OHCI_Int_BusReset) { 428 s = splbio(); 429 sc->sc_intmask &= ~OHCI_Int_BusReset; 430 splx(s); 431 fwohci_buf_stop(sc); 432 fwohci_buf_init(sc); 433 if (sc->sc_uidtbl != NULL) { 434 free(sc->sc_uidtbl, M_DEVBUF); 435 sc->sc_uidtbl = NULL; 436 } 437 438 callout_reset(&sc->sc_selfid_callout, 439 OHCI_SELFID_TIMEOUT, 440 (void (*)(void *)) 441 fwohci_phy_busreset, sc); 442 sc->sc_nodeid = 0xffff; /* indicate 443 invalid */ 444 sc->sc_rootid = 0; 445 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 446 } 447 if (intmask & OHCI_Int_SelfIDComplete) { 448 s = splbio(); 449 sc->sc_intmask &= 450 ~OHCI_Int_SelfIDComplete; 451 OHCI_CSR_WRITE(sc, 452 OHCI_REG_IntEventClear, 453 OHCI_Int_BusReset); 454 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 455 OHCI_Int_BusReset); 456 splx(s); 457 callout_stop(&sc->sc_selfid_callout); 458 if (fwohci_selfid_input(sc) == 0) { 459 fwohci_buf_start(sc); 460 fwohci_uid_collect(sc); 461 } 462 } 463 if (intmask & OHCI_Int_ReqTxComplete) { 464 s = splbio(); 465 sc->sc_intmask &= 466 ~OHCI_Int_ReqTxComplete; 467 splx(s); 468 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 469 } 470 if (intmask & OHCI_Int_RespTxComplete) { 471 s = splbio(); 472 sc->sc_intmask &= 473 ~OHCI_Int_RespTxComplete; 474 splx(s); 475 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 476 } 477 if (intmask & OHCI_Int_RQPkt) { 478 s = splbio(); 479 sc->sc_intmask &= ~OHCI_Int_RQPkt; 480 splx(s); 481 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 482 } 483 if (intmask & OHCI_Int_RSPkt) { 484 s = splbio(); 485 sc->sc_intmask &= ~OHCI_Int_RSPkt; 486 splx(s); 487 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 488 } 489 if (intmask & OHCI_Int_IsochTx) { 490 s = splbio(); 491 sc->sc_intmask &= ~OHCI_Int_IsochTx; 492 splx(s); 493 } 494 if (intmask & OHCI_Int_IsochRx) { 495 s = splbio(); 496 sc->sc_intmask &= ~OHCI_Int_IsochRx; 497 iso = sc->sc_iso; 498 sc->sc_iso = 0; 499 splx(s); 500 for (i = 0; i < sc->sc_isoctx; i++) { 501 if ((iso & (1 << i)) && 502 sc->sc_ctx_ir[i] != NULL) 503 fwohci_ir_input(sc, 504 sc->sc_ctx_ir[i]); 505 } 506 } 507 } else 508 break; 509 } 510 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 511 splx(s); 512 } 513 } 514 515 #if 0 516 static int 517 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 518 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 519 { 520 bus_dma_segment_t segs[1]; 521 int error, nsegs, steps; 522 523 steps = 0; 524 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 525 segs, 1, &nsegs, flags); 526 if (error) 527 goto cleanup; 528 529 steps = 1; 530 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 531 kvap, flags); 532 if (error) 533 goto cleanup; 534 535 if (error == 0) 536 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 537 size, flags, mapp); 538 if (error) 539 goto cleanup; 540 if (error == 0) 541 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 542 flags); 543 if (error) 544 goto cleanup; 545 546 cleanup: 547 switch (steps) { 548 case 1: 549 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 550 } 551 552 return error; 553 } 554 #endif 555 556 int 557 fwohci_print(void *aux, const char *pnp) 558 { 559 char *name = aux; 560 561 if (pnp) 562 printf("%s at %s", name, pnp); 563 564 return QUIET; 565 } 566 567 static void 568 fwohci_hw_init(struct fwohci_softc *sc) 569 { 570 int i; 571 u_int32_t val; 572 573 /* 574 * Software Reset. 575 */ 576 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 577 for (i = 0; i < OHCI_LOOP; i++) { 578 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 579 if ((val & OHCI_HCControl_SoftReset) == 0) 580 break; 581 } 582 583 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 584 585 /* 586 * First, initilize CSRs with undefined value to default settings. 587 */ 588 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 589 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 590 #if 0 591 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 592 #else 593 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 594 #endif 595 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 596 for (i = 0; i < sc->sc_isoctx; i++) { 597 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 598 ~0); 599 } 600 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 601 602 fwohci_configrom_init(sc); 603 fwohci_selfid_init(sc); 604 fwohci_buf_init(sc); 605 fwohci_csr_init(sc); 606 607 /* 608 * Final CSR settings. 609 */ 610 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 611 OHCI_LinkControl_CycleTimerEnable | 612 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 613 614 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 615 616 /* clear receive filter */ 617 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 618 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 619 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 620 621 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 622 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 623 #if BYTE_ORDER == BIG_ENDIAN 624 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 625 OHCI_HCControl_NoByteSwapData); 626 #endif 627 628 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 629 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 630 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 631 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 632 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 633 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 634 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 635 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 636 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 637 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 638 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 639 640 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 641 642 /* 643 * Start the receivers 644 */ 645 fwohci_buf_start(sc); 646 } 647 648 static void 649 fwohci_power(int why, void *arg) 650 { 651 struct fwohci_softc *sc = arg; 652 int s; 653 654 s = splbio(); 655 switch (why) { 656 case PWR_SUSPEND: 657 case PWR_STANDBY: 658 fwohci_shutdown(sc); 659 break; 660 case PWR_RESUME: 661 fwohci_hw_init(sc); 662 fwohci_phy_busreset(sc); 663 break; 664 case PWR_SOFTSUSPEND: 665 case PWR_SOFTSTANDBY: 666 case PWR_SOFTRESUME: 667 break; 668 } 669 splx(s); 670 } 671 672 static void 673 fwohci_shutdown(void *arg) 674 { 675 struct fwohci_softc *sc = arg; 676 u_int32_t val; 677 678 callout_stop(&sc->sc_selfid_callout); 679 /* disable all interrupt */ 680 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 681 fwohci_buf_stop(sc); 682 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 683 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 684 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 685 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 686 fwohci_phy_busreset(sc); 687 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 688 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 689 } 690 691 /* 692 * COMMON FUNCTIONS 693 */ 694 695 /* 696 * read the PHY Register. 697 */ 698 static u_int8_t 699 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 700 { 701 int i; 702 u_int32_t val; 703 704 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 705 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 706 for (i = 0; i < OHCI_LOOP; i++) { 707 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 708 OHCI_PhyControl_RdDone) 709 break; 710 } 711 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 712 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 713 } 714 715 /* 716 * write the PHY Register. 717 */ 718 static void 719 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 720 { 721 int i; 722 723 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 724 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 725 (val << OHCI_PhyControl_WrData_BITPOS)); 726 for (i = 0; i < OHCI_LOOP; i++) { 727 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 728 OHCI_PhyControl_WrReg)) 729 break; 730 } 731 } 732 733 /* 734 * Initiate Bus Reset 735 */ 736 static void 737 fwohci_phy_busreset(struct fwohci_softc *sc) 738 { 739 int s; 740 u_int8_t val; 741 742 s = splbio(); 743 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 744 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 745 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 746 callout_stop(&sc->sc_selfid_callout); 747 val = fwohci_phy_read(sc, 1); 748 val = (val & 0x80) | /* preserve RHB (force root) */ 749 0x40 | /* Initiate Bus Reset */ 750 0x3f; /* default GAP count */ 751 fwohci_phy_write(sc, 1, val); 752 splx(s); 753 } 754 755 /* 756 * PHY Packet 757 */ 758 static void 759 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 760 { 761 u_int32_t val; 762 763 val = pkt->fp_hdr[1]; 764 if (val != ~pkt->fp_hdr[2]) { 765 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 766 OHCI_CTXCTL_EVENT_BUS_RESET) { 767 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 768 pkt->fp_hdr[2])); 769 } else { 770 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 771 sc->sc_sc1394.sc1394_dev.dv_xname, val, 772 pkt->fp_hdr[2]); 773 } 774 return; 775 } 776 #ifdef FW_DEBUG 777 if (fwdebug > 1) 778 fwohci_show_phypkt(sc, val); 779 #endif 780 } 781 782 /* 783 * Descriptor for context DMA. 784 */ 785 static int 786 fwohci_desc_alloc(struct fwohci_softc *sc) 787 { 788 int error, mapsize, dsize; 789 790 /* 791 * allocate descriptor buffer 792 */ 793 794 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 795 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 796 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 797 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 798 mapsize = howmany(sc->sc_descsize, NBBY); 799 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 800 memset(sc->sc_descmap, 0, mapsize); 801 802 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 803 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 804 printf("%s: unable to allocate descriptor buffer, error = %d\n", 805 sc->sc_sc1394.sc1394_dev.dv_xname, error); 806 goto fail_0; 807 } 808 809 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 810 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 811 != 0) { 812 printf("%s: unable to map descriptor buffer, error = %d\n", 813 sc->sc_sc1394.sc1394_dev.dv_xname, error); 814 goto fail_1; 815 } 816 817 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 818 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 819 printf("%s: unable to create descriptor buffer DMA map, " 820 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 821 goto fail_2; 822 } 823 824 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 825 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 826 printf("%s: unable to load descriptor buffer DMA map, " 827 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 828 goto fail_3; 829 } 830 831 return 0; 832 833 fail_3: 834 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 835 fail_2: 836 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 837 fail_1: 838 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 839 fail_0: 840 return error; 841 } 842 843 static struct fwohci_desc * 844 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 845 { 846 int i, n; 847 848 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 849 for (i = 0; ; i++) { 850 if (i == ndesc) { 851 for (i = 0; i < ndesc; i++) 852 setbit(sc->sc_descmap, n + i); 853 return sc->sc_desc + n; 854 } 855 if (isset(sc->sc_descmap, n + i)) 856 break; 857 } 858 } 859 return NULL; 860 } 861 862 static void 863 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 864 { 865 int i, n; 866 867 n = fd - sc->sc_desc; 868 for (i = 0; i < ndesc; i++, n++) { 869 #ifdef DIAGNOSTIC 870 if (isclr(sc->sc_descmap, n)) 871 panic("fwohci_desc_put: duplicated free"); 872 #endif 873 clrbit(sc->sc_descmap, n); 874 } 875 } 876 877 /* 878 * Asyncronous/Isochronous Transmit/Receive Context 879 */ 880 static int 881 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 882 int bufcnt, int ctx) 883 { 884 int i, error; 885 struct fwohci_ctx *fc; 886 struct fwohci_buf *fb; 887 struct fwohci_desc *fd; 888 889 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 890 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 891 LIST_INIT(&fc->fc_handler); 892 TAILQ_INIT(&fc->fc_buf); 893 fc->fc_ctx = ctx; 894 fc->fc_bufcnt = bufcnt; 895 fb = (struct fwohci_buf *)&fc[1]; 896 for (i = 0; i < bufcnt; i++, fb++) { 897 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 898 goto fail; 899 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 900 error = ENOBUFS; 901 goto fail; 902 } 903 fb->fb_desc = fd; 904 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 905 ((caddr_t)fd - (caddr_t)sc->sc_desc); 906 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 907 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 908 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 909 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 910 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 911 } 912 *fcp = fc; 913 return 0; 914 915 fail: 916 while (i-- > 0) 917 fwohci_buf_free(sc, --fb); 918 free(fc, M_DEVBUF); 919 return error; 920 } 921 922 static void 923 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 924 { 925 struct fwohci_buf *fb; 926 struct fwohci_handler *fh; 927 928 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 929 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 930 NULL, NULL); 931 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 932 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 933 fwohci_buf_free(sc, fb); 934 } 935 free(fc, M_DEVBUF); 936 } 937 938 static void 939 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 940 { 941 struct fwohci_buf *fb, *nfb; 942 struct fwohci_desc *fd; 943 struct fwohci_handler *fh; 944 int n; 945 946 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 947 nfb = TAILQ_NEXT(fb, fb_list); 948 fb->fb_off = 0; 949 fd = fb->fb_desc; 950 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 951 fd->fd_rescount = fd->fd_reqcount; 952 } 953 954 n = fc->fc_ctx; 955 fb = TAILQ_FIRST(&fc->fc_buf); 956 if (fc->fc_isoch) { 957 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 958 fb->fb_daddr | 1); 959 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 960 OHCI_CTXCTL_RX_BUFFER_FILL | 961 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 962 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 963 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 964 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 965 OHCI_CTXCTL_RX_ISOCH_HEADER); 966 fh = LIST_FIRST(&fc->fc_handler); 967 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 968 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 969 } else { 970 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 971 fb->fb_daddr | 1); 972 } 973 } 974 975 /* 976 * DMA data buffer 977 */ 978 static int 979 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 980 { 981 int error; 982 983 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 984 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 985 printf("%s: unable to allocate buffer, error = %d\n", 986 sc->sc_sc1394.sc1394_dev.dv_xname, error); 987 goto fail_0; 988 } 989 990 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 991 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 992 printf("%s: unable to map buffer, error = %d\n", 993 sc->sc_sc1394.sc1394_dev.dv_xname, error); 994 goto fail_1; 995 } 996 997 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 998 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 999 printf("%s: unable to create buffer DMA map, " 1000 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1001 error); 1002 goto fail_2; 1003 } 1004 1005 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1006 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1007 printf("%s: unable to load buffer DMA map, " 1008 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1009 error); 1010 goto fail_3; 1011 } 1012 1013 return 0; 1014 1015 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1016 fail_3: 1017 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1018 fail_2: 1019 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1020 fail_1: 1021 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1022 fail_0: 1023 return error; 1024 } 1025 1026 static void 1027 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1028 { 1029 1030 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1031 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1032 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1033 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1034 } 1035 1036 static void 1037 fwohci_buf_init(struct fwohci_softc *sc) 1038 { 1039 int i; 1040 1041 /* 1042 * Initialize for Asynchronous Transmit Queue. 1043 */ 1044 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1045 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1046 1047 /* 1048 * Initialize for Asynchronous Receive Queue. 1049 */ 1050 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1051 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1052 1053 /* 1054 * Initialize for Isochronous Receive Queue. 1055 */ 1056 for (i = 0; i < sc->sc_isoctx; i++) { 1057 if (sc->sc_ctx_ir[i] != NULL) 1058 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1059 } 1060 } 1061 1062 static void 1063 fwohci_buf_start(struct fwohci_softc *sc) 1064 { 1065 int i; 1066 1067 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1068 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1069 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1070 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1071 for (i = 0; i < sc->sc_isoctx; i++) { 1072 if (sc->sc_ctx_ir[i] != NULL && 1073 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1074 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1075 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1076 } 1077 } 1078 } 1079 1080 static void 1081 fwohci_buf_stop(struct fwohci_softc *sc) 1082 { 1083 int i, j; 1084 1085 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1086 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1087 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1088 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1089 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1090 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1091 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1092 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1093 for (i = 0; i < sc->sc_isoctx; i++) { 1094 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1095 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1096 } 1097 1098 /* 1099 * Make sure the transmitter is stopped. 1100 */ 1101 for (j = 0; j < OHCI_LOOP; j++) { 1102 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1103 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1104 continue; 1105 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1106 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1107 continue; 1108 break; 1109 } 1110 } 1111 1112 static void 1113 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1114 { 1115 struct fwohci_buf *fb, *tfb; 1116 1117 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1118 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1119 fb->fb_desc->fd_rescount != 0) 1120 break; 1121 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1122 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1123 fb->fb_off = 0; 1124 fb->fb_desc->fd_branch = 0; 1125 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1126 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1127 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1128 } 1129 } 1130 1131 static int 1132 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1133 int len) 1134 { 1135 struct fwohci_buf *fb; 1136 struct fwohci_desc *fd; 1137 int bufend; 1138 1139 fb = TAILQ_FIRST(&fc->fc_buf); 1140 again: 1141 fd = fb->fb_desc; 1142 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1143 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1144 fd->fd_reqcount, fd->fd_rescount, len, 1145 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1146 bufend = fd->fd_reqcount - fd->fd_rescount; 1147 if (fb->fb_off >= bufend) { 1148 if (fc->fc_isoch && fb->fb_off > 0) { 1149 fb->fb_off = fd->fd_reqcount; 1150 fd->fd_rescount = 0; 1151 } 1152 if (fd->fd_rescount == 0) { 1153 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1154 goto again; 1155 } 1156 return 0; 1157 } 1158 if (fb->fb_off + len > bufend) 1159 len = bufend - fb->fb_off; 1160 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1161 BUS_DMASYNC_POSTREAD); 1162 *pp = fb->fb_buf + fb->fb_off; 1163 fb->fb_off += roundup(len, 4); 1164 return len; 1165 } 1166 1167 static int 1168 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1169 struct fwohci_pkt *pkt) 1170 { 1171 caddr_t p; 1172 int len, count, i; 1173 1174 memset(pkt, 0, sizeof(*pkt)); 1175 pkt->fp_uio.uio_iov = pkt->fp_iov; 1176 pkt->fp_uio.uio_rw = UIO_WRITE; 1177 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1178 1179 /* get first quadlet */ 1180 count = 4; 1181 if (fc->fc_isoch) { 1182 /* 1183 * get trailer first, may be bogus data unless status update 1184 * in descriptor is set. 1185 */ 1186 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1187 sizeof(*pkt->fp_trail)); 1188 if (len <= 0) { 1189 DPRINTFN(1, ("fwohci_buf_input: no input for is#%d\n", 1190 fc->fc_ctx)); 1191 return 0; 1192 } 1193 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1194 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1195 } 1196 len = fwohci_buf_pktget(sc, fc, &p, count); 1197 if (len <= 0) { 1198 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1199 fc->fc_ctx)); 1200 return 0; 1201 } 1202 pkt->fp_hdr[0] = *(u_int32_t *)p; 1203 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1204 switch (pkt->fp_tcode) { 1205 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1206 case IEEE1394_TCODE_READ_RESP_QUAD: 1207 pkt->fp_hlen = 12; 1208 pkt->fp_dlen = 4; 1209 break; 1210 case IEEE1394_TCODE_READ_REQ_BLOCK: 1211 pkt->fp_hlen = 16; 1212 pkt->fp_dlen = 0; 1213 break; 1214 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1215 case IEEE1394_TCODE_READ_RESP_BLOCK: 1216 case IEEE1394_TCODE_LOCK_REQ: 1217 case IEEE1394_TCODE_LOCK_RESP: 1218 pkt->fp_hlen = 16; 1219 break; 1220 case IEEE1394_TCODE_STREAM_DATA: 1221 pkt->fp_hlen = 4; 1222 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1223 break; 1224 default: 1225 pkt->fp_hlen = 12; 1226 pkt->fp_dlen = 0; 1227 break; 1228 } 1229 1230 /* get header */ 1231 while (count < pkt->fp_hlen) { 1232 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1233 if (len == 0) { 1234 printf("fwohci_buf_input: malformed input 1: %d\n", 1235 pkt->fp_hlen - count); 1236 return 0; 1237 } 1238 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1239 count += len; 1240 } 1241 if ((pkt->fp_hlen == 16) && 1242 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1243 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1244 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1245 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1246 1247 /* get data */ 1248 count = 0; 1249 i = 0; 1250 while (count < pkt->fp_dlen) { 1251 len = fwohci_buf_pktget(sc, fc, 1252 (caddr_t *)&pkt->fp_iov[i].iov_base, 1253 pkt->fp_dlen - count); 1254 if (len == 0) { 1255 printf("fwohci_buf_input: malformed input 2: %d\n", 1256 pkt->fp_hlen - count); 1257 return 0; 1258 } 1259 pkt->fp_iov[i++].iov_len = len; 1260 count += len; 1261 } 1262 pkt->fp_uio.uio_iovcnt = i; 1263 pkt->fp_uio.uio_resid = count; 1264 1265 if (!fc->fc_isoch) { 1266 /* get trailer */ 1267 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1268 sizeof(*pkt->fp_trail)); 1269 if (len <= 0) { 1270 printf("fwohci_buf_input: malformed input 3: %d\n", 1271 pkt->fp_hlen - count); 1272 return 0; 1273 } 1274 } 1275 return 1; 1276 } 1277 1278 static int 1279 fwohci_handler_set(struct fwohci_softc *sc, 1280 int tcode, u_int32_t key1, u_int32_t key2, 1281 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1282 void *arg) 1283 { 1284 struct fwohci_ctx *fc; 1285 struct fwohci_handler *fh; 1286 int i, j; 1287 1288 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1289 j = sc->sc_isoctx; 1290 fh = NULL; 1291 for (i = 0; i < sc->sc_isoctx; i++) { 1292 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1293 if (j == sc->sc_isoctx) 1294 j = i; 1295 continue; 1296 } 1297 fh = LIST_FIRST(&fc->fc_handler); 1298 if (fh == NULL) { 1299 j = i; 1300 break; 1301 } 1302 if (fh->fh_tcode == tcode && 1303 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1304 break; 1305 fh = NULL; 1306 } 1307 if (fh == NULL) { 1308 if (handler == NULL) 1309 return 0; 1310 if (j == sc->sc_isoctx) { 1311 DPRINTF(("fwohci_handler_set: no more free " 1312 "context\n")); 1313 return ENOMEM; 1314 } 1315 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1316 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1317 fc->fc_isoch = 1; 1318 sc->sc_ctx_ir[j] = fc; 1319 } 1320 } 1321 } else { 1322 switch (tcode) { 1323 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1324 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1325 case IEEE1394_TCODE_READ_REQ_QUAD: 1326 case IEEE1394_TCODE_READ_REQ_BLOCK: 1327 case IEEE1394_TCODE_LOCK_REQ: 1328 fc = sc->sc_ctx_arrq; 1329 break; 1330 case IEEE1394_TCODE_WRITE_RESP: 1331 case IEEE1394_TCODE_READ_RESP_QUAD: 1332 case IEEE1394_TCODE_READ_RESP_BLOCK: 1333 case IEEE1394_TCODE_LOCK_RESP: 1334 fc = sc->sc_ctx_arrs; 1335 break; 1336 default: 1337 return EIO; 1338 } 1339 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1340 fh = LIST_NEXT(fh, fh_list)) { 1341 if (fh->fh_tcode == tcode && 1342 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1343 break; 1344 } 1345 } 1346 if (handler == NULL) { 1347 if (fh != NULL) { 1348 LIST_REMOVE(fh, fh_list); 1349 free(fh, M_DEVBUF); 1350 } 1351 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1352 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1353 fwohci_ctx_free(sc, fc); 1354 } 1355 return 0; 1356 } 1357 if (fh == NULL) { 1358 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1359 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1360 } 1361 fh->fh_tcode = tcode; 1362 fh->fh_key1 = key1; 1363 fh->fh_key2 = key2; 1364 fh->fh_handler = handler; 1365 fh->fh_handarg = arg; 1366 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1367 fc->fc_ctx, tcode, key1, key2)); 1368 1369 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1370 fwohci_ctx_init(sc, fc); 1371 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1372 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1373 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1374 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1375 } 1376 return 0; 1377 } 1378 1379 /* 1380 * Asyncronous Receive Requests input frontend. 1381 */ 1382 static void 1383 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1384 { 1385 int rcode; 1386 u_int32_t key1, key2; 1387 struct fwohci_handler *fh; 1388 struct fwohci_pkt pkt, res; 1389 1390 while (fwohci_buf_input(sc, fc, &pkt)) { 1391 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1392 fwohci_phy_input(sc, &pkt); 1393 return; 1394 } 1395 key1 = pkt.fp_hdr[1] & 0xffff; 1396 key2 = pkt.fp_hdr[2]; 1397 memset(&res, 0, sizeof(res)); 1398 res.fp_uio.uio_rw = UIO_WRITE; 1399 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1400 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1401 fh = LIST_NEXT(fh, fh_list)) { 1402 if (pkt.fp_tcode == fh->fh_tcode && 1403 key1 == fh->fh_key1 && 1404 key2 == fh->fh_key2) { 1405 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1406 &pkt); 1407 break; 1408 } 1409 } 1410 if (fh == NULL) { 1411 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1412 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1413 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1414 key2)); 1415 } 1416 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1417 OHCI_CTXCTL_EVENT_ACK_PENDING) 1418 return; 1419 if (rcode != -1) 1420 fwohci_atrs_output(sc, rcode, &pkt, &res); 1421 } 1422 fwohci_buf_next(sc, fc); 1423 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1424 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1425 } 1426 1427 1428 /* 1429 * Asynchronous Receive Response input frontend. 1430 */ 1431 static void 1432 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1433 { 1434 struct fwohci_pkt pkt; 1435 struct fwohci_handler *fh; 1436 u_int16_t srcid; 1437 int rcode, tlabel; 1438 1439 while (fwohci_buf_input(sc, fc, &pkt)) { 1440 srcid = pkt.fp_hdr[1] >> 16; 1441 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1442 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1443 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1444 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1445 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1446 pkt.fp_dlen)); 1447 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1448 fh = LIST_NEXT(fh, fh_list)) { 1449 if (pkt.fp_tcode == fh->fh_tcode && 1450 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1451 tlabel == fh->fh_key2) { 1452 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1453 LIST_REMOVE(fh, fh_list); 1454 free(fh, M_DEVBUF); 1455 break; 1456 } 1457 } 1458 if (fh == NULL) 1459 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1460 } 1461 fwohci_buf_next(sc, fc); 1462 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1463 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1464 } 1465 1466 /* 1467 * Isochronous Receive input frontend. 1468 */ 1469 static void 1470 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1471 { 1472 int rcode, chan, tag; 1473 struct iovec *iov; 1474 struct fwohci_handler *fh; 1475 struct fwohci_pkt pkt; 1476 1477 while (fwohci_buf_input(sc, fc, &pkt)) { 1478 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1479 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1480 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1481 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1482 pkt.fp_dlen)); 1483 if (tag == IEEE1394_TAG_GASP) { 1484 /* 1485 * The pkt with tag=3 is GASP format. 1486 * Move GASP header to header part. 1487 */ 1488 if (pkt.fp_dlen < 8) 1489 continue; 1490 iov = pkt.fp_iov; 1491 /* assuming pkt per buffer mode */ 1492 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1493 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1494 iov->iov_base = (caddr_t)iov->iov_base + 8; 1495 iov->iov_len -= 8; 1496 pkt.fp_hlen += 8; 1497 pkt.fp_dlen -= 8; 1498 } 1499 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1500 fh = LIST_NEXT(fh, fh_list)) { 1501 if (pkt.fp_tcode == fh->fh_tcode && 1502 chan == fh->fh_key1 && tag == fh->fh_key2) { 1503 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1504 &pkt); 1505 break; 1506 } 1507 } 1508 #ifdef FW_DEBUG 1509 if (fh == NULL) { 1510 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1511 } else { 1512 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1513 } 1514 #endif 1515 } 1516 fwohci_buf_next(sc, fc); 1517 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1518 OHCI_CTXCTL_WAKE); 1519 } 1520 1521 /* 1522 * Asynchronous Transmit common routine. 1523 */ 1524 static int 1525 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1526 struct fwohci_pkt *pkt) 1527 { 1528 struct fwohci_buf *fb; 1529 struct fwohci_desc *fd; 1530 struct mbuf *m, *m0; 1531 int i, ndesc, error, off, len; 1532 u_int32_t val; 1533 #ifdef FW_DEBUG 1534 struct iovec *iov; 1535 #endif 1536 1537 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1538 /* We can't send anything during selfid duration */ 1539 return EAGAIN; 1540 1541 #ifdef FW_DEBUG 1542 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1543 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1544 for (i = 0; i < pkt->fp_hlen/4; i++) 1545 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 1546 DPRINTFN(2, ("$")); 1547 for (ndesc = 0, iov = pkt->fp_iov; 1548 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1549 for (i = 0; i < iov->iov_len; i++) 1550 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1551 ((u_int8_t *)iov->iov_base)[i])); 1552 DPRINTFN(2, ("$")); 1553 } 1554 DPRINTFN(1, ("\n")); 1555 #endif 1556 1557 if ((m = pkt->fp_m) != NULL) { 1558 for (ndesc = 2; m != NULL; m = m->m_next) 1559 ndesc++; 1560 if (ndesc > OHCI_DESC_MAX) { 1561 m0 = NULL; 1562 ndesc = 2; 1563 for (off = 0; off < pkt->fp_dlen; off += len) { 1564 if (m0 == NULL) { 1565 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1566 if (m0 != NULL) 1567 M_COPY_PKTHDR(m0, pkt->fp_m); 1568 m = m0; 1569 } else { 1570 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1571 m = m->m_next; 1572 } 1573 if (m != NULL) 1574 MCLGET(m, M_DONTWAIT); 1575 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1576 m_freem(m0); 1577 return ENOMEM; 1578 } 1579 len = pkt->fp_dlen - off; 1580 if (len > m->m_ext.ext_size) 1581 len = m->m_ext.ext_size; 1582 m_copydata(pkt->fp_m, off, len, 1583 mtod(m, caddr_t)); 1584 m->m_len = len; 1585 ndesc++; 1586 } 1587 m_freem(pkt->fp_m); 1588 pkt->fp_m = m0; 1589 } 1590 } else 1591 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1592 1593 if (ndesc > OHCI_DESC_MAX) 1594 return ENOBUFS; 1595 1596 if (fc->fc_bufcnt > 50) /*XXX*/ 1597 return ENOBUFS; 1598 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1599 fb->fb_nseg = ndesc; 1600 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1601 if (fb->fb_desc == NULL) { 1602 free(fb, M_DEVBUF); 1603 return ENOBUFS; 1604 } 1605 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1606 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1607 fb->fb_m = pkt->fp_m; 1608 fb->fb_callback = pkt->fp_callback; 1609 fb->fb_statuscb = pkt->fp_statuscb; 1610 fb->fb_statusarg = pkt->fp_statusarg; 1611 1612 if (ndesc > 2) { 1613 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1614 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1615 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1616 free(fb, M_DEVBUF); 1617 return error; 1618 } 1619 1620 if (pkt->fp_m != NULL) 1621 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1622 pkt->fp_m, BUS_DMA_WAITOK); 1623 else 1624 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1625 &pkt->fp_uio, BUS_DMA_WAITOK); 1626 if (error != 0) { 1627 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1628 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1629 free(fb, M_DEVBUF); 1630 return error; 1631 } 1632 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1633 BUS_DMASYNC_PREWRITE); 1634 } 1635 1636 fd = fb->fb_desc; 1637 fd->fd_flags = OHCI_DESC_IMMED; 1638 fd->fd_reqcount = pkt->fp_hlen; 1639 fd->fd_data = 0; 1640 fd->fd_branch = 0; 1641 fd->fd_status = 0; 1642 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1643 i = 3; /* XXX: 3 sec */ 1644 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1645 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1646 ((((val >> 25) + i) & 0x7) << 13); 1647 } else 1648 fd->fd_timestamp = 0; 1649 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1650 for (i = 0; i < ndesc - 2; i++) { 1651 fd = fb->fb_desc + 2 + i; 1652 fd->fd_flags = 0; 1653 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1654 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1655 fd->fd_branch = 0; 1656 fd->fd_status = 0; 1657 fd->fd_timestamp = 0; 1658 } 1659 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1660 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1661 1662 #ifdef FW_DEBUG 1663 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1664 (long)(fb->fb_desc - sc->sc_desc))); 1665 for (i = 0; i < ndesc * 4; i++) 1666 DPRINTFN(1, ("%s%08x", i&7?" ":"\n\t", 1667 ((u_int32_t *)fb->fb_desc)[i])); 1668 DPRINTFN(1, ("\n")); 1669 #endif 1670 1671 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1672 OHCI_SUBREG_ContextControlClear); 1673 1674 if (val & OHCI_CTXCTL_RUN) { 1675 if (fc->fc_branch == NULL) { 1676 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1677 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1678 goto run; 1679 } 1680 *fc->fc_branch = fb->fb_daddr | ndesc; 1681 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1682 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1683 } else { 1684 run: 1685 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1686 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1687 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1688 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1689 } 1690 fc->fc_branch = &fd->fd_branch; 1691 1692 fc->fc_bufcnt++; 1693 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1694 pkt->fp_m = NULL; 1695 return 0; 1696 } 1697 1698 static void 1699 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1700 { 1701 struct fwohci_buf *fb; 1702 struct fwohci_desc *fd; 1703 struct fwohci_pkt pkt; 1704 int i; 1705 1706 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1707 fd = fb->fb_desc; 1708 #ifdef FW_DEBUG 1709 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1710 force ? "force " : "", (long)(fd - sc->sc_desc), 1711 fb->fb_nseg)); 1712 for (i = 0; i < fb->fb_nseg * 4; i++) 1713 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", 1714 ((u_int32_t *)fd)[i])); 1715 DPRINTFN(1, ("\n")); 1716 #endif 1717 if (fb->fb_nseg > 2) 1718 fd += fb->fb_nseg - 1; 1719 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1720 break; 1721 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1722 if (fc->fc_branch == &fd->fd_branch) { 1723 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1724 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1725 fc->fc_branch = NULL; 1726 for (i = 0; i < OHCI_LOOP; i++) { 1727 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1728 OHCI_SUBREG_ContextControlClear) & 1729 OHCI_CTXCTL_ACTIVE)) 1730 break; 1731 } 1732 } 1733 1734 if (fb->fb_statuscb) { 1735 memset(&pkt, 0, sizeof(pkt)); 1736 pkt.fp_status = fd->fd_status; 1737 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1738 1739 /* Indicate this is just returning the status bits. */ 1740 pkt.fp_tcode = -1; 1741 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1742 fb->fb_statuscb = NULL; 1743 fb->fb_statusarg = NULL; 1744 } 1745 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1746 if (fb->fb_nseg > 2) 1747 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1748 fc->fc_bufcnt--; 1749 if (fb->fb_callback) { 1750 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1751 fb->fb_callback = NULL; 1752 } else if (fb->fb_m != NULL) 1753 m_freem(fb->fb_m); 1754 free(fb, M_DEVBUF); 1755 } 1756 } 1757 1758 /* 1759 * Asynchronous Transmit Reponse -- in response of request packet. 1760 */ 1761 static void 1762 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1763 struct fwohci_pkt *res) 1764 { 1765 1766 if (((*req->fp_trail & 0x001f0000) >> 16) != 1767 OHCI_CTXCTL_EVENT_ACK_PENDING) 1768 return; 1769 1770 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1771 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1772 switch (req->fp_tcode) { 1773 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1774 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1775 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1776 res->fp_hlen = 12; 1777 break; 1778 case IEEE1394_TCODE_READ_REQ_QUAD: 1779 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1780 res->fp_hlen = 16; 1781 res->fp_dlen = 0; 1782 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1783 res->fp_hdr[3] = 1784 *(u_int32_t *)res->fp_iov[0].iov_base; 1785 res->fp_uio.uio_iovcnt = 0; 1786 break; 1787 case IEEE1394_TCODE_READ_REQ_BLOCK: 1788 case IEEE1394_TCODE_LOCK_REQ: 1789 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1790 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1791 else 1792 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1793 res->fp_hlen = 16; 1794 res->fp_dlen = res->fp_uio.uio_resid; 1795 res->fp_hdr[3] = res->fp_dlen << 16; 1796 break; 1797 } 1798 res->fp_hdr[0] |= (res->fp_tcode << 4); 1799 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1800 } 1801 1802 /* 1803 * APPLICATION LAYER SERVICES 1804 */ 1805 1806 /* 1807 * Retrieve Global UID from GUID ROM 1808 */ 1809 static int 1810 fwohci_guidrom_init(struct fwohci_softc *sc) 1811 { 1812 int i, n, off; 1813 u_int32_t val1, val2; 1814 1815 /* Extract the Global UID 1816 */ 1817 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1818 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1819 1820 if (val1 != 0 || val2 != 0) { 1821 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1822 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1823 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1824 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1825 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1826 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1827 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1828 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1829 } else { 1830 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1831 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1832 return -1; 1833 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1834 for (i = 0; i < OHCI_LOOP; i++) { 1835 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1836 if (!(val1 & OHCI_Guid_AddrReset)) 1837 break; 1838 } 1839 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1840 val2 = 0; 1841 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1842 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1843 OHCI_Guid_RdStart); 1844 for (i = 0; i < OHCI_LOOP; i++) { 1845 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1846 if (!(val1 & OHCI_Guid_RdStart)) 1847 break; 1848 } 1849 if (n < off) 1850 continue; 1851 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1852 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1853 val2 |= val1; 1854 } 1855 if (val2 == 0) 1856 return -1; 1857 } 1858 return 0; 1859 } 1860 1861 /* 1862 * Initialization for Configuration ROM (no DMA context) 1863 */ 1864 1865 #define CFR_MAXUNIT 20 1866 1867 struct configromctx { 1868 u_int32_t *ptr; 1869 int curunit; 1870 struct { 1871 u_int32_t *start; 1872 int length; 1873 u_int32_t *refer; 1874 int refunit; 1875 } unit[CFR_MAXUNIT]; 1876 }; 1877 1878 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1879 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1880 1881 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1882 1883 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1884 1885 #define CFR_PUT_CRC(cfr, n) \ 1886 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1887 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1888 1889 #define CFR_START_UNIT(cfr, n) \ 1890 do { \ 1891 if ((cfr)->unit[n].refer != NULL) { \ 1892 *(cfr)->unit[n].refer |= \ 1893 (cfr)->ptr - (cfr)->unit[n].refer; \ 1894 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1895 } \ 1896 (cfr)->curunit = (n); \ 1897 (cfr)->unit[n].start = (cfr)->ptr++; \ 1898 } while (0 /* CONSTCOND */) 1899 1900 #define CFR_PUT_REFER(cfr, key, n) \ 1901 do { \ 1902 (cfr)->unit[n].refer = (cfr)->ptr; \ 1903 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1904 *(cfr)->ptr++ = (key) << 24; \ 1905 } while (0 /* CONSTCOND */) 1906 1907 #define CFR_END_UNIT(cfr) \ 1908 do { \ 1909 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1910 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1911 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1912 } while (0 /* CONSTCOND */) 1913 1914 static u_int16_t 1915 fwohci_crc16(u_int32_t *ptr, int len) 1916 { 1917 int shift; 1918 u_int32_t crc, sum, data; 1919 1920 crc = 0; 1921 while (len-- > 0) { 1922 data = *ptr++; 1923 for (shift = 28; shift >= 0; shift -= 4) { 1924 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1925 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1926 } 1927 crc &= 0xffff; 1928 } 1929 return crc; 1930 } 1931 1932 static void 1933 fwohci_configrom_init(struct fwohci_softc *sc) 1934 { 1935 int i, val; 1936 struct fwohci_buf *fb; 1937 u_int32_t *hdr; 1938 struct configromctx cfr; 1939 1940 fb = &sc->sc_buf_cnfrom; 1941 memset(&cfr, 0, sizeof(cfr)); 1942 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1943 1944 /* headers */ 1945 CFR_START_UNIT(&cfr, 0); 1946 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1947 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1948 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1949 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1950 CFR_END_UNIT(&cfr); 1951 /* copy info_length from crc_length */ 1952 *hdr |= (*hdr & 0x00ff0000) << 8; 1953 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1954 1955 /* root directory */ 1956 CFR_START_UNIT(&cfr, 1); 1957 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1958 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1959 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1960 /* spt,64,fix,lst,drq */ 1961 #ifdef INET 1962 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1963 #endif /* INET */ 1964 #ifdef INET6 1965 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1966 #endif /* INET6 */ 1967 CFR_END_UNIT(&cfr); 1968 1969 CFR_START_UNIT(&cfr, 2); 1970 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1971 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1972 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1973 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1974 CFR_END_UNIT(&cfr); 1975 1976 #ifdef INET 1977 /* IPv4 unit directory */ 1978 CFR_START_UNIT(&cfr, 3); 1979 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1980 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1981 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1982 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1983 CFR_END_UNIT(&cfr); 1984 1985 CFR_START_UNIT(&cfr, 6); 1986 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1987 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1988 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1989 CFR_END_UNIT(&cfr); 1990 1991 CFR_START_UNIT(&cfr, 7); 1992 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1993 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1994 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1995 CFR_END_UNIT(&cfr); 1996 #endif /* INET */ 1997 1998 #ifdef INET6 1999 /* IPv6 unit directory */ 2000 CFR_START_UNIT(&cfr, 4); 2001 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2002 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2003 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2004 /* XXX: TBA by IANA */ 2005 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2006 CFR_END_UNIT(&cfr); 2007 2008 CFR_START_UNIT(&cfr, 8); 2009 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2010 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2011 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2012 CFR_END_UNIT(&cfr); 2013 2014 CFR_START_UNIT(&cfr, 9); 2015 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2016 CFR_PUT_DATA1(&cfr, 0); 2017 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2018 CFR_END_UNIT(&cfr); 2019 #endif /* INET6 */ 2020 2021 fb->fb_off = cfr.ptr - hdr; 2022 #ifdef FW_DEBUG 2023 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2024 for (i = 0; i < fb->fb_off; i++) 2025 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2026 DPRINTFN(2, ("\n")); 2027 #endif /* FW_DEBUG */ 2028 2029 /* 2030 * Make network byte order for DMA 2031 */ 2032 for (i = 0; i < fb->fb_off; i++) 2033 HTONL(hdr[i]); 2034 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2035 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2036 2037 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2038 fb->fb_dmamap->dm_segs[0].ds_addr); 2039 2040 /* This register is only valid on OHCI 1.1. */ 2041 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2042 if ((OHCI_Version_GET_Version(val) == 1) && 2043 (OHCI_Version_GET_Revision(val) == 1)) 2044 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2045 OHCI_HCControl_BIBImageValid); 2046 2047 /* Just allow quad reads of the rom. */ 2048 for (i = 0; i < fb->fb_off; i++) 2049 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2050 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2051 fwohci_configrom_input, NULL); 2052 } 2053 2054 static int 2055 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2056 struct fwohci_pkt *pkt) 2057 { 2058 struct fwohci_pkt res; 2059 u_int32_t loc, *rom; 2060 2061 /* This will be used as an array index so size accordingly. */ 2062 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2063 if ((loc & 0x03) != 0) { 2064 /* alignment error */ 2065 return IEEE1394_RCODE_ADDRESS_ERROR; 2066 } 2067 else 2068 loc /= 4; 2069 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2070 2071 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2072 ntohl(rom[loc]))); 2073 2074 memset(&res, 0, sizeof(res)); 2075 res.fp_hdr[3] = rom[loc]; 2076 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2077 return -1; 2078 } 2079 2080 /* 2081 * SelfID buffer (no DMA context) 2082 */ 2083 static void 2084 fwohci_selfid_init(struct fwohci_softc *sc) 2085 { 2086 struct fwohci_buf *fb; 2087 2088 fb = &sc->sc_buf_selfid; 2089 #ifdef DIAGNOSTIC 2090 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2091 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2092 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2093 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2094 #endif 2095 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2096 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2097 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2098 2099 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2100 fb->fb_dmamap->dm_segs[0].ds_addr); 2101 } 2102 2103 static int 2104 fwohci_selfid_input(struct fwohci_softc *sc) 2105 { 2106 int i; 2107 u_int32_t count, val, gen; 2108 u_int32_t *buf; 2109 2110 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2111 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2112 again: 2113 if (val & OHCI_SelfID_Error) { 2114 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2115 return -1; 2116 } 2117 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2118 2119 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2120 0, count << 2, BUS_DMASYNC_POSTREAD); 2121 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2122 2123 #ifdef FW_DEBUG 2124 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2125 val)); 2126 for (i = 0; i < count; i++) 2127 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", buf[i])); 2128 DPRINTFN(1, ("\n")); 2129 #endif /* FW_DEBUG */ 2130 2131 for (i = 1; i < count; i += 2) { 2132 if (buf[i] != ~buf[i + 1]) 2133 break; 2134 if (buf[i] & 0x00000001) 2135 continue; /* more pkt */ 2136 if (buf[i] & 0x00800000) 2137 continue; /* external id */ 2138 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2139 if ((buf[i] & 0x00400800) == 0x00400800) 2140 sc->sc_irmid = sc->sc_rootid; 2141 } 2142 2143 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2144 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2145 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2146 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2147 goto again; 2148 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2149 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2150 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2151 return -1; 2152 } 2153 if (i != count) { 2154 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2155 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2156 #if 1 2157 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2158 /* 2159 * XXX: CXD3222 sometimes fails to DMA 2160 * selfid packet?? 2161 */ 2162 sc->sc_rootid = (count - 1) / 2 - 1; 2163 sc->sc_irmid = sc->sc_rootid; 2164 } else 2165 #endif 2166 return -1; 2167 } 2168 2169 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2170 if ((val & OHCI_NodeId_IDValid) == 0) { 2171 sc->sc_nodeid = 0xffff; /* invalid */ 2172 printf("%s: nodeid is invalid\n", 2173 sc->sc_sc1394.sc1394_dev.dv_xname); 2174 return -1; 2175 } 2176 sc->sc_nodeid = val & 0xffff; 2177 2178 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2179 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2180 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2181 sc->sc_irmid)); 2182 2183 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2184 return -1; 2185 2186 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2187 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2188 OHCI_LinkControl_CycleMaster); 2189 else 2190 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2191 OHCI_LinkControl_CycleMaster); 2192 return 0; 2193 } 2194 2195 /* 2196 * some CSRs are handled by driver. 2197 */ 2198 static void 2199 fwohci_csr_init(struct fwohci_softc *sc) 2200 { 2201 int i; 2202 static u_int32_t csr[] = { 2203 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2204 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2205 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2206 CSR_SB_BROADCAST_CHANNEL 2207 }; 2208 2209 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2210 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2211 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2212 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2213 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2214 } 2215 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2216 } 2217 2218 static int 2219 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2220 { 2221 struct fwohci_pkt res; 2222 u_int32_t reg; 2223 2224 /* 2225 * XXX need to do special functionality other than just r/w... 2226 */ 2227 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2228 2229 if ((reg & 0x03) != 0) { 2230 /* alignment error */ 2231 return IEEE1394_RCODE_ADDRESS_ERROR; 2232 } 2233 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2234 *(u_int32_t *)(&sc->sc_csr[reg]))); 2235 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2236 DPRINTFN(1, (" -> 0x%08x\n", 2237 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2238 *(u_int32_t *)&sc->sc_csr[reg] = 2239 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2240 } else { 2241 DPRINTFN(1, ("\n")); 2242 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2243 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2244 res.fp_iov[0].iov_len = 4; 2245 res.fp_uio.uio_resid = 4; 2246 res.fp_uio.uio_iovcnt = 1; 2247 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2248 return -1; 2249 } 2250 return IEEE1394_RCODE_COMPLETE; 2251 } 2252 2253 /* 2254 * Mapping between nodeid and unique ID (EUI-64). 2255 * 2256 * Track old mappings and simply update their devices with the new id's when 2257 * they match an existing EUI. This allows proper renumeration of the bus. 2258 */ 2259 static void 2260 fwohci_uid_collect(struct fwohci_softc *sc) 2261 { 2262 int i; 2263 struct fwohci_uidtbl *fu; 2264 struct fwohci_pkt pkt; 2265 struct ieee1394_softc *iea; 2266 2267 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2268 iea->sc1394_node_id = 0xffff; 2269 2270 if (sc->sc_uidtbl != NULL) 2271 free(sc->sc_uidtbl, M_DEVBUF); 2272 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2273 M_WAITOK); 2274 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2275 2276 memset(&pkt, 0, sizeof(pkt)); 2277 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2278 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2279 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2280 fu->fu_valid = 3; 2281 2282 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2283 if (iea) { 2284 iea->sc1394_node_id = i; 2285 DPRINTF(("%s: Updating nodeid to %d\n", 2286 iea->sc1394_dev.dv_xname, 2287 iea->sc1394_node_id)); 2288 } 2289 continue; 2290 } 2291 fu->fu_valid = 0; 2292 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2293 pkt.fp_hlen = 12; 2294 pkt.fp_dlen = 0; 2295 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2296 (pkt.fp_tcode << 4); 2297 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2298 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2299 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2300 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2301 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2302 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2303 2304 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2305 (pkt.fp_tcode << 4); 2306 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2307 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2308 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2309 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2310 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2311 2312 } 2313 if (sc->sc_rootid == 0) 2314 fwohci_check_nodes(sc); 2315 } 2316 2317 static int 2318 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2319 { 2320 struct fwohci_uidtbl *fu; 2321 struct ieee1394_softc *iea; 2322 struct ieee1394_attach_args fwa; 2323 int i, n, done, rcode, found; 2324 2325 found = 0; 2326 2327 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2328 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2329 if (rcode != IEEE1394_RCODE_COMPLETE || 2330 sc->sc_uidtbl == NULL || 2331 n > sc->sc_rootid) 2332 return 0; 2333 fu = &sc->sc_uidtbl[n]; 2334 if (arg == 0) { 2335 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2336 fu->fu_valid |= 0x1; 2337 } else { 2338 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2339 fu->fu_valid |= 0x2; 2340 } 2341 #ifdef FW_DEBUG 2342 if (fu->fu_valid == 0x3) 2343 DPRINTFN(1, ("fwohci_uid_input: " 2344 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2345 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2346 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2347 #endif 2348 if (fu->fu_valid == 0x3) { 2349 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2350 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2351 found = 1; 2352 iea->sc1394_node_id = n; 2353 DPRINTF(("%s: Updating nodeid to %d\n", 2354 iea->sc1394_dev.dv_xname, 2355 iea->sc1394_node_id)); 2356 break; 2357 } 2358 if (!found) { 2359 strcpy(fwa.name, "fwnode"); 2360 memcpy(fwa.uid, fu->fu_uid, 8); 2361 fwa.nodeid = n; 2362 fwa.read = fwohci_read; 2363 fwa.write = fwohci_write; 2364 fwa.inreg = fwohci_inreg; 2365 iea = (struct ieee1394_softc *) 2366 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2367 fwohci_print, fwohci_submatch); 2368 if (iea != NULL) 2369 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2370 sc1394_node); 2371 } 2372 } 2373 done = 1; 2374 2375 for (i = 0; i < sc->sc_rootid + 1; i++) { 2376 fu = &sc->sc_uidtbl[i]; 2377 if (fu->fu_valid != 0x3) { 2378 done = 0; 2379 break; 2380 } 2381 } 2382 if (done) 2383 fwohci_check_nodes(sc); 2384 2385 return 0; 2386 } 2387 2388 static void 2389 fwohci_check_nodes(struct fwohci_softc *sc) 2390 { 2391 struct device *detach = NULL; 2392 struct ieee1394_softc *iea; 2393 2394 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2395 2396 /* 2397 * Have to defer detachment until the next 2398 * loop iteration since config_detach 2399 * free's the softc and the loop iterator 2400 * needs data from the softc to move 2401 * forward. 2402 */ 2403 2404 if (detach) { 2405 config_detach(detach, 0); 2406 detach = NULL; 2407 } 2408 if (iea->sc1394_node_id == 0xffff) { 2409 detach = (struct device *)iea; 2410 LIST_REMOVE(iea, sc1394_node); 2411 } 2412 } 2413 if (detach) 2414 config_detach(detach, 0); 2415 } 2416 2417 static int 2418 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2419 { 2420 struct fwohci_uidtbl *fu; 2421 int n; 2422 static const u_int8_t bcast[] = 2423 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2424 2425 fu = sc->sc_uidtbl; 2426 if (fu == NULL) { 2427 notfound: 2428 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2429 return IEEE1394_BCAST_PHY_ID; 2430 fwohci_uid_collect(sc); /* try to get */ 2431 return -1; 2432 } 2433 for (n = 0; ; n++, fu++) { 2434 if (n > sc->sc_rootid) 2435 goto notfound; 2436 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2437 break; 2438 } 2439 return n; 2440 } 2441 2442 /* 2443 * functions to support network interface 2444 */ 2445 static int 2446 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2447 void (*handler)(struct device *, struct mbuf *)) 2448 { 2449 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2450 2451 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2452 fwohci_if_input, handler); 2453 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2454 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2455 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2456 return 0; 2457 } 2458 2459 static int 2460 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2461 { 2462 int n, len; 2463 struct mbuf *m; 2464 struct iovec *iov; 2465 void (*handler)(struct device *, struct mbuf *) = arg; 2466 2467 #ifdef FW_DEBUG 2468 int i; 2469 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2470 pkt->fp_dlen)); 2471 for (i = 0; i < pkt->fp_hlen/4; i++) 2472 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2473 DPRINTFN(2, ("$")); 2474 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2475 iov = &pkt->fp_iov[n]; 2476 for (i = 0; i < iov->iov_len; i++) 2477 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 2478 ((u_int8_t *)iov->iov_base)[i])); 2479 DPRINTFN(2, ("$")); 2480 } 2481 DPRINTFN(1, ("\n")); 2482 #endif /* FW_DEBUG */ 2483 len = pkt->fp_dlen; 2484 MGETHDR(m, M_DONTWAIT, MT_DATA); 2485 if (m == NULL) 2486 return IEEE1394_RCODE_COMPLETE; 2487 m->m_len = 16; 2488 if (len + m->m_len > MHLEN) { 2489 MCLGET(m, M_DONTWAIT); 2490 if ((m->m_flags & M_EXT) == 0) { 2491 m_freem(m); 2492 return IEEE1394_RCODE_COMPLETE; 2493 } 2494 } 2495 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2496 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2497 sc->sc_uidtbl[n].fu_valid != 0x3) { 2498 printf("%s: packet from unknown node: phy id %d\n", 2499 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2500 m_freem(m); 2501 return IEEE1394_RCODE_COMPLETE; 2502 } 2503 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2504 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2505 m->m_flags |= M_BCAST; 2506 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2507 } else { 2508 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2509 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2510 } 2511 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2512 mtod(m, u_int8_t *)[9] = 2513 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2514 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2515 2516 m->m_pkthdr.rcvif = NULL; /* set in child */ 2517 m->m_pkthdr.len = len + m->m_len; 2518 /* 2519 * We may use receive buffer by external mbuf instead of copy here. 2520 * But asynchronous receive buffer must be operate in buffer fill 2521 * mode, so that each receive buffer will shared by multiple mbufs. 2522 * If upper layer doesn't free mbuf soon, e.g. application program 2523 * is suspended, buffer must be reallocated. 2524 * Isochronous buffer must be operate in packet buffer mode, and 2525 * it is easy to map receive buffer to external mbuf. But it is 2526 * used for broadcast/multicast only, and is expected not so 2527 * performance sensitive for now. 2528 * XXX: The performance may be important for multicast case, 2529 * so we should revisit here later. 2530 * -- onoe 2531 */ 2532 n = 0; 2533 iov = pkt->fp_uio.uio_iov; 2534 while (len > 0) { 2535 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2536 iov->iov_len); 2537 m->m_len += iov->iov_len; 2538 len -= iov->iov_len; 2539 iov++; 2540 } 2541 (*handler)(sc->sc_sc1394.sc1394_if, m); 2542 return IEEE1394_RCODE_COMPLETE; 2543 } 2544 2545 static int 2546 fwohci_if_output(struct device *self, struct mbuf *m0, 2547 void (*callback)(struct device *, struct mbuf *)) 2548 { 2549 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2550 struct fwohci_pkt pkt; 2551 u_int8_t *p; 2552 int n, error, spd, hdrlen, maxrec; 2553 #ifdef FW_DEBUG 2554 struct mbuf *m; 2555 #endif 2556 2557 p = mtod(m0, u_int8_t *); 2558 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2559 spd = IEEE1394_SPD_S100; /*XXX*/ 2560 maxrec = 512; /*XXX*/ 2561 hdrlen = 8; 2562 } else { 2563 n = fwohci_uid_lookup(sc, p); 2564 if (n < 0) { 2565 printf("%s: nodeid unknown:" 2566 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2567 sc->sc_sc1394.sc1394_dev.dv_xname, 2568 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2569 error = EHOSTUNREACH; 2570 goto end; 2571 } 2572 if (n == IEEE1394_BCAST_PHY_ID) { 2573 printf("%s: broadcast with !M_MCAST\n", 2574 sc->sc_sc1394.sc1394_dev.dv_xname); 2575 #ifdef FW_DEBUG 2576 DPRINTFN(2, ("packet:")); 2577 for (m = m0; m != NULL; m = m->m_next) { 2578 for (n = 0; n < m->m_len; n++) 2579 DPRINTFN(2, ("%s%02x", (n%32)? 2580 ((n%4)?"":" "):"\n\t", 2581 mtod(m, u_int8_t *)[n])); 2582 DPRINTFN(2, ("$")); 2583 } 2584 DPRINTFN(2, ("\n")); 2585 #endif 2586 error = EHOSTUNREACH; 2587 goto end; 2588 } 2589 maxrec = 2 << p[8]; 2590 spd = p[9]; 2591 hdrlen = 0; 2592 } 2593 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2594 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2595 spd, sc->sc_sc1394.sc1394_link_speed)); 2596 spd = sc->sc_sc1394.sc1394_link_speed; 2597 } 2598 if (maxrec > (512 << spd)) { 2599 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2600 "\n", maxrec, spd)); 2601 maxrec = 512 << spd; 2602 } 2603 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2604 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2605 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2606 maxrec >>= 1; 2607 } 2608 if (maxrec < 512) { 2609 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2610 "minimum\n", maxrec)); 2611 maxrec = 512; 2612 } 2613 2614 m_adj(m0, 16 - hdrlen); 2615 if (m0->m_pkthdr.len > maxrec) { 2616 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2617 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2618 error = E2BIG; /*XXX*/ 2619 goto end; 2620 } 2621 2622 memset(&pkt, 0, sizeof(pkt)); 2623 pkt.fp_uio.uio_iov = pkt.fp_iov; 2624 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2625 pkt.fp_uio.uio_rw = UIO_WRITE; 2626 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2627 /* construct GASP header */ 2628 p = mtod(m0, u_int8_t *); 2629 p[0] = sc->sc_nodeid >> 8; 2630 p[1] = sc->sc_nodeid & 0xff; 2631 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2632 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2633 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2634 pkt.fp_hlen = 8; 2635 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2636 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2637 OHCI_NodeId_NodeNumber) << 8); 2638 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2639 } else { 2640 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2641 pkt.fp_hlen = 16; 2642 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2643 (spd << 16); 2644 pkt.fp_hdr[1] = 2645 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2646 (p[10] << 8) | p[11]; 2647 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2648 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2649 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2650 } 2651 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2652 pkt.fp_dlen = m0->m_pkthdr.len; 2653 pkt.fp_m = m0; 2654 pkt.fp_callback = callback; 2655 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2656 m0 = pkt.fp_m; 2657 end: 2658 if (m0 != NULL) { 2659 if (callback) 2660 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2661 else 2662 m_freem(m0); 2663 } 2664 return error; 2665 } 2666 2667 /* 2668 * High level routines to provide abstraction to attaching layers to 2669 * send/receive data. 2670 */ 2671 2672 /* 2673 * These break down into 4 routines as follows: 2674 * 2675 * int fwohci_read(struct ieee1394_abuf *) 2676 * 2677 * This routine will attempt to read a region from the requested node. 2678 * A callback must be provided which will be called when either the completed 2679 * read is done or an unrecoverable error occurs. This is mainly a convenience 2680 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2681 * and recombining all the returned data. This could also be done with a series 2682 * of write/inreg's for each packet sent. 2683 * 2684 * int fwohci_write(struct ieee1394_abuf *) 2685 * 2686 * The work horse main entry point for putting packets on the bus. This is the 2687 * generalized interface for fwnode/etc code to put packets out onto the bus. 2688 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2689 * will callback via a func pointer to the calling code with the resulting ACK 2690 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2691 * write routine will take care of free'ing the abuf since the fwnode/etc code 2692 * won't have any knowledge of when to do this. This allows for simple one-off 2693 * packets to be sent from the upper-level code without worrying about a callback 2694 * for cleanup. 2695 * 2696 * int fwohci_inreg(struct ieee1394_abuf *, int) 2697 * 2698 * This is very simple. It evals the abuf passed in and registers an internal 2699 * handler as the callback for packets received for that operation. 2700 * The integer argument specifies whether on a block read/write operation to 2701 * allow sub-regions to be read/written (in block form) as well. 2702 * 2703 * XXX: This whole structure needs to be redone as a list of regions and 2704 * operations allowed on those regions. 2705 * 2706 * int fwohci_unreg(struct ieee1394_abuf *, int) 2707 * 2708 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2709 * routine will simply verify ab_cb is NULL and call inreg. 2710 * 2711 * This simply unregisters the respective callback done via inreg for items 2712 * which only need to register an area for a one-time operation (like a status 2713 * buffer a remote node will write to when the current operation is done). The 2714 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2715 * it unregisters). 2716 */ 2717 2718 static int 2719 fwohci_read(struct ieee1394_abuf *ab) 2720 { 2721 struct fwohci_pkt pkt; 2722 struct ieee1394_softc *sc = ab->ab_req; 2723 struct fwohci_softc *psc = 2724 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2725 struct fwohci_cb *fcb; 2726 u_int32_t high, lo; 2727 int rv, tcode; 2728 2729 /* Have to have a callback when reading. */ 2730 if (ab->ab_cb == NULL) 2731 return -1; 2732 2733 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2734 fcb->ab = ab; 2735 fcb->count = 0; 2736 fcb->abuf_valid = 1; 2737 2738 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2739 lo = (ab->ab_csr & 0x00000000ffffffff); 2740 2741 memset(&pkt, 0, sizeof(pkt)); 2742 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2743 pkt.fp_hdr[2] = lo; 2744 pkt.fp_dlen = 0; 2745 2746 if (ab->ab_length == 4) { 2747 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2748 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2749 pkt.fp_hlen = 12; 2750 } else { 2751 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2752 pkt.fp_hlen = 16; 2753 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2754 pkt.fp_hdr[3] = (ab->ab_length << 16); 2755 } 2756 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2757 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2758 2759 pkt.fp_statusarg = fcb; 2760 pkt.fp_statuscb = fwohci_read_resp; 2761 2762 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2763 psc->sc_tlabel, fwohci_read_resp, fcb); 2764 if (rv) 2765 return rv; 2766 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2767 if (rv) 2768 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2769 psc->sc_tlabel, NULL, NULL); 2770 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2771 fcb->count = 1; 2772 return rv; 2773 } 2774 2775 static int 2776 fwohci_write(struct ieee1394_abuf *ab) 2777 { 2778 struct fwohci_pkt pkt; 2779 struct ieee1394_softc *sc = ab->ab_req; 2780 struct fwohci_softc *psc = 2781 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2782 u_int32_t high, lo; 2783 int rv; 2784 2785 if (ab->ab_length > sc->sc1394_max_receive) { 2786 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2787 return E2BIG; 2788 } 2789 2790 memset(&pkt, 0, sizeof(pkt)); 2791 2792 pkt.fp_tcode = ab->ab_tcode; 2793 pkt.fp_uio.uio_iov = pkt.fp_iov; 2794 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2795 pkt.fp_uio.uio_rw = UIO_WRITE; 2796 2797 pkt.fp_statusarg = ab; 2798 pkt.fp_statuscb = fwohci_write_ack; 2799 2800 switch (ab->ab_tcode) { 2801 case IEEE1394_TCODE_WRITE_RESP: 2802 pkt.fp_hlen = 12; 2803 case IEEE1394_TCODE_READ_RESP_QUAD: 2804 case IEEE1394_TCODE_READ_RESP_BLOCK: 2805 if (!pkt.fp_hlen) 2806 pkt.fp_hlen = 16; 2807 high = ab->ab_retlen; 2808 ab->ab_retlen = 0; 2809 lo = 0; 2810 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2811 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2812 break; 2813 default: 2814 pkt.fp_hlen = 16; 2815 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2816 lo = (ab->ab_csr & 0x00000000ffffffff); 2817 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2818 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2819 break; 2820 } 2821 2822 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2823 pkt.fp_hdr[2] = lo; 2824 if (pkt.fp_hlen == 16) { 2825 if (ab->ab_length == 4) { 2826 pkt.fp_hdr[3] = ab->ab_data[0]; 2827 pkt.fp_dlen = 0; 2828 } else { 2829 pkt.fp_hdr[3] = (ab->ab_length << 16); 2830 pkt.fp_dlen = ab->ab_length; 2831 pkt.fp_uio.uio_iovcnt = 1; 2832 pkt.fp_uio.uio_resid = ab->ab_length; 2833 pkt.fp_iov[0].iov_base = ab->ab_data; 2834 pkt.fp_iov[0].iov_len = ab->ab_length; 2835 } 2836 } 2837 switch (ab->ab_tcode) { 2838 case IEEE1394_TCODE_WRITE_RESP: 2839 case IEEE1394_TCODE_READ_RESP_QUAD: 2840 case IEEE1394_TCODE_READ_RESP_BLOCK: 2841 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2842 break; 2843 default: 2844 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2845 break; 2846 } 2847 return rv; 2848 } 2849 2850 static int 2851 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2852 { 2853 struct fwohci_cb *fcb = arg; 2854 struct ieee1394_abuf *ab = fcb->ab; 2855 struct fwohci_pkt newpkt; 2856 u_int32_t *cur, high, lo; 2857 int i, tcode, rcode, status, rv; 2858 2859 /* 2860 * Both the ACK handling and normal response callbacks are handled here. 2861 * The main reason for this is the various error conditions that can 2862 * occur trying to block read some areas and the ways that gets reported 2863 * back to calling station. This is a variety of ACK codes, responses, 2864 * etc which makes it much more difficult to process if both aren't 2865 * handled here. 2866 */ 2867 2868 /* Check for status packet. */ 2869 2870 if (pkt->fp_tcode == -1) { 2871 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2872 rcode = -1; 2873 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2874 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2875 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2876 DPRINTF(("Got status packet: 0x%02x\n", 2877 (unsigned int)status)); 2878 fcb->count--; 2879 2880 /* 2881 * Got all the ack's back and the buffer is invalid (i.e. the 2882 * callback has been called. Clean up. 2883 */ 2884 2885 if (fcb->abuf_valid == 0) { 2886 if (fcb->count == 0) 2887 free(fcb, M_DEVBUF); 2888 return IEEE1394_RCODE_COMPLETE; 2889 } 2890 } else { 2891 status = -1; 2892 tcode = pkt->fp_tcode; 2893 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2894 } 2895 2896 /* 2897 * Some area's (like the config rom want to be read as quadlets only. 2898 * 2899 * The current ideas to try are: 2900 * 2901 * Got an ACK_TYPE_ERROR on a block read. 2902 * 2903 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2904 * response. 2905 * 2906 * In all cases construct a new packet for a quadlet read and let 2907 * mutli_resp handle the iteration over the space. 2908 */ 2909 2910 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2911 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2912 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2913 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2914 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2915 2916 /* Read the area in quadlet chunks (internally track this). */ 2917 2918 memset(&newpkt, 0, sizeof(newpkt)); 2919 2920 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2921 lo = (ab->ab_csr & 0x00000000ffffffff); 2922 2923 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2924 newpkt.fp_hlen = 12; 2925 newpkt.fp_dlen = 0; 2926 newpkt.fp_hdr[1] = 2927 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2928 newpkt.fp_hdr[2] = lo; 2929 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2930 (newpkt.fp_tcode << 4); 2931 2932 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2933 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2934 fwohci_read_multi_resp, fcb); 2935 if (rv) { 2936 (*ab->ab_cb)(ab, -1); 2937 goto cleanup; 2938 } 2939 newpkt.fp_statusarg = fcb; 2940 newpkt.fp_statuscb = fwohci_read_resp; 2941 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 2942 if (rv) { 2943 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2944 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 2945 NULL); 2946 (*ab->ab_cb)(ab, -1); 2947 goto cleanup; 2948 } 2949 fcb->count++; 2950 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2951 return IEEE1394_RCODE_COMPLETE; 2952 } else if ((rcode != -1) || ((status != -1) && 2953 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2954 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 2955 2956 /* 2957 * Recombine all the iov data into 1 chunk for higher 2958 * level code. 2959 */ 2960 2961 if (rcode != -1) { 2962 cur = ab->ab_data; 2963 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 2964 /* 2965 * Make sure and don't exceed the buffer 2966 * allocated for return. 2967 */ 2968 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 2969 ab->ab_length) { 2970 memcpy(cur, pkt->fp_iov[i].iov_base, 2971 (ab->ab_length - ab->ab_retlen)); 2972 ab->ab_retlen = ab->ab_length; 2973 break; 2974 } 2975 memcpy(cur, pkt->fp_iov[i].iov_base, 2976 pkt->fp_iov[i].iov_len); 2977 cur += pkt->fp_iov[i].iov_len; 2978 ab->ab_retlen += pkt->fp_iov[i].iov_len; 2979 } 2980 } 2981 if (status != -1) 2982 /* XXX: Need a complete tlabel interface. */ 2983 for (i = 0; i < 64; i++) 2984 fwohci_handler_set(sc, 2985 IEEE1394_TCODE_READ_RESP_QUAD, 2986 ab->ab_req->sc1394_node_id, i, NULL, NULL); 2987 (*ab->ab_cb)(ab, rcode); 2988 goto cleanup; 2989 } else 2990 /* Good ack packet. */ 2991 return IEEE1394_RCODE_COMPLETE; 2992 2993 /* Can't get here unless ab->ab_cb has been called. */ 2994 2995 cleanup: 2996 fcb->abuf_valid = 0; 2997 if (fcb->count == 0) 2998 free(fcb, M_DEVBUF); 2999 return IEEE1394_RCODE_COMPLETE; 3000 } 3001 3002 static int 3003 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3004 struct fwohci_pkt *pkt) 3005 { 3006 struct fwohci_cb *fcb = arg; 3007 struct ieee1394_abuf *ab = fcb->ab; 3008 struct fwohci_pkt newpkt; 3009 u_int32_t high, lo; 3010 int rcode, rv; 3011 3012 /* 3013 * Bad return codes from the wire, just return what's already in the 3014 * buf. 3015 */ 3016 3017 /* Make sure a response packet didn't arrive after a bad ACK. */ 3018 if (fcb->abuf_valid == 0) 3019 return IEEE1394_RCODE_COMPLETE; 3020 3021 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3022 3023 if (rcode) { 3024 (*ab->ab_cb)(ab, rcode); 3025 goto cleanup; 3026 } 3027 3028 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3029 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3030 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3031 ab->ab_retlen = ab->ab_length; 3032 } else { 3033 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3034 pkt->fp_iov[0].iov_base, 4); 3035 ab->ab_retlen += 4; 3036 } 3037 /* Still more, loop and read 4 more bytes. */ 3038 if (ab->ab_retlen < ab->ab_length) { 3039 memset(&newpkt, 0, sizeof(newpkt)); 3040 3041 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3042 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3043 3044 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3045 newpkt.fp_hlen = 12; 3046 newpkt.fp_dlen = 0; 3047 newpkt.fp_hdr[1] = 3048 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3049 newpkt.fp_hdr[2] = lo; 3050 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3051 (newpkt.fp_tcode << 4); 3052 3053 newpkt.fp_statusarg = fcb; 3054 newpkt.fp_statuscb = fwohci_read_resp; 3055 3056 /* 3057 * Bad return code. Just give up and return what's 3058 * come in now. 3059 */ 3060 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3061 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3062 fwohci_read_multi_resp, fcb); 3063 if (rv) 3064 (*ab->ab_cb)(ab, -1); 3065 else { 3066 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3067 if (rv) { 3068 fwohci_handler_set(sc, 3069 IEEE1394_TCODE_READ_RESP_QUAD, 3070 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3071 NULL, NULL); 3072 (*ab->ab_cb)(ab, -1); 3073 } else { 3074 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3075 fcb->count++; 3076 return IEEE1394_RCODE_COMPLETE; 3077 } 3078 } 3079 } else 3080 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3081 3082 cleanup: 3083 /* Can't get here unless ab_cb has been called. */ 3084 fcb->abuf_valid = 0; 3085 if (fcb->count == 0) 3086 free(fcb, M_DEVBUF); 3087 return IEEE1394_RCODE_COMPLETE; 3088 } 3089 3090 static int 3091 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3092 { 3093 struct ieee1394_abuf *ab = arg; 3094 u_int16_t status; 3095 3096 3097 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3098 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3099 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3100 DPRINTF(("Got status packet: 0x%02x\n", 3101 (unsigned int)status)); 3102 3103 /* No callback means this level should free the buffers. */ 3104 if (ab->ab_cb) 3105 (*ab->ab_cb)(ab, status); 3106 else { 3107 if (ab->ab_data) 3108 free(ab->ab_data, M_1394DATA); 3109 free(ab, M_1394DATA); 3110 } 3111 return IEEE1394_RCODE_COMPLETE; 3112 } 3113 3114 static int 3115 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3116 { 3117 struct ieee1394_softc *sc = ab->ab_req; 3118 struct fwohci_softc *psc = 3119 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3120 u_int32_t high, lo; 3121 int i, j, rv; 3122 3123 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3124 lo = (ab->ab_csr & 0x00000000ffffffff); 3125 3126 rv = 0; 3127 switch (ab->ab_tcode) { 3128 case IEEE1394_TCODE_READ_REQ_QUAD: 3129 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3130 if (ab->ab_cb) 3131 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3132 fwohci_parse_input, ab); 3133 else 3134 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3135 NULL); 3136 break; 3137 case IEEE1394_TCODE_READ_REQ_BLOCK: 3138 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3139 if (allow) { 3140 for (i = 0; i < (ab->ab_length / 4); i++) { 3141 if (ab->ab_cb) { 3142 rv = fwohci_handler_set(psc, 3143 ab->ab_tcode, high, lo + (i * 4), 3144 fwohci_parse_input, ab); 3145 if (rv) 3146 break; 3147 } else 3148 fwohci_handler_set(psc, ab->ab_tcode, 3149 high, lo + (i * 4), NULL, NULL); 3150 } 3151 if (i != (ab->ab_length / 4)) { 3152 j = i + 1; 3153 for (i = 0; i < j; i++) 3154 fwohci_handler_set(psc, ab->ab_tcode, 3155 high, lo + (i * 4), NULL, NULL); 3156 } else 3157 ab->ab_data = (void *)1; 3158 } else { 3159 if (ab->ab_cb) 3160 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3161 lo, fwohci_parse_input, ab); 3162 else 3163 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3164 NULL, NULL); 3165 } 3166 break; 3167 default: 3168 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3169 return -1; 3170 break; 3171 } 3172 return rv; 3173 } 3174 3175 static int 3176 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3177 { 3178 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3179 u_int64_t csr; 3180 u_int32_t *cur; 3181 int i, count; 3182 3183 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3184 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3185 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3186 3187 switch (ab->ab_tcode) { 3188 case IEEE1394_TCODE_READ_REQ_QUAD: 3189 ab->ab_retlen = 4; 3190 break; 3191 case IEEE1394_TCODE_READ_REQ_BLOCK: 3192 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3193 if (ab->ab_data) { 3194 if ((csr + ab->ab_retlen) > 3195 (ab->ab_csr + ab->ab_length)) 3196 return IEEE1394_RCODE_ADDRESS_ERROR; 3197 ab->ab_data = NULL; 3198 } else 3199 if (ab->ab_retlen != ab->ab_length) 3200 return IEEE1394_RCODE_ADDRESS_ERROR; 3201 break; 3202 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3203 ab->ab_retlen = 4; 3204 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3205 if (!ab->ab_retlen) 3206 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3207 if (ab->ab_data) { 3208 if ((csr + ab->ab_retlen) > 3209 (ab->ab_csr + ab->ab_length)) 3210 return IEEE1394_RCODE_ADDRESS_ERROR; 3211 ab->ab_data = NULL; 3212 } else 3213 if (ab->ab_retlen != ab->ab_length) 3214 return IEEE1394_RCODE_ADDRESS_ERROR; 3215 3216 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3217 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3218 ab->ab_data[0] = pkt->fp_hdr[3]; 3219 else { 3220 count = 0; 3221 cur = ab->ab_data; 3222 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3223 memcpy(cur, pkt->fp_iov[i].iov_base, 3224 pkt->fp_iov[i].iov_len); 3225 cur += pkt->fp_iov[i].iov_len; 3226 count += pkt->fp_iov[i].iov_len; 3227 } 3228 if (ab->ab_retlen != count) 3229 panic("Packet claims %d length " 3230 "but only %d bytes returned\n", 3231 ab->ab_retlen, count); 3232 } 3233 break; 3234 default: 3235 panic("Got a callback for a tcode that wasn't requested: %d\n", 3236 ab->ab_tcode); 3237 break; 3238 } 3239 ab->ab_csr = csr; 3240 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3241 return -1; 3242 } 3243 3244 static int 3245 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3246 { 3247 struct ieee1394_attach_args *fwa = aux; 3248 3249 /* Both halves must be filled in for a match. */ 3250 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3251 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3252 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3253 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3254 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3255 return 0; 3256 } 3257 3258 #ifdef FW_DEBUG 3259 static void 3260 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3261 { 3262 3263 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3264 intmask); 3265 if (intmask & OHCI_Int_CycleTooLong) 3266 printf(" CycleTooLong"); 3267 if (intmask & OHCI_Int_UnrecoverableError) 3268 printf(" UnrecoverableError"); 3269 if (intmask & OHCI_Int_CycleInconsistent) 3270 printf(" CycleInconsistent"); 3271 if (intmask & OHCI_Int_BusReset) 3272 printf(" BusReset"); 3273 if (intmask & OHCI_Int_SelfIDComplete) 3274 printf(" SelfIDComplete"); 3275 if (intmask & OHCI_Int_LockRespErr) 3276 printf(" LockRespErr"); 3277 if (intmask & OHCI_Int_PostedWriteErr) 3278 printf(" PostedWriteErr"); 3279 if (intmask & OHCI_Int_ReqTxComplete) 3280 printf(" ReqTxComplete(0x%04x)", 3281 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3282 OHCI_SUBREG_ContextControlClear)); 3283 if (intmask & OHCI_Int_RespTxComplete) 3284 printf(" RespTxComplete(0x%04x)", 3285 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3286 OHCI_SUBREG_ContextControlClear)); 3287 if (intmask & OHCI_Int_ARRS) 3288 printf(" ARRS(0x%04x)", 3289 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3290 OHCI_SUBREG_ContextControlClear)); 3291 if (intmask & OHCI_Int_ARRQ) 3292 printf(" ARRQ(0x%04x)", 3293 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3294 OHCI_SUBREG_ContextControlClear)); 3295 if (intmask & OHCI_Int_IsochRx) 3296 printf(" IsochRx(0x%08x)", 3297 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3298 if (intmask & OHCI_Int_IsochTx) 3299 printf(" IsochTx(0x%08x)", 3300 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3301 if (intmask & OHCI_Int_RQPkt) 3302 printf(" RQPkt(0x%04x)", 3303 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3304 OHCI_SUBREG_ContextControlClear)); 3305 if (intmask & OHCI_Int_RSPkt) 3306 printf(" RSPkt(0x%04x)", 3307 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3308 OHCI_SUBREG_ContextControlClear)); 3309 printf("\n"); 3310 } 3311 3312 static void 3313 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3314 { 3315 u_int8_t key, phyid; 3316 3317 key = (val & 0xc0000000) >> 30; 3318 phyid = (val & 0x3f000000) >> 24; 3319 printf("%s: PHY packet from %d: ", 3320 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3321 switch (key) { 3322 case 0: 3323 printf("PHY Config:"); 3324 if (val & 0x00800000) 3325 printf(" ForceRoot"); 3326 if (val & 0x00400000) 3327 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3328 printf("\n"); 3329 break; 3330 case 1: 3331 printf("Link-on\n"); 3332 break; 3333 case 2: 3334 printf("SelfID:"); 3335 if (val & 0x00800000) { 3336 printf(" #%d", (val & 0x00700000) >> 20); 3337 } else { 3338 if (val & 0x00400000) 3339 printf(" LinkActive"); 3340 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3341 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3342 if (val & 0x00000800) 3343 printf(" Cont"); 3344 if (val & 0x00000002) 3345 printf(" InitiateBusReset"); 3346 } 3347 if (val & 0x00000001) 3348 printf(" +"); 3349 printf("\n"); 3350 break; 3351 default: 3352 printf("unknown: 0x%08x\n", val); 3353 break; 3354 } 3355 } 3356 #endif /* FW_DEBUG */ 3357
Indexes created Sun Sep 28 07:09:56 GMT 2025