fwohci.c revision 1.35
1 /* $NetBSD: fwohci.c,v 1.35 2001/06/28 14:41:28 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init(struct fwohci_softc *); 100 static void fwohci_buf_start(struct fwohci_softc *); 101 static void fwohci_buf_stop(struct fwohci_softc *); 102 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 103 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 104 caddr_t *, int); 105 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 106 struct fwohci_pkt *); 107 108 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 109 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 110 static void fwohci_phy_busreset(struct fwohci_softc *); 111 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 112 113 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 114 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 115 116 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 117 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 118 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 119 120 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 121 struct fwohci_pkt *); 122 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 123 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 124 struct fwohci_pkt *); 125 126 static int fwohci_guidrom_init(struct fwohci_softc *); 127 static void fwohci_configrom_init(struct fwohci_softc *); 128 static int fwohci_configrom_input(struct fwohci_softc *, void *, 129 struct fwohci_pkt *); 130 static void fwohci_selfid_init(struct fwohci_softc *); 131 static int fwohci_selfid_input(struct fwohci_softc *); 132 133 static void fwohci_csr_init(struct fwohci_softc *); 134 static int fwohci_csr_input(struct fwohci_softc *, void *, 135 struct fwohci_pkt *); 136 137 static void fwohci_uid_collect(struct fwohci_softc *); 138 static int fwohci_uid_input(struct fwohci_softc *, void *, 139 struct fwohci_pkt *); 140 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 141 static void fwohci_check_nodes(struct fwohci_softc *); 142 143 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 144 void (*)(struct device *, struct mbuf *)); 145 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 146 static int fwohci_if_output(struct device *, struct mbuf *, 147 void (*)(struct device *, struct mbuf *)); 148 static int fwohci_read(struct ieee1394_abuf *); 149 static int fwohci_write(struct ieee1394_abuf *); 150 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 151 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 152 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_inreg(struct ieee1394_abuf *, int); 155 static int fwohci_parse_input(struct fwohci_softc *, void *, 156 struct fwohci_pkt *); 157 static int fwohci_submatch(struct device *, struct cfdata *, void *); 158 159 #ifdef FW_DEBUG 160 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 161 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 162 163 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 164 165 #define DPRINTF(x) if (fwdebug) printf x 166 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 167 int fwdebug = 0; 168 #else 169 #define DPRINTF(x) 170 #define DPRINTFN(n,x) 171 #endif 172 173 int 174 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 175 { 176 int i; 177 u_int32_t val; 178 #if 0 179 int error; 180 #endif 181 182 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 183 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 184 185 /* 186 * Wait for reset completion 187 */ 188 for (i = 0; i < OHCI_LOOP; i++) { 189 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 190 if ((val & OHCI_HCControl_SoftReset) == 0) 191 break; 192 } 193 194 /* What dialect of OHCI is this device? 195 */ 196 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 197 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 198 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 199 200 LIST_INIT(&sc->sc_nodelist); 201 202 if (fwohci_guidrom_init(sc) != 0) { 203 printf("\n%s: fatal: no global UID ROM\n", 204 sc->sc_sc1394.sc1394_dev.dv_xname); 205 return -1; 206 } 207 208 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 209 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 210 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 211 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 212 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 213 214 /* Get the maximum link speed and receive size 215 */ 216 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 217 sc->sc_sc1394.sc1394_link_speed = 218 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 219 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 220 printf(", %s", 221 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 222 } else { 223 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 224 } 225 226 /* MaxRec is encoded as log2(max_rec_octets)-1 227 */ 228 sc->sc_sc1394.sc1394_max_receive = 229 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 230 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 231 232 /* 233 * Count how many isochronous ctx we have. 234 */ 235 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 236 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 237 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 238 for (i = 0; val != 0; val >>= 1) { 239 if (val & 0x1) 240 i++; 241 } 242 sc->sc_isoctx = i; 243 printf(", %d iso_ctx", sc->sc_isoctx); 244 245 printf("\n"); 246 247 #if 0 248 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 249 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 250 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 251 return error; 252 #endif 253 254 sc->sc_dying = 0; 255 256 kthread_create(fwohci_create_event_thread, sc); 257 return 0; 258 } 259 260 int 261 fwohci_intr(void *arg) 262 { 263 struct fwohci_softc * const sc = arg; 264 int progress = 0; 265 u_int32_t intmask, iso; 266 267 for (;;) { 268 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 269 270 /* 271 * On a bus reset, everything except bus reset gets 272 * cleared. That can't get cleared until the selfid 273 * phase completes (which happens outside the 274 * interrupt routines). So if just a bus reset is left 275 * in the mask and it's already in the sc_intmask, 276 * just return. 277 */ 278 279 if ((intmask == 0) || 280 (progress && (intmask == OHCI_Int_BusReset) && 281 (sc->sc_intmask & OHCI_Int_BusReset))) { 282 if (progress) 283 wakeup(fwohci_event_thread); 284 return progress; 285 } 286 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 287 intmask & ~OHCI_Int_BusReset); 288 #ifdef FW_DEBUG 289 if (fwdebug > 1) 290 fwohci_show_intr(sc, intmask); 291 #endif 292 293 if (intmask & OHCI_Int_BusReset) { 294 /* 295 * According to OHCI spec 6.1.1 "busReset", 296 * All asynchronous transmit must be stopped before 297 * clearing BusReset. Moreover, the BusReset 298 * interrupt bit should not be cleared during the 299 * SelfID phase. Thus we turned off interrupt mask 300 * bit of BusReset instead until SelfID completion 301 * or SelfID timeout. 302 */ 303 intmask &= OHCI_Int_SelfIDComplete; 304 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 305 OHCI_Int_BusReset); 306 sc->sc_intmask = OHCI_Int_BusReset; 307 } 308 sc->sc_intmask |= intmask; 309 310 if (intmask & OHCI_Int_IsochTx) { 311 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 312 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 313 } 314 if (intmask & OHCI_Int_IsochRx) { 315 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 316 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 317 sc->sc_iso |= iso; 318 } 319 320 if (!progress) { 321 sc->sc_intrcnt.ev_count++; 322 progress = 1; 323 } 324 } 325 } 326 327 static void 328 fwohci_create_event_thread(void *arg) 329 { 330 struct fwohci_softc *sc = arg; 331 332 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 333 sc->sc_sc1394.sc1394_dev.dv_xname)) { 334 printf("%s: unable to create event thread\n", 335 sc->sc_sc1394.sc1394_dev.dv_xname); 336 panic("fwohci_create_event_thread"); 337 } 338 } 339 340 static void 341 fwohci_thread_init(void *arg) 342 { 343 struct fwohci_softc *sc = arg; 344 int i; 345 346 /* 347 * Allocate descriptors 348 */ 349 if (fwohci_desc_alloc(sc)) { 350 printf("%s: not enabling interrupts\n", 351 sc->sc_sc1394.sc1394_dev.dv_xname); 352 kthread_exit(1); 353 } 354 355 /* 356 * Enable Link Power 357 */ 358 359 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 360 361 /* 362 * Allocate DMA Context 363 */ 364 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 365 OHCI_CTX_ASYNC_RX_REQUEST); 366 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 367 OHCI_CTX_ASYNC_RX_RESPONSE); 368 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 369 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 370 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 371 M_DEVBUF, M_WAITOK); 372 for (i = 0; i < sc->sc_isoctx; i++) 373 sc->sc_ctx_ir[i] = NULL; 374 375 /* 376 * Allocate buffer for configuration ROM and SelfID buffer 377 */ 378 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 379 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 380 381 callout_init(&sc->sc_selfid_callout); 382 383 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 384 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 385 386 /* 387 * establish hooks for shutdown and suspend/resume 388 */ 389 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 390 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 391 392 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 393 fwohci_print); 394 395 /* Main loop. It's not coming back normally. */ 396 397 fwohci_event_thread(sc); 398 399 kthread_exit(0); 400 } 401 402 static void 403 fwohci_event_thread(struct fwohci_softc *sc) 404 { 405 int i, s; 406 u_int32_t intmask, iso; 407 408 s = splbio(); 409 410 /* 411 * Initialize hardware registers. 412 */ 413 414 fwohci_hw_init(sc); 415 416 /* Initial Bus Reset */ 417 fwohci_phy_busreset(sc); 418 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 419 splx(s); 420 421 while (!sc->sc_dying) { 422 s = splbio(); 423 intmask = sc->sc_intmask; 424 if (intmask == 0) { 425 tsleep(fwohci_event_thread, PZERO, "fwohci_event", 0); 426 splx(s); 427 continue; 428 } 429 sc->sc_intmask = 0; 430 splx(s); 431 432 if (intmask & OHCI_Int_BusReset) { 433 fwohci_buf_stop(sc); 434 fwohci_buf_init(sc); 435 if (sc->sc_uidtbl != NULL) { 436 free(sc->sc_uidtbl, M_DEVBUF); 437 sc->sc_uidtbl = NULL; 438 } 439 440 callout_reset(&sc->sc_selfid_callout, 441 OHCI_SELFID_TIMEOUT, 442 (void (*)(void *))fwohci_phy_busreset, sc); 443 sc->sc_nodeid = 0xffff; /* indicate invalid */ 444 sc->sc_rootid = 0; 445 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 446 } 447 if (intmask & OHCI_Int_SelfIDComplete) { 448 s = splbio(); 449 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 450 OHCI_Int_BusReset); 451 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 452 OHCI_Int_BusReset); 453 splx(s); 454 callout_stop(&sc->sc_selfid_callout); 455 if (fwohci_selfid_input(sc) == 0) { 456 fwohci_buf_start(sc); 457 fwohci_uid_collect(sc); 458 } 459 } 460 if (intmask & OHCI_Int_ReqTxComplete) 461 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 462 if (intmask & OHCI_Int_RespTxComplete) 463 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 464 if (intmask & OHCI_Int_RQPkt) 465 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 466 if (intmask & OHCI_Int_RSPkt) 467 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 468 if (intmask & OHCI_Int_IsochRx) { 469 s = splbio(); 470 iso = sc->sc_iso; 471 sc->sc_iso = 0; 472 splx(s); 473 for (i = 0; i < sc->sc_isoctx; i++) { 474 if ((iso & (1 << i)) && 475 sc->sc_ctx_ir[i] != NULL) 476 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 477 } 478 } 479 } 480 } 481 482 #if 0 483 static int 484 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 485 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 486 { 487 bus_dma_segment_t segs[1]; 488 int error, nsegs, steps; 489 490 steps = 0; 491 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 492 segs, 1, &nsegs, flags); 493 if (error) 494 goto cleanup; 495 496 steps = 1; 497 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 498 kvap, flags); 499 if (error) 500 goto cleanup; 501 502 if (error == 0) 503 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 504 size, flags, mapp); 505 if (error) 506 goto cleanup; 507 if (error == 0) 508 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 509 flags); 510 if (error) 511 goto cleanup; 512 513 cleanup: 514 switch (steps) { 515 case 1: 516 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 517 } 518 519 return error; 520 } 521 #endif 522 523 int 524 fwohci_print(void *aux, const char *pnp) 525 { 526 char *name = aux; 527 528 if (pnp) 529 printf("%s at %s", name, pnp); 530 531 return QUIET; 532 } 533 534 static void 535 fwohci_hw_init(struct fwohci_softc *sc) 536 { 537 int i; 538 u_int32_t val; 539 540 /* 541 * Software Reset. 542 */ 543 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 544 for (i = 0; i < OHCI_LOOP; i++) { 545 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 546 if ((val & OHCI_HCControl_SoftReset) == 0) 547 break; 548 } 549 550 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 551 552 /* 553 * First, initilize CSRs with undefined value to default settings. 554 */ 555 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 556 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 557 #if 0 558 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 559 #else 560 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 561 #endif 562 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 563 for (i = 0; i < sc->sc_isoctx; i++) { 564 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 565 ~0); 566 } 567 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 568 569 fwohci_configrom_init(sc); 570 fwohci_selfid_init(sc); 571 fwohci_buf_init(sc); 572 fwohci_csr_init(sc); 573 574 /* 575 * Final CSR settings. 576 */ 577 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 578 OHCI_LinkControl_CycleTimerEnable | 579 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 580 581 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 582 583 /* clear receive filter */ 584 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 585 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 586 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 587 588 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 589 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 590 #if BYTE_ORDER == BIG_ENDIAN 591 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 592 OHCI_HCControl_NoByteSwapData); 593 #endif 594 595 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 596 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 597 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 598 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 599 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 600 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 601 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 602 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 603 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 604 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 605 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 606 607 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 608 609 /* 610 * Start the receivers 611 */ 612 fwohci_buf_start(sc); 613 } 614 615 static void 616 fwohci_power(int why, void *arg) 617 { 618 struct fwohci_softc *sc = arg; 619 int s; 620 621 s = splbio(); 622 switch (why) { 623 case PWR_SUSPEND: 624 case PWR_STANDBY: 625 fwohci_shutdown(sc); 626 break; 627 case PWR_RESUME: 628 fwohci_hw_init(sc); 629 fwohci_phy_busreset(sc); 630 break; 631 case PWR_SOFTSUSPEND: 632 case PWR_SOFTSTANDBY: 633 case PWR_SOFTRESUME: 634 break; 635 } 636 splx(s); 637 } 638 639 static void 640 fwohci_shutdown(void *arg) 641 { 642 struct fwohci_softc *sc = arg; 643 u_int32_t val; 644 645 callout_stop(&sc->sc_selfid_callout); 646 /* disable all interrupt */ 647 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 648 fwohci_buf_stop(sc); 649 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 650 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 651 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 652 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 653 fwohci_phy_busreset(sc); 654 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 655 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 656 } 657 658 /* 659 * COMMON FUNCTIONS 660 */ 661 662 /* 663 * read the PHY Register. 664 */ 665 static u_int8_t 666 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 667 { 668 int i; 669 u_int32_t val; 670 671 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 672 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 673 for (i = 0; i < OHCI_LOOP; i++) { 674 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 675 OHCI_PhyControl_RdDone) 676 break; 677 } 678 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 679 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 680 } 681 682 /* 683 * write the PHY Register. 684 */ 685 static void 686 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 687 { 688 int i; 689 690 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 691 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 692 (val << OHCI_PhyControl_WrData_BITPOS)); 693 for (i = 0; i < OHCI_LOOP; i++) { 694 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 695 OHCI_PhyControl_WrReg)) 696 break; 697 } 698 } 699 700 /* 701 * Initiate Bus Reset 702 */ 703 static void 704 fwohci_phy_busreset(struct fwohci_softc *sc) 705 { 706 int s; 707 u_int8_t val; 708 709 s = splbio(); 710 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 711 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 712 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 713 callout_stop(&sc->sc_selfid_callout); 714 val = fwohci_phy_read(sc, 1); 715 val = (val & 0x80) | /* preserve RHB (force root) */ 716 0x40 | /* Initiate Bus Reset */ 717 0x3f; /* default GAP count */ 718 fwohci_phy_write(sc, 1, val); 719 splx(s); 720 } 721 722 /* 723 * PHY Packet 724 */ 725 static void 726 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 727 { 728 u_int32_t val; 729 730 val = pkt->fp_hdr[1]; 731 if (val != ~pkt->fp_hdr[2]) { 732 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 733 OHCI_CTXCTL_EVENT_BUS_RESET) { 734 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 735 pkt->fp_hdr[2])); 736 } else { 737 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 738 sc->sc_sc1394.sc1394_dev.dv_xname, val, 739 pkt->fp_hdr[2]); 740 } 741 return; 742 } 743 #ifdef FW_DEBUG 744 if (fwdebug > 1) 745 fwohci_show_phypkt(sc, val); 746 #endif 747 } 748 749 /* 750 * Descriptor for context DMA. 751 */ 752 static int 753 fwohci_desc_alloc(struct fwohci_softc *sc) 754 { 755 int error, mapsize, dsize; 756 757 /* 758 * allocate descriptor buffer 759 */ 760 761 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 762 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 763 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 764 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 765 mapsize = howmany(sc->sc_descsize, NBBY); 766 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 767 memset(sc->sc_descmap, 0, mapsize); 768 769 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 770 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 771 printf("%s: unable to allocate descriptor buffer, error = %d\n", 772 sc->sc_sc1394.sc1394_dev.dv_xname, error); 773 goto fail_0; 774 } 775 776 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 777 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 778 != 0) { 779 printf("%s: unable to map descriptor buffer, error = %d\n", 780 sc->sc_sc1394.sc1394_dev.dv_xname, error); 781 goto fail_1; 782 } 783 784 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 785 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 786 printf("%s: unable to create descriptor buffer DMA map, " 787 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 788 goto fail_2; 789 } 790 791 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 792 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 793 printf("%s: unable to load descriptor buffer DMA map, " 794 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 795 goto fail_3; 796 } 797 798 return 0; 799 800 fail_3: 801 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 802 fail_2: 803 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 804 fail_1: 805 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 806 fail_0: 807 return error; 808 } 809 810 static struct fwohci_desc * 811 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 812 { 813 int i, n; 814 815 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 816 for (i = 0; ; i++) { 817 if (i == ndesc) { 818 for (i = 0; i < ndesc; i++) 819 setbit(sc->sc_descmap, n + i); 820 return sc->sc_desc + n; 821 } 822 if (isset(sc->sc_descmap, n + i)) 823 break; 824 } 825 } 826 return NULL; 827 } 828 829 static void 830 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 831 { 832 int i, n; 833 834 n = fd - sc->sc_desc; 835 for (i = 0; i < ndesc; i++, n++) { 836 #ifdef DIAGNOSTIC 837 if (isclr(sc->sc_descmap, n)) 838 panic("fwohci_desc_put: duplicated free"); 839 #endif 840 clrbit(sc->sc_descmap, n); 841 } 842 } 843 844 /* 845 * Asyncronous/Isochronous Transmit/Receive Context 846 */ 847 static int 848 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 849 int bufcnt, int ctx) 850 { 851 int i, error; 852 struct fwohci_ctx *fc; 853 struct fwohci_buf *fb; 854 struct fwohci_desc *fd; 855 856 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 857 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 858 LIST_INIT(&fc->fc_handler); 859 TAILQ_INIT(&fc->fc_buf); 860 fc->fc_ctx = ctx; 861 fc->fc_bufcnt = bufcnt; 862 fb = (struct fwohci_buf *)&fc[1]; 863 for (i = 0; i < bufcnt; i++, fb++) { 864 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 865 goto fail; 866 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 867 error = ENOBUFS; 868 goto fail; 869 } 870 fb->fb_desc = fd; 871 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 872 ((caddr_t)fd - (caddr_t)sc->sc_desc); 873 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 874 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 875 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 876 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 877 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 878 } 879 *fcp = fc; 880 return 0; 881 882 fail: 883 while (i-- > 0) 884 fwohci_buf_free(sc, --fb); 885 free(fc, M_DEVBUF); 886 return error; 887 } 888 889 static void 890 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 891 { 892 struct fwohci_buf *fb; 893 struct fwohci_handler *fh; 894 895 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 896 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 897 NULL, NULL); 898 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 899 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 900 fwohci_buf_free(sc, fb); 901 } 902 free(fc, M_DEVBUF); 903 } 904 905 static void 906 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 907 { 908 struct fwohci_buf *fb, *nfb; 909 struct fwohci_desc *fd; 910 struct fwohci_handler *fh; 911 int n; 912 913 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 914 nfb = TAILQ_NEXT(fb, fb_list); 915 fb->fb_off = 0; 916 fd = fb->fb_desc; 917 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 918 fd->fd_rescount = fd->fd_reqcount; 919 } 920 921 n = fc->fc_ctx; 922 fb = TAILQ_FIRST(&fc->fc_buf); 923 if (fc->fc_isoch) { 924 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 925 fb->fb_daddr | 1); 926 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 927 OHCI_CTXCTL_RX_BUFFER_FILL | 928 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 929 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 930 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 931 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 932 OHCI_CTXCTL_RX_ISOCH_HEADER); 933 fh = LIST_FIRST(&fc->fc_handler); 934 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 935 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 936 } else { 937 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 938 fb->fb_daddr | 1); 939 } 940 } 941 942 /* 943 * DMA data buffer 944 */ 945 static int 946 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 947 { 948 int error; 949 950 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 951 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 952 printf("%s: unable to allocate buffer, error = %d\n", 953 sc->sc_sc1394.sc1394_dev.dv_xname, error); 954 goto fail_0; 955 } 956 957 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 958 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 959 printf("%s: unable to map buffer, error = %d\n", 960 sc->sc_sc1394.sc1394_dev.dv_xname, error); 961 goto fail_1; 962 } 963 964 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 965 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 966 printf("%s: unable to create buffer DMA map, " 967 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 968 error); 969 goto fail_2; 970 } 971 972 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 973 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 974 printf("%s: unable to load buffer DMA map, " 975 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 976 error); 977 goto fail_3; 978 } 979 980 return 0; 981 982 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 983 fail_3: 984 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 985 fail_2: 986 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 987 fail_1: 988 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 989 fail_0: 990 return error; 991 } 992 993 static void 994 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 995 { 996 997 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 998 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 999 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1000 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1001 } 1002 1003 static void 1004 fwohci_buf_init(struct fwohci_softc *sc) 1005 { 1006 int i; 1007 1008 /* 1009 * Initialize for Asynchronous Transmit Queue. 1010 */ 1011 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1012 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1013 1014 /* 1015 * Initialize for Asynchronous Receive Queue. 1016 */ 1017 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1018 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1019 1020 /* 1021 * Initialize for Isochronous Receive Queue. 1022 */ 1023 for (i = 0; i < sc->sc_isoctx; i++) { 1024 if (sc->sc_ctx_ir[i] != NULL) 1025 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1026 } 1027 } 1028 1029 static void 1030 fwohci_buf_start(struct fwohci_softc *sc) 1031 { 1032 int i; 1033 1034 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1035 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1036 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1037 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1038 for (i = 0; i < sc->sc_isoctx; i++) { 1039 if (sc->sc_ctx_ir[i] != NULL && 1040 LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 1041 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1042 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1043 } 1044 } 1045 } 1046 1047 static void 1048 fwohci_buf_stop(struct fwohci_softc *sc) 1049 { 1050 int i, j; 1051 1052 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1053 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1054 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1055 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1056 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1057 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1058 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1059 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1060 for (i = 0; i < sc->sc_isoctx; i++) { 1061 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1062 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1063 } 1064 1065 /* 1066 * Make sure the transmitter is stopped. 1067 */ 1068 for (j = 0; j < OHCI_LOOP; j++) { 1069 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1070 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1071 continue; 1072 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1073 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1074 continue; 1075 break; 1076 } 1077 } 1078 1079 static void 1080 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1081 { 1082 struct fwohci_buf *fb, *tfb; 1083 1084 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1085 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1086 fb->fb_desc->fd_rescount != 0) 1087 break; 1088 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1089 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1090 fb->fb_off = 0; 1091 fb->fb_desc->fd_branch = 0; 1092 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1093 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1094 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1095 } 1096 } 1097 1098 static int 1099 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1100 int len) 1101 { 1102 struct fwohci_buf *fb; 1103 struct fwohci_desc *fd; 1104 int bufend; 1105 1106 fb = TAILQ_FIRST(&fc->fc_buf); 1107 again: 1108 fd = fb->fb_desc; 1109 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1110 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1111 fd->fd_reqcount, fd->fd_rescount, len, 1112 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1113 bufend = fd->fd_reqcount - fd->fd_rescount; 1114 if (fb->fb_off >= bufend) { 1115 if (fc->fc_isoch && fb->fb_off > 0) { 1116 fb->fb_off = fd->fd_reqcount; 1117 fd->fd_rescount = 0; 1118 } 1119 if (fd->fd_rescount == 0) { 1120 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1121 goto again; 1122 } 1123 return 0; 1124 } 1125 if (fb->fb_off + len > bufend) 1126 len = bufend - fb->fb_off; 1127 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1128 BUS_DMASYNC_POSTREAD); 1129 *pp = fb->fb_buf + fb->fb_off; 1130 fb->fb_off += roundup(len, 4); 1131 return len; 1132 } 1133 1134 static int 1135 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1136 struct fwohci_pkt *pkt) 1137 { 1138 caddr_t p; 1139 int len, count, i; 1140 1141 memset(pkt, 0, sizeof(*pkt)); 1142 pkt->fp_uio.uio_iov = pkt->fp_iov; 1143 pkt->fp_uio.uio_rw = UIO_WRITE; 1144 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1145 1146 /* get first quadlet */ 1147 count = 4; 1148 if (fc->fc_isoch) { 1149 /* 1150 * get trailer first, may be bogus data unless status update 1151 * in descriptor is set. 1152 */ 1153 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1154 sizeof(*pkt->fp_trail)); 1155 if (len <= 0) { 1156 DPRINTFN(1, ("fwohci_buf_input: no input for is#%d\n", 1157 fc->fc_ctx)); 1158 return 0; 1159 } 1160 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | 1161 (TAILQ_FIRST(&fc->fc_buf)->fb_desc->fd_status << 16); 1162 } 1163 len = fwohci_buf_pktget(sc, fc, &p, count); 1164 if (len <= 0) { 1165 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1166 fc->fc_ctx)); 1167 return 0; 1168 } 1169 pkt->fp_hdr[0] = *(u_int32_t *)p; 1170 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1171 switch (pkt->fp_tcode) { 1172 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1173 case IEEE1394_TCODE_READ_RESP_QUAD: 1174 pkt->fp_hlen = 12; 1175 pkt->fp_dlen = 4; 1176 break; 1177 case IEEE1394_TCODE_READ_REQ_BLOCK: 1178 pkt->fp_hlen = 16; 1179 pkt->fp_dlen = 0; 1180 break; 1181 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1182 case IEEE1394_TCODE_READ_RESP_BLOCK: 1183 case IEEE1394_TCODE_LOCK_REQ: 1184 case IEEE1394_TCODE_LOCK_RESP: 1185 pkt->fp_hlen = 16; 1186 break; 1187 case IEEE1394_TCODE_STREAM_DATA: 1188 pkt->fp_hlen = 4; 1189 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1190 break; 1191 default: 1192 pkt->fp_hlen = 12; 1193 pkt->fp_dlen = 0; 1194 break; 1195 } 1196 1197 /* get header */ 1198 while (count < pkt->fp_hlen) { 1199 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1200 if (len == 0) { 1201 printf("fwohci_buf_input: malformed input 1: %d\n", 1202 pkt->fp_hlen - count); 1203 return 0; 1204 } 1205 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1206 count += len; 1207 } 1208 if ((pkt->fp_hlen == 16) && 1209 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1210 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1211 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1212 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1213 1214 /* get data */ 1215 count = 0; 1216 i = 0; 1217 while (count < pkt->fp_dlen) { 1218 len = fwohci_buf_pktget(sc, fc, 1219 (caddr_t *)&pkt->fp_iov[i].iov_base, 1220 pkt->fp_dlen - count); 1221 if (len == 0) { 1222 printf("fwohci_buf_input: malformed input 2: %d\n", 1223 pkt->fp_hlen - count); 1224 return 0; 1225 } 1226 pkt->fp_iov[i++].iov_len = len; 1227 count += len; 1228 } 1229 pkt->fp_uio.uio_iovcnt = i; 1230 pkt->fp_uio.uio_resid = count; 1231 1232 if (!fc->fc_isoch) { 1233 /* get trailer */ 1234 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1235 sizeof(*pkt->fp_trail)); 1236 if (len <= 0) { 1237 printf("fwohci_buf_input: malformed input 3: %d\n", 1238 pkt->fp_hlen - count); 1239 return 0; 1240 } 1241 } 1242 return 1; 1243 } 1244 1245 static int 1246 fwohci_handler_set(struct fwohci_softc *sc, 1247 int tcode, u_int32_t key1, u_int32_t key2, 1248 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1249 void *arg) 1250 { 1251 struct fwohci_ctx *fc; 1252 struct fwohci_handler *fh; 1253 int i, j; 1254 1255 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1256 j = sc->sc_isoctx; 1257 fh = NULL; 1258 for (i = 0; i < sc->sc_isoctx; i++) { 1259 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1260 if (j == sc->sc_isoctx) 1261 j = i; 1262 continue; 1263 } 1264 fh = LIST_FIRST(&fc->fc_handler); 1265 if (fh == NULL) { 1266 j = i; 1267 break; 1268 } 1269 if (fh->fh_tcode == tcode && 1270 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1271 break; 1272 fh = NULL; 1273 } 1274 if (fh == NULL) { 1275 if (handler == NULL) 1276 return 0; 1277 if (j == sc->sc_isoctx) { 1278 DPRINTF(("fwohci_handler_set: no more free " 1279 "context\n")); 1280 return ENOMEM; 1281 } 1282 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1283 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1284 fc->fc_isoch = 1; 1285 sc->sc_ctx_ir[j] = fc; 1286 } 1287 } 1288 } else { 1289 switch (tcode) { 1290 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1291 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1292 case IEEE1394_TCODE_READ_REQ_QUAD: 1293 case IEEE1394_TCODE_READ_REQ_BLOCK: 1294 case IEEE1394_TCODE_LOCK_REQ: 1295 fc = sc->sc_ctx_arrq; 1296 break; 1297 case IEEE1394_TCODE_WRITE_RESP: 1298 case IEEE1394_TCODE_READ_RESP_QUAD: 1299 case IEEE1394_TCODE_READ_RESP_BLOCK: 1300 case IEEE1394_TCODE_LOCK_RESP: 1301 fc = sc->sc_ctx_arrs; 1302 break; 1303 default: 1304 return EIO; 1305 } 1306 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1307 fh = LIST_NEXT(fh, fh_list)) { 1308 if (fh->fh_tcode == tcode && 1309 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1310 break; 1311 } 1312 } 1313 if (handler == NULL) { 1314 if (fh != NULL) { 1315 LIST_REMOVE(fh, fh_list); 1316 free(fh, M_DEVBUF); 1317 } 1318 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1319 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1320 fwohci_ctx_free(sc, fc); 1321 } 1322 return 0; 1323 } 1324 if (fh == NULL) { 1325 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1326 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1327 } 1328 fh->fh_tcode = tcode; 1329 fh->fh_key1 = key1; 1330 fh->fh_key2 = key2; 1331 fh->fh_handler = handler; 1332 fh->fh_handarg = arg; 1333 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1334 fc->fc_ctx, tcode, key1, key2)); 1335 1336 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1337 fwohci_ctx_init(sc, fc); 1338 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1339 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1340 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1341 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1342 } 1343 return 0; 1344 } 1345 1346 /* 1347 * Asyncronous Receive Requests input frontend. 1348 */ 1349 static void 1350 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1351 { 1352 int rcode; 1353 u_int32_t key1, key2; 1354 struct fwohci_handler *fh; 1355 struct fwohci_pkt pkt, res; 1356 1357 while (fwohci_buf_input(sc, fc, &pkt)) { 1358 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1359 fwohci_phy_input(sc, &pkt); 1360 return; 1361 } 1362 key1 = pkt.fp_hdr[1] & 0xffff; 1363 key2 = pkt.fp_hdr[2]; 1364 memset(&res, 0, sizeof(res)); 1365 res.fp_uio.uio_rw = UIO_WRITE; 1366 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1367 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1368 fh = LIST_NEXT(fh, fh_list)) { 1369 if (pkt.fp_tcode == fh->fh_tcode && 1370 key1 == fh->fh_key1 && 1371 key2 == fh->fh_key2) { 1372 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1373 &pkt); 1374 break; 1375 } 1376 } 1377 if (fh == NULL) { 1378 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1379 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1380 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1381 key2)); 1382 } 1383 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1384 OHCI_CTXCTL_EVENT_ACK_PENDING) 1385 return; 1386 if (rcode != -1) 1387 fwohci_atrs_output(sc, rcode, &pkt, &res); 1388 } 1389 fwohci_buf_next(sc, fc); 1390 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1391 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1392 } 1393 1394 1395 /* 1396 * Asynchronous Receive Response input frontend. 1397 */ 1398 static void 1399 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1400 { 1401 struct fwohci_pkt pkt; 1402 struct fwohci_handler *fh; 1403 u_int16_t srcid; 1404 int rcode, tlabel; 1405 1406 while (fwohci_buf_input(sc, fc, &pkt)) { 1407 srcid = pkt.fp_hdr[1] >> 16; 1408 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1409 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1410 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1411 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1412 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1413 pkt.fp_dlen)); 1414 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1415 fh = LIST_NEXT(fh, fh_list)) { 1416 if (pkt.fp_tcode == fh->fh_tcode && 1417 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1418 tlabel == fh->fh_key2) { 1419 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1420 LIST_REMOVE(fh, fh_list); 1421 free(fh, M_DEVBUF); 1422 break; 1423 } 1424 } 1425 if (fh == NULL) 1426 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1427 } 1428 fwohci_buf_next(sc, fc); 1429 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1430 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1431 } 1432 1433 /* 1434 * Isochronous Receive input frontend. 1435 */ 1436 static void 1437 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1438 { 1439 int rcode, chan, tag; 1440 struct iovec *iov; 1441 struct fwohci_handler *fh; 1442 struct fwohci_pkt pkt; 1443 1444 while (fwohci_buf_input(sc, fc, &pkt)) { 1445 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1446 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1447 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1448 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1449 pkt.fp_dlen)); 1450 if (tag == IEEE1394_TAG_GASP) { 1451 /* 1452 * The pkt with tag=3 is GASP format. 1453 * Move GASP header to header part. 1454 */ 1455 if (pkt.fp_dlen < 8) 1456 continue; 1457 iov = pkt.fp_iov; 1458 /* assuming pkt per buffer mode */ 1459 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1460 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1461 iov->iov_base = (caddr_t)iov->iov_base + 8; 1462 iov->iov_len -= 8; 1463 pkt.fp_hlen += 8; 1464 pkt.fp_dlen -= 8; 1465 } 1466 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1467 fh = LIST_NEXT(fh, fh_list)) { 1468 if (pkt.fp_tcode == fh->fh_tcode && 1469 chan == fh->fh_key1 && tag == fh->fh_key2) { 1470 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1471 &pkt); 1472 break; 1473 } 1474 } 1475 #ifdef FW_DEBUG 1476 if (fh == NULL) { 1477 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1478 } else { 1479 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1480 } 1481 #endif 1482 } 1483 fwohci_buf_next(sc, fc); 1484 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1485 OHCI_CTXCTL_WAKE); 1486 } 1487 1488 /* 1489 * Asynchronous Transmit common routine. 1490 */ 1491 static int 1492 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1493 struct fwohci_pkt *pkt) 1494 { 1495 struct fwohci_buf *fb; 1496 struct fwohci_desc *fd; 1497 struct mbuf *m, *m0; 1498 int i, ndesc, error, off, len; 1499 u_int32_t val; 1500 #ifdef FW_DEBUG 1501 struct iovec *iov; 1502 #endif 1503 1504 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1505 /* We can't send anything during selfid duration */ 1506 return EAGAIN; 1507 1508 #ifdef FW_DEBUG 1509 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1510 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1511 for (i = 0; i < pkt->fp_hlen/4; i++) 1512 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 1513 DPRINTFN(2, ("$")); 1514 for (ndesc = 0, iov = pkt->fp_iov; 1515 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1516 for (i = 0; i < iov->iov_len; i++) 1517 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1518 ((u_int8_t *)iov->iov_base)[i])); 1519 DPRINTFN(2, ("$")); 1520 } 1521 DPRINTFN(1, ("\n")); 1522 #endif 1523 1524 if ((m = pkt->fp_m) != NULL) { 1525 for (ndesc = 2; m != NULL; m = m->m_next) 1526 ndesc++; 1527 if (ndesc > OHCI_DESC_MAX) { 1528 m0 = NULL; 1529 ndesc = 2; 1530 for (off = 0; off < pkt->fp_dlen; off += len) { 1531 if (m0 == NULL) { 1532 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1533 if (m0 != NULL) 1534 M_COPY_PKTHDR(m0, pkt->fp_m); 1535 m = m0; 1536 } else { 1537 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1538 m = m->m_next; 1539 } 1540 if (m != NULL) 1541 MCLGET(m, M_DONTWAIT); 1542 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1543 m_freem(m0); 1544 return ENOMEM; 1545 } 1546 len = pkt->fp_dlen - off; 1547 if (len > m->m_ext.ext_size) 1548 len = m->m_ext.ext_size; 1549 m_copydata(pkt->fp_m, off, len, 1550 mtod(m, caddr_t)); 1551 m->m_len = len; 1552 ndesc++; 1553 } 1554 m_freem(pkt->fp_m); 1555 pkt->fp_m = m0; 1556 } 1557 } else 1558 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1559 1560 if (ndesc > OHCI_DESC_MAX) 1561 return ENOBUFS; 1562 1563 if (fc->fc_bufcnt > 50) /*XXX*/ 1564 return ENOBUFS; 1565 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1566 fb->fb_nseg = ndesc; 1567 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1568 if (fb->fb_desc == NULL) { 1569 free(fb, M_DEVBUF); 1570 return ENOBUFS; 1571 } 1572 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1573 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1574 fb->fb_m = pkt->fp_m; 1575 fb->fb_callback = pkt->fp_callback; 1576 fb->fb_statuscb = pkt->fp_statuscb; 1577 fb->fb_statusarg = pkt->fp_statusarg; 1578 1579 if (ndesc > 2) { 1580 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1581 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1582 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1583 free(fb, M_DEVBUF); 1584 return error; 1585 } 1586 1587 if (pkt->fp_m != NULL) 1588 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1589 pkt->fp_m, BUS_DMA_WAITOK); 1590 else 1591 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1592 &pkt->fp_uio, BUS_DMA_WAITOK); 1593 if (error != 0) { 1594 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1595 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1596 free(fb, M_DEVBUF); 1597 return error; 1598 } 1599 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1600 BUS_DMASYNC_PREWRITE); 1601 } 1602 1603 fd = fb->fb_desc; 1604 fd->fd_flags = OHCI_DESC_IMMED; 1605 fd->fd_reqcount = pkt->fp_hlen; 1606 fd->fd_data = 0; 1607 fd->fd_branch = 0; 1608 fd->fd_status = 0; 1609 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1610 i = 3; /* XXX: 3 sec */ 1611 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1612 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1613 ((((val >> 25) + i) & 0x7) << 13); 1614 } else 1615 fd->fd_timestamp = 0; 1616 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1617 for (i = 0; i < ndesc - 2; i++) { 1618 fd = fb->fb_desc + 2 + i; 1619 fd->fd_flags = 0; 1620 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1621 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1622 fd->fd_branch = 0; 1623 fd->fd_status = 0; 1624 fd->fd_timestamp = 0; 1625 } 1626 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1627 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1628 1629 #ifdef FW_DEBUG 1630 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1631 (long)(fb->fb_desc - sc->sc_desc))); 1632 for (i = 0; i < ndesc * 4; i++) 1633 DPRINTFN(1, ("%s%08x", i&7?" ":"\n\t", 1634 ((u_int32_t *)fb->fb_desc)[i])); 1635 DPRINTFN(1, ("\n")); 1636 #endif 1637 1638 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1639 OHCI_SUBREG_ContextControlClear); 1640 1641 if (val & OHCI_CTXCTL_RUN) { 1642 if (fc->fc_branch == NULL) { 1643 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1644 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1645 goto run; 1646 } 1647 *fc->fc_branch = fb->fb_daddr | ndesc; 1648 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1649 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1650 } else { 1651 run: 1652 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1653 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1654 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1655 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1656 } 1657 fc->fc_branch = &fd->fd_branch; 1658 1659 fc->fc_bufcnt++; 1660 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1661 pkt->fp_m = NULL; 1662 return 0; 1663 } 1664 1665 static void 1666 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1667 { 1668 struct fwohci_buf *fb; 1669 struct fwohci_desc *fd; 1670 struct fwohci_pkt pkt; 1671 int i; 1672 1673 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1674 fd = fb->fb_desc; 1675 #ifdef FW_DEBUG 1676 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1677 force ? "force " : "", (long)(fd - sc->sc_desc), 1678 fb->fb_nseg)); 1679 for (i = 0; i < fb->fb_nseg * 4; i++) 1680 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", 1681 ((u_int32_t *)fd)[i])); 1682 DPRINTFN(1, ("\n")); 1683 #endif 1684 if (fb->fb_nseg > 2) 1685 fd += fb->fb_nseg - 1; 1686 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1687 break; 1688 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1689 if (fc->fc_branch == &fd->fd_branch) { 1690 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1691 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1692 fc->fc_branch = NULL; 1693 for (i = 0; i < OHCI_LOOP; i++) { 1694 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1695 OHCI_SUBREG_ContextControlClear) & 1696 OHCI_CTXCTL_ACTIVE)) 1697 break; 1698 } 1699 } 1700 1701 if (fb->fb_statuscb) { 1702 memset(&pkt, 0, sizeof(pkt)); 1703 pkt.fp_status = fd->fd_status; 1704 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1705 1706 /* Indicate this is just returning the status bits. */ 1707 pkt.fp_tcode = -1; 1708 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1709 fb->fb_statuscb = NULL; 1710 fb->fb_statusarg = NULL; 1711 } 1712 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1713 if (fb->fb_nseg > 2) 1714 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1715 fc->fc_bufcnt--; 1716 if (fb->fb_callback) { 1717 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1718 fb->fb_callback = NULL; 1719 } else if (fb->fb_m != NULL) 1720 m_freem(fb->fb_m); 1721 free(fb, M_DEVBUF); 1722 } 1723 } 1724 1725 /* 1726 * Asynchronous Transmit Reponse -- in response of request packet. 1727 */ 1728 static void 1729 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1730 struct fwohci_pkt *res) 1731 { 1732 1733 if (((*req->fp_trail & 0x001f0000) >> 16) != 1734 OHCI_CTXCTL_EVENT_ACK_PENDING) 1735 return; 1736 1737 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1738 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1739 switch (req->fp_tcode) { 1740 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1741 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1742 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1743 res->fp_hlen = 12; 1744 break; 1745 case IEEE1394_TCODE_READ_REQ_QUAD: 1746 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1747 res->fp_hlen = 16; 1748 res->fp_dlen = 0; 1749 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1750 res->fp_hdr[3] = 1751 *(u_int32_t *)res->fp_iov[0].iov_base; 1752 res->fp_uio.uio_iovcnt = 0; 1753 break; 1754 case IEEE1394_TCODE_READ_REQ_BLOCK: 1755 case IEEE1394_TCODE_LOCK_REQ: 1756 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1757 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1758 else 1759 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1760 res->fp_hlen = 16; 1761 res->fp_dlen = res->fp_uio.uio_resid; 1762 res->fp_hdr[3] = res->fp_dlen << 16; 1763 break; 1764 } 1765 res->fp_hdr[0] |= (res->fp_tcode << 4); 1766 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1767 } 1768 1769 /* 1770 * APPLICATION LAYER SERVICES 1771 */ 1772 1773 /* 1774 * Retrieve Global UID from GUID ROM 1775 */ 1776 static int 1777 fwohci_guidrom_init(struct fwohci_softc *sc) 1778 { 1779 int i, n, off; 1780 u_int32_t val1, val2; 1781 1782 /* Extract the Global UID 1783 */ 1784 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1785 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1786 1787 if (val1 != 0 || val2 != 0) { 1788 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1789 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1790 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1791 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1792 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1793 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1794 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1795 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1796 } else { 1797 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1798 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1799 return -1; 1800 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1801 for (i = 0; i < OHCI_LOOP; i++) { 1802 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1803 if (!(val1 & OHCI_Guid_AddrReset)) 1804 break; 1805 } 1806 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1807 val2 = 0; 1808 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1809 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1810 OHCI_Guid_RdStart); 1811 for (i = 0; i < OHCI_LOOP; i++) { 1812 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1813 if (!(val1 & OHCI_Guid_RdStart)) 1814 break; 1815 } 1816 if (n < off) 1817 continue; 1818 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1819 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1820 val2 |= val1; 1821 } 1822 if (val2 == 0) 1823 return -1; 1824 } 1825 return 0; 1826 } 1827 1828 /* 1829 * Initialization for Configuration ROM (no DMA context) 1830 */ 1831 1832 #define CFR_MAXUNIT 20 1833 1834 struct configromctx { 1835 u_int32_t *ptr; 1836 int curunit; 1837 struct { 1838 u_int32_t *start; 1839 int length; 1840 u_int32_t *refer; 1841 int refunit; 1842 } unit[CFR_MAXUNIT]; 1843 }; 1844 1845 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1846 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1847 1848 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1849 1850 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1851 1852 #define CFR_PUT_CRC(cfr, n) \ 1853 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1854 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1855 1856 #define CFR_START_UNIT(cfr, n) \ 1857 do { \ 1858 if ((cfr)->unit[n].refer != NULL) { \ 1859 *(cfr)->unit[n].refer |= \ 1860 (cfr)->ptr - (cfr)->unit[n].refer; \ 1861 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1862 } \ 1863 (cfr)->curunit = (n); \ 1864 (cfr)->unit[n].start = (cfr)->ptr++; \ 1865 } while (0 /* CONSTCOND */) 1866 1867 #define CFR_PUT_REFER(cfr, key, n) \ 1868 do { \ 1869 (cfr)->unit[n].refer = (cfr)->ptr; \ 1870 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1871 *(cfr)->ptr++ = (key) << 24; \ 1872 } while (0 /* CONSTCOND */) 1873 1874 #define CFR_END_UNIT(cfr) \ 1875 do { \ 1876 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1877 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1878 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1879 } while (0 /* CONSTCOND */) 1880 1881 static u_int16_t 1882 fwohci_crc16(u_int32_t *ptr, int len) 1883 { 1884 int shift; 1885 u_int32_t crc, sum, data; 1886 1887 crc = 0; 1888 while (len-- > 0) { 1889 data = *ptr++; 1890 for (shift = 28; shift >= 0; shift -= 4) { 1891 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1892 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1893 } 1894 crc &= 0xffff; 1895 } 1896 return crc; 1897 } 1898 1899 static void 1900 fwohci_configrom_init(struct fwohci_softc *sc) 1901 { 1902 int i, val; 1903 struct fwohci_buf *fb; 1904 u_int32_t *hdr; 1905 struct configromctx cfr; 1906 1907 fb = &sc->sc_buf_cnfrom; 1908 memset(&cfr, 0, sizeof(cfr)); 1909 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1910 1911 /* headers */ 1912 CFR_START_UNIT(&cfr, 0); 1913 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1914 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1915 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1916 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1917 CFR_END_UNIT(&cfr); 1918 /* copy info_length from crc_length */ 1919 *hdr |= (*hdr & 0x00ff0000) << 8; 1920 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1921 1922 /* root directory */ 1923 CFR_START_UNIT(&cfr, 1); 1924 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1925 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1926 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1927 /* spt,64,fix,lst,drq */ 1928 #ifdef INET 1929 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1930 #endif /* INET */ 1931 #ifdef INET6 1932 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1933 #endif /* INET6 */ 1934 CFR_END_UNIT(&cfr); 1935 1936 CFR_START_UNIT(&cfr, 2); 1937 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1938 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1939 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1940 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1941 CFR_END_UNIT(&cfr); 1942 1943 #ifdef INET 1944 /* IPv4 unit directory */ 1945 CFR_START_UNIT(&cfr, 3); 1946 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1947 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1948 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1949 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1950 CFR_END_UNIT(&cfr); 1951 1952 CFR_START_UNIT(&cfr, 6); 1953 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1954 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1955 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1956 CFR_END_UNIT(&cfr); 1957 1958 CFR_START_UNIT(&cfr, 7); 1959 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1960 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1961 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1962 CFR_END_UNIT(&cfr); 1963 #endif /* INET */ 1964 1965 #ifdef INET6 1966 /* IPv6 unit directory */ 1967 CFR_START_UNIT(&cfr, 4); 1968 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1969 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1970 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 1971 /* XXX: TBA by IANA */ 1972 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1973 CFR_END_UNIT(&cfr); 1974 1975 CFR_START_UNIT(&cfr, 8); 1976 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1977 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1978 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1979 CFR_END_UNIT(&cfr); 1980 1981 CFR_START_UNIT(&cfr, 9); 1982 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1983 CFR_PUT_DATA1(&cfr, 0); 1984 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1985 CFR_END_UNIT(&cfr); 1986 #endif /* INET6 */ 1987 1988 fb->fb_off = cfr.ptr - hdr; 1989 #ifdef FW_DEBUG 1990 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 1991 for (i = 0; i < fb->fb_off; i++) 1992 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 1993 DPRINTFN(2, ("\n")); 1994 #endif /* FW_DEBUG */ 1995 1996 /* 1997 * Make network byte order for DMA 1998 */ 1999 for (i = 0; i < fb->fb_off; i++) 2000 HTONL(hdr[i]); 2001 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2002 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2003 2004 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2005 fb->fb_dmamap->dm_segs[0].ds_addr); 2006 2007 /* This register is only valid on OHCI 1.1. */ 2008 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2009 if ((OHCI_Version_GET_Version(val) == 1) && 2010 (OHCI_Version_GET_Revision(val) == 1)) 2011 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2012 OHCI_HCControl_BIBImageValid); 2013 2014 /* Just allow quad reads of the rom. */ 2015 for (i = 0; i < fb->fb_off; i++) 2016 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2017 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2018 fwohci_configrom_input, NULL); 2019 } 2020 2021 static int 2022 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2023 struct fwohci_pkt *pkt) 2024 { 2025 struct fwohci_pkt res; 2026 u_int32_t loc, *rom; 2027 2028 /* This will be used as an array index so size accordingly. */ 2029 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2030 if ((loc & 0x03) != 0) { 2031 /* alignment error */ 2032 return IEEE1394_RCODE_ADDRESS_ERROR; 2033 } 2034 else 2035 loc /= 4; 2036 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2037 2038 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2039 ntohl(rom[loc]))); 2040 2041 memset(&res, 0, sizeof(res)); 2042 res.fp_hdr[3] = rom[loc]; 2043 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2044 return -1; 2045 } 2046 2047 /* 2048 * SelfID buffer (no DMA context) 2049 */ 2050 static void 2051 fwohci_selfid_init(struct fwohci_softc *sc) 2052 { 2053 struct fwohci_buf *fb; 2054 2055 fb = &sc->sc_buf_selfid; 2056 #ifdef DIAGNOSTIC 2057 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2058 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2059 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2060 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2061 #endif 2062 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2063 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2064 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2065 2066 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2067 fb->fb_dmamap->dm_segs[0].ds_addr); 2068 } 2069 2070 static int 2071 fwohci_selfid_input(struct fwohci_softc *sc) 2072 { 2073 int i; 2074 u_int32_t count, val, gen; 2075 u_int32_t *buf; 2076 2077 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2078 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2079 again: 2080 if (val & OHCI_SelfID_Error) { 2081 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2082 return -1; 2083 } 2084 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2085 2086 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2087 0, count << 2, BUS_DMASYNC_POSTREAD); 2088 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2089 2090 #ifdef FW_DEBUG 2091 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2092 val)); 2093 for (i = 0; i < count; i++) 2094 DPRINTFN(1, ("%s%08x", i&7?" ":"\n ", buf[i])); 2095 DPRINTFN(1, ("\n")); 2096 #endif /* FW_DEBUG */ 2097 2098 for (i = 1; i < count; i += 2) { 2099 if (buf[i] != ~buf[i + 1]) 2100 break; 2101 if (buf[i] & 0x00000001) 2102 continue; /* more pkt */ 2103 if (buf[i] & 0x00800000) 2104 continue; /* external id */ 2105 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2106 if ((buf[i] & 0x00400800) == 0x00400800) 2107 sc->sc_irmid = sc->sc_rootid; 2108 } 2109 2110 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2111 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2112 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2113 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2114 goto again; 2115 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2116 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2117 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2118 return -1; 2119 } 2120 if (i != count) { 2121 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2122 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2123 #if 1 2124 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2125 /* 2126 * XXX: CXD3222 sometimes fails to DMA 2127 * selfid packet?? 2128 */ 2129 sc->sc_rootid = (count - 1) / 2 - 1; 2130 sc->sc_irmid = sc->sc_rootid; 2131 } else 2132 #endif 2133 return -1; 2134 } 2135 2136 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2137 if ((val & OHCI_NodeId_IDValid) == 0) { 2138 sc->sc_nodeid = 0xffff; /* invalid */ 2139 printf("%s: nodeid is invalid\n", 2140 sc->sc_sc1394.sc1394_dev.dv_xname); 2141 return -1; 2142 } 2143 sc->sc_nodeid = val & 0xffff; 2144 2145 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2146 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2147 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2148 sc->sc_irmid)); 2149 2150 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2151 return -1; 2152 2153 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2154 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2155 OHCI_LinkControl_CycleMaster); 2156 else 2157 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2158 OHCI_LinkControl_CycleMaster); 2159 return 0; 2160 } 2161 2162 /* 2163 * some CSRs are handled by driver. 2164 */ 2165 static void 2166 fwohci_csr_init(struct fwohci_softc *sc) 2167 { 2168 int i; 2169 static u_int32_t csr[] = { 2170 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2171 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2172 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2173 CSR_SB_BROADCAST_CHANNEL 2174 }; 2175 2176 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2177 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2178 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2179 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2180 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2181 } 2182 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2183 } 2184 2185 static int 2186 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2187 { 2188 struct fwohci_pkt res; 2189 u_int32_t reg; 2190 2191 /* 2192 * XXX need to do special functionality other than just r/w... 2193 */ 2194 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2195 2196 if ((reg & 0x03) != 0) { 2197 /* alignment error */ 2198 return IEEE1394_RCODE_ADDRESS_ERROR; 2199 } 2200 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2201 *(u_int32_t *)(&sc->sc_csr[reg]))); 2202 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2203 DPRINTFN(1, (" -> 0x%08x\n", 2204 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2205 *(u_int32_t *)&sc->sc_csr[reg] = 2206 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2207 } else { 2208 DPRINTFN(1, ("\n")); 2209 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2210 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2211 res.fp_iov[0].iov_len = 4; 2212 res.fp_uio.uio_resid = 4; 2213 res.fp_uio.uio_iovcnt = 1; 2214 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2215 return -1; 2216 } 2217 return IEEE1394_RCODE_COMPLETE; 2218 } 2219 2220 /* 2221 * Mapping between nodeid and unique ID (EUI-64). 2222 * 2223 * Track old mappings and simply update their devices with the new id's when 2224 * they match an existing EUI. This allows proper renumeration of the bus. 2225 */ 2226 static void 2227 fwohci_uid_collect(struct fwohci_softc *sc) 2228 { 2229 int i; 2230 struct fwohci_uidtbl *fu; 2231 struct fwohci_pkt pkt; 2232 struct ieee1394_softc *iea; 2233 2234 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2235 iea->sc1394_node_id = 0xffff; 2236 2237 if (sc->sc_uidtbl != NULL) 2238 free(sc->sc_uidtbl, M_DEVBUF); 2239 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2240 M_WAITOK); 2241 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2242 2243 memset(&pkt, 0, sizeof(pkt)); 2244 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2245 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2246 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2247 fu->fu_valid = 3; 2248 2249 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2250 if (iea) { 2251 iea->sc1394_node_id = i; 2252 DPRINTF(("%s: Updating nodeid to %d\n", 2253 iea->sc1394_dev.dv_xname, 2254 iea->sc1394_node_id)); 2255 } 2256 continue; 2257 } 2258 fu->fu_valid = 0; 2259 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2260 pkt.fp_hlen = 12; 2261 pkt.fp_dlen = 0; 2262 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2263 (pkt.fp_tcode << 4); 2264 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 2265 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2266 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2267 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2268 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2269 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2270 2271 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2272 (pkt.fp_tcode << 4); 2273 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2274 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 2275 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2276 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2277 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2278 2279 } 2280 if (sc->sc_rootid == 0) 2281 fwohci_check_nodes(sc); 2282 } 2283 2284 static int 2285 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2286 { 2287 struct fwohci_uidtbl *fu; 2288 struct ieee1394_softc *iea; 2289 struct ieee1394_attach_args fwa; 2290 int i, n, done, rcode, found; 2291 2292 found = 0; 2293 2294 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2295 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2296 if (rcode != IEEE1394_RCODE_COMPLETE || 2297 sc->sc_uidtbl == NULL || 2298 n > sc->sc_rootid) 2299 return 0; 2300 fu = &sc->sc_uidtbl[n]; 2301 if (arg == 0) { 2302 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2303 fu->fu_valid |= 0x1; 2304 } else { 2305 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2306 fu->fu_valid |= 0x2; 2307 } 2308 #ifdef FW_DEBUG 2309 if (fu->fu_valid == 0x3) 2310 DPRINTFN(1, ("fwohci_uid_input: " 2311 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2312 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2313 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2314 #endif 2315 if (fu->fu_valid == 0x3) { 2316 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2317 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2318 found = 1; 2319 iea->sc1394_node_id = n; 2320 DPRINTF(("%s: Updating nodeid to %d\n", 2321 iea->sc1394_dev.dv_xname, 2322 iea->sc1394_node_id)); 2323 break; 2324 } 2325 if (!found) { 2326 strcpy(fwa.name, "fwnode"); 2327 memcpy(fwa.uid, fu->fu_uid, 8); 2328 fwa.nodeid = n; 2329 fwa.read = fwohci_read; 2330 fwa.write = fwohci_write; 2331 fwa.inreg = fwohci_inreg; 2332 iea = (struct ieee1394_softc *) 2333 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2334 fwohci_print, fwohci_submatch); 2335 if (iea != NULL) 2336 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2337 sc1394_node); 2338 } 2339 } 2340 done = 1; 2341 2342 for (i = 0; i < sc->sc_rootid + 1; i++) { 2343 fu = &sc->sc_uidtbl[i]; 2344 if (fu->fu_valid != 0x3) { 2345 done = 0; 2346 break; 2347 } 2348 } 2349 if (done) 2350 fwohci_check_nodes(sc); 2351 2352 return 0; 2353 } 2354 2355 static void 2356 fwohci_check_nodes(struct fwohci_softc *sc) 2357 { 2358 struct device *detach = NULL; 2359 struct ieee1394_softc *iea; 2360 2361 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2362 2363 /* 2364 * Have to defer detachment until the next 2365 * loop iteration since config_detach 2366 * free's the softc and the loop iterator 2367 * needs data from the softc to move 2368 * forward. 2369 */ 2370 2371 if (detach) { 2372 config_detach(detach, 0); 2373 detach = NULL; 2374 } 2375 if (iea->sc1394_node_id == 0xffff) { 2376 detach = (struct device *)iea; 2377 LIST_REMOVE(iea, sc1394_node); 2378 } 2379 } 2380 if (detach) 2381 config_detach(detach, 0); 2382 } 2383 2384 static int 2385 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2386 { 2387 struct fwohci_uidtbl *fu; 2388 int n; 2389 static const u_int8_t bcast[] = 2390 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2391 2392 fu = sc->sc_uidtbl; 2393 if (fu == NULL) { 2394 notfound: 2395 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2396 return IEEE1394_BCAST_PHY_ID; 2397 fwohci_uid_collect(sc); /* try to get */ 2398 return -1; 2399 } 2400 for (n = 0; ; n++, fu++) { 2401 if (n > sc->sc_rootid) 2402 goto notfound; 2403 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2404 break; 2405 } 2406 return n; 2407 } 2408 2409 /* 2410 * functions to support network interface 2411 */ 2412 static int 2413 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2414 void (*handler)(struct device *, struct mbuf *)) 2415 { 2416 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2417 2418 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2419 fwohci_if_input, handler); 2420 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2421 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2422 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2423 return 0; 2424 } 2425 2426 static int 2427 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2428 { 2429 int n, len; 2430 struct mbuf *m; 2431 struct iovec *iov; 2432 void (*handler)(struct device *, struct mbuf *) = arg; 2433 2434 #ifdef FW_DEBUG 2435 int i; 2436 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2437 pkt->fp_dlen)); 2438 for (i = 0; i < pkt->fp_hlen/4; i++) 2439 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2440 DPRINTFN(2, ("$")); 2441 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2442 iov = &pkt->fp_iov[n]; 2443 for (i = 0; i < iov->iov_len; i++) 2444 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 2445 ((u_int8_t *)iov->iov_base)[i])); 2446 DPRINTFN(2, ("$")); 2447 } 2448 DPRINTFN(1, ("\n")); 2449 #endif /* FW_DEBUG */ 2450 len = pkt->fp_dlen; 2451 MGETHDR(m, M_DONTWAIT, MT_DATA); 2452 if (m == NULL) 2453 return IEEE1394_RCODE_COMPLETE; 2454 m->m_len = 16; 2455 if (len + m->m_len > MHLEN) { 2456 MCLGET(m, M_DONTWAIT); 2457 if ((m->m_flags & M_EXT) == 0) { 2458 m_freem(m); 2459 return IEEE1394_RCODE_COMPLETE; 2460 } 2461 } 2462 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2463 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2464 sc->sc_uidtbl[n].fu_valid != 0x3) { 2465 printf("%s: packet from unknown node: phy id %d\n", 2466 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2467 m_freem(m); 2468 return IEEE1394_RCODE_COMPLETE; 2469 } 2470 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2471 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2472 m->m_flags |= M_BCAST; 2473 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2474 } else { 2475 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2476 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2477 } 2478 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2479 mtod(m, u_int8_t *)[9] = 2480 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2481 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2482 2483 m->m_pkthdr.rcvif = NULL; /* set in child */ 2484 m->m_pkthdr.len = len + m->m_len; 2485 /* 2486 * We may use receive buffer by external mbuf instead of copy here. 2487 * But asynchronous receive buffer must be operate in buffer fill 2488 * mode, so that each receive buffer will shared by multiple mbufs. 2489 * If upper layer doesn't free mbuf soon, e.g. application program 2490 * is suspended, buffer must be reallocated. 2491 * Isochronous buffer must be operate in packet buffer mode, and 2492 * it is easy to map receive buffer to external mbuf. But it is 2493 * used for broadcast/multicast only, and is expected not so 2494 * performance sensitive for now. 2495 * XXX: The performance may be important for multicast case, 2496 * so we should revisit here later. 2497 * -- onoe 2498 */ 2499 n = 0; 2500 iov = pkt->fp_uio.uio_iov; 2501 while (len > 0) { 2502 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2503 iov->iov_len); 2504 m->m_len += iov->iov_len; 2505 len -= iov->iov_len; 2506 iov++; 2507 } 2508 (*handler)(sc->sc_sc1394.sc1394_if, m); 2509 return IEEE1394_RCODE_COMPLETE; 2510 } 2511 2512 static int 2513 fwohci_if_output(struct device *self, struct mbuf *m0, 2514 void (*callback)(struct device *, struct mbuf *)) 2515 { 2516 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2517 struct fwohci_pkt pkt; 2518 u_int8_t *p; 2519 int n, error, spd, hdrlen, maxrec; 2520 #ifdef FW_DEBUG 2521 struct mbuf *m; 2522 #endif 2523 2524 p = mtod(m0, u_int8_t *); 2525 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2526 spd = IEEE1394_SPD_S100; /*XXX*/ 2527 maxrec = 512; /*XXX*/ 2528 hdrlen = 8; 2529 } else { 2530 n = fwohci_uid_lookup(sc, p); 2531 if (n < 0) { 2532 printf("%s: nodeid unknown:" 2533 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2534 sc->sc_sc1394.sc1394_dev.dv_xname, 2535 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2536 error = EHOSTUNREACH; 2537 goto end; 2538 } 2539 if (n == IEEE1394_BCAST_PHY_ID) { 2540 printf("%s: broadcast with !M_MCAST\n", 2541 sc->sc_sc1394.sc1394_dev.dv_xname); 2542 #ifdef FW_DEBUG 2543 DPRINTFN(2, ("packet:")); 2544 for (m = m0; m != NULL; m = m->m_next) { 2545 for (n = 0; n < m->m_len; n++) 2546 DPRINTFN(2, ("%s%02x", (n%32)? 2547 ((n%4)?"":" "):"\n\t", 2548 mtod(m, u_int8_t *)[n])); 2549 DPRINTFN(2, ("$")); 2550 } 2551 DPRINTFN(2, ("\n")); 2552 #endif 2553 error = EHOSTUNREACH; 2554 goto end; 2555 } 2556 maxrec = 2 << p[8]; 2557 spd = p[9]; 2558 hdrlen = 0; 2559 } 2560 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2561 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2562 spd, sc->sc_sc1394.sc1394_link_speed)); 2563 spd = sc->sc_sc1394.sc1394_link_speed; 2564 } 2565 if (maxrec > (512 << spd)) { 2566 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2567 "\n", maxrec, spd)); 2568 maxrec = 512 << spd; 2569 } 2570 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2571 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2572 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2573 maxrec >>= 1; 2574 } 2575 if (maxrec < 512) { 2576 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2577 "minimum\n", maxrec)); 2578 maxrec = 512; 2579 } 2580 2581 m_adj(m0, 16 - hdrlen); 2582 if (m0->m_pkthdr.len > maxrec) { 2583 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2584 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2585 error = E2BIG; /*XXX*/ 2586 goto end; 2587 } 2588 2589 memset(&pkt, 0, sizeof(pkt)); 2590 pkt.fp_uio.uio_iov = pkt.fp_iov; 2591 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2592 pkt.fp_uio.uio_rw = UIO_WRITE; 2593 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2594 /* construct GASP header */ 2595 p = mtod(m0, u_int8_t *); 2596 p[0] = sc->sc_nodeid >> 8; 2597 p[1] = sc->sc_nodeid & 0xff; 2598 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2599 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2600 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2601 pkt.fp_hlen = 8; 2602 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2603 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2604 OHCI_NodeId_NodeNumber) << 8); 2605 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2606 } else { 2607 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2608 pkt.fp_hlen = 16; 2609 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2610 (spd << 16); 2611 pkt.fp_hdr[1] = 2612 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2613 (p[10] << 8) | p[11]; 2614 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2615 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2616 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2617 } 2618 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2619 pkt.fp_dlen = m0->m_pkthdr.len; 2620 pkt.fp_m = m0; 2621 pkt.fp_callback = callback; 2622 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2623 m0 = pkt.fp_m; 2624 end: 2625 if (m0 != NULL) { 2626 if (callback) 2627 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2628 else 2629 m_freem(m0); 2630 } 2631 return error; 2632 } 2633 2634 /* 2635 * High level routines to provide abstraction to attaching layers to 2636 * send/receive data. 2637 */ 2638 2639 /* 2640 * These break down into 4 routines as follows: 2641 * 2642 * int fwohci_read(struct ieee1394_abuf *) 2643 * 2644 * This routine will attempt to read a region from the requested node. 2645 * A callback must be provided which will be called when either the completed 2646 * read is done or an unrecoverable error occurs. This is mainly a convenience 2647 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2648 * and recombining all the returned data. This could also be done with a series 2649 * of write/inreg's for each packet sent. 2650 * 2651 * int fwohci_write(struct ieee1394_abuf *) 2652 * 2653 * The work horse main entry point for putting packets on the bus. This is the 2654 * generalized interface for fwnode/etc code to put packets out onto the bus. 2655 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2656 * will callback via a func pointer to the calling code with the resulting ACK 2657 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2658 * write routine will take care of free'ing the abuf since the fwnode/etc code 2659 * won't have any knowledge of when to do this. This allows for simple one-off 2660 * packets to be sent from the upper-level code without worrying about a callback 2661 * for cleanup. 2662 * 2663 * int fwohci_inreg(struct ieee1394_abuf *, int) 2664 * 2665 * This is very simple. It evals the abuf passed in and registers an internal 2666 * handler as the callback for packets received for that operation. 2667 * The integer argument specifies whether on a block read/write operation to 2668 * allow sub-regions to be read/written (in block form) as well. 2669 * 2670 * XXX: This whole structure needs to be redone as a list of regions and 2671 * operations allowed on those regions. 2672 * 2673 * int fwohci_unreg(struct ieee1394_abuf *, int) 2674 * 2675 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2676 * routine will simply verify ab_cb is NULL and call inreg. 2677 * 2678 * This simply unregisters the respective callback done via inreg for items 2679 * which only need to register an area for a one-time operation (like a status 2680 * buffer a remote node will write to when the current operation is done). The 2681 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2682 * it unregisters). 2683 */ 2684 2685 static int 2686 fwohci_read(struct ieee1394_abuf *ab) 2687 { 2688 struct fwohci_pkt pkt; 2689 struct ieee1394_softc *sc = ab->ab_req; 2690 struct fwohci_softc *psc = 2691 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2692 struct fwohci_cb *fcb; 2693 u_int32_t high, lo; 2694 int rv, tcode; 2695 2696 /* Have to have a callback when reading. */ 2697 if (ab->ab_cb == NULL) 2698 return -1; 2699 2700 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2701 fcb->ab = ab; 2702 fcb->count = 0; 2703 fcb->abuf_valid = 1; 2704 2705 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2706 lo = (ab->ab_csr & 0x00000000ffffffff); 2707 2708 memset(&pkt, 0, sizeof(pkt)); 2709 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2710 pkt.fp_hdr[2] = lo; 2711 pkt.fp_dlen = 0; 2712 2713 if (ab->ab_length == 4) { 2714 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2715 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2716 pkt.fp_hlen = 12; 2717 } else { 2718 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2719 pkt.fp_hlen = 16; 2720 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2721 pkt.fp_hdr[3] = (ab->ab_length << 16); 2722 } 2723 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2724 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2725 2726 pkt.fp_statusarg = fcb; 2727 pkt.fp_statuscb = fwohci_read_resp; 2728 2729 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2730 psc->sc_tlabel, fwohci_read_resp, fcb); 2731 if (rv) 2732 return rv; 2733 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2734 if (rv) 2735 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2736 psc->sc_tlabel, NULL, NULL); 2737 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2738 fcb->count = 1; 2739 return rv; 2740 } 2741 2742 static int 2743 fwohci_write(struct ieee1394_abuf *ab) 2744 { 2745 struct fwohci_pkt pkt; 2746 struct ieee1394_softc *sc = ab->ab_req; 2747 struct fwohci_softc *psc = 2748 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2749 u_int32_t high, lo; 2750 int rv; 2751 2752 if (ab->ab_length > sc->sc1394_max_receive) { 2753 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2754 return E2BIG; 2755 } 2756 2757 memset(&pkt, 0, sizeof(pkt)); 2758 2759 pkt.fp_tcode = ab->ab_tcode; 2760 pkt.fp_uio.uio_iov = pkt.fp_iov; 2761 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2762 pkt.fp_uio.uio_rw = UIO_WRITE; 2763 2764 pkt.fp_statusarg = ab; 2765 pkt.fp_statuscb = fwohci_write_ack; 2766 2767 switch (ab->ab_tcode) { 2768 case IEEE1394_TCODE_WRITE_RESP: 2769 pkt.fp_hlen = 12; 2770 case IEEE1394_TCODE_READ_RESP_QUAD: 2771 case IEEE1394_TCODE_READ_RESP_BLOCK: 2772 if (!pkt.fp_hlen) 2773 pkt.fp_hlen = 16; 2774 high = ab->ab_retlen; 2775 ab->ab_retlen = 0; 2776 lo = 0; 2777 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2778 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2779 break; 2780 default: 2781 pkt.fp_hlen = 16; 2782 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2783 lo = (ab->ab_csr & 0x00000000ffffffff); 2784 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2785 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2786 break; 2787 } 2788 2789 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2790 pkt.fp_hdr[2] = lo; 2791 if (pkt.fp_hlen == 16) { 2792 if (ab->ab_length == 4) { 2793 pkt.fp_hdr[3] = ab->ab_data[0]; 2794 pkt.fp_dlen = 0; 2795 } else { 2796 pkt.fp_hdr[3] = (ab->ab_length << 16); 2797 pkt.fp_dlen = ab->ab_length; 2798 pkt.fp_uio.uio_iovcnt = 1; 2799 pkt.fp_uio.uio_resid = ab->ab_length; 2800 pkt.fp_iov[0].iov_base = ab->ab_data; 2801 pkt.fp_iov[0].iov_len = ab->ab_length; 2802 } 2803 } 2804 switch (ab->ab_tcode) { 2805 case IEEE1394_TCODE_WRITE_RESP: 2806 case IEEE1394_TCODE_READ_RESP_QUAD: 2807 case IEEE1394_TCODE_READ_RESP_BLOCK: 2808 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2809 break; 2810 default: 2811 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2812 break; 2813 } 2814 return rv; 2815 } 2816 2817 static int 2818 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2819 { 2820 struct fwohci_cb *fcb = arg; 2821 struct ieee1394_abuf *ab = fcb->ab; 2822 struct fwohci_pkt newpkt; 2823 u_int32_t *cur, high, lo; 2824 int i, tcode, rcode, status, rv; 2825 2826 /* 2827 * Both the ACK handling and normal response callbacks are handled here. 2828 * The main reason for this is the various error conditions that can 2829 * occur trying to block read some areas and the ways that gets reported 2830 * back to calling station. This is a variety of ACK codes, responses, 2831 * etc which makes it much more difficult to process if both aren't 2832 * handled here. 2833 */ 2834 2835 /* Check for status packet. */ 2836 2837 if (pkt->fp_tcode == -1) { 2838 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2839 rcode = -1; 2840 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2841 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2842 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2843 DPRINTF(("Got status packet: 0x%02x\n", 2844 (unsigned int)status)); 2845 fcb->count--; 2846 2847 /* 2848 * Got all the ack's back and the buffer is invalid (i.e. the 2849 * callback has been called. Clean up. 2850 */ 2851 2852 if (fcb->abuf_valid == 0) { 2853 if (fcb->count == 0) 2854 free(fcb, M_DEVBUF); 2855 return IEEE1394_RCODE_COMPLETE; 2856 } 2857 } else { 2858 status = -1; 2859 tcode = pkt->fp_tcode; 2860 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2861 } 2862 2863 /* 2864 * Some area's (like the config rom want to be read as quadlets only. 2865 * 2866 * The current ideas to try are: 2867 * 2868 * Got an ACK_TYPE_ERROR on a block read. 2869 * 2870 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2871 * response. 2872 * 2873 * In all cases construct a new packet for a quadlet read and let 2874 * mutli_resp handle the iteration over the space. 2875 */ 2876 2877 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2878 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2879 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2880 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2881 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2882 2883 /* Read the area in quadlet chunks (internally track this). */ 2884 2885 memset(&newpkt, 0, sizeof(newpkt)); 2886 2887 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2888 lo = (ab->ab_csr & 0x00000000ffffffff); 2889 2890 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2891 newpkt.fp_hlen = 12; 2892 newpkt.fp_dlen = 0; 2893 newpkt.fp_hdr[1] = 2894 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2895 newpkt.fp_hdr[2] = lo; 2896 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2897 (newpkt.fp_tcode << 4); 2898 2899 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2900 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2901 fwohci_read_multi_resp, fcb); 2902 if (rv) { 2903 (*ab->ab_cb)(ab, -1); 2904 goto cleanup; 2905 } 2906 newpkt.fp_statusarg = fcb; 2907 newpkt.fp_statuscb = fwohci_read_resp; 2908 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 2909 if (rv) { 2910 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2911 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 2912 NULL); 2913 (*ab->ab_cb)(ab, -1); 2914 goto cleanup; 2915 } 2916 fcb->count++; 2917 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2918 return IEEE1394_RCODE_COMPLETE; 2919 } else if ((rcode != -1) || ((status != -1) && 2920 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2921 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 2922 2923 /* 2924 * Recombine all the iov data into 1 chunk for higher 2925 * level code. 2926 */ 2927 2928 if (rcode != -1) { 2929 cur = ab->ab_data; 2930 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 2931 /* 2932 * Make sure and don't exceed the buffer 2933 * allocated for return. 2934 */ 2935 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 2936 ab->ab_length) { 2937 memcpy(cur, pkt->fp_iov[i].iov_base, 2938 (ab->ab_length - ab->ab_retlen)); 2939 ab->ab_retlen = ab->ab_length; 2940 break; 2941 } 2942 memcpy(cur, pkt->fp_iov[i].iov_base, 2943 pkt->fp_iov[i].iov_len); 2944 cur += pkt->fp_iov[i].iov_len; 2945 ab->ab_retlen += pkt->fp_iov[i].iov_len; 2946 } 2947 } 2948 if (status != -1) 2949 /* XXX: Need a complete tlabel interface. */ 2950 for (i = 0; i < 64; i++) 2951 fwohci_handler_set(sc, 2952 IEEE1394_TCODE_READ_RESP_QUAD, 2953 ab->ab_req->sc1394_node_id, i, NULL, NULL); 2954 (*ab->ab_cb)(ab, rcode); 2955 goto cleanup; 2956 } else 2957 /* Good ack packet. */ 2958 return IEEE1394_RCODE_COMPLETE; 2959 2960 /* Can't get here unless ab->ab_cb has been called. */ 2961 2962 cleanup: 2963 fcb->abuf_valid = 0; 2964 if (fcb->count == 0) 2965 free(fcb, M_DEVBUF); 2966 return IEEE1394_RCODE_COMPLETE; 2967 } 2968 2969 static int 2970 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 2971 struct fwohci_pkt *pkt) 2972 { 2973 struct fwohci_cb *fcb = arg; 2974 struct ieee1394_abuf *ab = fcb->ab; 2975 struct fwohci_pkt newpkt; 2976 u_int32_t high, lo; 2977 int rcode, rv; 2978 2979 /* 2980 * Bad return codes from the wire, just return what's already in the 2981 * buf. 2982 */ 2983 2984 /* Make sure a response packet didn't arrive after a bad ACK. */ 2985 if (fcb->abuf_valid == 0) 2986 return IEEE1394_RCODE_COMPLETE; 2987 2988 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2989 2990 if (rcode) { 2991 (*ab->ab_cb)(ab, rcode); 2992 goto cleanup; 2993 } 2994 2995 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 2996 memcpy(((char *)ab->ab_data + ab->ab_retlen), 2997 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 2998 ab->ab_retlen = ab->ab_length; 2999 } else { 3000 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3001 pkt->fp_iov[0].iov_base, 4); 3002 ab->ab_retlen += 4; 3003 } 3004 /* Still more, loop and read 4 more bytes. */ 3005 if (ab->ab_retlen < ab->ab_length) { 3006 memset(&newpkt, 0, sizeof(newpkt)); 3007 3008 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3009 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3010 3011 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3012 newpkt.fp_hlen = 12; 3013 newpkt.fp_dlen = 0; 3014 newpkt.fp_hdr[1] = 3015 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3016 newpkt.fp_hdr[2] = lo; 3017 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3018 (newpkt.fp_tcode << 4); 3019 3020 newpkt.fp_statusarg = fcb; 3021 newpkt.fp_statuscb = fwohci_read_resp; 3022 3023 /* 3024 * Bad return code. Just give up and return what's 3025 * come in now. 3026 */ 3027 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3028 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3029 fwohci_read_multi_resp, fcb); 3030 if (rv) 3031 (*ab->ab_cb)(ab, -1); 3032 else { 3033 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3034 if (rv) { 3035 fwohci_handler_set(sc, 3036 IEEE1394_TCODE_READ_RESP_QUAD, 3037 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3038 NULL, NULL); 3039 (*ab->ab_cb)(ab, -1); 3040 } else { 3041 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3042 fcb->count++; 3043 return IEEE1394_RCODE_COMPLETE; 3044 } 3045 } 3046 } else 3047 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3048 3049 cleanup: 3050 /* Can't get here unless ab_cb has been called. */ 3051 fcb->abuf_valid = 0; 3052 if (fcb->count == 0) 3053 free(fcb, M_DEVBUF); 3054 return IEEE1394_RCODE_COMPLETE; 3055 } 3056 3057 static int 3058 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3059 { 3060 struct ieee1394_abuf *ab = arg; 3061 u_int16_t status; 3062 3063 3064 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3065 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3066 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3067 DPRINTF(("Got status packet: 0x%02x\n", 3068 (unsigned int)status)); 3069 3070 /* No callback means this level should free the buffers. */ 3071 if (ab->ab_cb) 3072 (*ab->ab_cb)(ab, status); 3073 else { 3074 if (ab->ab_data) 3075 free(ab->ab_data, M_1394DATA); 3076 free(ab, M_1394DATA); 3077 } 3078 return IEEE1394_RCODE_COMPLETE; 3079 } 3080 3081 static int 3082 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3083 { 3084 struct ieee1394_softc *sc = ab->ab_req; 3085 struct fwohci_softc *psc = 3086 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3087 u_int32_t high, lo; 3088 int i, j, rv; 3089 3090 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3091 lo = (ab->ab_csr & 0x00000000ffffffff); 3092 3093 rv = 0; 3094 switch (ab->ab_tcode) { 3095 case IEEE1394_TCODE_READ_REQ_QUAD: 3096 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3097 if (ab->ab_cb) 3098 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3099 fwohci_parse_input, ab); 3100 else 3101 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3102 NULL); 3103 break; 3104 case IEEE1394_TCODE_READ_REQ_BLOCK: 3105 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3106 if (allow) { 3107 for (i = 0; i < (ab->ab_length / 4); i++) { 3108 if (ab->ab_cb) { 3109 rv = fwohci_handler_set(psc, 3110 ab->ab_tcode, high, lo + (i * 4), 3111 fwohci_parse_input, ab); 3112 if (rv) 3113 break; 3114 } else 3115 fwohci_handler_set(psc, ab->ab_tcode, 3116 high, lo + (i * 4), NULL, NULL); 3117 } 3118 if (i != (ab->ab_length / 4)) { 3119 j = i + 1; 3120 for (i = 0; i < j; i++) 3121 fwohci_handler_set(psc, ab->ab_tcode, 3122 high, lo + (i * 4), NULL, NULL); 3123 } else 3124 ab->ab_data = (void *)1; 3125 } else { 3126 if (ab->ab_cb) 3127 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3128 lo, fwohci_parse_input, ab); 3129 else 3130 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3131 NULL, NULL); 3132 } 3133 break; 3134 default: 3135 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3136 return -1; 3137 break; 3138 } 3139 return rv; 3140 } 3141 3142 static int 3143 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3144 { 3145 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3146 u_int64_t csr; 3147 u_int32_t *cur; 3148 int i, count; 3149 3150 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3151 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3152 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3153 3154 switch (ab->ab_tcode) { 3155 case IEEE1394_TCODE_READ_REQ_QUAD: 3156 ab->ab_retlen = 4; 3157 break; 3158 case IEEE1394_TCODE_READ_REQ_BLOCK: 3159 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3160 if (ab->ab_data) { 3161 if ((csr + ab->ab_retlen) > 3162 (ab->ab_csr + ab->ab_length)) 3163 return IEEE1394_RCODE_ADDRESS_ERROR; 3164 ab->ab_data = NULL; 3165 } else 3166 if (ab->ab_retlen != ab->ab_length) 3167 return IEEE1394_RCODE_ADDRESS_ERROR; 3168 break; 3169 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3170 ab->ab_retlen = 4; 3171 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3172 if (!ab->ab_retlen) 3173 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3174 if (ab->ab_data) { 3175 if ((csr + ab->ab_retlen) > 3176 (ab->ab_csr + ab->ab_length)) 3177 return IEEE1394_RCODE_ADDRESS_ERROR; 3178 ab->ab_data = NULL; 3179 } else 3180 if (ab->ab_retlen != ab->ab_length) 3181 return IEEE1394_RCODE_ADDRESS_ERROR; 3182 3183 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3184 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3185 ab->ab_data[0] = pkt->fp_hdr[3]; 3186 else { 3187 count = 0; 3188 cur = ab->ab_data; 3189 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3190 memcpy(cur, pkt->fp_iov[i].iov_base, 3191 pkt->fp_iov[i].iov_len); 3192 cur += pkt->fp_iov[i].iov_len; 3193 count += pkt->fp_iov[i].iov_len; 3194 } 3195 if (ab->ab_retlen != count) 3196 panic("Packet claims %d length " 3197 "but only %d bytes returned\n", 3198 ab->ab_retlen, count); 3199 } 3200 break; 3201 default: 3202 panic("Got a callback for a tcode that wasn't requested: %d\n", 3203 ab->ab_tcode); 3204 break; 3205 } 3206 ab->ab_csr = csr; 3207 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3208 return -1; 3209 } 3210 3211 static int 3212 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3213 { 3214 struct ieee1394_attach_args *fwa = aux; 3215 3216 /* Both halves must be filled in for a match. */ 3217 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3218 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3219 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3220 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3221 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3222 return 0; 3223 } 3224 3225 #ifdef FW_DEBUG 3226 static void 3227 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3228 { 3229 3230 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3231 intmask); 3232 if (intmask & OHCI_Int_CycleTooLong) 3233 printf(" CycleTooLong"); 3234 if (intmask & OHCI_Int_UnrecoverableError) 3235 printf(" UnrecoverableError"); 3236 if (intmask & OHCI_Int_CycleInconsistent) 3237 printf(" CycleInconsistent"); 3238 if (intmask & OHCI_Int_BusReset) 3239 printf(" BusReset"); 3240 if (intmask & OHCI_Int_SelfIDComplete) 3241 printf(" SelfIDComplete"); 3242 if (intmask & OHCI_Int_LockRespErr) 3243 printf(" LockRespErr"); 3244 if (intmask & OHCI_Int_PostedWriteErr) 3245 printf(" PostedWriteErr"); 3246 if (intmask & OHCI_Int_ReqTxComplete) 3247 printf(" ReqTxComplete(0x%04x)", 3248 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3249 OHCI_SUBREG_ContextControlClear)); 3250 if (intmask & OHCI_Int_RespTxComplete) 3251 printf(" RespTxComplete(0x%04x)", 3252 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3253 OHCI_SUBREG_ContextControlClear)); 3254 if (intmask & OHCI_Int_ARRS) 3255 printf(" ARRS(0x%04x)", 3256 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3257 OHCI_SUBREG_ContextControlClear)); 3258 if (intmask & OHCI_Int_ARRQ) 3259 printf(" ARRQ(0x%04x)", 3260 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3261 OHCI_SUBREG_ContextControlClear)); 3262 if (intmask & OHCI_Int_IsochRx) 3263 printf(" IsochRx(0x%08x)", 3264 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3265 if (intmask & OHCI_Int_IsochTx) 3266 printf(" IsochTx(0x%08x)", 3267 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3268 if (intmask & OHCI_Int_RQPkt) 3269 printf(" RQPkt(0x%04x)", 3270 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3271 OHCI_SUBREG_ContextControlClear)); 3272 if (intmask & OHCI_Int_RSPkt) 3273 printf(" RSPkt(0x%04x)", 3274 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3275 OHCI_SUBREG_ContextControlClear)); 3276 printf("\n"); 3277 } 3278 3279 static void 3280 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3281 { 3282 u_int8_t key, phyid; 3283 3284 key = (val & 0xc0000000) >> 30; 3285 phyid = (val & 0x3f000000) >> 24; 3286 printf("%s: PHY packet from %d: ", 3287 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3288 switch (key) { 3289 case 0: 3290 printf("PHY Config:"); 3291 if (val & 0x00800000) 3292 printf(" ForceRoot"); 3293 if (val & 0x00400000) 3294 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3295 printf("\n"); 3296 break; 3297 case 1: 3298 printf("Link-on\n"); 3299 break; 3300 case 2: 3301 printf("SelfID:"); 3302 if (val & 0x00800000) { 3303 printf(" #%d", (val & 0x00700000) >> 20); 3304 } else { 3305 if (val & 0x00400000) 3306 printf(" LinkActive"); 3307 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3308 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3309 if (val & 0x00000800) 3310 printf(" Cont"); 3311 if (val & 0x00000002) 3312 printf(" InitiateBusReset"); 3313 } 3314 if (val & 0x00000001) 3315 printf(" +"); 3316 printf("\n"); 3317 break; 3318 default: 3319 printf("unknown: 0x%08x\n", val); 3320 break; 3321 } 3322 } 3323 #endif /* FW_DEBUG */ 3324
Indexes created Thu Sep 25 16:09:42 GMT 2025