fwohci.c revision 1.37
1 /* $NetBSD: fwohci.c,v 1.37 2001/07/02 02:26:40 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init_rx(struct fwohci_softc *); 100 static void fwohci_buf_start_rx(struct fwohci_softc *); 101 static void fwohci_buf_stop_tx(struct fwohci_softc *); 102 static void fwohci_buf_stop_rx(struct fwohci_softc *); 103 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 104 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 105 caddr_t *, int); 106 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 107 struct fwohci_pkt *); 108 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 109 struct fwohci_pkt *); 110 111 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 112 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 113 static void fwohci_phy_busreset(struct fwohci_softc *); 114 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 115 116 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 117 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 118 119 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 120 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 121 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 122 123 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 124 struct fwohci_pkt *); 125 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 126 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 127 struct fwohci_pkt *); 128 129 static int fwohci_guidrom_init(struct fwohci_softc *); 130 static void fwohci_configrom_init(struct fwohci_softc *); 131 static int fwohci_configrom_input(struct fwohci_softc *, void *, 132 struct fwohci_pkt *); 133 static void fwohci_selfid_init(struct fwohci_softc *); 134 static int fwohci_selfid_input(struct fwohci_softc *); 135 136 static void fwohci_csr_init(struct fwohci_softc *); 137 static int fwohci_csr_input(struct fwohci_softc *, void *, 138 struct fwohci_pkt *); 139 140 static void fwohci_uid_collect(struct fwohci_softc *); 141 static void fwohci_uid_req(struct fwohci_softc *, int); 142 static int fwohci_uid_input(struct fwohci_softc *, void *, 143 struct fwohci_pkt *); 144 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 145 static void fwohci_check_nodes(struct fwohci_softc *); 146 147 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 148 void (*)(struct device *, struct mbuf *)); 149 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 150 static int fwohci_if_output(struct device *, struct mbuf *, 151 void (*)(struct device *, struct mbuf *)); 152 static int fwohci_read(struct ieee1394_abuf *); 153 static int fwohci_write(struct ieee1394_abuf *); 154 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 155 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 156 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 157 struct fwohci_pkt *); 158 static int fwohci_inreg(struct ieee1394_abuf *, int); 159 static int fwohci_parse_input(struct fwohci_softc *, void *, 160 struct fwohci_pkt *); 161 static int fwohci_submatch(struct device *, struct cfdata *, void *); 162 163 #ifdef FW_DEBUG 164 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 165 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 166 167 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 168 169 #define DPRINTF(x) if (fwdebug) printf x 170 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 171 int fwdebug = 0; 172 #else 173 #define DPRINTF(x) 174 #define DPRINTFN(n,x) 175 #endif 176 177 int 178 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 179 { 180 int i; 181 u_int32_t val; 182 #if 0 183 int error; 184 #endif 185 186 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 187 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 188 189 /* 190 * Wait for reset completion 191 */ 192 for (i = 0; i < OHCI_LOOP; i++) { 193 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 194 if ((val & OHCI_HCControl_SoftReset) == 0) 195 break; 196 DELAY(10); 197 } 198 199 /* What dialect of OHCI is this device? 200 */ 201 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 202 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 203 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 204 205 LIST_INIT(&sc->sc_nodelist); 206 207 if (fwohci_guidrom_init(sc) != 0) { 208 printf("\n%s: fatal: no global UID ROM\n", 209 sc->sc_sc1394.sc1394_dev.dv_xname); 210 return -1; 211 } 212 213 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 214 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 215 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 216 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 217 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 218 219 /* Get the maximum link speed and receive size 220 */ 221 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 222 sc->sc_sc1394.sc1394_link_speed = 223 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 224 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 225 printf(", %s", 226 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 227 } else { 228 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 229 } 230 231 /* MaxRec is encoded as log2(max_rec_octets)-1 232 */ 233 sc->sc_sc1394.sc1394_max_receive = 234 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 235 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 236 237 /* 238 * Count how many isochronous ctx we have. 239 */ 240 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 241 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 242 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 243 for (i = 0; val != 0; val >>= 1) { 244 if (val & 0x1) 245 i++; 246 } 247 sc->sc_isoctx = i; 248 printf(", %d iso_ctx", sc->sc_isoctx); 249 250 printf("\n"); 251 252 #if 0 253 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 254 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 255 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 256 return error; 257 #endif 258 259 sc->sc_dying = 0; 260 sc->sc_nodeid = 0xffff; /* invalid */ 261 262 kthread_create(fwohci_create_event_thread, sc); 263 return 0; 264 } 265 266 int 267 fwohci_intr(void *arg) 268 { 269 struct fwohci_softc * const sc = arg; 270 int progress = 0; 271 u_int32_t intmask, iso; 272 273 for (;;) { 274 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 275 276 /* 277 * On a bus reset, everything except bus reset gets 278 * cleared. That can't get cleared until the selfid 279 * phase completes (which happens outside the 280 * interrupt routines). So if just a bus reset is left 281 * in the mask and it's already in the sc_intmask, 282 * just return. 283 */ 284 285 if ((intmask == 0) || 286 (progress && (intmask == OHCI_Int_BusReset) && 287 (sc->sc_intmask & OHCI_Int_BusReset))) { 288 if (progress) 289 wakeup(fwohci_event_thread); 290 return progress; 291 } 292 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 293 intmask & ~OHCI_Int_BusReset); 294 #ifdef FW_DEBUG 295 if (fwdebug > 1) 296 fwohci_show_intr(sc, intmask); 297 #endif 298 299 if (intmask & OHCI_Int_BusReset) { 300 /* 301 * According to OHCI spec 6.1.1 "busReset", 302 * All asynchronous transmit must be stopped before 303 * clearing BusReset. Moreover, the BusReset 304 * interrupt bit should not be cleared during the 305 * SelfID phase. Thus we turned off interrupt mask 306 * bit of BusReset instead until SelfID completion 307 * or SelfID timeout. 308 */ 309 intmask &= OHCI_Int_SelfIDComplete; 310 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 311 OHCI_Int_BusReset); 312 sc->sc_intmask = OHCI_Int_BusReset; 313 } 314 sc->sc_intmask |= intmask; 315 316 if (intmask & OHCI_Int_IsochTx) { 317 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 318 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 319 } 320 if (intmask & OHCI_Int_IsochRx) { 321 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 322 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 323 sc->sc_iso |= iso; 324 } 325 326 if (!progress) { 327 sc->sc_intrcnt.ev_count++; 328 progress = 1; 329 } 330 } 331 } 332 333 static void 334 fwohci_create_event_thread(void *arg) 335 { 336 struct fwohci_softc *sc = arg; 337 338 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 339 sc->sc_sc1394.sc1394_dev.dv_xname)) { 340 printf("%s: unable to create event thread\n", 341 sc->sc_sc1394.sc1394_dev.dv_xname); 342 panic("fwohci_create_event_thread"); 343 } 344 } 345 346 static void 347 fwohci_thread_init(void *arg) 348 { 349 struct fwohci_softc *sc = arg; 350 int i; 351 352 /* 353 * Allocate descriptors 354 */ 355 if (fwohci_desc_alloc(sc)) { 356 printf("%s: not enabling interrupts\n", 357 sc->sc_sc1394.sc1394_dev.dv_xname); 358 kthread_exit(1); 359 } 360 361 /* 362 * Enable Link Power 363 */ 364 365 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 366 367 /* 368 * Allocate DMA Context 369 */ 370 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 371 OHCI_CTX_ASYNC_RX_REQUEST); 372 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 373 OHCI_CTX_ASYNC_RX_RESPONSE); 374 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 375 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 376 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 377 M_DEVBUF, M_WAITOK); 378 for (i = 0; i < sc->sc_isoctx; i++) 379 sc->sc_ctx_ir[i] = NULL; 380 381 /* 382 * Allocate buffer for configuration ROM and SelfID buffer 383 */ 384 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 385 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 386 387 callout_init(&sc->sc_selfid_callout); 388 389 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 390 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 391 392 /* 393 * establish hooks for shutdown and suspend/resume 394 */ 395 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 396 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 397 398 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 399 fwohci_print); 400 401 /* Main loop. It's not coming back normally. */ 402 403 fwohci_event_thread(sc); 404 405 kthread_exit(0); 406 } 407 408 static void 409 fwohci_event_thread(struct fwohci_softc *sc) 410 { 411 int i, s; 412 u_int32_t intmask, iso; 413 414 s = splbio(); 415 416 /* 417 * Initialize hardware registers. 418 */ 419 420 fwohci_hw_init(sc); 421 422 /* Initial Bus Reset */ 423 fwohci_phy_busreset(sc); 424 splx(s); 425 426 while (!sc->sc_dying) { 427 s = splbio(); 428 intmask = sc->sc_intmask; 429 if (intmask == 0) { 430 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 431 splx(s); 432 continue; 433 } 434 sc->sc_intmask = 0; 435 splx(s); 436 437 if (intmask & OHCI_Int_BusReset) { 438 fwohci_buf_stop_tx(sc); 439 if (sc->sc_uidtbl != NULL) { 440 free(sc->sc_uidtbl, M_DEVBUF); 441 sc->sc_uidtbl = NULL; 442 } 443 444 callout_reset(&sc->sc_selfid_callout, 445 OHCI_SELFID_TIMEOUT, 446 (void (*)(void *))fwohci_phy_busreset, sc); 447 sc->sc_nodeid = 0xffff; /* indicate invalid */ 448 sc->sc_rootid = 0; 449 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 450 } 451 if (intmask & OHCI_Int_SelfIDComplete) { 452 s = splbio(); 453 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 454 OHCI_Int_BusReset); 455 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 456 OHCI_Int_BusReset); 457 splx(s); 458 callout_stop(&sc->sc_selfid_callout); 459 if (fwohci_selfid_input(sc) == 0) { 460 fwohci_buf_start_rx(sc); 461 fwohci_uid_collect(sc); 462 } 463 } 464 if (intmask & OHCI_Int_ReqTxComplete) 465 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 466 if (intmask & OHCI_Int_RespTxComplete) 467 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 468 if (intmask & OHCI_Int_RQPkt) 469 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 470 if (intmask & OHCI_Int_RSPkt) 471 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 472 if (intmask & OHCI_Int_IsochRx) { 473 s = splbio(); 474 iso = sc->sc_iso; 475 sc->sc_iso = 0; 476 splx(s); 477 for (i = 0; i < sc->sc_isoctx; i++) { 478 if ((iso & (1 << i)) && 479 sc->sc_ctx_ir[i] != NULL) 480 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 481 } 482 } 483 } 484 } 485 486 #if 0 487 static int 488 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 489 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 490 { 491 bus_dma_segment_t segs[1]; 492 int error, nsegs, steps; 493 494 steps = 0; 495 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 496 segs, 1, &nsegs, flags); 497 if (error) 498 goto cleanup; 499 500 steps = 1; 501 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 502 kvap, flags); 503 if (error) 504 goto cleanup; 505 506 if (error == 0) 507 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 508 size, flags, mapp); 509 if (error) 510 goto cleanup; 511 if (error == 0) 512 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 513 flags); 514 if (error) 515 goto cleanup; 516 517 cleanup: 518 switch (steps) { 519 case 1: 520 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 521 } 522 523 return error; 524 } 525 #endif 526 527 int 528 fwohci_print(void *aux, const char *pnp) 529 { 530 char *name = aux; 531 532 if (pnp) 533 printf("%s at %s", name, pnp); 534 535 return QUIET; 536 } 537 538 static void 539 fwohci_hw_init(struct fwohci_softc *sc) 540 { 541 int i; 542 u_int32_t val; 543 544 /* 545 * Software Reset. 546 */ 547 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 548 for (i = 0; i < OHCI_LOOP; i++) { 549 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 550 if ((val & OHCI_HCControl_SoftReset) == 0) 551 break; 552 DELAY(10); 553 } 554 555 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 556 557 /* 558 * First, initilize CSRs with undefined value to default settings. 559 */ 560 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 561 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 562 #if 0 563 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 564 #else 565 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 566 #endif 567 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 568 for (i = 0; i < sc->sc_isoctx; i++) { 569 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 570 ~0); 571 } 572 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 573 574 fwohci_configrom_init(sc); 575 fwohci_selfid_init(sc); 576 fwohci_buf_init_rx(sc); 577 fwohci_csr_init(sc); 578 579 /* 580 * Final CSR settings. 581 */ 582 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 583 OHCI_LinkControl_CycleTimerEnable | 584 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 585 586 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 587 588 /* clear receive filter */ 589 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 590 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 591 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 592 593 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 594 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 595 #if BYTE_ORDER == BIG_ENDIAN 596 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 597 OHCI_HCControl_NoByteSwapData); 598 #endif 599 600 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 601 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 602 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 603 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 604 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 605 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 606 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 607 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 608 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 609 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 610 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 611 612 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 613 614 /* 615 * Start the receivers 616 */ 617 fwohci_buf_start_rx(sc); 618 } 619 620 static void 621 fwohci_power(int why, void *arg) 622 { 623 struct fwohci_softc *sc = arg; 624 int s; 625 626 s = splbio(); 627 switch (why) { 628 case PWR_SUSPEND: 629 case PWR_STANDBY: 630 fwohci_shutdown(sc); 631 break; 632 case PWR_RESUME: 633 fwohci_hw_init(sc); 634 fwohci_phy_busreset(sc); 635 break; 636 case PWR_SOFTSUSPEND: 637 case PWR_SOFTSTANDBY: 638 case PWR_SOFTRESUME: 639 break; 640 } 641 splx(s); 642 } 643 644 static void 645 fwohci_shutdown(void *arg) 646 { 647 struct fwohci_softc *sc = arg; 648 u_int32_t val; 649 650 callout_stop(&sc->sc_selfid_callout); 651 /* disable all interrupt */ 652 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 653 fwohci_buf_stop_tx(sc); 654 fwohci_buf_stop_rx(sc); 655 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 656 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 657 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 658 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 659 fwohci_phy_busreset(sc); 660 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 661 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 662 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 663 } 664 665 /* 666 * COMMON FUNCTIONS 667 */ 668 669 /* 670 * read the PHY Register. 671 */ 672 static u_int8_t 673 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 674 { 675 int i; 676 u_int32_t val; 677 678 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 679 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 680 for (i = 0; i < OHCI_LOOP; i++) { 681 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 682 OHCI_PhyControl_RdDone) 683 break; 684 DELAY(10); 685 } 686 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 687 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 688 } 689 690 /* 691 * write the PHY Register. 692 */ 693 static void 694 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 695 { 696 int i; 697 698 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 699 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 700 (val << OHCI_PhyControl_WrData_BITPOS)); 701 for (i = 0; i < OHCI_LOOP; i++) { 702 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 703 OHCI_PhyControl_WrReg)) 704 break; 705 DELAY(10); 706 } 707 } 708 709 /* 710 * Initiate Bus Reset 711 */ 712 static void 713 fwohci_phy_busreset(struct fwohci_softc *sc) 714 { 715 int s; 716 u_int8_t val; 717 718 s = splbio(); 719 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 720 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 721 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 722 callout_stop(&sc->sc_selfid_callout); 723 val = fwohci_phy_read(sc, 1); 724 val = (val & 0x80) | /* preserve RHB (force root) */ 725 0x40 | /* Initiate Bus Reset */ 726 0x3f; /* default GAP count */ 727 fwohci_phy_write(sc, 1, val); 728 splx(s); 729 } 730 731 /* 732 * PHY Packet 733 */ 734 static void 735 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 736 { 737 u_int32_t val; 738 739 val = pkt->fp_hdr[1]; 740 if (val != ~pkt->fp_hdr[2]) { 741 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 742 OHCI_CTXCTL_EVENT_BUS_RESET) { 743 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 744 pkt->fp_hdr[2])); 745 } else { 746 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 747 sc->sc_sc1394.sc1394_dev.dv_xname, val, 748 pkt->fp_hdr[2]); 749 } 750 return; 751 } 752 #ifdef FW_DEBUG 753 if (fwdebug > 1) 754 fwohci_show_phypkt(sc, val); 755 #endif 756 } 757 758 /* 759 * Descriptor for context DMA. 760 */ 761 static int 762 fwohci_desc_alloc(struct fwohci_softc *sc) 763 { 764 int error, mapsize, dsize; 765 766 /* 767 * allocate descriptor buffer 768 */ 769 770 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 771 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 772 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 773 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 774 mapsize = howmany(sc->sc_descsize, NBBY); 775 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 776 memset(sc->sc_descmap, 0, mapsize); 777 778 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 779 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 780 printf("%s: unable to allocate descriptor buffer, error = %d\n", 781 sc->sc_sc1394.sc1394_dev.dv_xname, error); 782 goto fail_0; 783 } 784 785 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 786 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 787 != 0) { 788 printf("%s: unable to map descriptor buffer, error = %d\n", 789 sc->sc_sc1394.sc1394_dev.dv_xname, error); 790 goto fail_1; 791 } 792 793 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 794 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 795 printf("%s: unable to create descriptor buffer DMA map, " 796 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 797 goto fail_2; 798 } 799 800 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 801 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 802 printf("%s: unable to load descriptor buffer DMA map, " 803 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 804 goto fail_3; 805 } 806 807 return 0; 808 809 fail_3: 810 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 811 fail_2: 812 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 815 fail_0: 816 return error; 817 } 818 819 static struct fwohci_desc * 820 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 821 { 822 int i, n; 823 824 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 825 for (i = 0; ; i++) { 826 if (i == ndesc) { 827 for (i = 0; i < ndesc; i++) 828 setbit(sc->sc_descmap, n + i); 829 return sc->sc_desc + n; 830 } 831 if (isset(sc->sc_descmap, n + i)) 832 break; 833 } 834 } 835 return NULL; 836 } 837 838 static void 839 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 840 { 841 int i, n; 842 843 n = fd - sc->sc_desc; 844 for (i = 0; i < ndesc; i++, n++) { 845 #ifdef DIAGNOSTIC 846 if (isclr(sc->sc_descmap, n)) 847 panic("fwohci_desc_put: duplicated free"); 848 #endif 849 clrbit(sc->sc_descmap, n); 850 } 851 } 852 853 /* 854 * Asyncronous/Isochronous Transmit/Receive Context 855 */ 856 static int 857 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 858 int bufcnt, int ctx) 859 { 860 int i, error; 861 struct fwohci_ctx *fc; 862 struct fwohci_buf *fb; 863 struct fwohci_desc *fd; 864 865 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 866 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 867 LIST_INIT(&fc->fc_handler); 868 TAILQ_INIT(&fc->fc_buf); 869 fc->fc_ctx = ctx; 870 fc->fc_bufcnt = bufcnt; 871 fb = (struct fwohci_buf *)&fc[1]; 872 for (i = 0; i < bufcnt; i++, fb++) { 873 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 874 goto fail; 875 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 876 error = ENOBUFS; 877 goto fail; 878 } 879 fb->fb_desc = fd; 880 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 881 ((caddr_t)fd - (caddr_t)sc->sc_desc); 882 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 883 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 884 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 885 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 886 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 887 } 888 *fcp = fc; 889 return 0; 890 891 fail: 892 while (i-- > 0) 893 fwohci_buf_free(sc, --fb); 894 free(fc, M_DEVBUF); 895 return error; 896 } 897 898 static void 899 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 900 { 901 struct fwohci_buf *fb; 902 struct fwohci_handler *fh; 903 904 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 905 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 906 NULL, NULL); 907 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 908 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 909 fwohci_buf_free(sc, fb); 910 } 911 free(fc, M_DEVBUF); 912 } 913 914 static void 915 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 916 { 917 struct fwohci_buf *fb, *nfb; 918 struct fwohci_desc *fd; 919 struct fwohci_handler *fh; 920 int n; 921 922 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 923 nfb = TAILQ_NEXT(fb, fb_list); 924 fb->fb_off = 0; 925 fd = fb->fb_desc; 926 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 927 fd->fd_rescount = fd->fd_reqcount; 928 } 929 930 n = fc->fc_ctx; 931 fb = TAILQ_FIRST(&fc->fc_buf); 932 if (fc->fc_isoch) { 933 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 934 fb->fb_daddr | 1); 935 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 936 OHCI_CTXCTL_RX_BUFFER_FILL | 937 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 938 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 939 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 940 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 941 OHCI_CTXCTL_RX_ISOCH_HEADER); 942 fh = LIST_FIRST(&fc->fc_handler); 943 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 944 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 945 } else { 946 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 947 fb->fb_daddr | 1); 948 } 949 } 950 951 /* 952 * DMA data buffer 953 */ 954 static int 955 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 956 { 957 int error; 958 959 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 960 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 961 printf("%s: unable to allocate buffer, error = %d\n", 962 sc->sc_sc1394.sc1394_dev.dv_xname, error); 963 goto fail_0; 964 } 965 966 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 967 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 968 printf("%s: unable to map buffer, error = %d\n", 969 sc->sc_sc1394.sc1394_dev.dv_xname, error); 970 goto fail_1; 971 } 972 973 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 974 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 975 printf("%s: unable to create buffer DMA map, " 976 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 977 error); 978 goto fail_2; 979 } 980 981 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 982 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 983 printf("%s: unable to load buffer DMA map, " 984 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 985 error); 986 goto fail_3; 987 } 988 989 return 0; 990 991 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 992 fail_3: 993 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 994 fail_2: 995 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 996 fail_1: 997 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 998 fail_0: 999 return error; 1000 } 1001 1002 static void 1003 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1004 { 1005 1006 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1007 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1008 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1009 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1010 } 1011 1012 static void 1013 fwohci_buf_init_rx(struct fwohci_softc *sc) 1014 { 1015 int i; 1016 1017 /* 1018 * Initialize for Asynchronous Receive Queue. 1019 */ 1020 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1021 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1022 1023 /* 1024 * Initialize for Isochronous Receive Queue. 1025 */ 1026 for (i = 0; i < sc->sc_isoctx; i++) { 1027 if (sc->sc_ctx_ir[i] != NULL) 1028 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1029 } 1030 } 1031 1032 static void 1033 fwohci_buf_start_rx(struct fwohci_softc *sc) 1034 { 1035 int i; 1036 1037 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1038 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1039 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1040 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1041 for (i = 0; i < sc->sc_isoctx; i++) { 1042 if (sc->sc_ctx_ir[i] != NULL) 1043 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1044 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1045 } 1046 } 1047 1048 static void 1049 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1050 { 1051 int i; 1052 1053 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1054 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1055 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1056 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1057 1058 /* 1059 * Make sure the transmitter is stopped. 1060 */ 1061 for (i = 0; i < OHCI_LOOP; i++) { 1062 DELAY(10); 1063 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1064 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1065 continue; 1066 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1067 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1068 continue; 1069 break; 1070 } 1071 1072 /* 1073 * Initialize for Asynchronous Transmit Queue. 1074 */ 1075 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1076 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1077 } 1078 1079 static void 1080 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1081 { 1082 int i; 1083 1084 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1085 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1086 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1087 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1088 for (i = 0; i < sc->sc_isoctx; i++) { 1089 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1090 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1091 } 1092 } 1093 1094 static void 1095 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1096 { 1097 struct fwohci_buf *fb, *tfb; 1098 1099 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1100 if (fc->fc_isoch) { 1101 if (fb->fb_off == 0) 1102 break; 1103 } else { 1104 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1105 fb->fb_desc->fd_rescount != 0) 1106 break; 1107 } 1108 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1109 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1110 fb->fb_off = 0; 1111 fb->fb_desc->fd_branch = 0; 1112 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1113 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1114 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1115 } 1116 } 1117 1118 static int 1119 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1120 int len) 1121 { 1122 struct fwohci_buf *fb; 1123 struct fwohci_desc *fd; 1124 int bufend; 1125 1126 fb = TAILQ_FIRST(&fc->fc_buf); 1127 again: 1128 fd = fb->fb_desc; 1129 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1130 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1131 fd->fd_reqcount, fd->fd_rescount, len, 1132 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1133 bufend = fd->fd_reqcount - fd->fd_rescount; 1134 if (fb->fb_off >= bufend) { 1135 if (fd->fd_rescount == 0) { 1136 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1137 goto again; 1138 } 1139 return 0; 1140 } 1141 if (fb->fb_off + len > bufend) 1142 len = bufend - fb->fb_off; 1143 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1144 BUS_DMASYNC_POSTREAD); 1145 *pp = fb->fb_buf + fb->fb_off; 1146 fb->fb_off += roundup(len, 4); 1147 return len; 1148 } 1149 1150 static int 1151 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1152 struct fwohci_pkt *pkt) 1153 { 1154 caddr_t p; 1155 int len, count, i; 1156 1157 memset(pkt, 0, sizeof(*pkt)); 1158 pkt->fp_uio.uio_iov = pkt->fp_iov; 1159 pkt->fp_uio.uio_rw = UIO_WRITE; 1160 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1161 1162 /* get first quadlet */ 1163 count = 4; 1164 len = fwohci_buf_pktget(sc, fc, &p, count); 1165 if (len <= 0) { 1166 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1167 fc->fc_ctx)); 1168 return 0; 1169 } 1170 pkt->fp_hdr[0] = *(u_int32_t *)p; 1171 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1172 switch (pkt->fp_tcode) { 1173 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1174 case IEEE1394_TCODE_READ_RESP_QUAD: 1175 pkt->fp_hlen = 12; 1176 pkt->fp_dlen = 4; 1177 break; 1178 case IEEE1394_TCODE_READ_REQ_BLOCK: 1179 pkt->fp_hlen = 16; 1180 pkt->fp_dlen = 0; 1181 break; 1182 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1183 case IEEE1394_TCODE_READ_RESP_BLOCK: 1184 case IEEE1394_TCODE_LOCK_REQ: 1185 case IEEE1394_TCODE_LOCK_RESP: 1186 pkt->fp_hlen = 16; 1187 break; 1188 #ifdef DIAGNOSTICS 1189 case IEEE1394_TCODE_STREAM_DATA: 1190 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1191 return 0; 1192 #endif 1193 default: 1194 pkt->fp_hlen = 12; 1195 pkt->fp_dlen = 0; 1196 break; 1197 } 1198 1199 /* get header */ 1200 while (count < pkt->fp_hlen) { 1201 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1202 if (len == 0) { 1203 printf("fwohci_buf_input: malformed input 1: %d\n", 1204 pkt->fp_hlen - count); 1205 return 0; 1206 } 1207 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1208 count += len; 1209 } 1210 if (pkt->fp_hlen == 16 && 1211 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1212 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1213 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1214 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1215 1216 /* get data */ 1217 count = 0; 1218 i = 0; 1219 while (count < pkt->fp_dlen) { 1220 len = fwohci_buf_pktget(sc, fc, 1221 (caddr_t *)&pkt->fp_iov[i].iov_base, 1222 pkt->fp_dlen - count); 1223 if (len == 0) { 1224 printf("fwohci_buf_input: malformed input 2: %d\n", 1225 pkt->fp_dlen - count); 1226 return 0; 1227 } 1228 pkt->fp_iov[i++].iov_len = len; 1229 count += len; 1230 } 1231 pkt->fp_uio.uio_iovcnt = i; 1232 pkt->fp_uio.uio_resid = count; 1233 1234 /* get trailer */ 1235 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1236 sizeof(*pkt->fp_trail)); 1237 if (len <= 0) { 1238 printf("fwohci_buf_input: malformed input 3: %d\n", 1239 pkt->fp_hlen - count); 1240 return 0; 1241 } 1242 return 1; 1243 } 1244 1245 static int 1246 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1247 struct fwohci_pkt *pkt) 1248 { 1249 caddr_t p; 1250 int len; 1251 struct fwohci_buf *fb; 1252 struct fwohci_desc *fd; 1253 1254 memset(pkt, 0, sizeof(*pkt)); 1255 pkt->fp_uio.uio_iov = pkt->fp_iov; 1256 pkt->fp_uio.uio_rw = UIO_WRITE; 1257 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1258 1259 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1260 if (fb == NULL) 1261 return 0; 1262 if (fb->fb_off == 0) 1263 break; 1264 } 1265 fd = fb->fb_desc; 1266 len = fd->fd_reqcount - fd->fd_rescount; 1267 if (len == 0) 1268 return 0; 1269 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1270 BUS_DMASYNC_POSTREAD); 1271 1272 p = fb->fb_buf; 1273 fb->fb_off += roundup(len, 4); 1274 if (len < 8) { 1275 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1276 return 0; 1277 } 1278 1279 /* 1280 * get trailer first, may be bogus data unless status update 1281 * in descriptor is set. 1282 */ 1283 pkt->fp_trail = (u_int32_t *)p; 1284 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1285 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1286 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1287 #ifdef DIAGNOSTICS 1288 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1289 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1290 pkt->fp_tcode); 1291 return 0; 1292 } 1293 #endif 1294 pkt->fp_hlen = 4; 1295 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1296 p += 8; 1297 len -= 8; 1298 if (pkt->fp_dlen != len) { 1299 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1300 pkt->fp_dlen, len); 1301 return 0; 1302 } 1303 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1304 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1305 pkt->fp_iov[0].iov_base = p; 1306 pkt->fp_iov[0].iov_len = len; 1307 pkt->fp_uio.uio_iovcnt = 0; 1308 pkt->fp_uio.uio_resid = len; 1309 return 1; 1310 } 1311 1312 static int 1313 fwohci_handler_set(struct fwohci_softc *sc, 1314 int tcode, u_int32_t key1, u_int32_t key2, 1315 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1316 void *arg) 1317 { 1318 struct fwohci_ctx *fc; 1319 struct fwohci_handler *fh; 1320 int i, j; 1321 1322 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1323 j = sc->sc_isoctx; 1324 fh = NULL; 1325 for (i = 0; i < sc->sc_isoctx; i++) { 1326 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1327 if (j == sc->sc_isoctx) 1328 j = i; 1329 continue; 1330 } 1331 fh = LIST_FIRST(&fc->fc_handler); 1332 if (fh->fh_tcode == tcode && 1333 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1334 break; 1335 fh = NULL; 1336 } 1337 if (fh == NULL) { 1338 if (handler == NULL) 1339 return 0; 1340 if (j == sc->sc_isoctx) { 1341 DPRINTF(("fwohci_handler_set: no more free " 1342 "context\n")); 1343 return ENOMEM; 1344 } 1345 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1346 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1347 fc->fc_isoch = 1; 1348 sc->sc_ctx_ir[j] = fc; 1349 } 1350 } 1351 } else { 1352 switch (tcode) { 1353 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1354 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1355 case IEEE1394_TCODE_READ_REQ_QUAD: 1356 case IEEE1394_TCODE_READ_REQ_BLOCK: 1357 case IEEE1394_TCODE_LOCK_REQ: 1358 fc = sc->sc_ctx_arrq; 1359 break; 1360 case IEEE1394_TCODE_WRITE_RESP: 1361 case IEEE1394_TCODE_READ_RESP_QUAD: 1362 case IEEE1394_TCODE_READ_RESP_BLOCK: 1363 case IEEE1394_TCODE_LOCK_RESP: 1364 fc = sc->sc_ctx_arrs; 1365 break; 1366 default: 1367 return EIO; 1368 } 1369 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1370 fh = LIST_NEXT(fh, fh_list)) { 1371 if (fh->fh_tcode == tcode && 1372 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1373 break; 1374 } 1375 } 1376 if (handler == NULL) { 1377 if (fh != NULL) { 1378 LIST_REMOVE(fh, fh_list); 1379 free(fh, M_DEVBUF); 1380 } 1381 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1382 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1383 fwohci_ctx_free(sc, fc); 1384 } 1385 return 0; 1386 } 1387 if (fh == NULL) { 1388 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1389 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1390 } 1391 fh->fh_tcode = tcode; 1392 fh->fh_key1 = key1; 1393 fh->fh_key2 = key2; 1394 fh->fh_handler = handler; 1395 fh->fh_handarg = arg; 1396 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1397 fc->fc_ctx, tcode, key1, key2)); 1398 1399 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1400 fwohci_ctx_init(sc, fc); 1401 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1402 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1403 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1404 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1405 } 1406 return 0; 1407 } 1408 1409 /* 1410 * Asyncronous Receive Requests input frontend. 1411 */ 1412 static void 1413 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1414 { 1415 int rcode; 1416 u_int32_t key1, key2; 1417 struct fwohci_handler *fh; 1418 struct fwohci_pkt pkt, res; 1419 1420 /* 1421 * Do not return if next packet is in the buffer, or the next 1422 * packet cannot be received until the next receive interrupt. 1423 */ 1424 while (fwohci_buf_input(sc, fc, &pkt)) { 1425 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1426 fwohci_phy_input(sc, &pkt); 1427 continue; 1428 } 1429 key1 = pkt.fp_hdr[1] & 0xffff; 1430 key2 = pkt.fp_hdr[2]; 1431 memset(&res, 0, sizeof(res)); 1432 res.fp_uio.uio_rw = UIO_WRITE; 1433 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1434 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1435 fh = LIST_NEXT(fh, fh_list)) { 1436 if (pkt.fp_tcode == fh->fh_tcode && 1437 key1 == fh->fh_key1 && 1438 key2 == fh->fh_key2) { 1439 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1440 &pkt); 1441 break; 1442 } 1443 } 1444 if (fh == NULL) { 1445 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1446 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1447 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1448 key2)); 1449 } 1450 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1451 OHCI_CTXCTL_EVENT_ACK_PENDING) 1452 continue; 1453 if (rcode != -1) 1454 fwohci_atrs_output(sc, rcode, &pkt, &res); 1455 } 1456 fwohci_buf_next(sc, fc); 1457 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1458 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1459 } 1460 1461 1462 /* 1463 * Asynchronous Receive Response input frontend. 1464 */ 1465 static void 1466 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1467 { 1468 struct fwohci_pkt pkt; 1469 struct fwohci_handler *fh; 1470 u_int16_t srcid; 1471 int rcode, tlabel; 1472 1473 while (fwohci_buf_input(sc, fc, &pkt)) { 1474 srcid = pkt.fp_hdr[1] >> 16; 1475 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1476 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1477 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1478 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1479 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1480 pkt.fp_dlen)); 1481 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1482 fh = LIST_NEXT(fh, fh_list)) { 1483 if (pkt.fp_tcode == fh->fh_tcode && 1484 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1485 tlabel == fh->fh_key2) { 1486 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1487 LIST_REMOVE(fh, fh_list); 1488 free(fh, M_DEVBUF); 1489 break; 1490 } 1491 } 1492 if (fh == NULL) 1493 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1494 } 1495 fwohci_buf_next(sc, fc); 1496 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1497 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1498 } 1499 1500 /* 1501 * Isochronous Receive input frontend. 1502 */ 1503 static void 1504 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1505 { 1506 int rcode, chan, tag; 1507 struct iovec *iov; 1508 struct fwohci_handler *fh; 1509 struct fwohci_pkt pkt; 1510 1511 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 1512 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1513 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1514 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1515 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1516 pkt.fp_dlen)); 1517 if (tag == IEEE1394_TAG_GASP) { 1518 /* 1519 * The pkt with tag=3 is GASP format. 1520 * Move GASP header to header part. 1521 */ 1522 if (pkt.fp_dlen < 8) 1523 continue; 1524 iov = pkt.fp_iov; 1525 /* assuming pkt per buffer mode */ 1526 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1527 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1528 iov->iov_base = (caddr_t)iov->iov_base + 8; 1529 iov->iov_len -= 8; 1530 pkt.fp_hlen += 8; 1531 pkt.fp_dlen -= 8; 1532 } 1533 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1534 fh = LIST_NEXT(fh, fh_list)) { 1535 if (pkt.fp_tcode == fh->fh_tcode && 1536 chan == fh->fh_key1 && tag == fh->fh_key2) { 1537 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1538 &pkt); 1539 break; 1540 } 1541 } 1542 #ifdef FW_DEBUG 1543 if (fh == NULL) { 1544 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1545 } else { 1546 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1547 } 1548 #endif 1549 } 1550 fwohci_buf_next(sc, fc); 1551 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1552 OHCI_CTXCTL_WAKE); 1553 } 1554 1555 /* 1556 * Asynchronous Transmit common routine. 1557 */ 1558 static int 1559 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1560 struct fwohci_pkt *pkt) 1561 { 1562 struct fwohci_buf *fb; 1563 struct fwohci_desc *fd; 1564 struct mbuf *m, *m0; 1565 int i, ndesc, error, off, len; 1566 u_int32_t val; 1567 #ifdef FW_DEBUG 1568 struct iovec *iov; 1569 #endif 1570 1571 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 1572 /* We can't send anything during selfid duration */ 1573 return EAGAIN; 1574 1575 #ifdef FW_DEBUG 1576 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1577 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1578 for (i = 0; i < pkt->fp_hlen/4; i++) 1579 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 1580 DPRINTFN(2, ("$")); 1581 for (ndesc = 0, iov = pkt->fp_iov; 1582 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1583 for (i = 0; i < iov->iov_len; i++) 1584 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 1585 ((u_int8_t *)iov->iov_base)[i])); 1586 DPRINTFN(2, ("$")); 1587 } 1588 DPRINTFN(1, ("\n")); 1589 #endif 1590 1591 if ((m = pkt->fp_m) != NULL) { 1592 for (ndesc = 2; m != NULL; m = m->m_next) 1593 ndesc++; 1594 if (ndesc > OHCI_DESC_MAX) { 1595 m0 = NULL; 1596 ndesc = 2; 1597 for (off = 0; off < pkt->fp_dlen; off += len) { 1598 if (m0 == NULL) { 1599 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1600 if (m0 != NULL) 1601 M_COPY_PKTHDR(m0, pkt->fp_m); 1602 m = m0; 1603 } else { 1604 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1605 m = m->m_next; 1606 } 1607 if (m != NULL) 1608 MCLGET(m, M_DONTWAIT); 1609 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1610 m_freem(m0); 1611 return ENOMEM; 1612 } 1613 len = pkt->fp_dlen - off; 1614 if (len > m->m_ext.ext_size) 1615 len = m->m_ext.ext_size; 1616 m_copydata(pkt->fp_m, off, len, 1617 mtod(m, caddr_t)); 1618 m->m_len = len; 1619 ndesc++; 1620 } 1621 m_freem(pkt->fp_m); 1622 pkt->fp_m = m0; 1623 } 1624 } else 1625 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1626 1627 if (ndesc > OHCI_DESC_MAX) 1628 return ENOBUFS; 1629 1630 if (fc->fc_bufcnt > 50) /*XXX*/ 1631 return ENOBUFS; 1632 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1633 fb->fb_nseg = ndesc; 1634 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1635 if (fb->fb_desc == NULL) { 1636 free(fb, M_DEVBUF); 1637 return ENOBUFS; 1638 } 1639 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1640 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1641 fb->fb_m = pkt->fp_m; 1642 fb->fb_callback = pkt->fp_callback; 1643 fb->fb_statuscb = pkt->fp_statuscb; 1644 fb->fb_statusarg = pkt->fp_statusarg; 1645 1646 if (ndesc > 2) { 1647 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1648 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1649 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1650 free(fb, M_DEVBUF); 1651 return error; 1652 } 1653 1654 if (pkt->fp_m != NULL) 1655 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1656 pkt->fp_m, BUS_DMA_WAITOK); 1657 else 1658 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1659 &pkt->fp_uio, BUS_DMA_WAITOK); 1660 if (error != 0) { 1661 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1662 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1663 free(fb, M_DEVBUF); 1664 return error; 1665 } 1666 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1667 BUS_DMASYNC_PREWRITE); 1668 } 1669 1670 fd = fb->fb_desc; 1671 fd->fd_flags = OHCI_DESC_IMMED; 1672 fd->fd_reqcount = pkt->fp_hlen; 1673 fd->fd_data = 0; 1674 fd->fd_branch = 0; 1675 fd->fd_status = 0; 1676 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1677 i = 3; /* XXX: 3 sec */ 1678 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1679 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1680 ((((val >> 25) + i) & 0x7) << 13); 1681 } else 1682 fd->fd_timestamp = 0; 1683 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1684 for (i = 0; i < ndesc - 2; i++) { 1685 fd = fb->fb_desc + 2 + i; 1686 fd->fd_flags = 0; 1687 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1688 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1689 fd->fd_branch = 0; 1690 fd->fd_status = 0; 1691 fd->fd_timestamp = 0; 1692 } 1693 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1694 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1695 1696 #ifdef FW_DEBUG 1697 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1698 (long)(fb->fb_desc - sc->sc_desc))); 1699 for (i = 0; i < ndesc * 4; i++) 1700 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1701 ((u_int32_t *)fb->fb_desc)[i])); 1702 DPRINTFN(1, ("\n")); 1703 #endif 1704 1705 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1706 OHCI_SUBREG_ContextControlClear); 1707 1708 if (val & OHCI_CTXCTL_RUN) { 1709 if (fc->fc_branch == NULL) { 1710 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1711 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1712 goto run; 1713 } 1714 *fc->fc_branch = fb->fb_daddr | ndesc; 1715 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1716 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1717 } else { 1718 run: 1719 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1720 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1721 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1722 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1723 } 1724 fc->fc_branch = &fd->fd_branch; 1725 1726 fc->fc_bufcnt++; 1727 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1728 pkt->fp_m = NULL; 1729 return 0; 1730 } 1731 1732 static void 1733 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1734 { 1735 struct fwohci_buf *fb; 1736 struct fwohci_desc *fd; 1737 struct fwohci_pkt pkt; 1738 int i; 1739 1740 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1741 fd = fb->fb_desc; 1742 #ifdef FW_DEBUG 1743 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1744 force ? "force " : "", (long)(fd - sc->sc_desc), 1745 fb->fb_nseg)); 1746 for (i = 0; i < fb->fb_nseg * 4; i++) 1747 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1748 ((u_int32_t *)fd)[i])); 1749 DPRINTFN(1, ("\n")); 1750 #endif 1751 if (fb->fb_nseg > 2) 1752 fd += fb->fb_nseg - 1; 1753 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1754 break; 1755 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1756 if (fc->fc_branch == &fd->fd_branch) { 1757 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1758 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1759 fc->fc_branch = NULL; 1760 for (i = 0; i < OHCI_LOOP; i++) { 1761 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1762 OHCI_SUBREG_ContextControlClear) & 1763 OHCI_CTXCTL_ACTIVE)) 1764 break; 1765 DELAY(10); 1766 } 1767 } 1768 1769 if (fb->fb_statuscb) { 1770 memset(&pkt, 0, sizeof(pkt)); 1771 pkt.fp_status = fd->fd_status; 1772 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1773 1774 /* Indicate this is just returning the status bits. */ 1775 pkt.fp_tcode = -1; 1776 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1777 fb->fb_statuscb = NULL; 1778 fb->fb_statusarg = NULL; 1779 } 1780 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1781 if (fb->fb_nseg > 2) 1782 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1783 fc->fc_bufcnt--; 1784 if (fb->fb_callback) { 1785 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1786 fb->fb_callback = NULL; 1787 } else if (fb->fb_m != NULL) 1788 m_freem(fb->fb_m); 1789 free(fb, M_DEVBUF); 1790 } 1791 } 1792 1793 /* 1794 * Asynchronous Transmit Reponse -- in response of request packet. 1795 */ 1796 static void 1797 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1798 struct fwohci_pkt *res) 1799 { 1800 1801 if (((*req->fp_trail & 0x001f0000) >> 16) != 1802 OHCI_CTXCTL_EVENT_ACK_PENDING) 1803 return; 1804 1805 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1806 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1807 switch (req->fp_tcode) { 1808 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1809 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1810 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1811 res->fp_hlen = 12; 1812 break; 1813 case IEEE1394_TCODE_READ_REQ_QUAD: 1814 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1815 res->fp_hlen = 16; 1816 res->fp_dlen = 0; 1817 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1818 res->fp_hdr[3] = 1819 *(u_int32_t *)res->fp_iov[0].iov_base; 1820 res->fp_uio.uio_iovcnt = 0; 1821 break; 1822 case IEEE1394_TCODE_READ_REQ_BLOCK: 1823 case IEEE1394_TCODE_LOCK_REQ: 1824 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1825 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1826 else 1827 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1828 res->fp_hlen = 16; 1829 res->fp_dlen = res->fp_uio.uio_resid; 1830 res->fp_hdr[3] = res->fp_dlen << 16; 1831 break; 1832 } 1833 res->fp_hdr[0] |= (res->fp_tcode << 4); 1834 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1835 } 1836 1837 /* 1838 * APPLICATION LAYER SERVICES 1839 */ 1840 1841 /* 1842 * Retrieve Global UID from GUID ROM 1843 */ 1844 static int 1845 fwohci_guidrom_init(struct fwohci_softc *sc) 1846 { 1847 int i, n, off; 1848 u_int32_t val1, val2; 1849 1850 /* Extract the Global UID 1851 */ 1852 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1853 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1854 1855 if (val1 != 0 || val2 != 0) { 1856 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1857 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1858 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1859 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1860 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1861 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1862 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1863 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1864 } else { 1865 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1866 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1867 return -1; 1868 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1869 for (i = 0; i < OHCI_LOOP; i++) { 1870 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1871 if (!(val1 & OHCI_Guid_AddrReset)) 1872 break; 1873 DELAY(10); 1874 } 1875 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1876 val2 = 0; 1877 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1878 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1879 OHCI_Guid_RdStart); 1880 for (i = 0; i < OHCI_LOOP; i++) { 1881 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1882 if (!(val1 & OHCI_Guid_RdStart)) 1883 break; 1884 DELAY(10); 1885 } 1886 if (n < off) 1887 continue; 1888 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1889 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1890 val2 |= val1; 1891 } 1892 if (val2 == 0) 1893 return -1; 1894 } 1895 return 0; 1896 } 1897 1898 /* 1899 * Initialization for Configuration ROM (no DMA context) 1900 */ 1901 1902 #define CFR_MAXUNIT 20 1903 1904 struct configromctx { 1905 u_int32_t *ptr; 1906 int curunit; 1907 struct { 1908 u_int32_t *start; 1909 int length; 1910 u_int32_t *refer; 1911 int refunit; 1912 } unit[CFR_MAXUNIT]; 1913 }; 1914 1915 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1916 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1917 1918 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1919 1920 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1921 1922 #define CFR_PUT_CRC(cfr, n) \ 1923 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1924 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1925 1926 #define CFR_START_UNIT(cfr, n) \ 1927 do { \ 1928 if ((cfr)->unit[n].refer != NULL) { \ 1929 *(cfr)->unit[n].refer |= \ 1930 (cfr)->ptr - (cfr)->unit[n].refer; \ 1931 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1932 } \ 1933 (cfr)->curunit = (n); \ 1934 (cfr)->unit[n].start = (cfr)->ptr++; \ 1935 } while (0 /* CONSTCOND */) 1936 1937 #define CFR_PUT_REFER(cfr, key, n) \ 1938 do { \ 1939 (cfr)->unit[n].refer = (cfr)->ptr; \ 1940 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1941 *(cfr)->ptr++ = (key) << 24; \ 1942 } while (0 /* CONSTCOND */) 1943 1944 #define CFR_END_UNIT(cfr) \ 1945 do { \ 1946 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1947 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1948 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1949 } while (0 /* CONSTCOND */) 1950 1951 static u_int16_t 1952 fwohci_crc16(u_int32_t *ptr, int len) 1953 { 1954 int shift; 1955 u_int32_t crc, sum, data; 1956 1957 crc = 0; 1958 while (len-- > 0) { 1959 data = *ptr++; 1960 for (shift = 28; shift >= 0; shift -= 4) { 1961 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1962 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1963 } 1964 crc &= 0xffff; 1965 } 1966 return crc; 1967 } 1968 1969 static void 1970 fwohci_configrom_init(struct fwohci_softc *sc) 1971 { 1972 int i, val; 1973 struct fwohci_buf *fb; 1974 u_int32_t *hdr; 1975 struct configromctx cfr; 1976 1977 fb = &sc->sc_buf_cnfrom; 1978 memset(&cfr, 0, sizeof(cfr)); 1979 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1980 1981 /* headers */ 1982 CFR_START_UNIT(&cfr, 0); 1983 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1984 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1985 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1986 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1987 CFR_END_UNIT(&cfr); 1988 /* copy info_length from crc_length */ 1989 *hdr |= (*hdr & 0x00ff0000) << 8; 1990 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1991 1992 /* root directory */ 1993 CFR_START_UNIT(&cfr, 1); 1994 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1995 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1996 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1997 /* spt,64,fix,lst,drq */ 1998 #ifdef INET 1999 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2000 #endif /* INET */ 2001 #ifdef INET6 2002 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2003 #endif /* INET6 */ 2004 CFR_END_UNIT(&cfr); 2005 2006 CFR_START_UNIT(&cfr, 2); 2007 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2008 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2009 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2010 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2011 CFR_END_UNIT(&cfr); 2012 2013 #ifdef INET 2014 /* IPv4 unit directory */ 2015 CFR_START_UNIT(&cfr, 3); 2016 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2017 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2018 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2019 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2020 CFR_END_UNIT(&cfr); 2021 2022 CFR_START_UNIT(&cfr, 6); 2023 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2024 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2025 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2026 CFR_END_UNIT(&cfr); 2027 2028 CFR_START_UNIT(&cfr, 7); 2029 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2030 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2031 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2032 CFR_END_UNIT(&cfr); 2033 #endif /* INET */ 2034 2035 #ifdef INET6 2036 /* IPv6 unit directory */ 2037 CFR_START_UNIT(&cfr, 4); 2038 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2039 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2040 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2041 /* XXX: TBA by IANA */ 2042 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2043 CFR_END_UNIT(&cfr); 2044 2045 CFR_START_UNIT(&cfr, 8); 2046 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2047 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2048 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2049 CFR_END_UNIT(&cfr); 2050 2051 CFR_START_UNIT(&cfr, 9); 2052 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2053 CFR_PUT_DATA1(&cfr, 0); 2054 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2055 CFR_END_UNIT(&cfr); 2056 #endif /* INET6 */ 2057 2058 fb->fb_off = cfr.ptr - hdr; 2059 #ifdef FW_DEBUG 2060 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2061 for (i = 0; i < fb->fb_off; i++) 2062 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2063 DPRINTFN(2, ("\n")); 2064 #endif /* FW_DEBUG */ 2065 2066 /* 2067 * Make network byte order for DMA 2068 */ 2069 for (i = 0; i < fb->fb_off; i++) 2070 HTONL(hdr[i]); 2071 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2072 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2073 2074 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2075 fb->fb_dmamap->dm_segs[0].ds_addr); 2076 2077 /* This register is only valid on OHCI 1.1. */ 2078 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2079 if ((OHCI_Version_GET_Version(val) == 1) && 2080 (OHCI_Version_GET_Revision(val) == 1)) 2081 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2082 OHCI_HCControl_BIBImageValid); 2083 2084 /* Just allow quad reads of the rom. */ 2085 for (i = 0; i < fb->fb_off; i++) 2086 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2087 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2088 fwohci_configrom_input, NULL); 2089 } 2090 2091 static int 2092 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2093 struct fwohci_pkt *pkt) 2094 { 2095 struct fwohci_pkt res; 2096 u_int32_t loc, *rom; 2097 2098 /* This will be used as an array index so size accordingly. */ 2099 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2100 if ((loc & 0x03) != 0) { 2101 /* alignment error */ 2102 return IEEE1394_RCODE_ADDRESS_ERROR; 2103 } 2104 else 2105 loc /= 4; 2106 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2107 2108 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2109 ntohl(rom[loc]))); 2110 2111 memset(&res, 0, sizeof(res)); 2112 res.fp_hdr[3] = rom[loc]; 2113 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2114 return -1; 2115 } 2116 2117 /* 2118 * SelfID buffer (no DMA context) 2119 */ 2120 static void 2121 fwohci_selfid_init(struct fwohci_softc *sc) 2122 { 2123 struct fwohci_buf *fb; 2124 2125 fb = &sc->sc_buf_selfid; 2126 #ifdef DIAGNOSTIC 2127 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2128 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2129 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2130 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2131 #endif 2132 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2133 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2134 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2135 2136 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2137 fb->fb_dmamap->dm_segs[0].ds_addr); 2138 } 2139 2140 static int 2141 fwohci_selfid_input(struct fwohci_softc *sc) 2142 { 2143 int i; 2144 u_int32_t count, val, gen; 2145 u_int32_t *buf; 2146 2147 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2148 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2149 again: 2150 if (val & OHCI_SelfID_Error) { 2151 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2152 return -1; 2153 } 2154 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2155 2156 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2157 0, count << 2, BUS_DMASYNC_POSTREAD); 2158 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2159 2160 #ifdef FW_DEBUG 2161 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2162 val)); 2163 for (i = 0; i < count; i++) 2164 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2165 DPRINTFN(1, ("\n")); 2166 #endif /* FW_DEBUG */ 2167 2168 for (i = 1; i < count; i += 2) { 2169 if (buf[i] != ~buf[i + 1]) 2170 break; 2171 if (buf[i] & 0x00000001) 2172 continue; /* more pkt */ 2173 if (buf[i] & 0x00800000) 2174 continue; /* external id */ 2175 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2176 if ((buf[i] & 0x00400800) == 0x00400800) 2177 sc->sc_irmid = sc->sc_rootid; 2178 } 2179 2180 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2181 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2182 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2183 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2184 goto again; 2185 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2186 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2187 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2188 return -1; 2189 } 2190 if (i != count) { 2191 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2192 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2193 #if 1 2194 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2195 /* 2196 * XXX: CXD3222 sometimes fails to DMA 2197 * selfid packet?? 2198 */ 2199 sc->sc_rootid = (count - 1) / 2 - 1; 2200 sc->sc_irmid = sc->sc_rootid; 2201 } else 2202 #endif 2203 return -1; 2204 } 2205 2206 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2207 if ((val & OHCI_NodeId_IDValid) == 0) { 2208 sc->sc_nodeid = 0xffff; /* invalid */ 2209 printf("%s: nodeid is invalid\n", 2210 sc->sc_sc1394.sc1394_dev.dv_xname); 2211 return -1; 2212 } 2213 sc->sc_nodeid = val & 0xffff; 2214 2215 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2216 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2217 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2218 sc->sc_irmid)); 2219 2220 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2221 return -1; 2222 2223 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2224 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2225 OHCI_LinkControl_CycleMaster); 2226 else 2227 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2228 OHCI_LinkControl_CycleMaster); 2229 return 0; 2230 } 2231 2232 /* 2233 * some CSRs are handled by driver. 2234 */ 2235 static void 2236 fwohci_csr_init(struct fwohci_softc *sc) 2237 { 2238 int i; 2239 static u_int32_t csr[] = { 2240 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2241 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2242 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2243 CSR_SB_BROADCAST_CHANNEL 2244 }; 2245 2246 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2247 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2248 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2249 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2250 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2251 } 2252 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2253 } 2254 2255 static int 2256 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2257 { 2258 struct fwohci_pkt res; 2259 u_int32_t reg; 2260 2261 /* 2262 * XXX need to do special functionality other than just r/w... 2263 */ 2264 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2265 2266 if ((reg & 0x03) != 0) { 2267 /* alignment error */ 2268 return IEEE1394_RCODE_ADDRESS_ERROR; 2269 } 2270 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2271 *(u_int32_t *)(&sc->sc_csr[reg]))); 2272 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2273 DPRINTFN(1, (" -> 0x%08x\n", 2274 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2275 *(u_int32_t *)&sc->sc_csr[reg] = 2276 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2277 } else { 2278 DPRINTFN(1, ("\n")); 2279 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2280 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2281 res.fp_iov[0].iov_len = 4; 2282 res.fp_uio.uio_resid = 4; 2283 res.fp_uio.uio_iovcnt = 1; 2284 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2285 return -1; 2286 } 2287 return IEEE1394_RCODE_COMPLETE; 2288 } 2289 2290 /* 2291 * Mapping between nodeid and unique ID (EUI-64). 2292 * 2293 * Track old mappings and simply update their devices with the new id's when 2294 * they match an existing EUI. This allows proper renumeration of the bus. 2295 */ 2296 static void 2297 fwohci_uid_collect(struct fwohci_softc *sc) 2298 { 2299 int i; 2300 struct fwohci_uidtbl *fu; 2301 struct ieee1394_softc *iea; 2302 2303 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2304 iea->sc1394_node_id = 0xffff; 2305 2306 if (sc->sc_uidtbl != NULL) 2307 free(sc->sc_uidtbl, M_DEVBUF); 2308 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2309 M_NOWAIT); /* XXX M_WAITOK requires locks */ 2310 if (sc->sc_uidtbl == NULL) 2311 return; 2312 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2313 2314 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2315 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2316 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2317 fu->fu_valid = 3; 2318 2319 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2320 if (iea) { 2321 iea->sc1394_node_id = i; 2322 DPRINTF(("%s: Updating nodeid to %d\n", 2323 iea->sc1394_dev.dv_xname, 2324 iea->sc1394_node_id)); 2325 } 2326 } else { 2327 fu->fu_valid = 0; 2328 fwohci_uid_req(sc, i); 2329 } 2330 } 2331 if (sc->sc_rootid == 0) 2332 fwohci_check_nodes(sc); 2333 } 2334 2335 static void 2336 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 2337 { 2338 struct fwohci_pkt pkt; 2339 2340 memset(&pkt, 0, sizeof(pkt)); 2341 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2342 pkt.fp_hlen = 12; 2343 pkt.fp_dlen = 0; 2344 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2345 (pkt.fp_tcode << 4); 2346 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 2347 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2348 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2349 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2350 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2351 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2352 2353 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2354 (pkt.fp_tcode << 4); 2355 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2356 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2357 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2358 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2359 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2360 } 2361 2362 static int 2363 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2364 { 2365 struct fwohci_uidtbl *fu; 2366 struct ieee1394_softc *iea; 2367 struct ieee1394_attach_args fwa; 2368 int i, n, done, rcode, found; 2369 2370 found = 0; 2371 2372 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2373 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2374 if (rcode != IEEE1394_RCODE_COMPLETE || 2375 sc->sc_uidtbl == NULL || 2376 n > sc->sc_rootid) 2377 return 0; 2378 fu = &sc->sc_uidtbl[n]; 2379 if (arg == 0) { 2380 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2381 fu->fu_valid |= 0x1; 2382 } else { 2383 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2384 fu->fu_valid |= 0x2; 2385 } 2386 #ifdef FW_DEBUG 2387 if (fu->fu_valid == 0x3) 2388 DPRINTFN(1, ("fwohci_uid_input: " 2389 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2390 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2391 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2392 #endif 2393 if (fu->fu_valid == 0x3) { 2394 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2395 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2396 found = 1; 2397 iea->sc1394_node_id = n; 2398 DPRINTF(("%s: Updating nodeid to %d\n", 2399 iea->sc1394_dev.dv_xname, 2400 iea->sc1394_node_id)); 2401 break; 2402 } 2403 if (!found) { 2404 strcpy(fwa.name, "fwnode"); 2405 memcpy(fwa.uid, fu->fu_uid, 8); 2406 fwa.nodeid = n; 2407 fwa.read = fwohci_read; 2408 fwa.write = fwohci_write; 2409 fwa.inreg = fwohci_inreg; 2410 iea = (struct ieee1394_softc *) 2411 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2412 fwohci_print, fwohci_submatch); 2413 if (iea != NULL) 2414 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2415 sc1394_node); 2416 } 2417 } 2418 done = 1; 2419 2420 for (i = 0; i < sc->sc_rootid + 1; i++) { 2421 fu = &sc->sc_uidtbl[i]; 2422 if (fu->fu_valid != 0x3) { 2423 done = 0; 2424 break; 2425 } 2426 } 2427 if (done) 2428 fwohci_check_nodes(sc); 2429 2430 return 0; 2431 } 2432 2433 static void 2434 fwohci_check_nodes(struct fwohci_softc *sc) 2435 { 2436 struct device *detach = NULL; 2437 struct ieee1394_softc *iea; 2438 2439 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2440 2441 /* 2442 * Have to defer detachment until the next 2443 * loop iteration since config_detach 2444 * free's the softc and the loop iterator 2445 * needs data from the softc to move 2446 * forward. 2447 */ 2448 2449 if (detach) { 2450 config_detach(detach, 0); 2451 detach = NULL; 2452 } 2453 if (iea->sc1394_node_id == 0xffff) { 2454 detach = (struct device *)iea; 2455 LIST_REMOVE(iea, sc1394_node); 2456 } 2457 } 2458 if (detach) 2459 config_detach(detach, 0); 2460 } 2461 2462 static int 2463 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2464 { 2465 struct fwohci_uidtbl *fu; 2466 int n; 2467 static const u_int8_t bcast[] = 2468 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2469 2470 fu = sc->sc_uidtbl; 2471 if (fu == NULL) { 2472 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2473 return IEEE1394_BCAST_PHY_ID; 2474 fwohci_uid_collect(sc); /* try to get */ 2475 return -1; 2476 } 2477 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 2478 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2479 return n; 2480 } 2481 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2482 return IEEE1394_BCAST_PHY_ID; 2483 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 2484 if (fu->fu_valid != 0x3) { 2485 /* 2486 * XXX: need timer before retransmission 2487 */ 2488 fwohci_uid_req(sc, n); 2489 } 2490 } 2491 return -1; 2492 } 2493 2494 /* 2495 * functions to support network interface 2496 */ 2497 static int 2498 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2499 void (*handler)(struct device *, struct mbuf *)) 2500 { 2501 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2502 2503 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2504 fwohci_if_input, handler); 2505 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2506 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2507 IEEE1394_TAG_GASP, fwohci_if_input, handler); 2508 return 0; 2509 } 2510 2511 static int 2512 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2513 { 2514 int n, len; 2515 struct mbuf *m; 2516 struct iovec *iov; 2517 void (*handler)(struct device *, struct mbuf *) = arg; 2518 2519 #ifdef FW_DEBUG 2520 int i; 2521 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2522 pkt->fp_dlen)); 2523 for (i = 0; i < pkt->fp_hlen/4; i++) 2524 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2525 DPRINTFN(2, ("$")); 2526 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2527 iov = &pkt->fp_iov[n]; 2528 for (i = 0; i < iov->iov_len; i++) 2529 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2530 ((u_int8_t *)iov->iov_base)[i])); 2531 DPRINTFN(2, ("$")); 2532 } 2533 DPRINTFN(1, ("\n")); 2534 #endif /* FW_DEBUG */ 2535 len = pkt->fp_dlen; 2536 MGETHDR(m, M_DONTWAIT, MT_DATA); 2537 if (m == NULL) 2538 return IEEE1394_RCODE_COMPLETE; 2539 m->m_len = 16; 2540 if (len + m->m_len > MHLEN) { 2541 MCLGET(m, M_DONTWAIT); 2542 if ((m->m_flags & M_EXT) == 0) { 2543 m_freem(m); 2544 return IEEE1394_RCODE_COMPLETE; 2545 } 2546 } 2547 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2548 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2549 sc->sc_uidtbl[n].fu_valid != 0x3) { 2550 printf("%s: packet from unknown node: phy id %d\n", 2551 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2552 m_freem(m); 2553 fwohci_uid_req(sc, n); 2554 return IEEE1394_RCODE_COMPLETE; 2555 } 2556 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2557 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2558 m->m_flags |= M_BCAST; 2559 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2560 } else { 2561 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2562 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2563 } 2564 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2565 mtod(m, u_int8_t *)[9] = 2566 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2567 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2568 2569 m->m_pkthdr.rcvif = NULL; /* set in child */ 2570 m->m_pkthdr.len = len + m->m_len; 2571 /* 2572 * We may use receive buffer by external mbuf instead of copy here. 2573 * But asynchronous receive buffer must be operate in buffer fill 2574 * mode, so that each receive buffer will shared by multiple mbufs. 2575 * If upper layer doesn't free mbuf soon, e.g. application program 2576 * is suspended, buffer must be reallocated. 2577 * Isochronous buffer must be operate in packet buffer mode, and 2578 * it is easy to map receive buffer to external mbuf. But it is 2579 * used for broadcast/multicast only, and is expected not so 2580 * performance sensitive for now. 2581 * XXX: The performance may be important for multicast case, 2582 * so we should revisit here later. 2583 * -- onoe 2584 */ 2585 n = 0; 2586 iov = pkt->fp_uio.uio_iov; 2587 while (len > 0) { 2588 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2589 iov->iov_len); 2590 m->m_len += iov->iov_len; 2591 len -= iov->iov_len; 2592 iov++; 2593 } 2594 (*handler)(sc->sc_sc1394.sc1394_if, m); 2595 return IEEE1394_RCODE_COMPLETE; 2596 } 2597 2598 static int 2599 fwohci_if_output(struct device *self, struct mbuf *m0, 2600 void (*callback)(struct device *, struct mbuf *)) 2601 { 2602 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2603 struct fwohci_pkt pkt; 2604 u_int8_t *p; 2605 int n, error, spd, hdrlen, maxrec; 2606 #ifdef FW_DEBUG 2607 struct mbuf *m; 2608 #endif 2609 2610 p = mtod(m0, u_int8_t *); 2611 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2612 spd = IEEE1394_SPD_S100; /*XXX*/ 2613 maxrec = 512; /*XXX*/ 2614 hdrlen = 8; 2615 } else { 2616 n = fwohci_uid_lookup(sc, p); 2617 if (n < 0) { 2618 printf("%s: nodeid unknown:" 2619 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2620 sc->sc_sc1394.sc1394_dev.dv_xname, 2621 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2622 error = EHOSTUNREACH; 2623 goto end; 2624 } 2625 if (n == IEEE1394_BCAST_PHY_ID) { 2626 printf("%s: broadcast with !M_MCAST\n", 2627 sc->sc_sc1394.sc1394_dev.dv_xname); 2628 #ifdef FW_DEBUG 2629 DPRINTFN(2, ("packet:")); 2630 for (m = m0; m != NULL; m = m->m_next) { 2631 for (n = 0; n < m->m_len; n++) 2632 DPRINTFN(2, ("%s%02x", (n%32)? 2633 ((n%4)?"":" "):"\n ", 2634 mtod(m, u_int8_t *)[n])); 2635 DPRINTFN(2, ("$")); 2636 } 2637 DPRINTFN(2, ("\n")); 2638 #endif 2639 error = EHOSTUNREACH; 2640 goto end; 2641 } 2642 maxrec = 2 << p[8]; 2643 spd = p[9]; 2644 hdrlen = 0; 2645 } 2646 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2647 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2648 spd, sc->sc_sc1394.sc1394_link_speed)); 2649 spd = sc->sc_sc1394.sc1394_link_speed; 2650 } 2651 if (maxrec > (512 << spd)) { 2652 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2653 "\n", maxrec, spd)); 2654 maxrec = 512 << spd; 2655 } 2656 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2657 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2658 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2659 maxrec >>= 1; 2660 } 2661 if (maxrec < 512) { 2662 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2663 "minimum\n", maxrec)); 2664 maxrec = 512; 2665 } 2666 2667 m_adj(m0, 16 - hdrlen); 2668 if (m0->m_pkthdr.len > maxrec) { 2669 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2670 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2671 error = E2BIG; /*XXX*/ 2672 goto end; 2673 } 2674 2675 memset(&pkt, 0, sizeof(pkt)); 2676 pkt.fp_uio.uio_iov = pkt.fp_iov; 2677 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2678 pkt.fp_uio.uio_rw = UIO_WRITE; 2679 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2680 /* construct GASP header */ 2681 p = mtod(m0, u_int8_t *); 2682 p[0] = sc->sc_nodeid >> 8; 2683 p[1] = sc->sc_nodeid & 0xff; 2684 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2685 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2686 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2687 pkt.fp_hlen = 8; 2688 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2689 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2690 OHCI_NodeId_NodeNumber) << 8); 2691 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2692 } else { 2693 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2694 pkt.fp_hlen = 16; 2695 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2696 (spd << 16); 2697 pkt.fp_hdr[1] = 2698 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2699 (p[10] << 8) | p[11]; 2700 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2701 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2702 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2703 } 2704 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2705 pkt.fp_dlen = m0->m_pkthdr.len; 2706 pkt.fp_m = m0; 2707 pkt.fp_callback = callback; 2708 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2709 m0 = pkt.fp_m; 2710 end: 2711 if (m0 != NULL) { 2712 if (callback) 2713 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2714 else 2715 m_freem(m0); 2716 } 2717 return error; 2718 } 2719 2720 /* 2721 * High level routines to provide abstraction to attaching layers to 2722 * send/receive data. 2723 */ 2724 2725 /* 2726 * These break down into 4 routines as follows: 2727 * 2728 * int fwohci_read(struct ieee1394_abuf *) 2729 * 2730 * This routine will attempt to read a region from the requested node. 2731 * A callback must be provided which will be called when either the completed 2732 * read is done or an unrecoverable error occurs. This is mainly a convenience 2733 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2734 * and recombining all the returned data. This could also be done with a series 2735 * of write/inreg's for each packet sent. 2736 * 2737 * int fwohci_write(struct ieee1394_abuf *) 2738 * 2739 * The work horse main entry point for putting packets on the bus. This is the 2740 * generalized interface for fwnode/etc code to put packets out onto the bus. 2741 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2742 * will callback via a func pointer to the calling code with the resulting ACK 2743 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2744 * write routine will take care of free'ing the abuf since the fwnode/etc code 2745 * won't have any knowledge of when to do this. This allows for simple one-off 2746 * packets to be sent from the upper-level code without worrying about a callback 2747 * for cleanup. 2748 * 2749 * int fwohci_inreg(struct ieee1394_abuf *, int) 2750 * 2751 * This is very simple. It evals the abuf passed in and registers an internal 2752 * handler as the callback for packets received for that operation. 2753 * The integer argument specifies whether on a block read/write operation to 2754 * allow sub-regions to be read/written (in block form) as well. 2755 * 2756 * XXX: This whole structure needs to be redone as a list of regions and 2757 * operations allowed on those regions. 2758 * 2759 * int fwohci_unreg(struct ieee1394_abuf *, int) 2760 * 2761 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2762 * routine will simply verify ab_cb is NULL and call inreg. 2763 * 2764 * This simply unregisters the respective callback done via inreg for items 2765 * which only need to register an area for a one-time operation (like a status 2766 * buffer a remote node will write to when the current operation is done). The 2767 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2768 * it unregisters). 2769 */ 2770 2771 static int 2772 fwohci_read(struct ieee1394_abuf *ab) 2773 { 2774 struct fwohci_pkt pkt; 2775 struct ieee1394_softc *sc = ab->ab_req; 2776 struct fwohci_softc *psc = 2777 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2778 struct fwohci_cb *fcb; 2779 u_int32_t high, lo; 2780 int rv, tcode; 2781 2782 /* Have to have a callback when reading. */ 2783 if (ab->ab_cb == NULL) 2784 return -1; 2785 2786 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2787 fcb->ab = ab; 2788 fcb->count = 0; 2789 fcb->abuf_valid = 1; 2790 2791 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2792 lo = (ab->ab_csr & 0x00000000ffffffff); 2793 2794 memset(&pkt, 0, sizeof(pkt)); 2795 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2796 pkt.fp_hdr[2] = lo; 2797 pkt.fp_dlen = 0; 2798 2799 if (ab->ab_length == 4) { 2800 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2801 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2802 pkt.fp_hlen = 12; 2803 } else { 2804 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2805 pkt.fp_hlen = 16; 2806 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2807 pkt.fp_hdr[3] = (ab->ab_length << 16); 2808 } 2809 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2810 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2811 2812 pkt.fp_statusarg = fcb; 2813 pkt.fp_statuscb = fwohci_read_resp; 2814 2815 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2816 psc->sc_tlabel, fwohci_read_resp, fcb); 2817 if (rv) 2818 return rv; 2819 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2820 if (rv) 2821 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2822 psc->sc_tlabel, NULL, NULL); 2823 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2824 fcb->count = 1; 2825 return rv; 2826 } 2827 2828 static int 2829 fwohci_write(struct ieee1394_abuf *ab) 2830 { 2831 struct fwohci_pkt pkt; 2832 struct ieee1394_softc *sc = ab->ab_req; 2833 struct fwohci_softc *psc = 2834 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2835 u_int32_t high, lo; 2836 int rv; 2837 2838 if (ab->ab_length > sc->sc1394_max_receive) { 2839 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2840 return E2BIG; 2841 } 2842 2843 memset(&pkt, 0, sizeof(pkt)); 2844 2845 pkt.fp_tcode = ab->ab_tcode; 2846 pkt.fp_uio.uio_iov = pkt.fp_iov; 2847 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2848 pkt.fp_uio.uio_rw = UIO_WRITE; 2849 2850 pkt.fp_statusarg = ab; 2851 pkt.fp_statuscb = fwohci_write_ack; 2852 2853 switch (ab->ab_tcode) { 2854 case IEEE1394_TCODE_WRITE_RESP: 2855 pkt.fp_hlen = 12; 2856 case IEEE1394_TCODE_READ_RESP_QUAD: 2857 case IEEE1394_TCODE_READ_RESP_BLOCK: 2858 if (!pkt.fp_hlen) 2859 pkt.fp_hlen = 16; 2860 high = ab->ab_retlen; 2861 ab->ab_retlen = 0; 2862 lo = 0; 2863 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2864 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2865 break; 2866 default: 2867 pkt.fp_hlen = 16; 2868 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2869 lo = (ab->ab_csr & 0x00000000ffffffff); 2870 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2871 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2872 break; 2873 } 2874 2875 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2876 pkt.fp_hdr[2] = lo; 2877 if (pkt.fp_hlen == 16) { 2878 if (ab->ab_length == 4) { 2879 pkt.fp_hdr[3] = ab->ab_data[0]; 2880 pkt.fp_dlen = 0; 2881 } else { 2882 pkt.fp_hdr[3] = (ab->ab_length << 16); 2883 pkt.fp_dlen = ab->ab_length; 2884 pkt.fp_uio.uio_iovcnt = 1; 2885 pkt.fp_uio.uio_resid = ab->ab_length; 2886 pkt.fp_iov[0].iov_base = ab->ab_data; 2887 pkt.fp_iov[0].iov_len = ab->ab_length; 2888 } 2889 } 2890 switch (ab->ab_tcode) { 2891 case IEEE1394_TCODE_WRITE_RESP: 2892 case IEEE1394_TCODE_READ_RESP_QUAD: 2893 case IEEE1394_TCODE_READ_RESP_BLOCK: 2894 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2895 break; 2896 default: 2897 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2898 break; 2899 } 2900 return rv; 2901 } 2902 2903 static int 2904 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2905 { 2906 struct fwohci_cb *fcb = arg; 2907 struct ieee1394_abuf *ab = fcb->ab; 2908 struct fwohci_pkt newpkt; 2909 u_int32_t *cur, high, lo; 2910 int i, tcode, rcode, status, rv; 2911 2912 /* 2913 * Both the ACK handling and normal response callbacks are handled here. 2914 * The main reason for this is the various error conditions that can 2915 * occur trying to block read some areas and the ways that gets reported 2916 * back to calling station. This is a variety of ACK codes, responses, 2917 * etc which makes it much more difficult to process if both aren't 2918 * handled here. 2919 */ 2920 2921 /* Check for status packet. */ 2922 2923 if (pkt->fp_tcode == -1) { 2924 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2925 rcode = -1; 2926 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2927 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2928 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2929 DPRINTF(("Got status packet: 0x%02x\n", 2930 (unsigned int)status)); 2931 fcb->count--; 2932 2933 /* 2934 * Got all the ack's back and the buffer is invalid (i.e. the 2935 * callback has been called. Clean up. 2936 */ 2937 2938 if (fcb->abuf_valid == 0) { 2939 if (fcb->count == 0) 2940 free(fcb, M_DEVBUF); 2941 return IEEE1394_RCODE_COMPLETE; 2942 } 2943 } else { 2944 status = -1; 2945 tcode = pkt->fp_tcode; 2946 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2947 } 2948 2949 /* 2950 * Some area's (like the config rom want to be read as quadlets only. 2951 * 2952 * The current ideas to try are: 2953 * 2954 * Got an ACK_TYPE_ERROR on a block read. 2955 * 2956 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2957 * response. 2958 * 2959 * In all cases construct a new packet for a quadlet read and let 2960 * mutli_resp handle the iteration over the space. 2961 */ 2962 2963 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2964 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2965 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2966 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2967 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2968 2969 /* Read the area in quadlet chunks (internally track this). */ 2970 2971 memset(&newpkt, 0, sizeof(newpkt)); 2972 2973 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2974 lo = (ab->ab_csr & 0x00000000ffffffff); 2975 2976 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2977 newpkt.fp_hlen = 12; 2978 newpkt.fp_dlen = 0; 2979 newpkt.fp_hdr[1] = 2980 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2981 newpkt.fp_hdr[2] = lo; 2982 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2983 (newpkt.fp_tcode << 4); 2984 2985 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2986 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2987 fwohci_read_multi_resp, fcb); 2988 if (rv) { 2989 (*ab->ab_cb)(ab, -1); 2990 goto cleanup; 2991 } 2992 newpkt.fp_statusarg = fcb; 2993 newpkt.fp_statuscb = fwohci_read_resp; 2994 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 2995 if (rv) { 2996 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2997 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 2998 NULL); 2999 (*ab->ab_cb)(ab, -1); 3000 goto cleanup; 3001 } 3002 fcb->count++; 3003 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3004 return IEEE1394_RCODE_COMPLETE; 3005 } else if ((rcode != -1) || ((status != -1) && 3006 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3007 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3008 3009 /* 3010 * Recombine all the iov data into 1 chunk for higher 3011 * level code. 3012 */ 3013 3014 if (rcode != -1) { 3015 cur = ab->ab_data; 3016 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3017 /* 3018 * Make sure and don't exceed the buffer 3019 * allocated for return. 3020 */ 3021 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3022 ab->ab_length) { 3023 memcpy(cur, pkt->fp_iov[i].iov_base, 3024 (ab->ab_length - ab->ab_retlen)); 3025 ab->ab_retlen = ab->ab_length; 3026 break; 3027 } 3028 memcpy(cur, pkt->fp_iov[i].iov_base, 3029 pkt->fp_iov[i].iov_len); 3030 cur += pkt->fp_iov[i].iov_len; 3031 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3032 } 3033 } 3034 if (status != -1) 3035 /* XXX: Need a complete tlabel interface. */ 3036 for (i = 0; i < 64; i++) 3037 fwohci_handler_set(sc, 3038 IEEE1394_TCODE_READ_RESP_QUAD, 3039 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3040 (*ab->ab_cb)(ab, rcode); 3041 goto cleanup; 3042 } else 3043 /* Good ack packet. */ 3044 return IEEE1394_RCODE_COMPLETE; 3045 3046 /* Can't get here unless ab->ab_cb has been called. */ 3047 3048 cleanup: 3049 fcb->abuf_valid = 0; 3050 if (fcb->count == 0) 3051 free(fcb, M_DEVBUF); 3052 return IEEE1394_RCODE_COMPLETE; 3053 } 3054 3055 static int 3056 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3057 struct fwohci_pkt *pkt) 3058 { 3059 struct fwohci_cb *fcb = arg; 3060 struct ieee1394_abuf *ab = fcb->ab; 3061 struct fwohci_pkt newpkt; 3062 u_int32_t high, lo; 3063 int rcode, rv; 3064 3065 /* 3066 * Bad return codes from the wire, just return what's already in the 3067 * buf. 3068 */ 3069 3070 /* Make sure a response packet didn't arrive after a bad ACK. */ 3071 if (fcb->abuf_valid == 0) 3072 return IEEE1394_RCODE_COMPLETE; 3073 3074 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3075 3076 if (rcode) { 3077 (*ab->ab_cb)(ab, rcode); 3078 goto cleanup; 3079 } 3080 3081 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3082 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3083 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3084 ab->ab_retlen = ab->ab_length; 3085 } else { 3086 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3087 pkt->fp_iov[0].iov_base, 4); 3088 ab->ab_retlen += 4; 3089 } 3090 /* Still more, loop and read 4 more bytes. */ 3091 if (ab->ab_retlen < ab->ab_length) { 3092 memset(&newpkt, 0, sizeof(newpkt)); 3093 3094 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3095 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3096 3097 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3098 newpkt.fp_hlen = 12; 3099 newpkt.fp_dlen = 0; 3100 newpkt.fp_hdr[1] = 3101 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3102 newpkt.fp_hdr[2] = lo; 3103 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3104 (newpkt.fp_tcode << 4); 3105 3106 newpkt.fp_statusarg = fcb; 3107 newpkt.fp_statuscb = fwohci_read_resp; 3108 3109 /* 3110 * Bad return code. Just give up and return what's 3111 * come in now. 3112 */ 3113 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3114 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3115 fwohci_read_multi_resp, fcb); 3116 if (rv) 3117 (*ab->ab_cb)(ab, -1); 3118 else { 3119 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3120 if (rv) { 3121 fwohci_handler_set(sc, 3122 IEEE1394_TCODE_READ_RESP_QUAD, 3123 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3124 NULL, NULL); 3125 (*ab->ab_cb)(ab, -1); 3126 } else { 3127 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3128 fcb->count++; 3129 return IEEE1394_RCODE_COMPLETE; 3130 } 3131 } 3132 } else 3133 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3134 3135 cleanup: 3136 /* Can't get here unless ab_cb has been called. */ 3137 fcb->abuf_valid = 0; 3138 if (fcb->count == 0) 3139 free(fcb, M_DEVBUF); 3140 return IEEE1394_RCODE_COMPLETE; 3141 } 3142 3143 static int 3144 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3145 { 3146 struct ieee1394_abuf *ab = arg; 3147 u_int16_t status; 3148 3149 3150 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3151 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3152 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3153 DPRINTF(("Got status packet: 0x%02x\n", 3154 (unsigned int)status)); 3155 3156 /* No callback means this level should free the buffers. */ 3157 if (ab->ab_cb) 3158 (*ab->ab_cb)(ab, status); 3159 else { 3160 if (ab->ab_data) 3161 free(ab->ab_data, M_1394DATA); 3162 free(ab, M_1394DATA); 3163 } 3164 return IEEE1394_RCODE_COMPLETE; 3165 } 3166 3167 static int 3168 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3169 { 3170 struct ieee1394_softc *sc = ab->ab_req; 3171 struct fwohci_softc *psc = 3172 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3173 u_int32_t high, lo; 3174 int i, j, rv; 3175 3176 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3177 lo = (ab->ab_csr & 0x00000000ffffffff); 3178 3179 rv = 0; 3180 switch (ab->ab_tcode) { 3181 case IEEE1394_TCODE_READ_REQ_QUAD: 3182 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3183 if (ab->ab_cb) 3184 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3185 fwohci_parse_input, ab); 3186 else 3187 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3188 NULL); 3189 break; 3190 case IEEE1394_TCODE_READ_REQ_BLOCK: 3191 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3192 if (allow) { 3193 for (i = 0; i < (ab->ab_length / 4); i++) { 3194 if (ab->ab_cb) { 3195 rv = fwohci_handler_set(psc, 3196 ab->ab_tcode, high, lo + (i * 4), 3197 fwohci_parse_input, ab); 3198 if (rv) 3199 break; 3200 } else 3201 fwohci_handler_set(psc, ab->ab_tcode, 3202 high, lo + (i * 4), NULL, NULL); 3203 } 3204 if (i != (ab->ab_length / 4)) { 3205 j = i + 1; 3206 for (i = 0; i < j; i++) 3207 fwohci_handler_set(psc, ab->ab_tcode, 3208 high, lo + (i * 4), NULL, NULL); 3209 } else 3210 ab->ab_data = (void *)1; 3211 } else { 3212 if (ab->ab_cb) 3213 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3214 lo, fwohci_parse_input, ab); 3215 else 3216 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3217 NULL, NULL); 3218 } 3219 break; 3220 default: 3221 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3222 return -1; 3223 break; 3224 } 3225 return rv; 3226 } 3227 3228 static int 3229 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3230 { 3231 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3232 u_int64_t csr; 3233 u_int32_t *cur; 3234 int i, count; 3235 3236 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3237 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3238 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3239 3240 switch (ab->ab_tcode) { 3241 case IEEE1394_TCODE_READ_REQ_QUAD: 3242 ab->ab_retlen = 4; 3243 break; 3244 case IEEE1394_TCODE_READ_REQ_BLOCK: 3245 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3246 if (ab->ab_data) { 3247 if ((csr + ab->ab_retlen) > 3248 (ab->ab_csr + ab->ab_length)) 3249 return IEEE1394_RCODE_ADDRESS_ERROR; 3250 ab->ab_data = NULL; 3251 } else 3252 if (ab->ab_retlen != ab->ab_length) 3253 return IEEE1394_RCODE_ADDRESS_ERROR; 3254 break; 3255 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3256 ab->ab_retlen = 4; 3257 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3258 if (!ab->ab_retlen) 3259 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3260 if (ab->ab_data) { 3261 if ((csr + ab->ab_retlen) > 3262 (ab->ab_csr + ab->ab_length)) 3263 return IEEE1394_RCODE_ADDRESS_ERROR; 3264 ab->ab_data = NULL; 3265 } else 3266 if (ab->ab_retlen != ab->ab_length) 3267 return IEEE1394_RCODE_ADDRESS_ERROR; 3268 3269 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3270 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3271 ab->ab_data[0] = pkt->fp_hdr[3]; 3272 else { 3273 count = 0; 3274 cur = ab->ab_data; 3275 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3276 memcpy(cur, pkt->fp_iov[i].iov_base, 3277 pkt->fp_iov[i].iov_len); 3278 cur += pkt->fp_iov[i].iov_len; 3279 count += pkt->fp_iov[i].iov_len; 3280 } 3281 if (ab->ab_retlen != count) 3282 panic("Packet claims %d length " 3283 "but only %d bytes returned\n", 3284 ab->ab_retlen, count); 3285 } 3286 break; 3287 default: 3288 panic("Got a callback for a tcode that wasn't requested: %d\n", 3289 ab->ab_tcode); 3290 break; 3291 } 3292 ab->ab_csr = csr; 3293 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3294 return -1; 3295 } 3296 3297 static int 3298 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3299 { 3300 struct ieee1394_attach_args *fwa = aux; 3301 3302 /* Both halves must be filled in for a match. */ 3303 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3304 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3305 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3306 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3307 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3308 return 0; 3309 } 3310 3311 #ifdef FW_DEBUG 3312 static void 3313 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3314 { 3315 3316 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3317 intmask); 3318 if (intmask & OHCI_Int_CycleTooLong) 3319 printf(" CycleTooLong"); 3320 if (intmask & OHCI_Int_UnrecoverableError) 3321 printf(" UnrecoverableError"); 3322 if (intmask & OHCI_Int_CycleInconsistent) 3323 printf(" CycleInconsistent"); 3324 if (intmask & OHCI_Int_BusReset) 3325 printf(" BusReset"); 3326 if (intmask & OHCI_Int_SelfIDComplete) 3327 printf(" SelfIDComplete"); 3328 if (intmask & OHCI_Int_LockRespErr) 3329 printf(" LockRespErr"); 3330 if (intmask & OHCI_Int_PostedWriteErr) 3331 printf(" PostedWriteErr"); 3332 if (intmask & OHCI_Int_ReqTxComplete) 3333 printf(" ReqTxComplete(0x%04x)", 3334 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3335 OHCI_SUBREG_ContextControlClear)); 3336 if (intmask & OHCI_Int_RespTxComplete) 3337 printf(" RespTxComplete(0x%04x)", 3338 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3339 OHCI_SUBREG_ContextControlClear)); 3340 if (intmask & OHCI_Int_ARRS) 3341 printf(" ARRS(0x%04x)", 3342 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3343 OHCI_SUBREG_ContextControlClear)); 3344 if (intmask & OHCI_Int_ARRQ) 3345 printf(" ARRQ(0x%04x)", 3346 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3347 OHCI_SUBREG_ContextControlClear)); 3348 if (intmask & OHCI_Int_IsochRx) 3349 printf(" IsochRx(0x%08x)", 3350 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3351 if (intmask & OHCI_Int_IsochTx) 3352 printf(" IsochTx(0x%08x)", 3353 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3354 if (intmask & OHCI_Int_RQPkt) 3355 printf(" RQPkt(0x%04x)", 3356 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3357 OHCI_SUBREG_ContextControlClear)); 3358 if (intmask & OHCI_Int_RSPkt) 3359 printf(" RSPkt(0x%04x)", 3360 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3361 OHCI_SUBREG_ContextControlClear)); 3362 printf("\n"); 3363 } 3364 3365 static void 3366 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3367 { 3368 u_int8_t key, phyid; 3369 3370 key = (val & 0xc0000000) >> 30; 3371 phyid = (val & 0x3f000000) >> 24; 3372 printf("%s: PHY packet from %d: ", 3373 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3374 switch (key) { 3375 case 0: 3376 printf("PHY Config:"); 3377 if (val & 0x00800000) 3378 printf(" ForceRoot"); 3379 if (val & 0x00400000) 3380 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3381 printf("\n"); 3382 break; 3383 case 1: 3384 printf("Link-on\n"); 3385 break; 3386 case 2: 3387 printf("SelfID:"); 3388 if (val & 0x00800000) { 3389 printf(" #%d", (val & 0x00700000) >> 20); 3390 } else { 3391 if (val & 0x00400000) 3392 printf(" LinkActive"); 3393 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3394 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3395 if (val & 0x00000800) 3396 printf(" Cont"); 3397 if (val & 0x00000002) 3398 printf(" InitiateBusReset"); 3399 } 3400 if (val & 0x00000001) 3401 printf(" +"); 3402 printf("\n"); 3403 break; 3404 default: 3405 printf("unknown: 0x%08x\n", val); 3406 break; 3407 } 3408 } 3409 #endif /* FW_DEBUG */ 3410
Indexes created Fri Sep 26 08:10:20 GMT 2025