fwohci.c revision 1.38
1 /* $NetBSD: fwohci.c,v 1.38 2001/07/02 10:46:03 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init_rx(struct fwohci_softc *); 100 static void fwohci_buf_start_rx(struct fwohci_softc *); 101 static void fwohci_buf_stop_tx(struct fwohci_softc *); 102 static void fwohci_buf_stop_rx(struct fwohci_softc *); 103 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 104 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 105 caddr_t *, int); 106 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 107 struct fwohci_pkt *); 108 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 109 struct fwohci_pkt *); 110 111 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 112 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 113 static void fwohci_phy_busreset(struct fwohci_softc *); 114 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 115 116 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 117 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 118 119 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 120 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 121 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 122 123 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 124 struct fwohci_pkt *); 125 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 126 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 127 struct fwohci_pkt *); 128 129 static int fwohci_guidrom_init(struct fwohci_softc *); 130 static void fwohci_configrom_init(struct fwohci_softc *); 131 static int fwohci_configrom_input(struct fwohci_softc *, void *, 132 struct fwohci_pkt *); 133 static void fwohci_selfid_init(struct fwohci_softc *); 134 static int fwohci_selfid_input(struct fwohci_softc *); 135 136 static void fwohci_csr_init(struct fwohci_softc *); 137 static int fwohci_csr_input(struct fwohci_softc *, void *, 138 struct fwohci_pkt *); 139 140 static void fwohci_uid_collect(struct fwohci_softc *); 141 static void fwohci_uid_req(struct fwohci_softc *, int); 142 static int fwohci_uid_input(struct fwohci_softc *, void *, 143 struct fwohci_pkt *); 144 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 145 static void fwohci_check_nodes(struct fwohci_softc *); 146 147 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 148 void (*)(struct device *, struct mbuf *)); 149 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 150 static int fwohci_if_output(struct device *, struct mbuf *, 151 void (*)(struct device *, struct mbuf *)); 152 static int fwohci_read(struct ieee1394_abuf *); 153 static int fwohci_write(struct ieee1394_abuf *); 154 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 155 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 156 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 157 struct fwohci_pkt *); 158 static int fwohci_inreg(struct ieee1394_abuf *, int); 159 static int fwohci_parse_input(struct fwohci_softc *, void *, 160 struct fwohci_pkt *); 161 static int fwohci_submatch(struct device *, struct cfdata *, void *); 162 163 #ifdef FW_DEBUG 164 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 165 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 166 167 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 168 169 #define DPRINTF(x) if (fwdebug) printf x 170 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 171 int fwdebug = 0; 172 #else 173 #define DPRINTF(x) 174 #define DPRINTFN(n,x) 175 #endif 176 177 int 178 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 179 { 180 int i; 181 u_int32_t val; 182 #if 0 183 int error; 184 #endif 185 186 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 187 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 188 189 /* 190 * Wait for reset completion 191 */ 192 for (i = 0; i < OHCI_LOOP; i++) { 193 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 194 if ((val & OHCI_HCControl_SoftReset) == 0) 195 break; 196 DELAY(10); 197 } 198 199 /* What dialect of OHCI is this device? 200 */ 201 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 202 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 203 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 204 205 LIST_INIT(&sc->sc_nodelist); 206 207 if (fwohci_guidrom_init(sc) != 0) { 208 printf("\n%s: fatal: no global UID ROM\n", 209 sc->sc_sc1394.sc1394_dev.dv_xname); 210 return -1; 211 } 212 213 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 214 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 215 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 216 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 217 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 218 219 /* Get the maximum link speed and receive size 220 */ 221 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 222 sc->sc_sc1394.sc1394_link_speed = 223 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 224 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 225 printf(", %s", 226 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 227 } else { 228 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 229 } 230 231 /* MaxRec is encoded as log2(max_rec_octets)-1 232 */ 233 sc->sc_sc1394.sc1394_max_receive = 234 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 235 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 236 237 /* 238 * Count how many isochronous ctx we have. 239 */ 240 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 241 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 242 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 243 for (i = 0; val != 0; val >>= 1) { 244 if (val & 0x1) 245 i++; 246 } 247 sc->sc_isoctx = i; 248 printf(", %d iso_ctx", sc->sc_isoctx); 249 250 printf("\n"); 251 252 #if 0 253 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 254 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 255 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 256 return error; 257 #endif 258 259 sc->sc_dying = 0; 260 sc->sc_nodeid = 0xffff; /* invalid */ 261 262 kthread_create(fwohci_create_event_thread, sc); 263 return 0; 264 } 265 266 int 267 fwohci_intr(void *arg) 268 { 269 struct fwohci_softc * const sc = arg; 270 int progress = 0; 271 u_int32_t intmask, iso; 272 273 for (;;) { 274 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 275 276 /* 277 * On a bus reset, everything except bus reset gets 278 * cleared. That can't get cleared until the selfid 279 * phase completes (which happens outside the 280 * interrupt routines). So if just a bus reset is left 281 * in the mask and it's already in the sc_intmask, 282 * just return. 283 */ 284 285 if ((intmask == 0) || 286 (progress && (intmask == OHCI_Int_BusReset) && 287 (sc->sc_intmask & OHCI_Int_BusReset))) { 288 if (progress) 289 wakeup(fwohci_event_thread); 290 return progress; 291 } 292 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 293 intmask & ~OHCI_Int_BusReset); 294 #ifdef FW_DEBUG 295 if (fwdebug > 1) 296 fwohci_show_intr(sc, intmask); 297 #endif 298 299 if (intmask & OHCI_Int_BusReset) { 300 /* 301 * According to OHCI spec 6.1.1 "busReset", 302 * All asynchronous transmit must be stopped before 303 * clearing BusReset. Moreover, the BusReset 304 * interrupt bit should not be cleared during the 305 * SelfID phase. Thus we turned off interrupt mask 306 * bit of BusReset instead until SelfID completion 307 * or SelfID timeout. 308 */ 309 intmask &= OHCI_Int_SelfIDComplete; 310 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 311 OHCI_Int_BusReset); 312 sc->sc_intmask = OHCI_Int_BusReset; 313 } 314 sc->sc_intmask |= intmask; 315 316 if (intmask & OHCI_Int_IsochTx) { 317 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 318 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 319 } 320 if (intmask & OHCI_Int_IsochRx) { 321 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 322 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 323 sc->sc_iso |= iso; 324 } 325 326 if (!progress) { 327 sc->sc_intrcnt.ev_count++; 328 progress = 1; 329 } 330 } 331 } 332 333 static void 334 fwohci_create_event_thread(void *arg) 335 { 336 struct fwohci_softc *sc = arg; 337 338 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 339 sc->sc_sc1394.sc1394_dev.dv_xname)) { 340 printf("%s: unable to create event thread\n", 341 sc->sc_sc1394.sc1394_dev.dv_xname); 342 panic("fwohci_create_event_thread"); 343 } 344 } 345 346 static void 347 fwohci_thread_init(void *arg) 348 { 349 struct fwohci_softc *sc = arg; 350 int i; 351 352 /* 353 * Allocate descriptors 354 */ 355 if (fwohci_desc_alloc(sc)) { 356 printf("%s: not enabling interrupts\n", 357 sc->sc_sc1394.sc1394_dev.dv_xname); 358 kthread_exit(1); 359 } 360 361 /* 362 * Enable Link Power 363 */ 364 365 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 366 367 /* 368 * Allocate DMA Context 369 */ 370 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 371 OHCI_CTX_ASYNC_RX_REQUEST); 372 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 373 OHCI_CTX_ASYNC_RX_RESPONSE); 374 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 375 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 376 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 377 M_DEVBUF, M_WAITOK); 378 for (i = 0; i < sc->sc_isoctx; i++) 379 sc->sc_ctx_ir[i] = NULL; 380 381 /* 382 * Allocate buffer for configuration ROM and SelfID buffer 383 */ 384 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 385 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 386 387 callout_init(&sc->sc_selfid_callout); 388 389 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 390 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 391 392 /* 393 * establish hooks for shutdown and suspend/resume 394 */ 395 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 396 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 397 398 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 399 fwohci_print); 400 401 /* Main loop. It's not coming back normally. */ 402 403 fwohci_event_thread(sc); 404 405 kthread_exit(0); 406 } 407 408 static void 409 fwohci_event_thread(struct fwohci_softc *sc) 410 { 411 int i, s; 412 u_int32_t intmask, iso; 413 414 s = splbio(); 415 416 /* 417 * Initialize hardware registers. 418 */ 419 420 fwohci_hw_init(sc); 421 422 /* Initial Bus Reset */ 423 fwohci_phy_busreset(sc); 424 splx(s); 425 426 while (!sc->sc_dying) { 427 s = splbio(); 428 intmask = sc->sc_intmask; 429 if (intmask == 0) { 430 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 431 splx(s); 432 continue; 433 } 434 sc->sc_intmask = 0; 435 splx(s); 436 437 if (intmask & OHCI_Int_BusReset) { 438 fwohci_buf_stop_tx(sc); 439 if (sc->sc_uidtbl != NULL) { 440 free(sc->sc_uidtbl, M_DEVBUF); 441 sc->sc_uidtbl = NULL; 442 } 443 444 callout_reset(&sc->sc_selfid_callout, 445 OHCI_SELFID_TIMEOUT, 446 (void (*)(void *))fwohci_phy_busreset, sc); 447 sc->sc_nodeid = 0xffff; /* indicate invalid */ 448 sc->sc_rootid = 0; 449 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 450 } 451 if (intmask & OHCI_Int_SelfIDComplete) { 452 s = splbio(); 453 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 454 OHCI_Int_BusReset); 455 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 456 OHCI_Int_BusReset); 457 splx(s); 458 callout_stop(&sc->sc_selfid_callout); 459 if (fwohci_selfid_input(sc) == 0) { 460 fwohci_buf_start_rx(sc); 461 fwohci_uid_collect(sc); 462 } 463 } 464 if (intmask & OHCI_Int_ReqTxComplete) 465 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 466 if (intmask & OHCI_Int_RespTxComplete) 467 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 468 if (intmask & OHCI_Int_RQPkt) 469 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 470 if (intmask & OHCI_Int_RSPkt) 471 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 472 if (intmask & OHCI_Int_IsochRx) { 473 s = splbio(); 474 iso = sc->sc_iso; 475 sc->sc_iso = 0; 476 splx(s); 477 for (i = 0; i < sc->sc_isoctx; i++) { 478 if ((iso & (1 << i)) && 479 sc->sc_ctx_ir[i] != NULL) 480 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 481 } 482 } 483 } 484 } 485 486 #if 0 487 static int 488 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 489 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 490 { 491 bus_dma_segment_t segs[1]; 492 int error, nsegs, steps; 493 494 steps = 0; 495 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 496 segs, 1, &nsegs, flags); 497 if (error) 498 goto cleanup; 499 500 steps = 1; 501 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 502 kvap, flags); 503 if (error) 504 goto cleanup; 505 506 if (error == 0) 507 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 508 size, flags, mapp); 509 if (error) 510 goto cleanup; 511 if (error == 0) 512 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 513 flags); 514 if (error) 515 goto cleanup; 516 517 cleanup: 518 switch (steps) { 519 case 1: 520 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 521 } 522 523 return error; 524 } 525 #endif 526 527 int 528 fwohci_print(void *aux, const char *pnp) 529 { 530 char *name = aux; 531 532 if (pnp) 533 printf("%s at %s", name, pnp); 534 535 return QUIET; 536 } 537 538 static void 539 fwohci_hw_init(struct fwohci_softc *sc) 540 { 541 int i; 542 u_int32_t val; 543 544 /* 545 * Software Reset. 546 */ 547 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 548 for (i = 0; i < OHCI_LOOP; i++) { 549 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 550 if ((val & OHCI_HCControl_SoftReset) == 0) 551 break; 552 DELAY(10); 553 } 554 555 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 556 557 /* 558 * First, initilize CSRs with undefined value to default settings. 559 */ 560 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 561 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 562 #if 0 563 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 564 #else 565 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 566 #endif 567 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 568 for (i = 0; i < sc->sc_isoctx; i++) { 569 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 570 ~0); 571 } 572 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 573 574 fwohci_configrom_init(sc); 575 fwohci_selfid_init(sc); 576 fwohci_buf_init_rx(sc); 577 fwohci_csr_init(sc); 578 579 /* 580 * Final CSR settings. 581 */ 582 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 583 OHCI_LinkControl_CycleTimerEnable | 584 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 585 586 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 587 588 /* clear receive filter */ 589 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 590 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 591 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 592 593 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 594 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 595 #if BYTE_ORDER == BIG_ENDIAN 596 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 597 OHCI_HCControl_NoByteSwapData); 598 #endif 599 600 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 601 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 602 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 603 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 604 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 605 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 606 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 607 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 608 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 609 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 610 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 611 612 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 613 614 /* 615 * Start the receivers 616 */ 617 fwohci_buf_start_rx(sc); 618 } 619 620 static void 621 fwohci_power(int why, void *arg) 622 { 623 struct fwohci_softc *sc = arg; 624 int s; 625 626 s = splbio(); 627 switch (why) { 628 case PWR_SUSPEND: 629 case PWR_STANDBY: 630 fwohci_shutdown(sc); 631 break; 632 case PWR_RESUME: 633 fwohci_hw_init(sc); 634 fwohci_phy_busreset(sc); 635 break; 636 case PWR_SOFTSUSPEND: 637 case PWR_SOFTSTANDBY: 638 case PWR_SOFTRESUME: 639 break; 640 } 641 splx(s); 642 } 643 644 static void 645 fwohci_shutdown(void *arg) 646 { 647 struct fwohci_softc *sc = arg; 648 u_int32_t val; 649 650 callout_stop(&sc->sc_selfid_callout); 651 /* disable all interrupt */ 652 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 653 fwohci_buf_stop_tx(sc); 654 fwohci_buf_stop_rx(sc); 655 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 656 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 657 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 658 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 659 fwohci_phy_busreset(sc); 660 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 661 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 662 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 663 } 664 665 /* 666 * COMMON FUNCTIONS 667 */ 668 669 /* 670 * read the PHY Register. 671 */ 672 static u_int8_t 673 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 674 { 675 int i; 676 u_int32_t val; 677 678 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 679 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 680 for (i = 0; i < OHCI_LOOP; i++) { 681 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 682 OHCI_PhyControl_RdDone) 683 break; 684 DELAY(10); 685 } 686 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 687 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 688 } 689 690 /* 691 * write the PHY Register. 692 */ 693 static void 694 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 695 { 696 int i; 697 698 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 699 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 700 (val << OHCI_PhyControl_WrData_BITPOS)); 701 for (i = 0; i < OHCI_LOOP; i++) { 702 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 703 OHCI_PhyControl_WrReg)) 704 break; 705 DELAY(10); 706 } 707 } 708 709 /* 710 * Initiate Bus Reset 711 */ 712 static void 713 fwohci_phy_busreset(struct fwohci_softc *sc) 714 { 715 int s; 716 u_int8_t val; 717 718 s = splbio(); 719 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 720 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 721 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 722 callout_stop(&sc->sc_selfid_callout); 723 val = fwohci_phy_read(sc, 1); 724 val = (val & 0x80) | /* preserve RHB (force root) */ 725 0x40 | /* Initiate Bus Reset */ 726 0x3f; /* default GAP count */ 727 fwohci_phy_write(sc, 1, val); 728 splx(s); 729 } 730 731 /* 732 * PHY Packet 733 */ 734 static void 735 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 736 { 737 u_int32_t val; 738 739 val = pkt->fp_hdr[1]; 740 if (val != ~pkt->fp_hdr[2]) { 741 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 742 OHCI_CTXCTL_EVENT_BUS_RESET) { 743 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 744 pkt->fp_hdr[2])); 745 } else { 746 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 747 sc->sc_sc1394.sc1394_dev.dv_xname, val, 748 pkt->fp_hdr[2]); 749 } 750 return; 751 } 752 #ifdef FW_DEBUG 753 if (fwdebug > 1) 754 fwohci_show_phypkt(sc, val); 755 #endif 756 } 757 758 /* 759 * Descriptor for context DMA. 760 */ 761 static int 762 fwohci_desc_alloc(struct fwohci_softc *sc) 763 { 764 int error, mapsize, dsize; 765 766 /* 767 * allocate descriptor buffer 768 */ 769 770 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 771 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 772 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 773 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 774 mapsize = howmany(sc->sc_descsize, NBBY); 775 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 776 memset(sc->sc_descmap, 0, mapsize); 777 778 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 779 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 780 printf("%s: unable to allocate descriptor buffer, error = %d\n", 781 sc->sc_sc1394.sc1394_dev.dv_xname, error); 782 goto fail_0; 783 } 784 785 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 786 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 787 != 0) { 788 printf("%s: unable to map descriptor buffer, error = %d\n", 789 sc->sc_sc1394.sc1394_dev.dv_xname, error); 790 goto fail_1; 791 } 792 793 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 794 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 795 printf("%s: unable to create descriptor buffer DMA map, " 796 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 797 goto fail_2; 798 } 799 800 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 801 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 802 printf("%s: unable to load descriptor buffer DMA map, " 803 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 804 goto fail_3; 805 } 806 807 return 0; 808 809 fail_3: 810 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 811 fail_2: 812 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 815 fail_0: 816 return error; 817 } 818 819 static struct fwohci_desc * 820 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 821 { 822 int i, n; 823 824 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 825 for (i = 0; ; i++) { 826 if (i == ndesc) { 827 for (i = 0; i < ndesc; i++) 828 setbit(sc->sc_descmap, n + i); 829 return sc->sc_desc + n; 830 } 831 if (isset(sc->sc_descmap, n + i)) 832 break; 833 } 834 } 835 return NULL; 836 } 837 838 static void 839 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 840 { 841 int i, n; 842 843 n = fd - sc->sc_desc; 844 for (i = 0; i < ndesc; i++, n++) { 845 #ifdef DIAGNOSTIC 846 if (isclr(sc->sc_descmap, n)) 847 panic("fwohci_desc_put: duplicated free"); 848 #endif 849 clrbit(sc->sc_descmap, n); 850 } 851 } 852 853 /* 854 * Asyncronous/Isochronous Transmit/Receive Context 855 */ 856 static int 857 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 858 int bufcnt, int ctx) 859 { 860 int i, error; 861 struct fwohci_ctx *fc; 862 struct fwohci_buf *fb; 863 struct fwohci_desc *fd; 864 865 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 866 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 867 LIST_INIT(&fc->fc_handler); 868 TAILQ_INIT(&fc->fc_buf); 869 fc->fc_ctx = ctx; 870 fc->fc_bufcnt = bufcnt; 871 fb = (struct fwohci_buf *)&fc[1]; 872 for (i = 0; i < bufcnt; i++, fb++) { 873 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 874 goto fail; 875 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 876 error = ENOBUFS; 877 goto fail; 878 } 879 fb->fb_desc = fd; 880 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 881 ((caddr_t)fd - (caddr_t)sc->sc_desc); 882 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 883 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 884 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 885 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 886 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 887 } 888 *fcp = fc; 889 return 0; 890 891 fail: 892 while (i-- > 0) { 893 fb--; 894 if (fb->fb_desc) 895 fwohci_desc_put(sc, fb->fb_desc, 1); 896 fwohci_buf_free(sc, fb); 897 } 898 free(fc, M_DEVBUF); 899 return error; 900 } 901 902 static void 903 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 904 { 905 struct fwohci_buf *fb; 906 struct fwohci_handler *fh; 907 908 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 909 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 910 NULL, NULL); 911 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 912 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 913 if (fb->fb_desc) 914 fwohci_desc_put(sc, fb->fb_desc, 1); 915 fwohci_buf_free(sc, fb); 916 } 917 free(fc, M_DEVBUF); 918 } 919 920 static void 921 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 922 { 923 struct fwohci_buf *fb, *nfb; 924 struct fwohci_desc *fd; 925 struct fwohci_handler *fh; 926 int n; 927 928 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 929 nfb = TAILQ_NEXT(fb, fb_list); 930 fb->fb_off = 0; 931 fd = fb->fb_desc; 932 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 933 fd->fd_rescount = fd->fd_reqcount; 934 } 935 936 n = fc->fc_ctx; 937 fb = TAILQ_FIRST(&fc->fc_buf); 938 if (fc->fc_isoch) { 939 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 940 fb->fb_daddr | 1); 941 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 942 OHCI_CTXCTL_RX_BUFFER_FILL | 943 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 944 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 945 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 946 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 947 OHCI_CTXCTL_RX_ISOCH_HEADER); 948 fh = LIST_FIRST(&fc->fc_handler); 949 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 950 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 951 } else { 952 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 953 fb->fb_daddr | 1); 954 } 955 } 956 957 /* 958 * DMA data buffer 959 */ 960 static int 961 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 962 { 963 int error; 964 965 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 966 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 967 printf("%s: unable to allocate buffer, error = %d\n", 968 sc->sc_sc1394.sc1394_dev.dv_xname, error); 969 goto fail_0; 970 } 971 972 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 973 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 974 printf("%s: unable to map buffer, error = %d\n", 975 sc->sc_sc1394.sc1394_dev.dv_xname, error); 976 goto fail_1; 977 } 978 979 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 980 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 981 printf("%s: unable to create buffer DMA map, " 982 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 983 error); 984 goto fail_2; 985 } 986 987 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 988 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 989 printf("%s: unable to load buffer DMA map, " 990 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 991 error); 992 goto fail_3; 993 } 994 995 return 0; 996 997 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 998 fail_3: 999 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1000 fail_2: 1001 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1002 fail_1: 1003 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1004 fail_0: 1005 return error; 1006 } 1007 1008 static void 1009 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1010 { 1011 1012 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1013 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1014 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1015 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1016 } 1017 1018 static void 1019 fwohci_buf_init_rx(struct fwohci_softc *sc) 1020 { 1021 int i; 1022 1023 /* 1024 * Initialize for Asynchronous Receive Queue. 1025 */ 1026 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1027 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1028 1029 /* 1030 * Initialize for Isochronous Receive Queue. 1031 */ 1032 for (i = 0; i < sc->sc_isoctx; i++) { 1033 if (sc->sc_ctx_ir[i] != NULL) 1034 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1035 } 1036 } 1037 1038 static void 1039 fwohci_buf_start_rx(struct fwohci_softc *sc) 1040 { 1041 int i; 1042 1043 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1044 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1045 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1046 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1047 for (i = 0; i < sc->sc_isoctx; i++) { 1048 if (sc->sc_ctx_ir[i] != NULL) 1049 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1050 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1051 } 1052 } 1053 1054 static void 1055 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1056 { 1057 int i; 1058 1059 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1060 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1061 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1062 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1063 1064 /* 1065 * Make sure the transmitter is stopped. 1066 */ 1067 for (i = 0; i < OHCI_LOOP; i++) { 1068 DELAY(10); 1069 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1070 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1071 continue; 1072 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1073 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1074 continue; 1075 break; 1076 } 1077 1078 /* 1079 * Initialize for Asynchronous Transmit Queue. 1080 */ 1081 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1082 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1083 } 1084 1085 static void 1086 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1087 { 1088 int i; 1089 1090 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1091 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1092 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1093 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1094 for (i = 0; i < sc->sc_isoctx; i++) { 1095 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1096 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1097 } 1098 } 1099 1100 static void 1101 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1102 { 1103 struct fwohci_buf *fb, *tfb; 1104 1105 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1106 if (fc->fc_isoch) { 1107 if (fb->fb_off == 0) 1108 break; 1109 } else { 1110 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1111 fb->fb_desc->fd_rescount != 0) 1112 break; 1113 } 1114 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1115 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1116 fb->fb_off = 0; 1117 fb->fb_desc->fd_branch = 0; 1118 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1119 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1120 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1121 } 1122 } 1123 1124 static int 1125 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 1126 int len) 1127 { 1128 struct fwohci_buf *fb; 1129 struct fwohci_desc *fd; 1130 int bufend; 1131 1132 fb = TAILQ_FIRST(&fc->fc_buf); 1133 again: 1134 fd = fb->fb_desc; 1135 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1136 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1137 fd->fd_reqcount, fd->fd_rescount, len, 1138 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1139 bufend = fd->fd_reqcount - fd->fd_rescount; 1140 if (fb->fb_off >= bufend) { 1141 if (fd->fd_rescount == 0) { 1142 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 1143 goto again; 1144 } 1145 return 0; 1146 } 1147 if (fb->fb_off + len > bufend) 1148 len = bufend - fb->fb_off; 1149 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1150 BUS_DMASYNC_POSTREAD); 1151 *pp = fb->fb_buf + fb->fb_off; 1152 fb->fb_off += roundup(len, 4); 1153 return len; 1154 } 1155 1156 static int 1157 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1158 struct fwohci_pkt *pkt) 1159 { 1160 caddr_t p; 1161 int len, count, i; 1162 1163 memset(pkt, 0, sizeof(*pkt)); 1164 pkt->fp_uio.uio_iov = pkt->fp_iov; 1165 pkt->fp_uio.uio_rw = UIO_WRITE; 1166 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1167 1168 /* get first quadlet */ 1169 count = 4; 1170 len = fwohci_buf_pktget(sc, fc, &p, count); 1171 if (len <= 0) { 1172 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1173 fc->fc_ctx)); 1174 return 0; 1175 } 1176 pkt->fp_hdr[0] = *(u_int32_t *)p; 1177 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1178 switch (pkt->fp_tcode) { 1179 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1180 case IEEE1394_TCODE_READ_RESP_QUAD: 1181 pkt->fp_hlen = 12; 1182 pkt->fp_dlen = 4; 1183 break; 1184 case IEEE1394_TCODE_READ_REQ_BLOCK: 1185 pkt->fp_hlen = 16; 1186 pkt->fp_dlen = 0; 1187 break; 1188 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1189 case IEEE1394_TCODE_READ_RESP_BLOCK: 1190 case IEEE1394_TCODE_LOCK_REQ: 1191 case IEEE1394_TCODE_LOCK_RESP: 1192 pkt->fp_hlen = 16; 1193 break; 1194 #ifdef DIAGNOSTICS 1195 case IEEE1394_TCODE_STREAM_DATA: 1196 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1197 return 0; 1198 #endif 1199 default: 1200 pkt->fp_hlen = 12; 1201 pkt->fp_dlen = 0; 1202 break; 1203 } 1204 1205 /* get header */ 1206 while (count < pkt->fp_hlen) { 1207 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 1208 if (len == 0) { 1209 printf("fwohci_buf_input: malformed input 1: %d\n", 1210 pkt->fp_hlen - count); 1211 return 0; 1212 } 1213 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1214 count += len; 1215 } 1216 if (pkt->fp_hlen == 16 && 1217 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1218 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1219 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1220 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1221 1222 /* get data */ 1223 count = 0; 1224 i = 0; 1225 while (count < pkt->fp_dlen) { 1226 len = fwohci_buf_pktget(sc, fc, 1227 (caddr_t *)&pkt->fp_iov[i].iov_base, 1228 pkt->fp_dlen - count); 1229 if (len == 0) { 1230 printf("fwohci_buf_input: malformed input 2: %d\n", 1231 pkt->fp_dlen - count); 1232 return 0; 1233 } 1234 pkt->fp_iov[i++].iov_len = len; 1235 count += len; 1236 } 1237 pkt->fp_uio.uio_iovcnt = i; 1238 pkt->fp_uio.uio_resid = count; 1239 1240 /* get trailer */ 1241 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 1242 sizeof(*pkt->fp_trail)); 1243 if (len <= 0) { 1244 printf("fwohci_buf_input: malformed input 3: %d\n", 1245 pkt->fp_hlen - count); 1246 return 0; 1247 } 1248 return 1; 1249 } 1250 1251 static int 1252 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1253 struct fwohci_pkt *pkt) 1254 { 1255 caddr_t p; 1256 int len; 1257 struct fwohci_buf *fb; 1258 struct fwohci_desc *fd; 1259 1260 memset(pkt, 0, sizeof(*pkt)); 1261 pkt->fp_uio.uio_iov = pkt->fp_iov; 1262 pkt->fp_uio.uio_rw = UIO_WRITE; 1263 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1264 1265 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1266 if (fb == NULL) 1267 return 0; 1268 if (fb->fb_off == 0) 1269 break; 1270 } 1271 fd = fb->fb_desc; 1272 len = fd->fd_reqcount - fd->fd_rescount; 1273 if (len == 0) 1274 return 0; 1275 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1276 BUS_DMASYNC_POSTREAD); 1277 1278 p = fb->fb_buf; 1279 fb->fb_off += roundup(len, 4); 1280 if (len < 8) { 1281 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1282 return 0; 1283 } 1284 1285 /* 1286 * get trailer first, may be bogus data unless status update 1287 * in descriptor is set. 1288 */ 1289 pkt->fp_trail = (u_int32_t *)p; 1290 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1291 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1292 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1293 #ifdef DIAGNOSTICS 1294 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1295 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1296 pkt->fp_tcode); 1297 return 0; 1298 } 1299 #endif 1300 pkt->fp_hlen = 4; 1301 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1302 p += 8; 1303 len -= 8; 1304 if (pkt->fp_dlen != len) { 1305 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1306 pkt->fp_dlen, len); 1307 return 0; 1308 } 1309 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1310 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1311 pkt->fp_iov[0].iov_base = p; 1312 pkt->fp_iov[0].iov_len = len; 1313 pkt->fp_uio.uio_iovcnt = 0; 1314 pkt->fp_uio.uio_resid = len; 1315 return 1; 1316 } 1317 1318 static int 1319 fwohci_handler_set(struct fwohci_softc *sc, 1320 int tcode, u_int32_t key1, u_int32_t key2, 1321 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1322 void *arg) 1323 { 1324 struct fwohci_ctx *fc; 1325 struct fwohci_handler *fh; 1326 int i, j; 1327 1328 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1329 j = sc->sc_isoctx; 1330 fh = NULL; 1331 for (i = 0; i < sc->sc_isoctx; i++) { 1332 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1333 if (j == sc->sc_isoctx) 1334 j = i; 1335 continue; 1336 } 1337 fh = LIST_FIRST(&fc->fc_handler); 1338 if (fh->fh_tcode == tcode && 1339 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1340 break; 1341 fh = NULL; 1342 } 1343 if (fh == NULL) { 1344 if (handler == NULL) 1345 return 0; 1346 if (j == sc->sc_isoctx) { 1347 DPRINTF(("fwohci_handler_set: no more free " 1348 "context\n")); 1349 return ENOMEM; 1350 } 1351 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1352 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1353 fc->fc_isoch = 1; 1354 sc->sc_ctx_ir[j] = fc; 1355 } 1356 } 1357 } else { 1358 switch (tcode) { 1359 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1360 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1361 case IEEE1394_TCODE_READ_REQ_QUAD: 1362 case IEEE1394_TCODE_READ_REQ_BLOCK: 1363 case IEEE1394_TCODE_LOCK_REQ: 1364 fc = sc->sc_ctx_arrq; 1365 break; 1366 case IEEE1394_TCODE_WRITE_RESP: 1367 case IEEE1394_TCODE_READ_RESP_QUAD: 1368 case IEEE1394_TCODE_READ_RESP_BLOCK: 1369 case IEEE1394_TCODE_LOCK_RESP: 1370 fc = sc->sc_ctx_arrs; 1371 break; 1372 default: 1373 return EIO; 1374 } 1375 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1376 fh = LIST_NEXT(fh, fh_list)) { 1377 if (fh->fh_tcode == tcode && 1378 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1379 break; 1380 } 1381 } 1382 if (handler == NULL) { 1383 if (fh != NULL) { 1384 LIST_REMOVE(fh, fh_list); 1385 free(fh, M_DEVBUF); 1386 } 1387 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1388 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1389 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1390 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1391 fwohci_ctx_free(sc, fc); 1392 } 1393 return 0; 1394 } 1395 if (fh == NULL) { 1396 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1397 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1398 } 1399 fh->fh_tcode = tcode; 1400 fh->fh_key1 = key1; 1401 fh->fh_key2 = key2; 1402 fh->fh_handler = handler; 1403 fh->fh_handarg = arg; 1404 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1405 fc->fc_ctx, tcode, key1, key2)); 1406 1407 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1408 fwohci_ctx_init(sc, fc); 1409 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1410 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1411 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1412 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1413 } 1414 return 0; 1415 } 1416 1417 /* 1418 * Asyncronous Receive Requests input frontend. 1419 */ 1420 static void 1421 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1422 { 1423 int rcode; 1424 u_int32_t key1, key2; 1425 struct fwohci_handler *fh; 1426 struct fwohci_pkt pkt, res; 1427 1428 /* 1429 * Do not return if next packet is in the buffer, or the next 1430 * packet cannot be received until the next receive interrupt. 1431 */ 1432 while (fwohci_buf_input(sc, fc, &pkt)) { 1433 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1434 fwohci_phy_input(sc, &pkt); 1435 continue; 1436 } 1437 key1 = pkt.fp_hdr[1] & 0xffff; 1438 key2 = pkt.fp_hdr[2]; 1439 memset(&res, 0, sizeof(res)); 1440 res.fp_uio.uio_rw = UIO_WRITE; 1441 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1442 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1443 fh = LIST_NEXT(fh, fh_list)) { 1444 if (pkt.fp_tcode == fh->fh_tcode && 1445 key1 == fh->fh_key1 && 1446 key2 == fh->fh_key2) { 1447 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1448 &pkt); 1449 break; 1450 } 1451 } 1452 if (fh == NULL) { 1453 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1454 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1455 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1456 key2)); 1457 } 1458 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1459 OHCI_CTXCTL_EVENT_ACK_PENDING) 1460 continue; 1461 if (rcode != -1) 1462 fwohci_atrs_output(sc, rcode, &pkt, &res); 1463 } 1464 fwohci_buf_next(sc, fc); 1465 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1466 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1467 } 1468 1469 1470 /* 1471 * Asynchronous Receive Response input frontend. 1472 */ 1473 static void 1474 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1475 { 1476 struct fwohci_pkt pkt; 1477 struct fwohci_handler *fh; 1478 u_int16_t srcid; 1479 int rcode, tlabel; 1480 1481 while (fwohci_buf_input(sc, fc, &pkt)) { 1482 srcid = pkt.fp_hdr[1] >> 16; 1483 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1484 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1485 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1486 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1487 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1488 pkt.fp_dlen)); 1489 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1490 fh = LIST_NEXT(fh, fh_list)) { 1491 if (pkt.fp_tcode == fh->fh_tcode && 1492 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1493 tlabel == fh->fh_key2) { 1494 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1495 LIST_REMOVE(fh, fh_list); 1496 free(fh, M_DEVBUF); 1497 break; 1498 } 1499 } 1500 if (fh == NULL) 1501 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1502 } 1503 fwohci_buf_next(sc, fc); 1504 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1505 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1506 } 1507 1508 /* 1509 * Isochronous Receive input frontend. 1510 */ 1511 static void 1512 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1513 { 1514 int rcode, chan, tag; 1515 struct iovec *iov; 1516 struct fwohci_handler *fh; 1517 struct fwohci_pkt pkt; 1518 1519 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 1520 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1521 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1522 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1523 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1524 pkt.fp_dlen)); 1525 if (tag == IEEE1394_TAG_GASP) { 1526 /* 1527 * The pkt with tag=3 is GASP format. 1528 * Move GASP header to header part. 1529 */ 1530 if (pkt.fp_dlen < 8) 1531 continue; 1532 iov = pkt.fp_iov; 1533 /* assuming pkt per buffer mode */ 1534 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1535 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1536 iov->iov_base = (caddr_t)iov->iov_base + 8; 1537 iov->iov_len -= 8; 1538 pkt.fp_hlen += 8; 1539 pkt.fp_dlen -= 8; 1540 } 1541 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1542 fh = LIST_NEXT(fh, fh_list)) { 1543 if (pkt.fp_tcode == fh->fh_tcode && 1544 chan == fh->fh_key1 && tag == fh->fh_key2) { 1545 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1546 &pkt); 1547 break; 1548 } 1549 } 1550 #ifdef FW_DEBUG 1551 if (fh == NULL) { 1552 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1553 } else { 1554 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1555 } 1556 #endif 1557 } 1558 fwohci_buf_next(sc, fc); 1559 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1560 OHCI_CTXCTL_WAKE); 1561 } 1562 1563 /* 1564 * Asynchronous Transmit common routine. 1565 */ 1566 static int 1567 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1568 struct fwohci_pkt *pkt) 1569 { 1570 struct fwohci_buf *fb; 1571 struct fwohci_desc *fd; 1572 struct mbuf *m, *m0; 1573 int i, ndesc, error, off, len; 1574 u_int32_t val; 1575 #ifdef FW_DEBUG 1576 struct iovec *iov; 1577 #endif 1578 1579 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 1580 /* We can't send anything during selfid duration */ 1581 return EAGAIN; 1582 1583 #ifdef FW_DEBUG 1584 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1585 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1586 for (i = 0; i < pkt->fp_hlen/4; i++) 1587 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 1588 DPRINTFN(2, ("$")); 1589 for (ndesc = 0, iov = pkt->fp_iov; 1590 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1591 for (i = 0; i < iov->iov_len; i++) 1592 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 1593 ((u_int8_t *)iov->iov_base)[i])); 1594 DPRINTFN(2, ("$")); 1595 } 1596 DPRINTFN(1, ("\n")); 1597 #endif 1598 1599 if ((m = pkt->fp_m) != NULL) { 1600 for (ndesc = 2; m != NULL; m = m->m_next) 1601 ndesc++; 1602 if (ndesc > OHCI_DESC_MAX) { 1603 m0 = NULL; 1604 ndesc = 2; 1605 for (off = 0; off < pkt->fp_dlen; off += len) { 1606 if (m0 == NULL) { 1607 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1608 if (m0 != NULL) 1609 M_COPY_PKTHDR(m0, pkt->fp_m); 1610 m = m0; 1611 } else { 1612 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1613 m = m->m_next; 1614 } 1615 if (m != NULL) 1616 MCLGET(m, M_DONTWAIT); 1617 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1618 m_freem(m0); 1619 return ENOMEM; 1620 } 1621 len = pkt->fp_dlen - off; 1622 if (len > m->m_ext.ext_size) 1623 len = m->m_ext.ext_size; 1624 m_copydata(pkt->fp_m, off, len, 1625 mtod(m, caddr_t)); 1626 m->m_len = len; 1627 ndesc++; 1628 } 1629 m_freem(pkt->fp_m); 1630 pkt->fp_m = m0; 1631 } 1632 } else 1633 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1634 1635 if (ndesc > OHCI_DESC_MAX) 1636 return ENOBUFS; 1637 1638 if (fc->fc_bufcnt > 50) /*XXX*/ 1639 return ENOBUFS; 1640 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1641 fb->fb_nseg = ndesc; 1642 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1643 if (fb->fb_desc == NULL) { 1644 free(fb, M_DEVBUF); 1645 return ENOBUFS; 1646 } 1647 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1648 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1649 fb->fb_m = pkt->fp_m; 1650 fb->fb_callback = pkt->fp_callback; 1651 fb->fb_statuscb = pkt->fp_statuscb; 1652 fb->fb_statusarg = pkt->fp_statusarg; 1653 1654 if (ndesc > 2) { 1655 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1656 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1657 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1658 free(fb, M_DEVBUF); 1659 return error; 1660 } 1661 1662 if (pkt->fp_m != NULL) 1663 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1664 pkt->fp_m, BUS_DMA_WAITOK); 1665 else 1666 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1667 &pkt->fp_uio, BUS_DMA_WAITOK); 1668 if (error != 0) { 1669 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1670 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1671 free(fb, M_DEVBUF); 1672 return error; 1673 } 1674 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1675 BUS_DMASYNC_PREWRITE); 1676 } 1677 1678 fd = fb->fb_desc; 1679 fd->fd_flags = OHCI_DESC_IMMED; 1680 fd->fd_reqcount = pkt->fp_hlen; 1681 fd->fd_data = 0; 1682 fd->fd_branch = 0; 1683 fd->fd_status = 0; 1684 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1685 i = 3; /* XXX: 3 sec */ 1686 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1687 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1688 ((((val >> 25) + i) & 0x7) << 13); 1689 } else 1690 fd->fd_timestamp = 0; 1691 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1692 for (i = 0; i < ndesc - 2; i++) { 1693 fd = fb->fb_desc + 2 + i; 1694 fd->fd_flags = 0; 1695 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1696 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1697 fd->fd_branch = 0; 1698 fd->fd_status = 0; 1699 fd->fd_timestamp = 0; 1700 } 1701 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1702 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1703 1704 #ifdef FW_DEBUG 1705 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1706 (long)(fb->fb_desc - sc->sc_desc))); 1707 for (i = 0; i < ndesc * 4; i++) 1708 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1709 ((u_int32_t *)fb->fb_desc)[i])); 1710 DPRINTFN(1, ("\n")); 1711 #endif 1712 1713 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1714 OHCI_SUBREG_ContextControlClear); 1715 1716 if (val & OHCI_CTXCTL_RUN) { 1717 if (fc->fc_branch == NULL) { 1718 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1719 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1720 goto run; 1721 } 1722 *fc->fc_branch = fb->fb_daddr | ndesc; 1723 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1724 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1725 } else { 1726 run: 1727 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1728 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1729 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1730 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1731 } 1732 fc->fc_branch = &fd->fd_branch; 1733 1734 fc->fc_bufcnt++; 1735 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1736 pkt->fp_m = NULL; 1737 return 0; 1738 } 1739 1740 static void 1741 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1742 { 1743 struct fwohci_buf *fb; 1744 struct fwohci_desc *fd; 1745 struct fwohci_pkt pkt; 1746 int i; 1747 1748 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1749 fd = fb->fb_desc; 1750 #ifdef FW_DEBUG 1751 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1752 force ? "force " : "", (long)(fd - sc->sc_desc), 1753 fb->fb_nseg)); 1754 for (i = 0; i < fb->fb_nseg * 4; i++) 1755 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1756 ((u_int32_t *)fd)[i])); 1757 DPRINTFN(1, ("\n")); 1758 #endif 1759 if (fb->fb_nseg > 2) 1760 fd += fb->fb_nseg - 1; 1761 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1762 break; 1763 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1764 if (fc->fc_branch == &fd->fd_branch) { 1765 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1766 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1767 fc->fc_branch = NULL; 1768 for (i = 0; i < OHCI_LOOP; i++) { 1769 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1770 OHCI_SUBREG_ContextControlClear) & 1771 OHCI_CTXCTL_ACTIVE)) 1772 break; 1773 DELAY(10); 1774 } 1775 } 1776 1777 if (fb->fb_statuscb) { 1778 memset(&pkt, 0, sizeof(pkt)); 1779 pkt.fp_status = fd->fd_status; 1780 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1781 1782 /* Indicate this is just returning the status bits. */ 1783 pkt.fp_tcode = -1; 1784 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1785 fb->fb_statuscb = NULL; 1786 fb->fb_statusarg = NULL; 1787 } 1788 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1789 if (fb->fb_nseg > 2) 1790 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1791 fc->fc_bufcnt--; 1792 if (fb->fb_callback) { 1793 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1794 fb->fb_callback = NULL; 1795 } else if (fb->fb_m != NULL) 1796 m_freem(fb->fb_m); 1797 free(fb, M_DEVBUF); 1798 } 1799 } 1800 1801 /* 1802 * Asynchronous Transmit Reponse -- in response of request packet. 1803 */ 1804 static void 1805 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1806 struct fwohci_pkt *res) 1807 { 1808 1809 if (((*req->fp_trail & 0x001f0000) >> 16) != 1810 OHCI_CTXCTL_EVENT_ACK_PENDING) 1811 return; 1812 1813 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1814 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1815 switch (req->fp_tcode) { 1816 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1817 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1818 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1819 res->fp_hlen = 12; 1820 break; 1821 case IEEE1394_TCODE_READ_REQ_QUAD: 1822 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1823 res->fp_hlen = 16; 1824 res->fp_dlen = 0; 1825 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1826 res->fp_hdr[3] = 1827 *(u_int32_t *)res->fp_iov[0].iov_base; 1828 res->fp_uio.uio_iovcnt = 0; 1829 break; 1830 case IEEE1394_TCODE_READ_REQ_BLOCK: 1831 case IEEE1394_TCODE_LOCK_REQ: 1832 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1833 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1834 else 1835 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1836 res->fp_hlen = 16; 1837 res->fp_dlen = res->fp_uio.uio_resid; 1838 res->fp_hdr[3] = res->fp_dlen << 16; 1839 break; 1840 } 1841 res->fp_hdr[0] |= (res->fp_tcode << 4); 1842 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1843 } 1844 1845 /* 1846 * APPLICATION LAYER SERVICES 1847 */ 1848 1849 /* 1850 * Retrieve Global UID from GUID ROM 1851 */ 1852 static int 1853 fwohci_guidrom_init(struct fwohci_softc *sc) 1854 { 1855 int i, n, off; 1856 u_int32_t val1, val2; 1857 1858 /* Extract the Global UID 1859 */ 1860 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1861 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1862 1863 if (val1 != 0 || val2 != 0) { 1864 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1865 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1866 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1867 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1868 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1869 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1870 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1871 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1872 } else { 1873 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1874 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1875 return -1; 1876 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1877 for (i = 0; i < OHCI_LOOP; i++) { 1878 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1879 if (!(val1 & OHCI_Guid_AddrReset)) 1880 break; 1881 DELAY(10); 1882 } 1883 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1884 val2 = 0; 1885 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1886 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1887 OHCI_Guid_RdStart); 1888 for (i = 0; i < OHCI_LOOP; i++) { 1889 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1890 if (!(val1 & OHCI_Guid_RdStart)) 1891 break; 1892 DELAY(10); 1893 } 1894 if (n < off) 1895 continue; 1896 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1897 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1898 val2 |= val1; 1899 } 1900 if (val2 == 0) 1901 return -1; 1902 } 1903 return 0; 1904 } 1905 1906 /* 1907 * Initialization for Configuration ROM (no DMA context) 1908 */ 1909 1910 #define CFR_MAXUNIT 20 1911 1912 struct configromctx { 1913 u_int32_t *ptr; 1914 int curunit; 1915 struct { 1916 u_int32_t *start; 1917 int length; 1918 u_int32_t *refer; 1919 int refunit; 1920 } unit[CFR_MAXUNIT]; 1921 }; 1922 1923 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1924 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1925 1926 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1927 1928 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1929 1930 #define CFR_PUT_CRC(cfr, n) \ 1931 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1932 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1933 1934 #define CFR_START_UNIT(cfr, n) \ 1935 do { \ 1936 if ((cfr)->unit[n].refer != NULL) { \ 1937 *(cfr)->unit[n].refer |= \ 1938 (cfr)->ptr - (cfr)->unit[n].refer; \ 1939 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1940 } \ 1941 (cfr)->curunit = (n); \ 1942 (cfr)->unit[n].start = (cfr)->ptr++; \ 1943 } while (0 /* CONSTCOND */) 1944 1945 #define CFR_PUT_REFER(cfr, key, n) \ 1946 do { \ 1947 (cfr)->unit[n].refer = (cfr)->ptr; \ 1948 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1949 *(cfr)->ptr++ = (key) << 24; \ 1950 } while (0 /* CONSTCOND */) 1951 1952 #define CFR_END_UNIT(cfr) \ 1953 do { \ 1954 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1955 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1956 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1957 } while (0 /* CONSTCOND */) 1958 1959 static u_int16_t 1960 fwohci_crc16(u_int32_t *ptr, int len) 1961 { 1962 int shift; 1963 u_int32_t crc, sum, data; 1964 1965 crc = 0; 1966 while (len-- > 0) { 1967 data = *ptr++; 1968 for (shift = 28; shift >= 0; shift -= 4) { 1969 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1970 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1971 } 1972 crc &= 0xffff; 1973 } 1974 return crc; 1975 } 1976 1977 static void 1978 fwohci_configrom_init(struct fwohci_softc *sc) 1979 { 1980 int i, val; 1981 struct fwohci_buf *fb; 1982 u_int32_t *hdr; 1983 struct configromctx cfr; 1984 1985 fb = &sc->sc_buf_cnfrom; 1986 memset(&cfr, 0, sizeof(cfr)); 1987 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1988 1989 /* headers */ 1990 CFR_START_UNIT(&cfr, 0); 1991 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1992 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1993 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1994 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1995 CFR_END_UNIT(&cfr); 1996 /* copy info_length from crc_length */ 1997 *hdr |= (*hdr & 0x00ff0000) << 8; 1998 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1999 2000 /* root directory */ 2001 CFR_START_UNIT(&cfr, 1); 2002 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2003 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2004 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2005 /* spt,64,fix,lst,drq */ 2006 #ifdef INET 2007 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2008 #endif /* INET */ 2009 #ifdef INET6 2010 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2011 #endif /* INET6 */ 2012 CFR_END_UNIT(&cfr); 2013 2014 CFR_START_UNIT(&cfr, 2); 2015 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2016 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2017 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2018 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2019 CFR_END_UNIT(&cfr); 2020 2021 #ifdef INET 2022 /* IPv4 unit directory */ 2023 CFR_START_UNIT(&cfr, 3); 2024 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2025 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2026 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2027 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2028 CFR_END_UNIT(&cfr); 2029 2030 CFR_START_UNIT(&cfr, 6); 2031 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2032 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2033 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2034 CFR_END_UNIT(&cfr); 2035 2036 CFR_START_UNIT(&cfr, 7); 2037 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2038 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2039 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2040 CFR_END_UNIT(&cfr); 2041 #endif /* INET */ 2042 2043 #ifdef INET6 2044 /* IPv6 unit directory */ 2045 CFR_START_UNIT(&cfr, 4); 2046 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2047 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2048 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2049 /* XXX: TBA by IANA */ 2050 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2051 CFR_END_UNIT(&cfr); 2052 2053 CFR_START_UNIT(&cfr, 8); 2054 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2055 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2056 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2057 CFR_END_UNIT(&cfr); 2058 2059 CFR_START_UNIT(&cfr, 9); 2060 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2061 CFR_PUT_DATA1(&cfr, 0); 2062 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2063 CFR_END_UNIT(&cfr); 2064 #endif /* INET6 */ 2065 2066 fb->fb_off = cfr.ptr - hdr; 2067 #ifdef FW_DEBUG 2068 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2069 for (i = 0; i < fb->fb_off; i++) 2070 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2071 DPRINTFN(2, ("\n")); 2072 #endif /* FW_DEBUG */ 2073 2074 /* 2075 * Make network byte order for DMA 2076 */ 2077 for (i = 0; i < fb->fb_off; i++) 2078 HTONL(hdr[i]); 2079 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2080 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2081 2082 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2083 fb->fb_dmamap->dm_segs[0].ds_addr); 2084 2085 /* This register is only valid on OHCI 1.1. */ 2086 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2087 if ((OHCI_Version_GET_Version(val) == 1) && 2088 (OHCI_Version_GET_Revision(val) == 1)) 2089 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2090 OHCI_HCControl_BIBImageValid); 2091 2092 /* Just allow quad reads of the rom. */ 2093 for (i = 0; i < fb->fb_off; i++) 2094 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2095 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2096 fwohci_configrom_input, NULL); 2097 } 2098 2099 static int 2100 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2101 struct fwohci_pkt *pkt) 2102 { 2103 struct fwohci_pkt res; 2104 u_int32_t loc, *rom; 2105 2106 /* This will be used as an array index so size accordingly. */ 2107 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2108 if ((loc & 0x03) != 0) { 2109 /* alignment error */ 2110 return IEEE1394_RCODE_ADDRESS_ERROR; 2111 } 2112 else 2113 loc /= 4; 2114 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2115 2116 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2117 ntohl(rom[loc]))); 2118 2119 memset(&res, 0, sizeof(res)); 2120 res.fp_hdr[3] = rom[loc]; 2121 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2122 return -1; 2123 } 2124 2125 /* 2126 * SelfID buffer (no DMA context) 2127 */ 2128 static void 2129 fwohci_selfid_init(struct fwohci_softc *sc) 2130 { 2131 struct fwohci_buf *fb; 2132 2133 fb = &sc->sc_buf_selfid; 2134 #ifdef DIAGNOSTIC 2135 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2136 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2137 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2138 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2139 #endif 2140 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2141 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2142 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2143 2144 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2145 fb->fb_dmamap->dm_segs[0].ds_addr); 2146 } 2147 2148 static int 2149 fwohci_selfid_input(struct fwohci_softc *sc) 2150 { 2151 int i; 2152 u_int32_t count, val, gen; 2153 u_int32_t *buf; 2154 2155 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2156 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2157 again: 2158 if (val & OHCI_SelfID_Error) { 2159 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2160 return -1; 2161 } 2162 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2163 2164 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2165 0, count << 2, BUS_DMASYNC_POSTREAD); 2166 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2167 2168 #ifdef FW_DEBUG 2169 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2170 val)); 2171 for (i = 0; i < count; i++) 2172 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2173 DPRINTFN(1, ("\n")); 2174 #endif /* FW_DEBUG */ 2175 2176 for (i = 1; i < count; i += 2) { 2177 if (buf[i] != ~buf[i + 1]) 2178 break; 2179 if (buf[i] & 0x00000001) 2180 continue; /* more pkt */ 2181 if (buf[i] & 0x00800000) 2182 continue; /* external id */ 2183 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2184 if ((buf[i] & 0x00400800) == 0x00400800) 2185 sc->sc_irmid = sc->sc_rootid; 2186 } 2187 2188 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2189 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2190 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2191 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2192 goto again; 2193 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2194 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2195 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2196 return -1; 2197 } 2198 if (i != count) { 2199 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2200 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2201 #if 1 2202 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2203 /* 2204 * XXX: CXD3222 sometimes fails to DMA 2205 * selfid packet?? 2206 */ 2207 sc->sc_rootid = (count - 1) / 2 - 1; 2208 sc->sc_irmid = sc->sc_rootid; 2209 } else 2210 #endif 2211 return -1; 2212 } 2213 2214 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2215 if ((val & OHCI_NodeId_IDValid) == 0) { 2216 sc->sc_nodeid = 0xffff; /* invalid */ 2217 printf("%s: nodeid is invalid\n", 2218 sc->sc_sc1394.sc1394_dev.dv_xname); 2219 return -1; 2220 } 2221 sc->sc_nodeid = val & 0xffff; 2222 2223 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2224 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2225 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2226 sc->sc_irmid)); 2227 2228 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2229 return -1; 2230 2231 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2232 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2233 OHCI_LinkControl_CycleMaster); 2234 else 2235 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2236 OHCI_LinkControl_CycleMaster); 2237 return 0; 2238 } 2239 2240 /* 2241 * some CSRs are handled by driver. 2242 */ 2243 static void 2244 fwohci_csr_init(struct fwohci_softc *sc) 2245 { 2246 int i; 2247 static u_int32_t csr[] = { 2248 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2249 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2250 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2251 CSR_SB_BROADCAST_CHANNEL 2252 }; 2253 2254 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2255 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2256 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2257 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2258 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2259 } 2260 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2261 } 2262 2263 static int 2264 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2265 { 2266 struct fwohci_pkt res; 2267 u_int32_t reg; 2268 2269 /* 2270 * XXX need to do special functionality other than just r/w... 2271 */ 2272 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2273 2274 if ((reg & 0x03) != 0) { 2275 /* alignment error */ 2276 return IEEE1394_RCODE_ADDRESS_ERROR; 2277 } 2278 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2279 *(u_int32_t *)(&sc->sc_csr[reg]))); 2280 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2281 DPRINTFN(1, (" -> 0x%08x\n", 2282 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2283 *(u_int32_t *)&sc->sc_csr[reg] = 2284 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2285 } else { 2286 DPRINTFN(1, ("\n")); 2287 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2288 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2289 res.fp_iov[0].iov_len = 4; 2290 res.fp_uio.uio_resid = 4; 2291 res.fp_uio.uio_iovcnt = 1; 2292 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2293 return -1; 2294 } 2295 return IEEE1394_RCODE_COMPLETE; 2296 } 2297 2298 /* 2299 * Mapping between nodeid and unique ID (EUI-64). 2300 * 2301 * Track old mappings and simply update their devices with the new id's when 2302 * they match an existing EUI. This allows proper renumeration of the bus. 2303 */ 2304 static void 2305 fwohci_uid_collect(struct fwohci_softc *sc) 2306 { 2307 int i; 2308 struct fwohci_uidtbl *fu; 2309 struct ieee1394_softc *iea; 2310 2311 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2312 iea->sc1394_node_id = 0xffff; 2313 2314 if (sc->sc_uidtbl != NULL) 2315 free(sc->sc_uidtbl, M_DEVBUF); 2316 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2317 M_NOWAIT); /* XXX M_WAITOK requires locks */ 2318 if (sc->sc_uidtbl == NULL) 2319 return; 2320 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2321 2322 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2323 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2324 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2325 fu->fu_valid = 3; 2326 2327 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2328 if (iea) { 2329 iea->sc1394_node_id = i; 2330 DPRINTF(("%s: Updating nodeid to %d\n", 2331 iea->sc1394_dev.dv_xname, 2332 iea->sc1394_node_id)); 2333 } 2334 } else { 2335 fu->fu_valid = 0; 2336 fwohci_uid_req(sc, i); 2337 } 2338 } 2339 if (sc->sc_rootid == 0) 2340 fwohci_check_nodes(sc); 2341 } 2342 2343 static void 2344 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 2345 { 2346 struct fwohci_pkt pkt; 2347 2348 memset(&pkt, 0, sizeof(pkt)); 2349 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2350 pkt.fp_hlen = 12; 2351 pkt.fp_dlen = 0; 2352 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2353 (pkt.fp_tcode << 4); 2354 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 2355 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2356 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2357 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2358 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2359 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2360 2361 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2362 (pkt.fp_tcode << 4); 2363 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2364 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2365 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2366 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2367 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2368 } 2369 2370 static int 2371 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2372 { 2373 struct fwohci_uidtbl *fu; 2374 struct ieee1394_softc *iea; 2375 struct ieee1394_attach_args fwa; 2376 int i, n, done, rcode, found; 2377 2378 found = 0; 2379 2380 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2381 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2382 if (rcode != IEEE1394_RCODE_COMPLETE || 2383 sc->sc_uidtbl == NULL || 2384 n > sc->sc_rootid) 2385 return 0; 2386 fu = &sc->sc_uidtbl[n]; 2387 if (arg == 0) { 2388 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2389 fu->fu_valid |= 0x1; 2390 } else { 2391 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2392 fu->fu_valid |= 0x2; 2393 } 2394 #ifdef FW_DEBUG 2395 if (fu->fu_valid == 0x3) 2396 DPRINTFN(1, ("fwohci_uid_input: " 2397 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2398 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2399 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2400 #endif 2401 if (fu->fu_valid == 0x3) { 2402 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2403 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2404 found = 1; 2405 iea->sc1394_node_id = n; 2406 DPRINTF(("%s: Updating nodeid to %d\n", 2407 iea->sc1394_dev.dv_xname, 2408 iea->sc1394_node_id)); 2409 break; 2410 } 2411 if (!found) { 2412 strcpy(fwa.name, "fwnode"); 2413 memcpy(fwa.uid, fu->fu_uid, 8); 2414 fwa.nodeid = n; 2415 fwa.read = fwohci_read; 2416 fwa.write = fwohci_write; 2417 fwa.inreg = fwohci_inreg; 2418 iea = (struct ieee1394_softc *) 2419 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2420 fwohci_print, fwohci_submatch); 2421 if (iea != NULL) 2422 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2423 sc1394_node); 2424 } 2425 } 2426 done = 1; 2427 2428 for (i = 0; i < sc->sc_rootid + 1; i++) { 2429 fu = &sc->sc_uidtbl[i]; 2430 if (fu->fu_valid != 0x3) { 2431 done = 0; 2432 break; 2433 } 2434 } 2435 if (done) 2436 fwohci_check_nodes(sc); 2437 2438 return 0; 2439 } 2440 2441 static void 2442 fwohci_check_nodes(struct fwohci_softc *sc) 2443 { 2444 struct device *detach = NULL; 2445 struct ieee1394_softc *iea; 2446 2447 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2448 2449 /* 2450 * Have to defer detachment until the next 2451 * loop iteration since config_detach 2452 * free's the softc and the loop iterator 2453 * needs data from the softc to move 2454 * forward. 2455 */ 2456 2457 if (detach) { 2458 config_detach(detach, 0); 2459 detach = NULL; 2460 } 2461 if (iea->sc1394_node_id == 0xffff) { 2462 detach = (struct device *)iea; 2463 LIST_REMOVE(iea, sc1394_node); 2464 } 2465 } 2466 if (detach) 2467 config_detach(detach, 0); 2468 } 2469 2470 static int 2471 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2472 { 2473 struct fwohci_uidtbl *fu; 2474 int n; 2475 static const u_int8_t bcast[] = 2476 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2477 2478 fu = sc->sc_uidtbl; 2479 if (fu == NULL) { 2480 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2481 return IEEE1394_BCAST_PHY_ID; 2482 fwohci_uid_collect(sc); /* try to get */ 2483 return -1; 2484 } 2485 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 2486 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2487 return n; 2488 } 2489 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2490 return IEEE1394_BCAST_PHY_ID; 2491 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 2492 if (fu->fu_valid != 0x3) { 2493 /* 2494 * XXX: need timer before retransmission 2495 */ 2496 fwohci_uid_req(sc, n); 2497 } 2498 } 2499 return -1; 2500 } 2501 2502 /* 2503 * functions to support network interface 2504 */ 2505 static int 2506 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2507 void (*handler)(struct device *, struct mbuf *)) 2508 { 2509 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2510 2511 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2512 handler ? fwohci_if_input : NULL, handler); 2513 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2514 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2515 IEEE1394_TAG_GASP, handler ? fwohci_if_input : NULL, handler); 2516 return 0; 2517 } 2518 2519 static int 2520 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2521 { 2522 int n, len; 2523 struct mbuf *m; 2524 struct iovec *iov; 2525 void (*handler)(struct device *, struct mbuf *) = arg; 2526 2527 #ifdef FW_DEBUG 2528 int i; 2529 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2530 pkt->fp_dlen)); 2531 for (i = 0; i < pkt->fp_hlen/4; i++) 2532 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2533 DPRINTFN(2, ("$")); 2534 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2535 iov = &pkt->fp_iov[n]; 2536 for (i = 0; i < iov->iov_len; i++) 2537 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2538 ((u_int8_t *)iov->iov_base)[i])); 2539 DPRINTFN(2, ("$")); 2540 } 2541 DPRINTFN(1, ("\n")); 2542 #endif /* FW_DEBUG */ 2543 len = pkt->fp_dlen; 2544 MGETHDR(m, M_DONTWAIT, MT_DATA); 2545 if (m == NULL) 2546 return IEEE1394_RCODE_COMPLETE; 2547 m->m_len = 16; 2548 if (len + m->m_len > MHLEN) { 2549 MCLGET(m, M_DONTWAIT); 2550 if ((m->m_flags & M_EXT) == 0) { 2551 m_freem(m); 2552 return IEEE1394_RCODE_COMPLETE; 2553 } 2554 } 2555 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2556 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2557 sc->sc_uidtbl[n].fu_valid != 0x3) { 2558 printf("%s: packet from unknown node: phy id %d\n", 2559 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2560 m_freem(m); 2561 fwohci_uid_req(sc, n); 2562 return IEEE1394_RCODE_COMPLETE; 2563 } 2564 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2565 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2566 m->m_flags |= M_BCAST; 2567 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2568 } else { 2569 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2570 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2571 } 2572 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2573 mtod(m, u_int8_t *)[9] = 2574 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2575 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2576 2577 m->m_pkthdr.rcvif = NULL; /* set in child */ 2578 m->m_pkthdr.len = len + m->m_len; 2579 /* 2580 * We may use receive buffer by external mbuf instead of copy here. 2581 * But asynchronous receive buffer must be operate in buffer fill 2582 * mode, so that each receive buffer will shared by multiple mbufs. 2583 * If upper layer doesn't free mbuf soon, e.g. application program 2584 * is suspended, buffer must be reallocated. 2585 * Isochronous buffer must be operate in packet buffer mode, and 2586 * it is easy to map receive buffer to external mbuf. But it is 2587 * used for broadcast/multicast only, and is expected not so 2588 * performance sensitive for now. 2589 * XXX: The performance may be important for multicast case, 2590 * so we should revisit here later. 2591 * -- onoe 2592 */ 2593 n = 0; 2594 iov = pkt->fp_uio.uio_iov; 2595 while (len > 0) { 2596 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2597 iov->iov_len); 2598 m->m_len += iov->iov_len; 2599 len -= iov->iov_len; 2600 iov++; 2601 } 2602 (*handler)(sc->sc_sc1394.sc1394_if, m); 2603 return IEEE1394_RCODE_COMPLETE; 2604 } 2605 2606 static int 2607 fwohci_if_output(struct device *self, struct mbuf *m0, 2608 void (*callback)(struct device *, struct mbuf *)) 2609 { 2610 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2611 struct fwohci_pkt pkt; 2612 u_int8_t *p; 2613 int n, error, spd, hdrlen, maxrec; 2614 #ifdef FW_DEBUG 2615 struct mbuf *m; 2616 #endif 2617 2618 p = mtod(m0, u_int8_t *); 2619 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2620 spd = IEEE1394_SPD_S100; /*XXX*/ 2621 maxrec = 512; /*XXX*/ 2622 hdrlen = 8; 2623 } else { 2624 n = fwohci_uid_lookup(sc, p); 2625 if (n < 0) { 2626 printf("%s: nodeid unknown:" 2627 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2628 sc->sc_sc1394.sc1394_dev.dv_xname, 2629 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2630 error = EHOSTUNREACH; 2631 goto end; 2632 } 2633 if (n == IEEE1394_BCAST_PHY_ID) { 2634 printf("%s: broadcast with !M_MCAST\n", 2635 sc->sc_sc1394.sc1394_dev.dv_xname); 2636 #ifdef FW_DEBUG 2637 DPRINTFN(2, ("packet:")); 2638 for (m = m0; m != NULL; m = m->m_next) { 2639 for (n = 0; n < m->m_len; n++) 2640 DPRINTFN(2, ("%s%02x", (n%32)? 2641 ((n%4)?"":" "):"\n ", 2642 mtod(m, u_int8_t *)[n])); 2643 DPRINTFN(2, ("$")); 2644 } 2645 DPRINTFN(2, ("\n")); 2646 #endif 2647 error = EHOSTUNREACH; 2648 goto end; 2649 } 2650 maxrec = 2 << p[8]; 2651 spd = p[9]; 2652 hdrlen = 0; 2653 } 2654 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2655 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2656 spd, sc->sc_sc1394.sc1394_link_speed)); 2657 spd = sc->sc_sc1394.sc1394_link_speed; 2658 } 2659 if (maxrec > (512 << spd)) { 2660 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2661 "\n", maxrec, spd)); 2662 maxrec = 512 << spd; 2663 } 2664 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2665 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2666 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2667 maxrec >>= 1; 2668 } 2669 if (maxrec < 512) { 2670 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2671 "minimum\n", maxrec)); 2672 maxrec = 512; 2673 } 2674 2675 m_adj(m0, 16 - hdrlen); 2676 if (m0->m_pkthdr.len > maxrec) { 2677 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2678 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2679 error = E2BIG; /*XXX*/ 2680 goto end; 2681 } 2682 2683 memset(&pkt, 0, sizeof(pkt)); 2684 pkt.fp_uio.uio_iov = pkt.fp_iov; 2685 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2686 pkt.fp_uio.uio_rw = UIO_WRITE; 2687 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2688 /* construct GASP header */ 2689 p = mtod(m0, u_int8_t *); 2690 p[0] = sc->sc_nodeid >> 8; 2691 p[1] = sc->sc_nodeid & 0xff; 2692 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2693 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2694 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2695 pkt.fp_hlen = 8; 2696 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2697 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2698 OHCI_NodeId_NodeNumber) << 8); 2699 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2700 } else { 2701 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2702 pkt.fp_hlen = 16; 2703 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2704 (spd << 16); 2705 pkt.fp_hdr[1] = 2706 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2707 (p[10] << 8) | p[11]; 2708 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2709 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2710 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2711 } 2712 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2713 pkt.fp_dlen = m0->m_pkthdr.len; 2714 pkt.fp_m = m0; 2715 pkt.fp_callback = callback; 2716 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2717 m0 = pkt.fp_m; 2718 end: 2719 if (m0 != NULL) { 2720 if (callback) 2721 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2722 else 2723 m_freem(m0); 2724 } 2725 return error; 2726 } 2727 2728 /* 2729 * High level routines to provide abstraction to attaching layers to 2730 * send/receive data. 2731 */ 2732 2733 /* 2734 * These break down into 4 routines as follows: 2735 * 2736 * int fwohci_read(struct ieee1394_abuf *) 2737 * 2738 * This routine will attempt to read a region from the requested node. 2739 * A callback must be provided which will be called when either the completed 2740 * read is done or an unrecoverable error occurs. This is mainly a convenience 2741 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2742 * and recombining all the returned data. This could also be done with a series 2743 * of write/inreg's for each packet sent. 2744 * 2745 * int fwohci_write(struct ieee1394_abuf *) 2746 * 2747 * The work horse main entry point for putting packets on the bus. This is the 2748 * generalized interface for fwnode/etc code to put packets out onto the bus. 2749 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2750 * will callback via a func pointer to the calling code with the resulting ACK 2751 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2752 * write routine will take care of free'ing the abuf since the fwnode/etc code 2753 * won't have any knowledge of when to do this. This allows for simple one-off 2754 * packets to be sent from the upper-level code without worrying about a callback 2755 * for cleanup. 2756 * 2757 * int fwohci_inreg(struct ieee1394_abuf *, int) 2758 * 2759 * This is very simple. It evals the abuf passed in and registers an internal 2760 * handler as the callback for packets received for that operation. 2761 * The integer argument specifies whether on a block read/write operation to 2762 * allow sub-regions to be read/written (in block form) as well. 2763 * 2764 * XXX: This whole structure needs to be redone as a list of regions and 2765 * operations allowed on those regions. 2766 * 2767 * int fwohci_unreg(struct ieee1394_abuf *, int) 2768 * 2769 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2770 * routine will simply verify ab_cb is NULL and call inreg. 2771 * 2772 * This simply unregisters the respective callback done via inreg for items 2773 * which only need to register an area for a one-time operation (like a status 2774 * buffer a remote node will write to when the current operation is done). The 2775 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2776 * it unregisters). 2777 */ 2778 2779 static int 2780 fwohci_read(struct ieee1394_abuf *ab) 2781 { 2782 struct fwohci_pkt pkt; 2783 struct ieee1394_softc *sc = ab->ab_req; 2784 struct fwohci_softc *psc = 2785 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2786 struct fwohci_cb *fcb; 2787 u_int32_t high, lo; 2788 int rv, tcode; 2789 2790 /* Have to have a callback when reading. */ 2791 if (ab->ab_cb == NULL) 2792 return -1; 2793 2794 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2795 fcb->ab = ab; 2796 fcb->count = 0; 2797 fcb->abuf_valid = 1; 2798 2799 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2800 lo = (ab->ab_csr & 0x00000000ffffffff); 2801 2802 memset(&pkt, 0, sizeof(pkt)); 2803 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2804 pkt.fp_hdr[2] = lo; 2805 pkt.fp_dlen = 0; 2806 2807 if (ab->ab_length == 4) { 2808 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2809 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2810 pkt.fp_hlen = 12; 2811 } else { 2812 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2813 pkt.fp_hlen = 16; 2814 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2815 pkt.fp_hdr[3] = (ab->ab_length << 16); 2816 } 2817 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2818 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2819 2820 pkt.fp_statusarg = fcb; 2821 pkt.fp_statuscb = fwohci_read_resp; 2822 2823 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2824 psc->sc_tlabel, fwohci_read_resp, fcb); 2825 if (rv) 2826 return rv; 2827 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2828 if (rv) 2829 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2830 psc->sc_tlabel, NULL, NULL); 2831 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2832 fcb->count = 1; 2833 return rv; 2834 } 2835 2836 static int 2837 fwohci_write(struct ieee1394_abuf *ab) 2838 { 2839 struct fwohci_pkt pkt; 2840 struct ieee1394_softc *sc = ab->ab_req; 2841 struct fwohci_softc *psc = 2842 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2843 u_int32_t high, lo; 2844 int rv; 2845 2846 if (ab->ab_length > sc->sc1394_max_receive) { 2847 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2848 return E2BIG; 2849 } 2850 2851 memset(&pkt, 0, sizeof(pkt)); 2852 2853 pkt.fp_tcode = ab->ab_tcode; 2854 pkt.fp_uio.uio_iov = pkt.fp_iov; 2855 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2856 pkt.fp_uio.uio_rw = UIO_WRITE; 2857 2858 pkt.fp_statusarg = ab; 2859 pkt.fp_statuscb = fwohci_write_ack; 2860 2861 switch (ab->ab_tcode) { 2862 case IEEE1394_TCODE_WRITE_RESP: 2863 pkt.fp_hlen = 12; 2864 case IEEE1394_TCODE_READ_RESP_QUAD: 2865 case IEEE1394_TCODE_READ_RESP_BLOCK: 2866 if (!pkt.fp_hlen) 2867 pkt.fp_hlen = 16; 2868 high = ab->ab_retlen; 2869 ab->ab_retlen = 0; 2870 lo = 0; 2871 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2872 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2873 break; 2874 default: 2875 pkt.fp_hlen = 16; 2876 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2877 lo = (ab->ab_csr & 0x00000000ffffffff); 2878 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2879 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2880 break; 2881 } 2882 2883 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2884 pkt.fp_hdr[2] = lo; 2885 if (pkt.fp_hlen == 16) { 2886 if (ab->ab_length == 4) { 2887 pkt.fp_hdr[3] = ab->ab_data[0]; 2888 pkt.fp_dlen = 0; 2889 } else { 2890 pkt.fp_hdr[3] = (ab->ab_length << 16); 2891 pkt.fp_dlen = ab->ab_length; 2892 pkt.fp_uio.uio_iovcnt = 1; 2893 pkt.fp_uio.uio_resid = ab->ab_length; 2894 pkt.fp_iov[0].iov_base = ab->ab_data; 2895 pkt.fp_iov[0].iov_len = ab->ab_length; 2896 } 2897 } 2898 switch (ab->ab_tcode) { 2899 case IEEE1394_TCODE_WRITE_RESP: 2900 case IEEE1394_TCODE_READ_RESP_QUAD: 2901 case IEEE1394_TCODE_READ_RESP_BLOCK: 2902 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2903 break; 2904 default: 2905 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2906 break; 2907 } 2908 return rv; 2909 } 2910 2911 static int 2912 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2913 { 2914 struct fwohci_cb *fcb = arg; 2915 struct ieee1394_abuf *ab = fcb->ab; 2916 struct fwohci_pkt newpkt; 2917 u_int32_t *cur, high, lo; 2918 int i, tcode, rcode, status, rv; 2919 2920 /* 2921 * Both the ACK handling and normal response callbacks are handled here. 2922 * The main reason for this is the various error conditions that can 2923 * occur trying to block read some areas and the ways that gets reported 2924 * back to calling station. This is a variety of ACK codes, responses, 2925 * etc which makes it much more difficult to process if both aren't 2926 * handled here. 2927 */ 2928 2929 /* Check for status packet. */ 2930 2931 if (pkt->fp_tcode == -1) { 2932 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2933 rcode = -1; 2934 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2935 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2936 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2937 DPRINTF(("Got status packet: 0x%02x\n", 2938 (unsigned int)status)); 2939 fcb->count--; 2940 2941 /* 2942 * Got all the ack's back and the buffer is invalid (i.e. the 2943 * callback has been called. Clean up. 2944 */ 2945 2946 if (fcb->abuf_valid == 0) { 2947 if (fcb->count == 0) 2948 free(fcb, M_DEVBUF); 2949 return IEEE1394_RCODE_COMPLETE; 2950 } 2951 } else { 2952 status = -1; 2953 tcode = pkt->fp_tcode; 2954 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2955 } 2956 2957 /* 2958 * Some area's (like the config rom want to be read as quadlets only. 2959 * 2960 * The current ideas to try are: 2961 * 2962 * Got an ACK_TYPE_ERROR on a block read. 2963 * 2964 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2965 * response. 2966 * 2967 * In all cases construct a new packet for a quadlet read and let 2968 * mutli_resp handle the iteration over the space. 2969 */ 2970 2971 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2972 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2973 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2974 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2975 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2976 2977 /* Read the area in quadlet chunks (internally track this). */ 2978 2979 memset(&newpkt, 0, sizeof(newpkt)); 2980 2981 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2982 lo = (ab->ab_csr & 0x00000000ffffffff); 2983 2984 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2985 newpkt.fp_hlen = 12; 2986 newpkt.fp_dlen = 0; 2987 newpkt.fp_hdr[1] = 2988 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2989 newpkt.fp_hdr[2] = lo; 2990 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2991 (newpkt.fp_tcode << 4); 2992 2993 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2994 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2995 fwohci_read_multi_resp, fcb); 2996 if (rv) { 2997 (*ab->ab_cb)(ab, -1); 2998 goto cleanup; 2999 } 3000 newpkt.fp_statusarg = fcb; 3001 newpkt.fp_statuscb = fwohci_read_resp; 3002 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3003 if (rv) { 3004 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3005 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3006 NULL); 3007 (*ab->ab_cb)(ab, -1); 3008 goto cleanup; 3009 } 3010 fcb->count++; 3011 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3012 return IEEE1394_RCODE_COMPLETE; 3013 } else if ((rcode != -1) || ((status != -1) && 3014 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3015 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3016 3017 /* 3018 * Recombine all the iov data into 1 chunk for higher 3019 * level code. 3020 */ 3021 3022 if (rcode != -1) { 3023 cur = ab->ab_data; 3024 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3025 /* 3026 * Make sure and don't exceed the buffer 3027 * allocated for return. 3028 */ 3029 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3030 ab->ab_length) { 3031 memcpy(cur, pkt->fp_iov[i].iov_base, 3032 (ab->ab_length - ab->ab_retlen)); 3033 ab->ab_retlen = ab->ab_length; 3034 break; 3035 } 3036 memcpy(cur, pkt->fp_iov[i].iov_base, 3037 pkt->fp_iov[i].iov_len); 3038 cur += pkt->fp_iov[i].iov_len; 3039 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3040 } 3041 } 3042 if (status != -1) 3043 /* XXX: Need a complete tlabel interface. */ 3044 for (i = 0; i < 64; i++) 3045 fwohci_handler_set(sc, 3046 IEEE1394_TCODE_READ_RESP_QUAD, 3047 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3048 (*ab->ab_cb)(ab, rcode); 3049 goto cleanup; 3050 } else 3051 /* Good ack packet. */ 3052 return IEEE1394_RCODE_COMPLETE; 3053 3054 /* Can't get here unless ab->ab_cb has been called. */ 3055 3056 cleanup: 3057 fcb->abuf_valid = 0; 3058 if (fcb->count == 0) 3059 free(fcb, M_DEVBUF); 3060 return IEEE1394_RCODE_COMPLETE; 3061 } 3062 3063 static int 3064 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3065 struct fwohci_pkt *pkt) 3066 { 3067 struct fwohci_cb *fcb = arg; 3068 struct ieee1394_abuf *ab = fcb->ab; 3069 struct fwohci_pkt newpkt; 3070 u_int32_t high, lo; 3071 int rcode, rv; 3072 3073 /* 3074 * Bad return codes from the wire, just return what's already in the 3075 * buf. 3076 */ 3077 3078 /* Make sure a response packet didn't arrive after a bad ACK. */ 3079 if (fcb->abuf_valid == 0) 3080 return IEEE1394_RCODE_COMPLETE; 3081 3082 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3083 3084 if (rcode) { 3085 (*ab->ab_cb)(ab, rcode); 3086 goto cleanup; 3087 } 3088 3089 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3090 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3091 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3092 ab->ab_retlen = ab->ab_length; 3093 } else { 3094 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3095 pkt->fp_iov[0].iov_base, 4); 3096 ab->ab_retlen += 4; 3097 } 3098 /* Still more, loop and read 4 more bytes. */ 3099 if (ab->ab_retlen < ab->ab_length) { 3100 memset(&newpkt, 0, sizeof(newpkt)); 3101 3102 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3103 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3104 3105 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3106 newpkt.fp_hlen = 12; 3107 newpkt.fp_dlen = 0; 3108 newpkt.fp_hdr[1] = 3109 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3110 newpkt.fp_hdr[2] = lo; 3111 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3112 (newpkt.fp_tcode << 4); 3113 3114 newpkt.fp_statusarg = fcb; 3115 newpkt.fp_statuscb = fwohci_read_resp; 3116 3117 /* 3118 * Bad return code. Just give up and return what's 3119 * come in now. 3120 */ 3121 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3122 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3123 fwohci_read_multi_resp, fcb); 3124 if (rv) 3125 (*ab->ab_cb)(ab, -1); 3126 else { 3127 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3128 if (rv) { 3129 fwohci_handler_set(sc, 3130 IEEE1394_TCODE_READ_RESP_QUAD, 3131 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3132 NULL, NULL); 3133 (*ab->ab_cb)(ab, -1); 3134 } else { 3135 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3136 fcb->count++; 3137 return IEEE1394_RCODE_COMPLETE; 3138 } 3139 } 3140 } else 3141 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3142 3143 cleanup: 3144 /* Can't get here unless ab_cb has been called. */ 3145 fcb->abuf_valid = 0; 3146 if (fcb->count == 0) 3147 free(fcb, M_DEVBUF); 3148 return IEEE1394_RCODE_COMPLETE; 3149 } 3150 3151 static int 3152 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3153 { 3154 struct ieee1394_abuf *ab = arg; 3155 u_int16_t status; 3156 3157 3158 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3159 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3160 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3161 DPRINTF(("Got status packet: 0x%02x\n", 3162 (unsigned int)status)); 3163 3164 /* No callback means this level should free the buffers. */ 3165 if (ab->ab_cb) 3166 (*ab->ab_cb)(ab, status); 3167 else { 3168 if (ab->ab_data) 3169 free(ab->ab_data, M_1394DATA); 3170 free(ab, M_1394DATA); 3171 } 3172 return IEEE1394_RCODE_COMPLETE; 3173 } 3174 3175 static int 3176 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3177 { 3178 struct ieee1394_softc *sc = ab->ab_req; 3179 struct fwohci_softc *psc = 3180 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3181 u_int32_t high, lo; 3182 int i, j, rv; 3183 3184 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3185 lo = (ab->ab_csr & 0x00000000ffffffff); 3186 3187 rv = 0; 3188 switch (ab->ab_tcode) { 3189 case IEEE1394_TCODE_READ_REQ_QUAD: 3190 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3191 if (ab->ab_cb) 3192 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3193 fwohci_parse_input, ab); 3194 else 3195 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3196 NULL); 3197 break; 3198 case IEEE1394_TCODE_READ_REQ_BLOCK: 3199 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3200 if (allow) { 3201 for (i = 0; i < (ab->ab_length / 4); i++) { 3202 if (ab->ab_cb) { 3203 rv = fwohci_handler_set(psc, 3204 ab->ab_tcode, high, lo + (i * 4), 3205 fwohci_parse_input, ab); 3206 if (rv) 3207 break; 3208 } else 3209 fwohci_handler_set(psc, ab->ab_tcode, 3210 high, lo + (i * 4), NULL, NULL); 3211 } 3212 if (i != (ab->ab_length / 4)) { 3213 j = i + 1; 3214 for (i = 0; i < j; i++) 3215 fwohci_handler_set(psc, ab->ab_tcode, 3216 high, lo + (i * 4), NULL, NULL); 3217 } else 3218 ab->ab_data = (void *)1; 3219 } else { 3220 if (ab->ab_cb) 3221 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3222 lo, fwohci_parse_input, ab); 3223 else 3224 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3225 NULL, NULL); 3226 } 3227 break; 3228 default: 3229 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3230 return -1; 3231 break; 3232 } 3233 return rv; 3234 } 3235 3236 static int 3237 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3238 { 3239 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3240 u_int64_t csr; 3241 u_int32_t *cur; 3242 int i, count; 3243 3244 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3245 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3246 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3247 3248 switch (ab->ab_tcode) { 3249 case IEEE1394_TCODE_READ_REQ_QUAD: 3250 ab->ab_retlen = 4; 3251 break; 3252 case IEEE1394_TCODE_READ_REQ_BLOCK: 3253 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3254 if (ab->ab_data) { 3255 if ((csr + ab->ab_retlen) > 3256 (ab->ab_csr + ab->ab_length)) 3257 return IEEE1394_RCODE_ADDRESS_ERROR; 3258 ab->ab_data = NULL; 3259 } else 3260 if (ab->ab_retlen != ab->ab_length) 3261 return IEEE1394_RCODE_ADDRESS_ERROR; 3262 break; 3263 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3264 ab->ab_retlen = 4; 3265 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3266 if (!ab->ab_retlen) 3267 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3268 if (ab->ab_data) { 3269 if ((csr + ab->ab_retlen) > 3270 (ab->ab_csr + ab->ab_length)) 3271 return IEEE1394_RCODE_ADDRESS_ERROR; 3272 ab->ab_data = NULL; 3273 } else 3274 if (ab->ab_retlen != ab->ab_length) 3275 return IEEE1394_RCODE_ADDRESS_ERROR; 3276 3277 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3278 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3279 ab->ab_data[0] = pkt->fp_hdr[3]; 3280 else { 3281 count = 0; 3282 cur = ab->ab_data; 3283 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3284 memcpy(cur, pkt->fp_iov[i].iov_base, 3285 pkt->fp_iov[i].iov_len); 3286 cur += pkt->fp_iov[i].iov_len; 3287 count += pkt->fp_iov[i].iov_len; 3288 } 3289 if (ab->ab_retlen != count) 3290 panic("Packet claims %d length " 3291 "but only %d bytes returned\n", 3292 ab->ab_retlen, count); 3293 } 3294 break; 3295 default: 3296 panic("Got a callback for a tcode that wasn't requested: %d\n", 3297 ab->ab_tcode); 3298 break; 3299 } 3300 ab->ab_csr = csr; 3301 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3302 return -1; 3303 } 3304 3305 static int 3306 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3307 { 3308 struct ieee1394_attach_args *fwa = aux; 3309 3310 /* Both halves must be filled in for a match. */ 3311 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3312 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3313 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3314 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3315 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3316 return 0; 3317 } 3318 3319 #ifdef FW_DEBUG 3320 static void 3321 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3322 { 3323 3324 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3325 intmask); 3326 if (intmask & OHCI_Int_CycleTooLong) 3327 printf(" CycleTooLong"); 3328 if (intmask & OHCI_Int_UnrecoverableError) 3329 printf(" UnrecoverableError"); 3330 if (intmask & OHCI_Int_CycleInconsistent) 3331 printf(" CycleInconsistent"); 3332 if (intmask & OHCI_Int_BusReset) 3333 printf(" BusReset"); 3334 if (intmask & OHCI_Int_SelfIDComplete) 3335 printf(" SelfIDComplete"); 3336 if (intmask & OHCI_Int_LockRespErr) 3337 printf(" LockRespErr"); 3338 if (intmask & OHCI_Int_PostedWriteErr) 3339 printf(" PostedWriteErr"); 3340 if (intmask & OHCI_Int_ReqTxComplete) 3341 printf(" ReqTxComplete(0x%04x)", 3342 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3343 OHCI_SUBREG_ContextControlClear)); 3344 if (intmask & OHCI_Int_RespTxComplete) 3345 printf(" RespTxComplete(0x%04x)", 3346 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3347 OHCI_SUBREG_ContextControlClear)); 3348 if (intmask & OHCI_Int_ARRS) 3349 printf(" ARRS(0x%04x)", 3350 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3351 OHCI_SUBREG_ContextControlClear)); 3352 if (intmask & OHCI_Int_ARRQ) 3353 printf(" ARRQ(0x%04x)", 3354 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3355 OHCI_SUBREG_ContextControlClear)); 3356 if (intmask & OHCI_Int_IsochRx) 3357 printf(" IsochRx(0x%08x)", 3358 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3359 if (intmask & OHCI_Int_IsochTx) 3360 printf(" IsochTx(0x%08x)", 3361 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3362 if (intmask & OHCI_Int_RQPkt) 3363 printf(" RQPkt(0x%04x)", 3364 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3365 OHCI_SUBREG_ContextControlClear)); 3366 if (intmask & OHCI_Int_RSPkt) 3367 printf(" RSPkt(0x%04x)", 3368 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3369 OHCI_SUBREG_ContextControlClear)); 3370 printf("\n"); 3371 } 3372 3373 static void 3374 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3375 { 3376 u_int8_t key, phyid; 3377 3378 key = (val & 0xc0000000) >> 30; 3379 phyid = (val & 0x3f000000) >> 24; 3380 printf("%s: PHY packet from %d: ", 3381 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3382 switch (key) { 3383 case 0: 3384 printf("PHY Config:"); 3385 if (val & 0x00800000) 3386 printf(" ForceRoot"); 3387 if (val & 0x00400000) 3388 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3389 printf("\n"); 3390 break; 3391 case 1: 3392 printf("Link-on\n"); 3393 break; 3394 case 2: 3395 printf("SelfID:"); 3396 if (val & 0x00800000) { 3397 printf(" #%d", (val & 0x00700000) >> 20); 3398 } else { 3399 if (val & 0x00400000) 3400 printf(" LinkActive"); 3401 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3402 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3403 if (val & 0x00000800) 3404 printf(" Cont"); 3405 if (val & 0x00000002) 3406 printf(" InitiateBusReset"); 3407 } 3408 if (val & 0x00000001) 3409 printf(" +"); 3410 printf("\n"); 3411 break; 3412 default: 3413 printf("unknown: 0x%08x\n", val); 3414 break; 3415 } 3416 } 3417 #endif /* FW_DEBUG */ 3418
Indexes created Mon Sep 29 13:09:55 GMT 2025