fwohci.c revision 1.39
1 /* $NetBSD: fwohci.c,v 1.39 2001/07/02 11:12:09 onoe Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 #include "opt_inet.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kthread.h> 51 #include <sys/types.h> 52 #include <sys/socket.h> 53 #include <sys/callout.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/mbuf.h> 58 59 #if __NetBSD_Version__ >= 105010000 60 #include <uvm/uvm_extern.h> 61 #else 62 #include <vm/vm.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ieee1394/ieee1394reg.h> 69 #include <dev/ieee1394/fwohcireg.h> 70 71 #include <dev/ieee1394/ieee1394var.h> 72 #include <dev/ieee1394/fwohcivar.h> 73 74 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 75 76 #if 0 77 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 78 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 79 #endif 80 static void fwohci_create_event_thread(void *); 81 static void fwohci_thread_init(void *); 82 83 static void fwohci_event_thread(struct fwohci_softc *); 84 static void fwohci_hw_init(struct fwohci_softc *); 85 static void fwohci_power(int, void *); 86 static void fwohci_shutdown(void *); 87 88 static int fwohci_desc_alloc(struct fwohci_softc *); 89 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 90 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 91 92 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 93 int, int); 94 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 95 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 96 97 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 98 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 99 static void fwohci_buf_init_rx(struct fwohci_softc *); 100 static void fwohci_buf_start_rx(struct fwohci_softc *); 101 static void fwohci_buf_stop_tx(struct fwohci_softc *); 102 static void fwohci_buf_stop_rx(struct fwohci_softc *); 103 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 104 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_buf **, 105 caddr_t *, int); 106 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 107 struct fwohci_pkt *); 108 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 109 struct fwohci_pkt *); 110 111 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 112 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 113 static void fwohci_phy_busreset(struct fwohci_softc *); 114 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 115 116 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 117 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 118 119 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 120 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 121 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 122 123 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 124 struct fwohci_pkt *); 125 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 126 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 127 struct fwohci_pkt *); 128 129 static int fwohci_guidrom_init(struct fwohci_softc *); 130 static void fwohci_configrom_init(struct fwohci_softc *); 131 static int fwohci_configrom_input(struct fwohci_softc *, void *, 132 struct fwohci_pkt *); 133 static void fwohci_selfid_init(struct fwohci_softc *); 134 static int fwohci_selfid_input(struct fwohci_softc *); 135 136 static void fwohci_csr_init(struct fwohci_softc *); 137 static int fwohci_csr_input(struct fwohci_softc *, void *, 138 struct fwohci_pkt *); 139 140 static void fwohci_uid_collect(struct fwohci_softc *); 141 static void fwohci_uid_req(struct fwohci_softc *, int); 142 static int fwohci_uid_input(struct fwohci_softc *, void *, 143 struct fwohci_pkt *); 144 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 145 static void fwohci_check_nodes(struct fwohci_softc *); 146 147 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 148 void (*)(struct device *, struct mbuf *)); 149 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 150 static int fwohci_if_output(struct device *, struct mbuf *, 151 void (*)(struct device *, struct mbuf *)); 152 static int fwohci_read(struct ieee1394_abuf *); 153 static int fwohci_write(struct ieee1394_abuf *); 154 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 155 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 156 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 157 struct fwohci_pkt *); 158 static int fwohci_inreg(struct ieee1394_abuf *, int); 159 static int fwohci_parse_input(struct fwohci_softc *, void *, 160 struct fwohci_pkt *); 161 static int fwohci_submatch(struct device *, struct cfdata *, void *); 162 163 #ifdef FW_DEBUG 164 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 165 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 166 167 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 168 169 #define DPRINTF(x) if (fwdebug) printf x 170 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 171 int fwdebug = 0; 172 #else 173 #define DPRINTF(x) 174 #define DPRINTFN(n,x) 175 #endif 176 177 int 178 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 179 { 180 int i; 181 u_int32_t val; 182 #if 0 183 int error; 184 #endif 185 186 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 187 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 188 189 /* 190 * Wait for reset completion 191 */ 192 for (i = 0; i < OHCI_LOOP; i++) { 193 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 194 if ((val & OHCI_HCControl_SoftReset) == 0) 195 break; 196 DELAY(10); 197 } 198 199 /* What dialect of OHCI is this device? 200 */ 201 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 202 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 203 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 204 205 LIST_INIT(&sc->sc_nodelist); 206 207 if (fwohci_guidrom_init(sc) != 0) { 208 printf("\n%s: fatal: no global UID ROM\n", 209 sc->sc_sc1394.sc1394_dev.dv_xname); 210 return -1; 211 } 212 213 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 214 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 215 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 216 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 217 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 218 219 /* Get the maximum link speed and receive size 220 */ 221 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 222 sc->sc_sc1394.sc1394_link_speed = 223 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 224 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 225 printf(", %s", 226 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 227 } else { 228 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 229 } 230 231 /* MaxRec is encoded as log2(max_rec_octets)-1 232 */ 233 sc->sc_sc1394.sc1394_max_receive = 234 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 235 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 236 237 /* 238 * Count how many isochronous ctx we have. 239 */ 240 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 241 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 242 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 243 for (i = 0; val != 0; val >>= 1) { 244 if (val & 0x1) 245 i++; 246 } 247 sc->sc_isoctx = i; 248 printf(", %d iso_ctx", sc->sc_isoctx); 249 250 printf("\n"); 251 252 #if 0 253 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 254 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 255 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 256 return error; 257 #endif 258 259 sc->sc_dying = 0; 260 sc->sc_nodeid = 0xffff; /* invalid */ 261 262 kthread_create(fwohci_create_event_thread, sc); 263 return 0; 264 } 265 266 int 267 fwohci_intr(void *arg) 268 { 269 struct fwohci_softc * const sc = arg; 270 int progress = 0; 271 u_int32_t intmask, iso; 272 273 for (;;) { 274 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 275 276 /* 277 * On a bus reset, everything except bus reset gets 278 * cleared. That can't get cleared until the selfid 279 * phase completes (which happens outside the 280 * interrupt routines). So if just a bus reset is left 281 * in the mask and it's already in the sc_intmask, 282 * just return. 283 */ 284 285 if ((intmask == 0) || 286 (progress && (intmask == OHCI_Int_BusReset) && 287 (sc->sc_intmask & OHCI_Int_BusReset))) { 288 if (progress) 289 wakeup(fwohci_event_thread); 290 return progress; 291 } 292 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 293 intmask & ~OHCI_Int_BusReset); 294 #ifdef FW_DEBUG 295 if (fwdebug > 1) 296 fwohci_show_intr(sc, intmask); 297 #endif 298 299 if (intmask & OHCI_Int_BusReset) { 300 /* 301 * According to OHCI spec 6.1.1 "busReset", 302 * All asynchronous transmit must be stopped before 303 * clearing BusReset. Moreover, the BusReset 304 * interrupt bit should not be cleared during the 305 * SelfID phase. Thus we turned off interrupt mask 306 * bit of BusReset instead until SelfID completion 307 * or SelfID timeout. 308 */ 309 intmask &= OHCI_Int_SelfIDComplete; 310 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 311 OHCI_Int_BusReset); 312 sc->sc_intmask = OHCI_Int_BusReset; 313 } 314 sc->sc_intmask |= intmask; 315 316 if (intmask & OHCI_Int_IsochTx) { 317 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 318 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 319 } 320 if (intmask & OHCI_Int_IsochRx) { 321 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 322 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 323 sc->sc_iso |= iso; 324 } 325 326 if (!progress) { 327 sc->sc_intrcnt.ev_count++; 328 progress = 1; 329 } 330 } 331 } 332 333 static void 334 fwohci_create_event_thread(void *arg) 335 { 336 struct fwohci_softc *sc = arg; 337 338 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 339 sc->sc_sc1394.sc1394_dev.dv_xname)) { 340 printf("%s: unable to create event thread\n", 341 sc->sc_sc1394.sc1394_dev.dv_xname); 342 panic("fwohci_create_event_thread"); 343 } 344 } 345 346 static void 347 fwohci_thread_init(void *arg) 348 { 349 struct fwohci_softc *sc = arg; 350 int i; 351 352 /* 353 * Allocate descriptors 354 */ 355 if (fwohci_desc_alloc(sc)) { 356 printf("%s: not enabling interrupts\n", 357 sc->sc_sc1394.sc1394_dev.dv_xname); 358 kthread_exit(1); 359 } 360 361 /* 362 * Enable Link Power 363 */ 364 365 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 366 367 /* 368 * Allocate DMA Context 369 */ 370 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 371 OHCI_CTX_ASYNC_RX_REQUEST); 372 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 373 OHCI_CTX_ASYNC_RX_RESPONSE); 374 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST); 375 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE); 376 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 377 M_DEVBUF, M_WAITOK); 378 for (i = 0; i < sc->sc_isoctx; i++) 379 sc->sc_ctx_ir[i] = NULL; 380 381 /* 382 * Allocate buffer for configuration ROM and SelfID buffer 383 */ 384 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 385 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 386 387 callout_init(&sc->sc_selfid_callout); 388 389 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 390 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 391 392 /* 393 * establish hooks for shutdown and suspend/resume 394 */ 395 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 396 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 397 398 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 399 fwohci_print); 400 401 /* Main loop. It's not coming back normally. */ 402 403 fwohci_event_thread(sc); 404 405 kthread_exit(0); 406 } 407 408 static void 409 fwohci_event_thread(struct fwohci_softc *sc) 410 { 411 int i, s; 412 u_int32_t intmask, iso; 413 414 s = splbio(); 415 416 /* 417 * Initialize hardware registers. 418 */ 419 420 fwohci_hw_init(sc); 421 422 /* Initial Bus Reset */ 423 fwohci_phy_busreset(sc); 424 splx(s); 425 426 while (!sc->sc_dying) { 427 s = splbio(); 428 intmask = sc->sc_intmask; 429 if (intmask == 0) { 430 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 431 splx(s); 432 continue; 433 } 434 sc->sc_intmask = 0; 435 splx(s); 436 437 if (intmask & OHCI_Int_BusReset) { 438 fwohci_buf_stop_tx(sc); 439 if (sc->sc_uidtbl != NULL) { 440 free(sc->sc_uidtbl, M_DEVBUF); 441 sc->sc_uidtbl = NULL; 442 } 443 444 callout_reset(&sc->sc_selfid_callout, 445 OHCI_SELFID_TIMEOUT, 446 (void (*)(void *))fwohci_phy_busreset, sc); 447 sc->sc_nodeid = 0xffff; /* indicate invalid */ 448 sc->sc_rootid = 0; 449 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 450 } 451 if (intmask & OHCI_Int_SelfIDComplete) { 452 s = splbio(); 453 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 454 OHCI_Int_BusReset); 455 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 456 OHCI_Int_BusReset); 457 splx(s); 458 callout_stop(&sc->sc_selfid_callout); 459 if (fwohci_selfid_input(sc) == 0) { 460 fwohci_buf_start_rx(sc); 461 fwohci_uid_collect(sc); 462 } 463 } 464 if (intmask & OHCI_Int_ReqTxComplete) 465 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 466 if (intmask & OHCI_Int_RespTxComplete) 467 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 468 if (intmask & OHCI_Int_RQPkt) 469 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 470 if (intmask & OHCI_Int_RSPkt) 471 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 472 if (intmask & OHCI_Int_IsochRx) { 473 s = splbio(); 474 iso = sc->sc_iso; 475 sc->sc_iso = 0; 476 splx(s); 477 for (i = 0; i < sc->sc_isoctx; i++) { 478 if ((iso & (1 << i)) && 479 sc->sc_ctx_ir[i] != NULL) 480 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 481 } 482 } 483 } 484 } 485 486 #if 0 487 static int 488 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 489 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 490 { 491 bus_dma_segment_t segs[1]; 492 int error, nsegs, steps; 493 494 steps = 0; 495 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 496 segs, 1, &nsegs, flags); 497 if (error) 498 goto cleanup; 499 500 steps = 1; 501 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 502 kvap, flags); 503 if (error) 504 goto cleanup; 505 506 if (error == 0) 507 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 508 size, flags, mapp); 509 if (error) 510 goto cleanup; 511 if (error == 0) 512 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 513 flags); 514 if (error) 515 goto cleanup; 516 517 cleanup: 518 switch (steps) { 519 case 1: 520 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 521 } 522 523 return error; 524 } 525 #endif 526 527 int 528 fwohci_print(void *aux, const char *pnp) 529 { 530 char *name = aux; 531 532 if (pnp) 533 printf("%s at %s", name, pnp); 534 535 return QUIET; 536 } 537 538 static void 539 fwohci_hw_init(struct fwohci_softc *sc) 540 { 541 int i; 542 u_int32_t val; 543 544 /* 545 * Software Reset. 546 */ 547 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 548 for (i = 0; i < OHCI_LOOP; i++) { 549 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 550 if ((val & OHCI_HCControl_SoftReset) == 0) 551 break; 552 DELAY(10); 553 } 554 555 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 556 557 /* 558 * First, initilize CSRs with undefined value to default settings. 559 */ 560 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 561 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 562 #if 0 563 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 564 #else 565 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 566 #endif 567 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 568 for (i = 0; i < sc->sc_isoctx; i++) { 569 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 570 ~0); 571 } 572 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 573 574 fwohci_configrom_init(sc); 575 fwohci_selfid_init(sc); 576 fwohci_buf_init_rx(sc); 577 fwohci_csr_init(sc); 578 579 /* 580 * Final CSR settings. 581 */ 582 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 583 OHCI_LinkControl_CycleTimerEnable | 584 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 585 586 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 587 588 /* clear receive filter */ 589 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 590 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 591 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 592 593 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 594 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 595 #if BYTE_ORDER == BIG_ENDIAN 596 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 597 OHCI_HCControl_NoByteSwapData); 598 #endif 599 600 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 601 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 602 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 603 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 604 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 605 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 606 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 607 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 608 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 609 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 610 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 611 612 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 613 614 /* 615 * Start the receivers 616 */ 617 fwohci_buf_start_rx(sc); 618 } 619 620 static void 621 fwohci_power(int why, void *arg) 622 { 623 struct fwohci_softc *sc = arg; 624 int s; 625 626 s = splbio(); 627 switch (why) { 628 case PWR_SUSPEND: 629 case PWR_STANDBY: 630 fwohci_shutdown(sc); 631 break; 632 case PWR_RESUME: 633 fwohci_hw_init(sc); 634 fwohci_phy_busreset(sc); 635 break; 636 case PWR_SOFTSUSPEND: 637 case PWR_SOFTSTANDBY: 638 case PWR_SOFTRESUME: 639 break; 640 } 641 splx(s); 642 } 643 644 static void 645 fwohci_shutdown(void *arg) 646 { 647 struct fwohci_softc *sc = arg; 648 u_int32_t val; 649 650 callout_stop(&sc->sc_selfid_callout); 651 /* disable all interrupt */ 652 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 653 fwohci_buf_stop_tx(sc); 654 fwohci_buf_stop_rx(sc); 655 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 656 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 657 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 658 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 659 fwohci_phy_busreset(sc); 660 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 661 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 662 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 663 } 664 665 /* 666 * COMMON FUNCTIONS 667 */ 668 669 /* 670 * read the PHY Register. 671 */ 672 static u_int8_t 673 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 674 { 675 int i; 676 u_int32_t val; 677 678 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 679 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 680 for (i = 0; i < OHCI_LOOP; i++) { 681 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 682 OHCI_PhyControl_RdDone) 683 break; 684 DELAY(10); 685 } 686 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 687 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 688 } 689 690 /* 691 * write the PHY Register. 692 */ 693 static void 694 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 695 { 696 int i; 697 698 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 699 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 700 (val << OHCI_PhyControl_WrData_BITPOS)); 701 for (i = 0; i < OHCI_LOOP; i++) { 702 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 703 OHCI_PhyControl_WrReg)) 704 break; 705 DELAY(10); 706 } 707 } 708 709 /* 710 * Initiate Bus Reset 711 */ 712 static void 713 fwohci_phy_busreset(struct fwohci_softc *sc) 714 { 715 int s; 716 u_int8_t val; 717 718 s = splbio(); 719 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 720 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 721 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 722 callout_stop(&sc->sc_selfid_callout); 723 val = fwohci_phy_read(sc, 1); 724 val = (val & 0x80) | /* preserve RHB (force root) */ 725 0x40 | /* Initiate Bus Reset */ 726 0x3f; /* default GAP count */ 727 fwohci_phy_write(sc, 1, val); 728 splx(s); 729 } 730 731 /* 732 * PHY Packet 733 */ 734 static void 735 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 736 { 737 u_int32_t val; 738 739 val = pkt->fp_hdr[1]; 740 if (val != ~pkt->fp_hdr[2]) { 741 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 742 OHCI_CTXCTL_EVENT_BUS_RESET) { 743 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 744 pkt->fp_hdr[2])); 745 } else { 746 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 747 sc->sc_sc1394.sc1394_dev.dv_xname, val, 748 pkt->fp_hdr[2]); 749 } 750 return; 751 } 752 #ifdef FW_DEBUG 753 if (fwdebug > 1) 754 fwohci_show_phypkt(sc, val); 755 #endif 756 } 757 758 /* 759 * Descriptor for context DMA. 760 */ 761 static int 762 fwohci_desc_alloc(struct fwohci_softc *sc) 763 { 764 int error, mapsize, dsize; 765 766 /* 767 * allocate descriptor buffer 768 */ 769 770 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 771 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 772 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 773 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 774 mapsize = howmany(sc->sc_descsize, NBBY); 775 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 776 memset(sc->sc_descmap, 0, mapsize); 777 778 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 779 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 780 printf("%s: unable to allocate descriptor buffer, error = %d\n", 781 sc->sc_sc1394.sc1394_dev.dv_xname, error); 782 goto fail_0; 783 } 784 785 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 786 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 787 != 0) { 788 printf("%s: unable to map descriptor buffer, error = %d\n", 789 sc->sc_sc1394.sc1394_dev.dv_xname, error); 790 goto fail_1; 791 } 792 793 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 794 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 795 printf("%s: unable to create descriptor buffer DMA map, " 796 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 797 goto fail_2; 798 } 799 800 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 801 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 802 printf("%s: unable to load descriptor buffer DMA map, " 803 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 804 goto fail_3; 805 } 806 807 return 0; 808 809 fail_3: 810 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 811 fail_2: 812 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 815 fail_0: 816 return error; 817 } 818 819 static struct fwohci_desc * 820 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 821 { 822 int i, n; 823 824 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 825 for (i = 0; ; i++) { 826 if (i == ndesc) { 827 for (i = 0; i < ndesc; i++) 828 setbit(sc->sc_descmap, n + i); 829 return sc->sc_desc + n; 830 } 831 if (isset(sc->sc_descmap, n + i)) 832 break; 833 } 834 } 835 return NULL; 836 } 837 838 static void 839 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 840 { 841 int i, n; 842 843 n = fd - sc->sc_desc; 844 for (i = 0; i < ndesc; i++, n++) { 845 #ifdef DIAGNOSTIC 846 if (isclr(sc->sc_descmap, n)) 847 panic("fwohci_desc_put: duplicated free"); 848 #endif 849 clrbit(sc->sc_descmap, n); 850 } 851 } 852 853 /* 854 * Asyncronous/Isochronous Transmit/Receive Context 855 */ 856 static int 857 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 858 int bufcnt, int ctx) 859 { 860 int i, error; 861 struct fwohci_ctx *fc; 862 struct fwohci_buf *fb; 863 struct fwohci_desc *fd; 864 865 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 866 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 867 LIST_INIT(&fc->fc_handler); 868 TAILQ_INIT(&fc->fc_buf); 869 fc->fc_ctx = ctx; 870 fc->fc_bufcnt = bufcnt; 871 fb = (struct fwohci_buf *)&fc[1]; 872 for (i = 0; i < bufcnt; i++, fb++) { 873 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 874 goto fail; 875 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 876 error = ENOBUFS; 877 goto fail; 878 } 879 fb->fb_desc = fd; 880 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 881 ((caddr_t)fd - (caddr_t)sc->sc_desc); 882 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 883 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 884 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 885 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 886 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 887 } 888 *fcp = fc; 889 return 0; 890 891 fail: 892 while (i-- > 0) { 893 fb--; 894 if (fb->fb_desc) 895 fwohci_desc_put(sc, fb->fb_desc, 1); 896 fwohci_buf_free(sc, fb); 897 } 898 free(fc, M_DEVBUF); 899 return error; 900 } 901 902 static void 903 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 904 { 905 struct fwohci_buf *fb; 906 struct fwohci_handler *fh; 907 908 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 909 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 910 NULL, NULL); 911 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 912 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 913 if (fb->fb_desc) 914 fwohci_desc_put(sc, fb->fb_desc, 1); 915 fwohci_buf_free(sc, fb); 916 } 917 free(fc, M_DEVBUF); 918 } 919 920 static void 921 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 922 { 923 struct fwohci_buf *fb, *nfb; 924 struct fwohci_desc *fd; 925 struct fwohci_handler *fh; 926 int n; 927 928 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 929 nfb = TAILQ_NEXT(fb, fb_list); 930 fb->fb_off = 0; 931 fd = fb->fb_desc; 932 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 933 fd->fd_rescount = fd->fd_reqcount; 934 } 935 936 n = fc->fc_ctx; 937 fb = TAILQ_FIRST(&fc->fc_buf); 938 if (fc->fc_isoch) { 939 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 940 fb->fb_daddr | 1); 941 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 942 OHCI_CTXCTL_RX_BUFFER_FILL | 943 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 944 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 945 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 946 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 947 OHCI_CTXCTL_RX_ISOCH_HEADER); 948 fh = LIST_FIRST(&fc->fc_handler); 949 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 950 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 951 } else { 952 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 953 fb->fb_daddr | 1); 954 } 955 } 956 957 /* 958 * DMA data buffer 959 */ 960 static int 961 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 962 { 963 int error; 964 965 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 966 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 967 printf("%s: unable to allocate buffer, error = %d\n", 968 sc->sc_sc1394.sc1394_dev.dv_xname, error); 969 goto fail_0; 970 } 971 972 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 973 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 974 printf("%s: unable to map buffer, error = %d\n", 975 sc->sc_sc1394.sc1394_dev.dv_xname, error); 976 goto fail_1; 977 } 978 979 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 980 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 981 printf("%s: unable to create buffer DMA map, " 982 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 983 error); 984 goto fail_2; 985 } 986 987 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 988 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 989 printf("%s: unable to load buffer DMA map, " 990 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 991 error); 992 goto fail_3; 993 } 994 995 return 0; 996 997 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 998 fail_3: 999 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1000 fail_2: 1001 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1002 fail_1: 1003 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1004 fail_0: 1005 return error; 1006 } 1007 1008 static void 1009 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1010 { 1011 1012 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1013 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1014 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1015 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1016 } 1017 1018 static void 1019 fwohci_buf_init_rx(struct fwohci_softc *sc) 1020 { 1021 int i; 1022 1023 /* 1024 * Initialize for Asynchronous Receive Queue. 1025 */ 1026 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1027 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1028 1029 /* 1030 * Initialize for Isochronous Receive Queue. 1031 */ 1032 for (i = 0; i < sc->sc_isoctx; i++) { 1033 if (sc->sc_ctx_ir[i] != NULL) 1034 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1035 } 1036 } 1037 1038 static void 1039 fwohci_buf_start_rx(struct fwohci_softc *sc) 1040 { 1041 int i; 1042 1043 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1044 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1045 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1046 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1047 for (i = 0; i < sc->sc_isoctx; i++) { 1048 if (sc->sc_ctx_ir[i] != NULL) 1049 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1050 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1051 } 1052 } 1053 1054 static void 1055 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1056 { 1057 int i; 1058 1059 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1060 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1061 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1062 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1063 1064 /* 1065 * Make sure the transmitter is stopped. 1066 */ 1067 for (i = 0; i < OHCI_LOOP; i++) { 1068 DELAY(10); 1069 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1070 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1071 continue; 1072 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1073 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1074 continue; 1075 break; 1076 } 1077 1078 /* 1079 * Initialize for Asynchronous Transmit Queue. 1080 */ 1081 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1082 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1083 } 1084 1085 static void 1086 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1087 { 1088 int i; 1089 1090 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1091 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1092 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1093 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1094 for (i = 0; i < sc->sc_isoctx; i++) { 1095 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1096 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1097 } 1098 } 1099 1100 static void 1101 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1102 { 1103 struct fwohci_buf *fb, *tfb; 1104 1105 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1106 if (fc->fc_isoch) { 1107 if (fb->fb_off == 0) 1108 break; 1109 } else { 1110 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1111 fb->fb_desc->fd_rescount != 0) 1112 break; 1113 } 1114 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1115 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1116 fb->fb_off = 0; 1117 fb->fb_desc->fd_branch = 0; 1118 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1119 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1120 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1121 } 1122 } 1123 1124 static int 1125 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_buf **fbp, caddr_t *pp, 1126 int len) 1127 { 1128 struct fwohci_buf *fb; 1129 struct fwohci_desc *fd; 1130 int bufend; 1131 1132 fb = *fbp; 1133 again: 1134 fd = fb->fb_desc; 1135 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1136 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1137 fd->fd_reqcount, fd->fd_rescount, len, 1138 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1139 bufend = fd->fd_reqcount - fd->fd_rescount; 1140 if (fb->fb_off >= bufend) { 1141 if (fd->fd_rescount == 0) { 1142 *fbp = fb = TAILQ_NEXT(fb, fb_list); 1143 if (fb != NULL) 1144 goto again; 1145 } 1146 return 0; 1147 } 1148 if (fb->fb_off + len > bufend) 1149 len = bufend - fb->fb_off; 1150 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1151 BUS_DMASYNC_POSTREAD); 1152 *pp = fb->fb_buf + fb->fb_off; 1153 fb->fb_off += roundup(len, 4); 1154 return len; 1155 } 1156 1157 static int 1158 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1159 struct fwohci_pkt *pkt) 1160 { 1161 caddr_t p; 1162 struct fwohci_buf *fb; 1163 int len, count, i; 1164 1165 memset(pkt, 0, sizeof(*pkt)); 1166 pkt->fp_uio.uio_iov = pkt->fp_iov; 1167 pkt->fp_uio.uio_rw = UIO_WRITE; 1168 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1169 1170 /* get first quadlet */ 1171 fb = TAILQ_FIRST(&fc->fc_buf); 1172 count = 4; 1173 len = fwohci_buf_pktget(sc, &fb, &p, count); 1174 if (len <= 0) { 1175 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1176 fc->fc_ctx)); 1177 return 0; 1178 } 1179 pkt->fp_hdr[0] = *(u_int32_t *)p; 1180 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1181 switch (pkt->fp_tcode) { 1182 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1183 case IEEE1394_TCODE_READ_RESP_QUAD: 1184 pkt->fp_hlen = 12; 1185 pkt->fp_dlen = 4; 1186 break; 1187 case IEEE1394_TCODE_READ_REQ_BLOCK: 1188 pkt->fp_hlen = 16; 1189 pkt->fp_dlen = 0; 1190 break; 1191 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1192 case IEEE1394_TCODE_READ_RESP_BLOCK: 1193 case IEEE1394_TCODE_LOCK_REQ: 1194 case IEEE1394_TCODE_LOCK_RESP: 1195 pkt->fp_hlen = 16; 1196 break; 1197 #ifdef DIAGNOSTIC 1198 case IEEE1394_TCODE_STREAM_DATA: 1199 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1200 return 0; 1201 #endif 1202 default: 1203 pkt->fp_hlen = 12; 1204 pkt->fp_dlen = 0; 1205 break; 1206 } 1207 1208 /* get header */ 1209 while (count < pkt->fp_hlen) { 1210 len = fwohci_buf_pktget(sc, &fb, &p, pkt->fp_hlen - count); 1211 if (len == 0) { 1212 printf("fwohci_buf_input: malformed input 1: %d\n", 1213 pkt->fp_hlen - count); 1214 return 0; 1215 } 1216 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1217 count += len; 1218 } 1219 if (pkt->fp_hlen == 16 && 1220 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1221 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1222 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1223 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1224 1225 /* get data */ 1226 count = 0; 1227 i = 0; 1228 while (count < pkt->fp_dlen) { 1229 len = fwohci_buf_pktget(sc, &fb, 1230 (caddr_t *)&pkt->fp_iov[i].iov_base, 1231 pkt->fp_dlen - count); 1232 if (len == 0) { 1233 printf("fwohci_buf_input: malformed input 2: %d\n", 1234 pkt->fp_dlen - count); 1235 return 0; 1236 } 1237 pkt->fp_iov[i++].iov_len = len; 1238 count += len; 1239 } 1240 pkt->fp_uio.uio_iovcnt = i; 1241 pkt->fp_uio.uio_resid = count; 1242 1243 /* get trailer */ 1244 len = fwohci_buf_pktget(sc, &fb, (caddr_t *)&pkt->fp_trail, 1245 sizeof(*pkt->fp_trail)); 1246 if (len <= 0) { 1247 printf("fwohci_buf_input: malformed input 3: %d\n", 1248 pkt->fp_hlen - count); 1249 return 0; 1250 } 1251 return 1; 1252 } 1253 1254 static int 1255 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1256 struct fwohci_pkt *pkt) 1257 { 1258 caddr_t p; 1259 int len; 1260 struct fwohci_buf *fb; 1261 struct fwohci_desc *fd; 1262 1263 memset(pkt, 0, sizeof(*pkt)); 1264 pkt->fp_uio.uio_iov = pkt->fp_iov; 1265 pkt->fp_uio.uio_rw = UIO_WRITE; 1266 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1267 1268 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1269 if (fb == NULL) 1270 return 0; 1271 if (fb->fb_off == 0) 1272 break; 1273 } 1274 fd = fb->fb_desc; 1275 len = fd->fd_reqcount - fd->fd_rescount; 1276 if (len == 0) 1277 return 0; 1278 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1279 BUS_DMASYNC_POSTREAD); 1280 1281 p = fb->fb_buf; 1282 fb->fb_off += roundup(len, 4); 1283 if (len < 8) { 1284 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1285 return 0; 1286 } 1287 1288 /* 1289 * get trailer first, may be bogus data unless status update 1290 * in descriptor is set. 1291 */ 1292 pkt->fp_trail = (u_int32_t *)p; 1293 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1294 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1295 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1296 #ifdef DIAGNOSTIC 1297 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1298 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1299 pkt->fp_tcode); 1300 return 0; 1301 } 1302 #endif 1303 pkt->fp_hlen = 4; 1304 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1305 p += 8; 1306 len -= 8; 1307 if (pkt->fp_dlen != len) { 1308 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1309 pkt->fp_dlen, len); 1310 return 0; 1311 } 1312 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1313 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1314 pkt->fp_iov[0].iov_base = p; 1315 pkt->fp_iov[0].iov_len = len; 1316 pkt->fp_uio.uio_iovcnt = 0; 1317 pkt->fp_uio.uio_resid = len; 1318 return 1; 1319 } 1320 1321 static int 1322 fwohci_handler_set(struct fwohci_softc *sc, 1323 int tcode, u_int32_t key1, u_int32_t key2, 1324 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1325 void *arg) 1326 { 1327 struct fwohci_ctx *fc; 1328 struct fwohci_handler *fh; 1329 int i, j; 1330 1331 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1332 j = sc->sc_isoctx; 1333 fh = NULL; 1334 for (i = 0; i < sc->sc_isoctx; i++) { 1335 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1336 if (j == sc->sc_isoctx) 1337 j = i; 1338 continue; 1339 } 1340 fh = LIST_FIRST(&fc->fc_handler); 1341 if (fh->fh_tcode == tcode && 1342 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1343 break; 1344 fh = NULL; 1345 } 1346 if (fh == NULL) { 1347 if (handler == NULL) 1348 return 0; 1349 if (j == sc->sc_isoctx) { 1350 DPRINTF(("fwohci_handler_set: no more free " 1351 "context\n")); 1352 return ENOMEM; 1353 } 1354 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1355 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j); 1356 fc->fc_isoch = 1; 1357 sc->sc_ctx_ir[j] = fc; 1358 } 1359 } 1360 } else { 1361 switch (tcode) { 1362 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1363 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1364 case IEEE1394_TCODE_READ_REQ_QUAD: 1365 case IEEE1394_TCODE_READ_REQ_BLOCK: 1366 case IEEE1394_TCODE_LOCK_REQ: 1367 fc = sc->sc_ctx_arrq; 1368 break; 1369 case IEEE1394_TCODE_WRITE_RESP: 1370 case IEEE1394_TCODE_READ_RESP_QUAD: 1371 case IEEE1394_TCODE_READ_RESP_BLOCK: 1372 case IEEE1394_TCODE_LOCK_RESP: 1373 fc = sc->sc_ctx_arrs; 1374 break; 1375 default: 1376 return EIO; 1377 } 1378 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1379 fh = LIST_NEXT(fh, fh_list)) { 1380 if (fh->fh_tcode == tcode && 1381 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1382 break; 1383 } 1384 } 1385 if (handler == NULL) { 1386 if (fh != NULL) { 1387 LIST_REMOVE(fh, fh_list); 1388 free(fh, M_DEVBUF); 1389 } 1390 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1391 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1392 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1393 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1394 fwohci_ctx_free(sc, fc); 1395 } 1396 return 0; 1397 } 1398 if (fh == NULL) { 1399 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1400 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1401 } 1402 fh->fh_tcode = tcode; 1403 fh->fh_key1 = key1; 1404 fh->fh_key2 = key2; 1405 fh->fh_handler = handler; 1406 fh->fh_handarg = arg; 1407 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1408 fc->fc_ctx, tcode, key1, key2)); 1409 1410 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1411 fwohci_ctx_init(sc, fc); 1412 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1413 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1414 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1415 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1416 } 1417 return 0; 1418 } 1419 1420 /* 1421 * Asyncronous Receive Requests input frontend. 1422 */ 1423 static void 1424 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1425 { 1426 int rcode; 1427 u_int32_t key1, key2; 1428 struct fwohci_handler *fh; 1429 struct fwohci_pkt pkt, res; 1430 1431 /* 1432 * Do not return if next packet is in the buffer, or the next 1433 * packet cannot be received until the next receive interrupt. 1434 */ 1435 while (fwohci_buf_input(sc, fc, &pkt)) { 1436 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1437 fwohci_phy_input(sc, &pkt); 1438 continue; 1439 } 1440 key1 = pkt.fp_hdr[1] & 0xffff; 1441 key2 = pkt.fp_hdr[2]; 1442 memset(&res, 0, sizeof(res)); 1443 res.fp_uio.uio_rw = UIO_WRITE; 1444 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1445 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1446 fh = LIST_NEXT(fh, fh_list)) { 1447 if (pkt.fp_tcode == fh->fh_tcode && 1448 key1 == fh->fh_key1 && 1449 key2 == fh->fh_key2) { 1450 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1451 &pkt); 1452 break; 1453 } 1454 } 1455 if (fh == NULL) { 1456 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1457 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1458 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1459 key2)); 1460 } 1461 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1462 OHCI_CTXCTL_EVENT_ACK_PENDING) 1463 continue; 1464 if (rcode != -1) 1465 fwohci_atrs_output(sc, rcode, &pkt, &res); 1466 } 1467 fwohci_buf_next(sc, fc); 1468 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1469 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1470 } 1471 1472 1473 /* 1474 * Asynchronous Receive Response input frontend. 1475 */ 1476 static void 1477 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1478 { 1479 struct fwohci_pkt pkt; 1480 struct fwohci_handler *fh; 1481 u_int16_t srcid; 1482 int rcode, tlabel; 1483 1484 while (fwohci_buf_input(sc, fc, &pkt)) { 1485 srcid = pkt.fp_hdr[1] >> 16; 1486 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1487 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1488 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1489 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1490 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1491 pkt.fp_dlen)); 1492 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1493 fh = LIST_NEXT(fh, fh_list)) { 1494 if (pkt.fp_tcode == fh->fh_tcode && 1495 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1496 tlabel == fh->fh_key2) { 1497 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1498 LIST_REMOVE(fh, fh_list); 1499 free(fh, M_DEVBUF); 1500 break; 1501 } 1502 } 1503 if (fh == NULL) 1504 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1505 } 1506 fwohci_buf_next(sc, fc); 1507 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1508 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1509 } 1510 1511 /* 1512 * Isochronous Receive input frontend. 1513 */ 1514 static void 1515 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1516 { 1517 int rcode, chan, tag; 1518 struct iovec *iov; 1519 struct fwohci_handler *fh; 1520 struct fwohci_pkt pkt; 1521 1522 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 1523 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1524 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1525 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1526 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1527 pkt.fp_dlen)); 1528 if (tag == IEEE1394_TAG_GASP) { 1529 /* 1530 * The pkt with tag=3 is GASP format. 1531 * Move GASP header to header part. 1532 */ 1533 if (pkt.fp_dlen < 8) 1534 continue; 1535 iov = pkt.fp_iov; 1536 /* assuming pkt per buffer mode */ 1537 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1538 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1539 iov->iov_base = (caddr_t)iov->iov_base + 8; 1540 iov->iov_len -= 8; 1541 pkt.fp_hlen += 8; 1542 pkt.fp_dlen -= 8; 1543 } 1544 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1545 fh = LIST_NEXT(fh, fh_list)) { 1546 if (pkt.fp_tcode == fh->fh_tcode && 1547 chan == fh->fh_key1 && tag == fh->fh_key2) { 1548 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1549 &pkt); 1550 break; 1551 } 1552 } 1553 #ifdef FW_DEBUG 1554 if (fh == NULL) { 1555 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1556 } else { 1557 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1558 } 1559 #endif 1560 } 1561 fwohci_buf_next(sc, fc); 1562 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1563 OHCI_CTXCTL_WAKE); 1564 } 1565 1566 /* 1567 * Asynchronous Transmit common routine. 1568 */ 1569 static int 1570 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1571 struct fwohci_pkt *pkt) 1572 { 1573 struct fwohci_buf *fb; 1574 struct fwohci_desc *fd; 1575 struct mbuf *m, *m0; 1576 int i, ndesc, error, off, len; 1577 u_int32_t val; 1578 #ifdef FW_DEBUG 1579 struct iovec *iov; 1580 #endif 1581 1582 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 1583 /* We can't send anything during selfid duration */ 1584 return EAGAIN; 1585 1586 #ifdef FW_DEBUG 1587 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1588 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1589 for (i = 0; i < pkt->fp_hlen/4; i++) 1590 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 1591 DPRINTFN(2, ("$")); 1592 for (ndesc = 0, iov = pkt->fp_iov; 1593 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1594 for (i = 0; i < iov->iov_len; i++) 1595 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 1596 ((u_int8_t *)iov->iov_base)[i])); 1597 DPRINTFN(2, ("$")); 1598 } 1599 DPRINTFN(1, ("\n")); 1600 #endif 1601 1602 if ((m = pkt->fp_m) != NULL) { 1603 for (ndesc = 2; m != NULL; m = m->m_next) 1604 ndesc++; 1605 if (ndesc > OHCI_DESC_MAX) { 1606 m0 = NULL; 1607 ndesc = 2; 1608 for (off = 0; off < pkt->fp_dlen; off += len) { 1609 if (m0 == NULL) { 1610 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1611 if (m0 != NULL) 1612 M_COPY_PKTHDR(m0, pkt->fp_m); 1613 m = m0; 1614 } else { 1615 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1616 m = m->m_next; 1617 } 1618 if (m != NULL) 1619 MCLGET(m, M_DONTWAIT); 1620 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1621 m_freem(m0); 1622 return ENOMEM; 1623 } 1624 len = pkt->fp_dlen - off; 1625 if (len > m->m_ext.ext_size) 1626 len = m->m_ext.ext_size; 1627 m_copydata(pkt->fp_m, off, len, 1628 mtod(m, caddr_t)); 1629 m->m_len = len; 1630 ndesc++; 1631 } 1632 m_freem(pkt->fp_m); 1633 pkt->fp_m = m0; 1634 } 1635 } else 1636 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1637 1638 if (ndesc > OHCI_DESC_MAX) 1639 return ENOBUFS; 1640 1641 if (fc->fc_bufcnt > 50) /*XXX*/ 1642 return ENOBUFS; 1643 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1644 fb->fb_nseg = ndesc; 1645 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1646 if (fb->fb_desc == NULL) { 1647 free(fb, M_DEVBUF); 1648 return ENOBUFS; 1649 } 1650 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1651 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1652 fb->fb_m = pkt->fp_m; 1653 fb->fb_callback = pkt->fp_callback; 1654 fb->fb_statuscb = pkt->fp_statuscb; 1655 fb->fb_statusarg = pkt->fp_statusarg; 1656 1657 if (ndesc > 2) { 1658 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1659 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1660 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1661 free(fb, M_DEVBUF); 1662 return error; 1663 } 1664 1665 if (pkt->fp_m != NULL) 1666 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1667 pkt->fp_m, BUS_DMA_WAITOK); 1668 else 1669 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1670 &pkt->fp_uio, BUS_DMA_WAITOK); 1671 if (error != 0) { 1672 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1673 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1674 free(fb, M_DEVBUF); 1675 return error; 1676 } 1677 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1678 BUS_DMASYNC_PREWRITE); 1679 } 1680 1681 fd = fb->fb_desc; 1682 fd->fd_flags = OHCI_DESC_IMMED; 1683 fd->fd_reqcount = pkt->fp_hlen; 1684 fd->fd_data = 0; 1685 fd->fd_branch = 0; 1686 fd->fd_status = 0; 1687 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1688 i = 3; /* XXX: 3 sec */ 1689 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1690 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1691 ((((val >> 25) + i) & 0x7) << 13); 1692 } else 1693 fd->fd_timestamp = 0; 1694 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1695 for (i = 0; i < ndesc - 2; i++) { 1696 fd = fb->fb_desc + 2 + i; 1697 fd->fd_flags = 0; 1698 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1699 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1700 fd->fd_branch = 0; 1701 fd->fd_status = 0; 1702 fd->fd_timestamp = 0; 1703 } 1704 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1705 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1706 1707 #ifdef FW_DEBUG 1708 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1709 (long)(fb->fb_desc - sc->sc_desc))); 1710 for (i = 0; i < ndesc * 4; i++) 1711 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1712 ((u_int32_t *)fb->fb_desc)[i])); 1713 DPRINTFN(1, ("\n")); 1714 #endif 1715 1716 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1717 OHCI_SUBREG_ContextControlClear); 1718 1719 if (val & OHCI_CTXCTL_RUN) { 1720 if (fc->fc_branch == NULL) { 1721 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1722 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1723 goto run; 1724 } 1725 *fc->fc_branch = fb->fb_daddr | ndesc; 1726 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1727 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1728 } else { 1729 run: 1730 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1731 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1732 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1733 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1734 } 1735 fc->fc_branch = &fd->fd_branch; 1736 1737 fc->fc_bufcnt++; 1738 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1739 pkt->fp_m = NULL; 1740 return 0; 1741 } 1742 1743 static void 1744 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1745 { 1746 struct fwohci_buf *fb; 1747 struct fwohci_desc *fd; 1748 struct fwohci_pkt pkt; 1749 int i; 1750 1751 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1752 fd = fb->fb_desc; 1753 #ifdef FW_DEBUG 1754 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1755 force ? "force " : "", (long)(fd - sc->sc_desc), 1756 fb->fb_nseg)); 1757 for (i = 0; i < fb->fb_nseg * 4; i++) 1758 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1759 ((u_int32_t *)fd)[i])); 1760 DPRINTFN(1, ("\n")); 1761 #endif 1762 if (fb->fb_nseg > 2) 1763 fd += fb->fb_nseg - 1; 1764 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 1765 break; 1766 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1767 if (fc->fc_branch == &fd->fd_branch) { 1768 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1769 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1770 fc->fc_branch = NULL; 1771 for (i = 0; i < OHCI_LOOP; i++) { 1772 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1773 OHCI_SUBREG_ContextControlClear) & 1774 OHCI_CTXCTL_ACTIVE)) 1775 break; 1776 DELAY(10); 1777 } 1778 } 1779 1780 if (fb->fb_statuscb) { 1781 memset(&pkt, 0, sizeof(pkt)); 1782 pkt.fp_status = fd->fd_status; 1783 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 1784 1785 /* Indicate this is just returning the status bits. */ 1786 pkt.fp_tcode = -1; 1787 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 1788 fb->fb_statuscb = NULL; 1789 fb->fb_statusarg = NULL; 1790 } 1791 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 1792 if (fb->fb_nseg > 2) 1793 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1794 fc->fc_bufcnt--; 1795 if (fb->fb_callback) { 1796 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 1797 fb->fb_callback = NULL; 1798 } else if (fb->fb_m != NULL) 1799 m_freem(fb->fb_m); 1800 free(fb, M_DEVBUF); 1801 } 1802 } 1803 1804 /* 1805 * Asynchronous Transmit Reponse -- in response of request packet. 1806 */ 1807 static void 1808 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1809 struct fwohci_pkt *res) 1810 { 1811 1812 if (((*req->fp_trail & 0x001f0000) >> 16) != 1813 OHCI_CTXCTL_EVENT_ACK_PENDING) 1814 return; 1815 1816 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1817 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1818 switch (req->fp_tcode) { 1819 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1820 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1821 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1822 res->fp_hlen = 12; 1823 break; 1824 case IEEE1394_TCODE_READ_REQ_QUAD: 1825 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1826 res->fp_hlen = 16; 1827 res->fp_dlen = 0; 1828 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1829 res->fp_hdr[3] = 1830 *(u_int32_t *)res->fp_iov[0].iov_base; 1831 res->fp_uio.uio_iovcnt = 0; 1832 break; 1833 case IEEE1394_TCODE_READ_REQ_BLOCK: 1834 case IEEE1394_TCODE_LOCK_REQ: 1835 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1836 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1837 else 1838 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1839 res->fp_hlen = 16; 1840 res->fp_dlen = res->fp_uio.uio_resid; 1841 res->fp_hdr[3] = res->fp_dlen << 16; 1842 break; 1843 } 1844 res->fp_hdr[0] |= (res->fp_tcode << 4); 1845 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1846 } 1847 1848 /* 1849 * APPLICATION LAYER SERVICES 1850 */ 1851 1852 /* 1853 * Retrieve Global UID from GUID ROM 1854 */ 1855 static int 1856 fwohci_guidrom_init(struct fwohci_softc *sc) 1857 { 1858 int i, n, off; 1859 u_int32_t val1, val2; 1860 1861 /* Extract the Global UID 1862 */ 1863 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 1864 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 1865 1866 if (val1 != 0 || val2 != 0) { 1867 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 1868 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 1869 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 1870 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 1871 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 1872 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 1873 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 1874 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 1875 } else { 1876 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 1877 if ((val1 & OHCI_Version_GUID_ROM) == 0) 1878 return -1; 1879 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 1880 for (i = 0; i < OHCI_LOOP; i++) { 1881 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1882 if (!(val1 & OHCI_Guid_AddrReset)) 1883 break; 1884 DELAY(10); 1885 } 1886 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 1887 val2 = 0; 1888 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 1889 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 1890 OHCI_Guid_RdStart); 1891 for (i = 0; i < OHCI_LOOP; i++) { 1892 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 1893 if (!(val1 & OHCI_Guid_RdStart)) 1894 break; 1895 DELAY(10); 1896 } 1897 if (n < off) 1898 continue; 1899 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 1900 sc->sc_sc1394.sc1394_guid[n - off] = val1; 1901 val2 |= val1; 1902 } 1903 if (val2 == 0) 1904 return -1; 1905 } 1906 return 0; 1907 } 1908 1909 /* 1910 * Initialization for Configuration ROM (no DMA context) 1911 */ 1912 1913 #define CFR_MAXUNIT 20 1914 1915 struct configromctx { 1916 u_int32_t *ptr; 1917 int curunit; 1918 struct { 1919 u_int32_t *start; 1920 int length; 1921 u_int32_t *refer; 1922 int refunit; 1923 } unit[CFR_MAXUNIT]; 1924 }; 1925 1926 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1927 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1928 1929 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1930 1931 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1932 1933 #define CFR_PUT_CRC(cfr, n) \ 1934 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1935 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1936 1937 #define CFR_START_UNIT(cfr, n) \ 1938 do { \ 1939 if ((cfr)->unit[n].refer != NULL) { \ 1940 *(cfr)->unit[n].refer |= \ 1941 (cfr)->ptr - (cfr)->unit[n].refer; \ 1942 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1943 } \ 1944 (cfr)->curunit = (n); \ 1945 (cfr)->unit[n].start = (cfr)->ptr++; \ 1946 } while (0 /* CONSTCOND */) 1947 1948 #define CFR_PUT_REFER(cfr, key, n) \ 1949 do { \ 1950 (cfr)->unit[n].refer = (cfr)->ptr; \ 1951 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1952 *(cfr)->ptr++ = (key) << 24; \ 1953 } while (0 /* CONSTCOND */) 1954 1955 #define CFR_END_UNIT(cfr) \ 1956 do { \ 1957 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1958 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1959 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1960 } while (0 /* CONSTCOND */) 1961 1962 static u_int16_t 1963 fwohci_crc16(u_int32_t *ptr, int len) 1964 { 1965 int shift; 1966 u_int32_t crc, sum, data; 1967 1968 crc = 0; 1969 while (len-- > 0) { 1970 data = *ptr++; 1971 for (shift = 28; shift >= 0; shift -= 4) { 1972 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1973 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1974 } 1975 crc &= 0xffff; 1976 } 1977 return crc; 1978 } 1979 1980 static void 1981 fwohci_configrom_init(struct fwohci_softc *sc) 1982 { 1983 int i, val; 1984 struct fwohci_buf *fb; 1985 u_int32_t *hdr; 1986 struct configromctx cfr; 1987 1988 fb = &sc->sc_buf_cnfrom; 1989 memset(&cfr, 0, sizeof(cfr)); 1990 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1991 1992 /* headers */ 1993 CFR_START_UNIT(&cfr, 0); 1994 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1995 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1996 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1997 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1998 CFR_END_UNIT(&cfr); 1999 /* copy info_length from crc_length */ 2000 *hdr |= (*hdr & 0x00ff0000) << 8; 2001 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2002 2003 /* root directory */ 2004 CFR_START_UNIT(&cfr, 1); 2005 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2006 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2007 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2008 /* spt,64,fix,lst,drq */ 2009 #ifdef INET 2010 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2011 #endif /* INET */ 2012 #ifdef INET6 2013 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2014 #endif /* INET6 */ 2015 CFR_END_UNIT(&cfr); 2016 2017 CFR_START_UNIT(&cfr, 2); 2018 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2019 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2020 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2021 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2022 CFR_END_UNIT(&cfr); 2023 2024 #ifdef INET 2025 /* IPv4 unit directory */ 2026 CFR_START_UNIT(&cfr, 3); 2027 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2028 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2029 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2030 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2031 CFR_END_UNIT(&cfr); 2032 2033 CFR_START_UNIT(&cfr, 6); 2034 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2035 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2036 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2037 CFR_END_UNIT(&cfr); 2038 2039 CFR_START_UNIT(&cfr, 7); 2040 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2041 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2042 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2043 CFR_END_UNIT(&cfr); 2044 #endif /* INET */ 2045 2046 #ifdef INET6 2047 /* IPv6 unit directory */ 2048 CFR_START_UNIT(&cfr, 4); 2049 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2050 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2051 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2052 /* XXX: TBA by IANA */ 2053 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2054 CFR_END_UNIT(&cfr); 2055 2056 CFR_START_UNIT(&cfr, 8); 2057 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2058 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2059 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2060 CFR_END_UNIT(&cfr); 2061 2062 CFR_START_UNIT(&cfr, 9); 2063 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2064 CFR_PUT_DATA1(&cfr, 0); 2065 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2066 CFR_END_UNIT(&cfr); 2067 #endif /* INET6 */ 2068 2069 fb->fb_off = cfr.ptr - hdr; 2070 #ifdef FW_DEBUG 2071 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2072 for (i = 0; i < fb->fb_off; i++) 2073 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2074 DPRINTFN(2, ("\n")); 2075 #endif /* FW_DEBUG */ 2076 2077 /* 2078 * Make network byte order for DMA 2079 */ 2080 for (i = 0; i < fb->fb_off; i++) 2081 HTONL(hdr[i]); 2082 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2083 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2084 2085 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2086 fb->fb_dmamap->dm_segs[0].ds_addr); 2087 2088 /* This register is only valid on OHCI 1.1. */ 2089 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2090 if ((OHCI_Version_GET_Version(val) == 1) && 2091 (OHCI_Version_GET_Revision(val) == 1)) 2092 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2093 OHCI_HCControl_BIBImageValid); 2094 2095 /* Just allow quad reads of the rom. */ 2096 for (i = 0; i < fb->fb_off; i++) 2097 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2098 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2099 fwohci_configrom_input, NULL); 2100 } 2101 2102 static int 2103 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2104 struct fwohci_pkt *pkt) 2105 { 2106 struct fwohci_pkt res; 2107 u_int32_t loc, *rom; 2108 2109 /* This will be used as an array index so size accordingly. */ 2110 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2111 if ((loc & 0x03) != 0) { 2112 /* alignment error */ 2113 return IEEE1394_RCODE_ADDRESS_ERROR; 2114 } 2115 else 2116 loc /= 4; 2117 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2118 2119 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2120 ntohl(rom[loc]))); 2121 2122 memset(&res, 0, sizeof(res)); 2123 res.fp_hdr[3] = rom[loc]; 2124 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2125 return -1; 2126 } 2127 2128 /* 2129 * SelfID buffer (no DMA context) 2130 */ 2131 static void 2132 fwohci_selfid_init(struct fwohci_softc *sc) 2133 { 2134 struct fwohci_buf *fb; 2135 2136 fb = &sc->sc_buf_selfid; 2137 #ifdef DIAGNOSTIC 2138 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2139 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2140 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2141 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2142 #endif 2143 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2144 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2145 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2146 2147 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2148 fb->fb_dmamap->dm_segs[0].ds_addr); 2149 } 2150 2151 static int 2152 fwohci_selfid_input(struct fwohci_softc *sc) 2153 { 2154 int i; 2155 u_int32_t count, val, gen; 2156 u_int32_t *buf; 2157 2158 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2159 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2160 again: 2161 if (val & OHCI_SelfID_Error) { 2162 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2163 return -1; 2164 } 2165 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2166 2167 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2168 0, count << 2, BUS_DMASYNC_POSTREAD); 2169 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2170 2171 #ifdef FW_DEBUG 2172 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2173 val)); 2174 for (i = 0; i < count; i++) 2175 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2176 DPRINTFN(1, ("\n")); 2177 #endif /* FW_DEBUG */ 2178 2179 for (i = 1; i < count; i += 2) { 2180 if (buf[i] != ~buf[i + 1]) 2181 break; 2182 if (buf[i] & 0x00000001) 2183 continue; /* more pkt */ 2184 if (buf[i] & 0x00800000) 2185 continue; /* external id */ 2186 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2187 if ((buf[i] & 0x00400800) == 0x00400800) 2188 sc->sc_irmid = sc->sc_rootid; 2189 } 2190 2191 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2192 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2193 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2194 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2195 goto again; 2196 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2197 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2198 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2199 return -1; 2200 } 2201 if (i != count) { 2202 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2203 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2204 #if 1 2205 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2206 /* 2207 * XXX: CXD3222 sometimes fails to DMA 2208 * selfid packet?? 2209 */ 2210 sc->sc_rootid = (count - 1) / 2 - 1; 2211 sc->sc_irmid = sc->sc_rootid; 2212 } else 2213 #endif 2214 return -1; 2215 } 2216 2217 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2218 if ((val & OHCI_NodeId_IDValid) == 0) { 2219 sc->sc_nodeid = 0xffff; /* invalid */ 2220 printf("%s: nodeid is invalid\n", 2221 sc->sc_sc1394.sc1394_dev.dv_xname); 2222 return -1; 2223 } 2224 sc->sc_nodeid = val & 0xffff; 2225 2226 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2227 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2228 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2229 sc->sc_irmid)); 2230 2231 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2232 return -1; 2233 2234 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2235 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2236 OHCI_LinkControl_CycleMaster); 2237 else 2238 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2239 OHCI_LinkControl_CycleMaster); 2240 return 0; 2241 } 2242 2243 /* 2244 * some CSRs are handled by driver. 2245 */ 2246 static void 2247 fwohci_csr_init(struct fwohci_softc *sc) 2248 { 2249 int i; 2250 static u_int32_t csr[] = { 2251 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2252 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2253 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2254 CSR_SB_BROADCAST_CHANNEL 2255 }; 2256 2257 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2258 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2259 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2260 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2261 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2262 } 2263 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2264 } 2265 2266 static int 2267 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2268 { 2269 struct fwohci_pkt res; 2270 u_int32_t reg; 2271 2272 /* 2273 * XXX need to do special functionality other than just r/w... 2274 */ 2275 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2276 2277 if ((reg & 0x03) != 0) { 2278 /* alignment error */ 2279 return IEEE1394_RCODE_ADDRESS_ERROR; 2280 } 2281 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2282 *(u_int32_t *)(&sc->sc_csr[reg]))); 2283 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2284 DPRINTFN(1, (" -> 0x%08x\n", 2285 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2286 *(u_int32_t *)&sc->sc_csr[reg] = 2287 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2288 } else { 2289 DPRINTFN(1, ("\n")); 2290 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2291 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2292 res.fp_iov[0].iov_len = 4; 2293 res.fp_uio.uio_resid = 4; 2294 res.fp_uio.uio_iovcnt = 1; 2295 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2296 return -1; 2297 } 2298 return IEEE1394_RCODE_COMPLETE; 2299 } 2300 2301 /* 2302 * Mapping between nodeid and unique ID (EUI-64). 2303 * 2304 * Track old mappings and simply update their devices with the new id's when 2305 * they match an existing EUI. This allows proper renumeration of the bus. 2306 */ 2307 static void 2308 fwohci_uid_collect(struct fwohci_softc *sc) 2309 { 2310 int i; 2311 struct fwohci_uidtbl *fu; 2312 struct ieee1394_softc *iea; 2313 2314 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2315 iea->sc1394_node_id = 0xffff; 2316 2317 if (sc->sc_uidtbl != NULL) 2318 free(sc->sc_uidtbl, M_DEVBUF); 2319 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2320 M_NOWAIT); /* XXX M_WAITOK requires locks */ 2321 if (sc->sc_uidtbl == NULL) 2322 return; 2323 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2324 2325 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2326 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2327 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2328 fu->fu_valid = 3; 2329 2330 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2331 if (iea) { 2332 iea->sc1394_node_id = i; 2333 DPRINTF(("%s: Updating nodeid to %d\n", 2334 iea->sc1394_dev.dv_xname, 2335 iea->sc1394_node_id)); 2336 } 2337 } else { 2338 fu->fu_valid = 0; 2339 fwohci_uid_req(sc, i); 2340 } 2341 } 2342 if (sc->sc_rootid == 0) 2343 fwohci_check_nodes(sc); 2344 } 2345 2346 static void 2347 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 2348 { 2349 struct fwohci_pkt pkt; 2350 2351 memset(&pkt, 0, sizeof(pkt)); 2352 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2353 pkt.fp_hlen = 12; 2354 pkt.fp_dlen = 0; 2355 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2356 (pkt.fp_tcode << 4); 2357 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 2358 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2359 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2360 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2361 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2362 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2363 2364 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2365 (pkt.fp_tcode << 4); 2366 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2367 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2368 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2369 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2370 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2371 } 2372 2373 static int 2374 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2375 { 2376 struct fwohci_uidtbl *fu; 2377 struct ieee1394_softc *iea; 2378 struct ieee1394_attach_args fwa; 2379 int i, n, done, rcode, found; 2380 2381 found = 0; 2382 2383 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2384 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2385 if (rcode != IEEE1394_RCODE_COMPLETE || 2386 sc->sc_uidtbl == NULL || 2387 n > sc->sc_rootid) 2388 return 0; 2389 fu = &sc->sc_uidtbl[n]; 2390 if (arg == 0) { 2391 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2392 fu->fu_valid |= 0x1; 2393 } else { 2394 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2395 fu->fu_valid |= 0x2; 2396 } 2397 #ifdef FW_DEBUG 2398 if (fu->fu_valid == 0x3) 2399 DPRINTFN(1, ("fwohci_uid_input: " 2400 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2401 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2402 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2403 #endif 2404 if (fu->fu_valid == 0x3) { 2405 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2406 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2407 found = 1; 2408 iea->sc1394_node_id = n; 2409 DPRINTF(("%s: Updating nodeid to %d\n", 2410 iea->sc1394_dev.dv_xname, 2411 iea->sc1394_node_id)); 2412 break; 2413 } 2414 if (!found) { 2415 strcpy(fwa.name, "fwnode"); 2416 memcpy(fwa.uid, fu->fu_uid, 8); 2417 fwa.nodeid = n; 2418 fwa.read = fwohci_read; 2419 fwa.write = fwohci_write; 2420 fwa.inreg = fwohci_inreg; 2421 iea = (struct ieee1394_softc *) 2422 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2423 fwohci_print, fwohci_submatch); 2424 if (iea != NULL) 2425 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2426 sc1394_node); 2427 } 2428 } 2429 done = 1; 2430 2431 for (i = 0; i < sc->sc_rootid + 1; i++) { 2432 fu = &sc->sc_uidtbl[i]; 2433 if (fu->fu_valid != 0x3) { 2434 done = 0; 2435 break; 2436 } 2437 } 2438 if (done) 2439 fwohci_check_nodes(sc); 2440 2441 return 0; 2442 } 2443 2444 static void 2445 fwohci_check_nodes(struct fwohci_softc *sc) 2446 { 2447 struct device *detach = NULL; 2448 struct ieee1394_softc *iea; 2449 2450 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2451 2452 /* 2453 * Have to defer detachment until the next 2454 * loop iteration since config_detach 2455 * free's the softc and the loop iterator 2456 * needs data from the softc to move 2457 * forward. 2458 */ 2459 2460 if (detach) { 2461 config_detach(detach, 0); 2462 detach = NULL; 2463 } 2464 if (iea->sc1394_node_id == 0xffff) { 2465 detach = (struct device *)iea; 2466 LIST_REMOVE(iea, sc1394_node); 2467 } 2468 } 2469 if (detach) 2470 config_detach(detach, 0); 2471 } 2472 2473 static int 2474 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2475 { 2476 struct fwohci_uidtbl *fu; 2477 int n; 2478 static const u_int8_t bcast[] = 2479 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2480 2481 fu = sc->sc_uidtbl; 2482 if (fu == NULL) { 2483 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2484 return IEEE1394_BCAST_PHY_ID; 2485 fwohci_uid_collect(sc); /* try to get */ 2486 return -1; 2487 } 2488 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 2489 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2490 return n; 2491 } 2492 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2493 return IEEE1394_BCAST_PHY_ID; 2494 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 2495 if (fu->fu_valid != 0x3) { 2496 /* 2497 * XXX: need timer before retransmission 2498 */ 2499 fwohci_uid_req(sc, n); 2500 } 2501 } 2502 return -1; 2503 } 2504 2505 /* 2506 * functions to support network interface 2507 */ 2508 static int 2509 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2510 void (*handler)(struct device *, struct mbuf *)) 2511 { 2512 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2513 2514 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2515 handler ? fwohci_if_input : NULL, handler); 2516 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2517 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 2518 IEEE1394_TAG_GASP, handler ? fwohci_if_input : NULL, handler); 2519 return 0; 2520 } 2521 2522 static int 2523 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2524 { 2525 int n, len; 2526 struct mbuf *m; 2527 struct iovec *iov; 2528 void (*handler)(struct device *, struct mbuf *) = arg; 2529 2530 #ifdef FW_DEBUG 2531 int i; 2532 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2533 pkt->fp_dlen)); 2534 for (i = 0; i < pkt->fp_hlen/4; i++) 2535 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2536 DPRINTFN(2, ("$")); 2537 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2538 iov = &pkt->fp_iov[n]; 2539 for (i = 0; i < iov->iov_len; i++) 2540 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2541 ((u_int8_t *)iov->iov_base)[i])); 2542 DPRINTFN(2, ("$")); 2543 } 2544 DPRINTFN(1, ("\n")); 2545 #endif /* FW_DEBUG */ 2546 len = pkt->fp_dlen; 2547 MGETHDR(m, M_DONTWAIT, MT_DATA); 2548 if (m == NULL) 2549 return IEEE1394_RCODE_COMPLETE; 2550 m->m_len = 16; 2551 if (len + m->m_len > MHLEN) { 2552 MCLGET(m, M_DONTWAIT); 2553 if ((m->m_flags & M_EXT) == 0) { 2554 m_freem(m); 2555 return IEEE1394_RCODE_COMPLETE; 2556 } 2557 } 2558 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2559 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2560 sc->sc_uidtbl[n].fu_valid != 0x3) { 2561 printf("%s: packet from unknown node: phy id %d\n", 2562 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2563 m_freem(m); 2564 fwohci_uid_req(sc, n); 2565 return IEEE1394_RCODE_COMPLETE; 2566 } 2567 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2568 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2569 m->m_flags |= M_BCAST; 2570 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2571 } else { 2572 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2573 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2574 } 2575 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2576 mtod(m, u_int8_t *)[9] = 2577 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2578 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2579 2580 m->m_pkthdr.rcvif = NULL; /* set in child */ 2581 m->m_pkthdr.len = len + m->m_len; 2582 /* 2583 * We may use receive buffer by external mbuf instead of copy here. 2584 * But asynchronous receive buffer must be operate in buffer fill 2585 * mode, so that each receive buffer will shared by multiple mbufs. 2586 * If upper layer doesn't free mbuf soon, e.g. application program 2587 * is suspended, buffer must be reallocated. 2588 * Isochronous buffer must be operate in packet buffer mode, and 2589 * it is easy to map receive buffer to external mbuf. But it is 2590 * used for broadcast/multicast only, and is expected not so 2591 * performance sensitive for now. 2592 * XXX: The performance may be important for multicast case, 2593 * so we should revisit here later. 2594 * -- onoe 2595 */ 2596 n = 0; 2597 iov = pkt->fp_uio.uio_iov; 2598 while (len > 0) { 2599 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2600 iov->iov_len); 2601 m->m_len += iov->iov_len; 2602 len -= iov->iov_len; 2603 iov++; 2604 } 2605 (*handler)(sc->sc_sc1394.sc1394_if, m); 2606 return IEEE1394_RCODE_COMPLETE; 2607 } 2608 2609 static int 2610 fwohci_if_output(struct device *self, struct mbuf *m0, 2611 void (*callback)(struct device *, struct mbuf *)) 2612 { 2613 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2614 struct fwohci_pkt pkt; 2615 u_int8_t *p; 2616 int n, error, spd, hdrlen, maxrec; 2617 #ifdef FW_DEBUG 2618 struct mbuf *m; 2619 #endif 2620 2621 p = mtod(m0, u_int8_t *); 2622 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2623 spd = IEEE1394_SPD_S100; /*XXX*/ 2624 maxrec = 512; /*XXX*/ 2625 hdrlen = 8; 2626 } else { 2627 n = fwohci_uid_lookup(sc, p); 2628 if (n < 0) { 2629 printf("%s: nodeid unknown:" 2630 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2631 sc->sc_sc1394.sc1394_dev.dv_xname, 2632 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2633 error = EHOSTUNREACH; 2634 goto end; 2635 } 2636 if (n == IEEE1394_BCAST_PHY_ID) { 2637 printf("%s: broadcast with !M_MCAST\n", 2638 sc->sc_sc1394.sc1394_dev.dv_xname); 2639 #ifdef FW_DEBUG 2640 DPRINTFN(2, ("packet:")); 2641 for (m = m0; m != NULL; m = m->m_next) { 2642 for (n = 0; n < m->m_len; n++) 2643 DPRINTFN(2, ("%s%02x", (n%32)? 2644 ((n%4)?"":" "):"\n ", 2645 mtod(m, u_int8_t *)[n])); 2646 DPRINTFN(2, ("$")); 2647 } 2648 DPRINTFN(2, ("\n")); 2649 #endif 2650 error = EHOSTUNREACH; 2651 goto end; 2652 } 2653 maxrec = 2 << p[8]; 2654 spd = p[9]; 2655 hdrlen = 0; 2656 } 2657 if (spd > sc->sc_sc1394.sc1394_link_speed) { 2658 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 2659 spd, sc->sc_sc1394.sc1394_link_speed)); 2660 spd = sc->sc_sc1394.sc1394_link_speed; 2661 } 2662 if (maxrec > (512 << spd)) { 2663 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 2664 "\n", maxrec, spd)); 2665 maxrec = 512 << spd; 2666 } 2667 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 2668 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 2669 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 2670 maxrec >>= 1; 2671 } 2672 if (maxrec < 512) { 2673 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 2674 "minimum\n", maxrec)); 2675 maxrec = 512; 2676 } 2677 2678 m_adj(m0, 16 - hdrlen); 2679 if (m0->m_pkthdr.len > maxrec) { 2680 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 2681 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 2682 error = E2BIG; /*XXX*/ 2683 goto end; 2684 } 2685 2686 memset(&pkt, 0, sizeof(pkt)); 2687 pkt.fp_uio.uio_iov = pkt.fp_iov; 2688 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2689 pkt.fp_uio.uio_rw = UIO_WRITE; 2690 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2691 /* construct GASP header */ 2692 p = mtod(m0, u_int8_t *); 2693 p[0] = sc->sc_nodeid >> 8; 2694 p[1] = sc->sc_nodeid & 0xff; 2695 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 2696 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 2697 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 2698 pkt.fp_hlen = 8; 2699 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 2700 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 2701 OHCI_NodeId_NodeNumber) << 8); 2702 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 2703 } else { 2704 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 2705 pkt.fp_hlen = 16; 2706 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 2707 (spd << 16); 2708 pkt.fp_hdr[1] = 2709 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 2710 (p[10] << 8) | p[11]; 2711 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 2712 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 2713 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2714 } 2715 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 2716 pkt.fp_dlen = m0->m_pkthdr.len; 2717 pkt.fp_m = m0; 2718 pkt.fp_callback = callback; 2719 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2720 m0 = pkt.fp_m; 2721 end: 2722 if (m0 != NULL) { 2723 if (callback) 2724 (*callback)(sc->sc_sc1394.sc1394_if, m0); 2725 else 2726 m_freem(m0); 2727 } 2728 return error; 2729 } 2730 2731 /* 2732 * High level routines to provide abstraction to attaching layers to 2733 * send/receive data. 2734 */ 2735 2736 /* 2737 * These break down into 4 routines as follows: 2738 * 2739 * int fwohci_read(struct ieee1394_abuf *) 2740 * 2741 * This routine will attempt to read a region from the requested node. 2742 * A callback must be provided which will be called when either the completed 2743 * read is done or an unrecoverable error occurs. This is mainly a convenience 2744 * routine since it will encapsulate retrying a region as quadlet vs. block reads 2745 * and recombining all the returned data. This could also be done with a series 2746 * of write/inreg's for each packet sent. 2747 * 2748 * int fwohci_write(struct ieee1394_abuf *) 2749 * 2750 * The work horse main entry point for putting packets on the bus. This is the 2751 * generalized interface for fwnode/etc code to put packets out onto the bus. 2752 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 2753 * will callback via a func pointer to the calling code with the resulting ACK 2754 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 2755 * write routine will take care of free'ing the abuf since the fwnode/etc code 2756 * won't have any knowledge of when to do this. This allows for simple one-off 2757 * packets to be sent from the upper-level code without worrying about a callback 2758 * for cleanup. 2759 * 2760 * int fwohci_inreg(struct ieee1394_abuf *, int) 2761 * 2762 * This is very simple. It evals the abuf passed in and registers an internal 2763 * handler as the callback for packets received for that operation. 2764 * The integer argument specifies whether on a block read/write operation to 2765 * allow sub-regions to be read/written (in block form) as well. 2766 * 2767 * XXX: This whole structure needs to be redone as a list of regions and 2768 * operations allowed on those regions. 2769 * 2770 * int fwohci_unreg(struct ieee1394_abuf *, int) 2771 * 2772 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 2773 * routine will simply verify ab_cb is NULL and call inreg. 2774 * 2775 * This simply unregisters the respective callback done via inreg for items 2776 * which only need to register an area for a one-time operation (like a status 2777 * buffer a remote node will write to when the current operation is done). The 2778 * int argument specifies the same behavior as inreg, except in reverse (i.e. 2779 * it unregisters). 2780 */ 2781 2782 static int 2783 fwohci_read(struct ieee1394_abuf *ab) 2784 { 2785 struct fwohci_pkt pkt; 2786 struct ieee1394_softc *sc = ab->ab_req; 2787 struct fwohci_softc *psc = 2788 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2789 struct fwohci_cb *fcb; 2790 u_int32_t high, lo; 2791 int rv, tcode; 2792 2793 /* Have to have a callback when reading. */ 2794 if (ab->ab_cb == NULL) 2795 return -1; 2796 2797 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 2798 fcb->ab = ab; 2799 fcb->count = 0; 2800 fcb->abuf_valid = 1; 2801 2802 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2803 lo = (ab->ab_csr & 0x00000000ffffffff); 2804 2805 memset(&pkt, 0, sizeof(pkt)); 2806 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2807 pkt.fp_hdr[2] = lo; 2808 pkt.fp_dlen = 0; 2809 2810 if (ab->ab_length == 4) { 2811 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2812 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2813 pkt.fp_hlen = 12; 2814 } else { 2815 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 2816 pkt.fp_hlen = 16; 2817 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2818 pkt.fp_hdr[3] = (ab->ab_length << 16); 2819 } 2820 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2821 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2822 2823 pkt.fp_statusarg = fcb; 2824 pkt.fp_statuscb = fwohci_read_resp; 2825 2826 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2827 psc->sc_tlabel, fwohci_read_resp, fcb); 2828 if (rv) 2829 return rv; 2830 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2831 if (rv) 2832 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 2833 psc->sc_tlabel, NULL, NULL); 2834 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 2835 fcb->count = 1; 2836 return rv; 2837 } 2838 2839 static int 2840 fwohci_write(struct ieee1394_abuf *ab) 2841 { 2842 struct fwohci_pkt pkt; 2843 struct ieee1394_softc *sc = ab->ab_req; 2844 struct fwohci_softc *psc = 2845 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 2846 u_int32_t high, lo; 2847 int rv; 2848 2849 if (ab->ab_length > sc->sc1394_max_receive) { 2850 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 2851 return E2BIG; 2852 } 2853 2854 memset(&pkt, 0, sizeof(pkt)); 2855 2856 pkt.fp_tcode = ab->ab_tcode; 2857 pkt.fp_uio.uio_iov = pkt.fp_iov; 2858 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 2859 pkt.fp_uio.uio_rw = UIO_WRITE; 2860 2861 pkt.fp_statusarg = ab; 2862 pkt.fp_statuscb = fwohci_write_ack; 2863 2864 switch (ab->ab_tcode) { 2865 case IEEE1394_TCODE_WRITE_RESP: 2866 pkt.fp_hlen = 12; 2867 case IEEE1394_TCODE_READ_RESP_QUAD: 2868 case IEEE1394_TCODE_READ_RESP_BLOCK: 2869 if (!pkt.fp_hlen) 2870 pkt.fp_hlen = 16; 2871 high = ab->ab_retlen; 2872 ab->ab_retlen = 0; 2873 lo = 0; 2874 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2875 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 2876 break; 2877 default: 2878 pkt.fp_hlen = 16; 2879 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2880 lo = (ab->ab_csr & 0x00000000ffffffff); 2881 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 2882 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 2883 break; 2884 } 2885 2886 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2887 pkt.fp_hdr[2] = lo; 2888 if (pkt.fp_hlen == 16) { 2889 if (ab->ab_length == 4) { 2890 pkt.fp_hdr[3] = ab->ab_data[0]; 2891 pkt.fp_dlen = 0; 2892 } else { 2893 pkt.fp_hdr[3] = (ab->ab_length << 16); 2894 pkt.fp_dlen = ab->ab_length; 2895 pkt.fp_uio.uio_iovcnt = 1; 2896 pkt.fp_uio.uio_resid = ab->ab_length; 2897 pkt.fp_iov[0].iov_base = ab->ab_data; 2898 pkt.fp_iov[0].iov_len = ab->ab_length; 2899 } 2900 } 2901 switch (ab->ab_tcode) { 2902 case IEEE1394_TCODE_WRITE_RESP: 2903 case IEEE1394_TCODE_READ_RESP_QUAD: 2904 case IEEE1394_TCODE_READ_RESP_BLOCK: 2905 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 2906 break; 2907 default: 2908 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 2909 break; 2910 } 2911 return rv; 2912 } 2913 2914 static int 2915 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2916 { 2917 struct fwohci_cb *fcb = arg; 2918 struct ieee1394_abuf *ab = fcb->ab; 2919 struct fwohci_pkt newpkt; 2920 u_int32_t *cur, high, lo; 2921 int i, tcode, rcode, status, rv; 2922 2923 /* 2924 * Both the ACK handling and normal response callbacks are handled here. 2925 * The main reason for this is the various error conditions that can 2926 * occur trying to block read some areas and the ways that gets reported 2927 * back to calling station. This is a variety of ACK codes, responses, 2928 * etc which makes it much more difficult to process if both aren't 2929 * handled here. 2930 */ 2931 2932 /* Check for status packet. */ 2933 2934 if (pkt->fp_tcode == -1) { 2935 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 2936 rcode = -1; 2937 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 2938 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 2939 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 2940 DPRINTF(("Got status packet: 0x%02x\n", 2941 (unsigned int)status)); 2942 fcb->count--; 2943 2944 /* 2945 * Got all the ack's back and the buffer is invalid (i.e. the 2946 * callback has been called. Clean up. 2947 */ 2948 2949 if (fcb->abuf_valid == 0) { 2950 if (fcb->count == 0) 2951 free(fcb, M_DEVBUF); 2952 return IEEE1394_RCODE_COMPLETE; 2953 } 2954 } else { 2955 status = -1; 2956 tcode = pkt->fp_tcode; 2957 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 2958 } 2959 2960 /* 2961 * Some area's (like the config rom want to be read as quadlets only. 2962 * 2963 * The current ideas to try are: 2964 * 2965 * Got an ACK_TYPE_ERROR on a block read. 2966 * 2967 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 2968 * response. 2969 * 2970 * In all cases construct a new packet for a quadlet read and let 2971 * mutli_resp handle the iteration over the space. 2972 */ 2973 2974 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 2975 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 2976 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 2977 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 2978 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 2979 2980 /* Read the area in quadlet chunks (internally track this). */ 2981 2982 memset(&newpkt, 0, sizeof(newpkt)); 2983 2984 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 2985 lo = (ab->ab_csr & 0x00000000ffffffff); 2986 2987 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2988 newpkt.fp_hlen = 12; 2989 newpkt.fp_dlen = 0; 2990 newpkt.fp_hdr[1] = 2991 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 2992 newpkt.fp_hdr[2] = lo; 2993 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2994 (newpkt.fp_tcode << 4); 2995 2996 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 2997 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 2998 fwohci_read_multi_resp, fcb); 2999 if (rv) { 3000 (*ab->ab_cb)(ab, -1); 3001 goto cleanup; 3002 } 3003 newpkt.fp_statusarg = fcb; 3004 newpkt.fp_statuscb = fwohci_read_resp; 3005 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3006 if (rv) { 3007 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3008 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3009 NULL); 3010 (*ab->ab_cb)(ab, -1); 3011 goto cleanup; 3012 } 3013 fcb->count++; 3014 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3015 return IEEE1394_RCODE_COMPLETE; 3016 } else if ((rcode != -1) || ((status != -1) && 3017 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3018 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3019 3020 /* 3021 * Recombine all the iov data into 1 chunk for higher 3022 * level code. 3023 */ 3024 3025 if (rcode != -1) { 3026 cur = ab->ab_data; 3027 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3028 /* 3029 * Make sure and don't exceed the buffer 3030 * allocated for return. 3031 */ 3032 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3033 ab->ab_length) { 3034 memcpy(cur, pkt->fp_iov[i].iov_base, 3035 (ab->ab_length - ab->ab_retlen)); 3036 ab->ab_retlen = ab->ab_length; 3037 break; 3038 } 3039 memcpy(cur, pkt->fp_iov[i].iov_base, 3040 pkt->fp_iov[i].iov_len); 3041 cur += pkt->fp_iov[i].iov_len; 3042 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3043 } 3044 } 3045 if (status != -1) 3046 /* XXX: Need a complete tlabel interface. */ 3047 for (i = 0; i < 64; i++) 3048 fwohci_handler_set(sc, 3049 IEEE1394_TCODE_READ_RESP_QUAD, 3050 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3051 (*ab->ab_cb)(ab, rcode); 3052 goto cleanup; 3053 } else 3054 /* Good ack packet. */ 3055 return IEEE1394_RCODE_COMPLETE; 3056 3057 /* Can't get here unless ab->ab_cb has been called. */ 3058 3059 cleanup: 3060 fcb->abuf_valid = 0; 3061 if (fcb->count == 0) 3062 free(fcb, M_DEVBUF); 3063 return IEEE1394_RCODE_COMPLETE; 3064 } 3065 3066 static int 3067 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3068 struct fwohci_pkt *pkt) 3069 { 3070 struct fwohci_cb *fcb = arg; 3071 struct ieee1394_abuf *ab = fcb->ab; 3072 struct fwohci_pkt newpkt; 3073 u_int32_t high, lo; 3074 int rcode, rv; 3075 3076 /* 3077 * Bad return codes from the wire, just return what's already in the 3078 * buf. 3079 */ 3080 3081 /* Make sure a response packet didn't arrive after a bad ACK. */ 3082 if (fcb->abuf_valid == 0) 3083 return IEEE1394_RCODE_COMPLETE; 3084 3085 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3086 3087 if (rcode) { 3088 (*ab->ab_cb)(ab, rcode); 3089 goto cleanup; 3090 } 3091 3092 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3093 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3094 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3095 ab->ab_retlen = ab->ab_length; 3096 } else { 3097 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3098 pkt->fp_iov[0].iov_base, 4); 3099 ab->ab_retlen += 4; 3100 } 3101 /* Still more, loop and read 4 more bytes. */ 3102 if (ab->ab_retlen < ab->ab_length) { 3103 memset(&newpkt, 0, sizeof(newpkt)); 3104 3105 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3106 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3107 3108 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3109 newpkt.fp_hlen = 12; 3110 newpkt.fp_dlen = 0; 3111 newpkt.fp_hdr[1] = 3112 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3113 newpkt.fp_hdr[2] = lo; 3114 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3115 (newpkt.fp_tcode << 4); 3116 3117 newpkt.fp_statusarg = fcb; 3118 newpkt.fp_statuscb = fwohci_read_resp; 3119 3120 /* 3121 * Bad return code. Just give up and return what's 3122 * come in now. 3123 */ 3124 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3125 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3126 fwohci_read_multi_resp, fcb); 3127 if (rv) 3128 (*ab->ab_cb)(ab, -1); 3129 else { 3130 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3131 if (rv) { 3132 fwohci_handler_set(sc, 3133 IEEE1394_TCODE_READ_RESP_QUAD, 3134 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3135 NULL, NULL); 3136 (*ab->ab_cb)(ab, -1); 3137 } else { 3138 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3139 fcb->count++; 3140 return IEEE1394_RCODE_COMPLETE; 3141 } 3142 } 3143 } else 3144 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3145 3146 cleanup: 3147 /* Can't get here unless ab_cb has been called. */ 3148 fcb->abuf_valid = 0; 3149 if (fcb->count == 0) 3150 free(fcb, M_DEVBUF); 3151 return IEEE1394_RCODE_COMPLETE; 3152 } 3153 3154 static int 3155 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3156 { 3157 struct ieee1394_abuf *ab = arg; 3158 u_int16_t status; 3159 3160 3161 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3162 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3163 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3164 DPRINTF(("Got status packet: 0x%02x\n", 3165 (unsigned int)status)); 3166 3167 /* No callback means this level should free the buffers. */ 3168 if (ab->ab_cb) 3169 (*ab->ab_cb)(ab, status); 3170 else { 3171 if (ab->ab_data) 3172 free(ab->ab_data, M_1394DATA); 3173 free(ab, M_1394DATA); 3174 } 3175 return IEEE1394_RCODE_COMPLETE; 3176 } 3177 3178 static int 3179 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3180 { 3181 struct ieee1394_softc *sc = ab->ab_req; 3182 struct fwohci_softc *psc = 3183 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3184 u_int32_t high, lo; 3185 int i, j, rv; 3186 3187 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3188 lo = (ab->ab_csr & 0x00000000ffffffff); 3189 3190 rv = 0; 3191 switch (ab->ab_tcode) { 3192 case IEEE1394_TCODE_READ_REQ_QUAD: 3193 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3194 if (ab->ab_cb) 3195 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3196 fwohci_parse_input, ab); 3197 else 3198 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3199 NULL); 3200 break; 3201 case IEEE1394_TCODE_READ_REQ_BLOCK: 3202 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3203 if (allow) { 3204 for (i = 0; i < (ab->ab_length / 4); i++) { 3205 if (ab->ab_cb) { 3206 rv = fwohci_handler_set(psc, 3207 ab->ab_tcode, high, lo + (i * 4), 3208 fwohci_parse_input, ab); 3209 if (rv) 3210 break; 3211 } else 3212 fwohci_handler_set(psc, ab->ab_tcode, 3213 high, lo + (i * 4), NULL, NULL); 3214 } 3215 if (i != (ab->ab_length / 4)) { 3216 j = i + 1; 3217 for (i = 0; i < j; i++) 3218 fwohci_handler_set(psc, ab->ab_tcode, 3219 high, lo + (i * 4), NULL, NULL); 3220 } else 3221 ab->ab_data = (void *)1; 3222 } else { 3223 if (ab->ab_cb) 3224 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3225 lo, fwohci_parse_input, ab); 3226 else 3227 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3228 NULL, NULL); 3229 } 3230 break; 3231 default: 3232 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3233 return -1; 3234 break; 3235 } 3236 return rv; 3237 } 3238 3239 static int 3240 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3241 { 3242 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3243 u_int64_t csr; 3244 u_int32_t *cur; 3245 int i, count; 3246 3247 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3248 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3249 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3250 3251 switch (ab->ab_tcode) { 3252 case IEEE1394_TCODE_READ_REQ_QUAD: 3253 ab->ab_retlen = 4; 3254 break; 3255 case IEEE1394_TCODE_READ_REQ_BLOCK: 3256 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3257 if (ab->ab_data) { 3258 if ((csr + ab->ab_retlen) > 3259 (ab->ab_csr + ab->ab_length)) 3260 return IEEE1394_RCODE_ADDRESS_ERROR; 3261 ab->ab_data = NULL; 3262 } else 3263 if (ab->ab_retlen != ab->ab_length) 3264 return IEEE1394_RCODE_ADDRESS_ERROR; 3265 break; 3266 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3267 ab->ab_retlen = 4; 3268 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3269 if (!ab->ab_retlen) 3270 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3271 if (ab->ab_data) { 3272 if ((csr + ab->ab_retlen) > 3273 (ab->ab_csr + ab->ab_length)) 3274 return IEEE1394_RCODE_ADDRESS_ERROR; 3275 ab->ab_data = NULL; 3276 } else 3277 if (ab->ab_retlen != ab->ab_length) 3278 return IEEE1394_RCODE_ADDRESS_ERROR; 3279 3280 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3281 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3282 ab->ab_data[0] = pkt->fp_hdr[3]; 3283 else { 3284 count = 0; 3285 cur = ab->ab_data; 3286 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3287 memcpy(cur, pkt->fp_iov[i].iov_base, 3288 pkt->fp_iov[i].iov_len); 3289 cur += pkt->fp_iov[i].iov_len; 3290 count += pkt->fp_iov[i].iov_len; 3291 } 3292 if (ab->ab_retlen != count) 3293 panic("Packet claims %d length " 3294 "but only %d bytes returned\n", 3295 ab->ab_retlen, count); 3296 } 3297 break; 3298 default: 3299 panic("Got a callback for a tcode that wasn't requested: %d\n", 3300 ab->ab_tcode); 3301 break; 3302 } 3303 ab->ab_csr = csr; 3304 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3305 return -1; 3306 } 3307 3308 static int 3309 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3310 { 3311 struct ieee1394_attach_args *fwa = aux; 3312 3313 /* Both halves must be filled in for a match. */ 3314 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3315 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3316 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3317 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3318 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3319 return 0; 3320 } 3321 3322 #ifdef FW_DEBUG 3323 static void 3324 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3325 { 3326 3327 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3328 intmask); 3329 if (intmask & OHCI_Int_CycleTooLong) 3330 printf(" CycleTooLong"); 3331 if (intmask & OHCI_Int_UnrecoverableError) 3332 printf(" UnrecoverableError"); 3333 if (intmask & OHCI_Int_CycleInconsistent) 3334 printf(" CycleInconsistent"); 3335 if (intmask & OHCI_Int_BusReset) 3336 printf(" BusReset"); 3337 if (intmask & OHCI_Int_SelfIDComplete) 3338 printf(" SelfIDComplete"); 3339 if (intmask & OHCI_Int_LockRespErr) 3340 printf(" LockRespErr"); 3341 if (intmask & OHCI_Int_PostedWriteErr) 3342 printf(" PostedWriteErr"); 3343 if (intmask & OHCI_Int_ReqTxComplete) 3344 printf(" ReqTxComplete(0x%04x)", 3345 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3346 OHCI_SUBREG_ContextControlClear)); 3347 if (intmask & OHCI_Int_RespTxComplete) 3348 printf(" RespTxComplete(0x%04x)", 3349 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3350 OHCI_SUBREG_ContextControlClear)); 3351 if (intmask & OHCI_Int_ARRS) 3352 printf(" ARRS(0x%04x)", 3353 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3354 OHCI_SUBREG_ContextControlClear)); 3355 if (intmask & OHCI_Int_ARRQ) 3356 printf(" ARRQ(0x%04x)", 3357 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3358 OHCI_SUBREG_ContextControlClear)); 3359 if (intmask & OHCI_Int_IsochRx) 3360 printf(" IsochRx(0x%08x)", 3361 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3362 if (intmask & OHCI_Int_IsochTx) 3363 printf(" IsochTx(0x%08x)", 3364 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3365 if (intmask & OHCI_Int_RQPkt) 3366 printf(" RQPkt(0x%04x)", 3367 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3368 OHCI_SUBREG_ContextControlClear)); 3369 if (intmask & OHCI_Int_RSPkt) 3370 printf(" RSPkt(0x%04x)", 3371 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3372 OHCI_SUBREG_ContextControlClear)); 3373 printf("\n"); 3374 } 3375 3376 static void 3377 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3378 { 3379 u_int8_t key, phyid; 3380 3381 key = (val & 0xc0000000) >> 30; 3382 phyid = (val & 0x3f000000) >> 24; 3383 printf("%s: PHY packet from %d: ", 3384 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3385 switch (key) { 3386 case 0: 3387 printf("PHY Config:"); 3388 if (val & 0x00800000) 3389 printf(" ForceRoot"); 3390 if (val & 0x00400000) 3391 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3392 printf("\n"); 3393 break; 3394 case 1: 3395 printf("Link-on\n"); 3396 break; 3397 case 2: 3398 printf("SelfID:"); 3399 if (val & 0x00800000) { 3400 printf(" #%d", (val & 0x00700000) >> 20); 3401 } else { 3402 if (val & 0x00400000) 3403 printf(" LinkActive"); 3404 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3405 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3406 if (val & 0x00000800) 3407 printf(" Cont"); 3408 if (val & 0x00000002) 3409 printf(" InitiateBusReset"); 3410 } 3411 if (val & 0x00000001) 3412 printf(" +"); 3413 printf("\n"); 3414 break; 3415 default: 3416 printf("unknown: 0x%08x\n", val); 3417 break; 3418 } 3419 } 3420 #endif /* FW_DEBUG */ 3421
Indexes created Fri Sep 26 20:09:58 GMT 2025