fwohci.c revision 1.4
1 /*- 2 * Copyright (c) 2000 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * IEEE1394 Open Host Controller Interface 39 * based on OHCI Specification 1.1 (January 6, 2000) 40 * The first version to support network interface part is wrtten by 41 * Atsushi Onoe <onoe (at) netbsd.org>. 42 */ 43 44 #include "opt_inet.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/socket.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/mbuf.h> 53 54 #include <machine/bus.h> 55 56 #include <dev/ieee1394/ieee1394reg.h> 57 #include <dev/ieee1394/fwohcireg.h> 58 59 #include <dev/ieee1394/ieee1394var.h> 60 #include <dev/ieee1394/fwohcivar.h> 61 62 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 63 64 static int fwohci_desc_alloc(struct fwohci_softc *); 65 66 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 67 int, int); 68 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 69 70 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 71 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 72 static void fwohci_buf_init(struct fwohci_softc *); 73 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 74 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 75 caddr_t *, int); 76 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 77 struct fwohci_pkt *); 78 79 static void fwohci_phy_busreset(struct fwohci_softc *); 80 81 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 82 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 83 void *); 84 85 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 86 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 87 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 88 89 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 90 struct fwohci_pkt *); 91 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *); 92 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 93 struct fwohci_pkt *); 94 95 static void fwohci_configrom_init(struct fwohci_softc *); 96 97 static void fwohci_selfid_init(struct fwohci_softc *); 98 static void fwohci_selfid_input(struct fwohci_softc *); 99 100 static void fwohci_csr_init(struct fwohci_softc *); 101 static int fwohci_csr_input(struct fwohci_softc *, void *, 102 struct fwohci_pkt *); 103 104 static void fwohci_uid_collect(struct fwohci_softc *); 105 static int fwohci_uid_input(struct fwohci_softc *, void *, 106 struct fwohci_pkt *); 107 static int fwohci_uid_lookup(struct fwohci_softc *, u_int8_t *); 108 109 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 110 void (*)(struct device *, struct mbuf *)); 111 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 112 static int fwohci_if_output(struct device *, struct mbuf *, 113 void (*)(struct device *, struct mbuf *)); 114 115 int 116 fwohci_init(struct fwohci_softc *sc) 117 { 118 int i; 119 u_int32_t val; 120 121 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_SoftReset); 122 /* 123 * Wait for reset completion 124 */ 125 for (i = 0; i < OHCI_LOOP; i++) { 126 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 127 if ((val & OHCI_HCControl_SoftReset) == 0) 128 break; 129 } 130 131 /* What dialect of OHCI is this device? 132 */ 133 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 134 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 135 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 136 137 /* Is the Global UID ROM present? 138 */ 139 if ((val & OHCI_Version_GUID_ROM) == 0) { 140 printf("\n%s: fatal: no global UID ROM\n", sc->sc_sc1394.sc1394_dev.dv_xname); 141 return -1; 142 } 143 144 /* Extract the Global UID 145 */ 146 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 147 sc->sc_sc1394.sc1394_guid[0] = (val >> 24) & 0xff; 148 sc->sc_sc1394.sc1394_guid[1] = (val >> 16) & 0xff; 149 sc->sc_sc1394.sc1394_guid[2] = (val >> 8) & 0xff; 150 sc->sc_sc1394.sc1394_guid[3] = (val >> 0) & 0xff; 151 152 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 153 sc->sc_sc1394.sc1394_guid[4] = (val >> 24) & 0xff; 154 sc->sc_sc1394.sc1394_guid[5] = (val >> 16) & 0xff; 155 sc->sc_sc1394.sc1394_guid[6] = (val >> 8) & 0xff; 156 sc->sc_sc1394.sc1394_guid[7] = (val >> 0) & 0xff; 157 158 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 159 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 160 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 161 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 162 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 163 164 /* Get the maximum link speed and receive size 165 */ 166 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 167 sc->sc_sc1394.sc1394_link_speed = 168 (val & OHCI_BusOptions_LinkSpd_MASK) 169 >> OHCI_BusOptions_LinkSpd_BITPOS; 170 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 171 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 172 } else { 173 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 174 } 175 176 /* MaxRec is encoded as log2(max_rec_octets)-1 177 */ 178 sc->sc_sc1394.sc1394_max_receive = 179 1 << (((val & OHCI_BusOptions_MaxRec_MASK) 180 >> OHCI_BusOptions_MaxRec_BITPOS) + 1); 181 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 182 183 /* 184 * Count how many isochronous ctx we have. 185 */ 186 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, 0xffffffff); 187 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 188 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, 0xffffffff); 189 for (i = 0; val != 0; val >>= 1) { 190 if (val & 0x1) 191 i++; 192 } 193 sc->sc_isoctx = i; 194 printf(", %d iso_ctx", sc->sc_isoctx); 195 196 printf("\n"); 197 198 /* 199 * Enable Link Power 200 */ 201 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 202 if (fwohci_desc_alloc(sc)) 203 return -1; 204 205 /* 206 * Allocate DMA Context 207 */ 208 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 209 OHCI_CTX_ASYNC_RX_REQUEST); 210 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 211 OHCI_CTX_ASYNC_RX_RESPONSE); 212 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, OHCI_BUF_ATRQ_CNT, 213 OHCI_CTX_ASYNC_TX_REQUEST); 214 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, OHCI_BUF_ATRS_CNT, 215 OHCI_CTX_ASYNC_TX_RESPONSE); 216 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 217 M_DEVBUF, M_WAITOK); 218 for (i = 0; i < sc->sc_isoctx; i++) { 219 fwohci_ctx_alloc(sc, &sc->sc_ctx_ir[i], OHCI_BUF_IR_CNT, i); 220 sc->sc_ctx_ir[i]->fc_ppbmode = 1; 221 } 222 223 /* 224 * Allocate buffer for configuration ROM and SelfID buffer 225 */ 226 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 227 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 228 229 /* 230 * First, initilize CSRs to default settings. 231 */ 232 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 233 #if 0 234 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 235 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC; 236 #endif 237 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 238 for (i = 0; i < sc->sc_isoctx; i++) { 239 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 240 ~0); 241 } 242 fwohci_configrom_init(sc); 243 fwohci_selfid_init(sc); 244 fwohci_buf_init(sc); 245 fwohci_csr_init(sc); 246 247 /* 248 * Final CSR settings. 249 */ 250 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 251 OHCI_LinkControl_CycleSource); 252 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 253 OHCI_LinkControl_CycleTimerEnable | OHCI_LinkControl_RcvSelfID | 254 OHCI_LinkControl_RcvPhyPkt); 255 256 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 257 258 /* clear receive filter */ 259 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 260 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 261 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 262 263 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 264 OHCI_HCControl_NoByteSwapData); 265 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 266 267 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 268 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 269 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 270 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 271 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 272 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 273 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 274 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 275 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 276 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 277 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 278 config_defer(&sc->sc_sc1394.sc1394_dev, 279 (void (*)(struct device *))fwohci_phy_busreset); 280 281 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 282 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 283 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 284 "fw", fwohci_print); 285 286 return 0; 287 } 288 289 int 290 fwohci_intr(void *arg) 291 { 292 struct fwohci_softc * const sc = arg; 293 int i; 294 int progress = 0; 295 u_int32_t intmask, iso; 296 297 for (;;) { 298 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 299 if (intmask == 0) 300 return progress; 301 #ifdef FW_DEBUG 302 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 303 if (intmask & OHCI_Int_CycleTooLong) 304 printf(" CycleTooLong"); 305 if (intmask & OHCI_Int_UnrecoverableError) 306 printf(" UnrecoverableError"); 307 if (intmask & OHCI_Int_CycleInconsistent) 308 printf(" CycleInconsistent"); 309 if (intmask & OHCI_Int_BusReset) 310 printf(" BusReset"); 311 if (intmask & OHCI_Int_SelfIDComplete) 312 printf(" SelfIDComplete"); 313 if (intmask & OHCI_Int_LockRespErr) 314 printf(" LockRespErr"); 315 if (intmask & OHCI_Int_PostedWriteErr) 316 printf(" PostedWriteErr"); 317 if (intmask & OHCI_Int_ReqTxComplete) 318 printf(" ReqTxComplete(0x%08x)", 319 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 320 OHCI_SUBREG_ContextControlClear)); 321 if (intmask & OHCI_Int_RespTxComplete) 322 printf(" RespTxComplete(0x%08x)", 323 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 324 OHCI_SUBREG_ContextControlClear)); 325 if (intmask & OHCI_Int_ARRS) 326 printf(" ARRS(0x%08x)", 327 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 328 OHCI_SUBREG_ContextControlClear)); 329 if (intmask & OHCI_Int_ARRQ) 330 printf(" ARRQ(0x%08x)", 331 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 332 OHCI_SUBREG_ContextControlClear)); 333 if (intmask & OHCI_Int_IsochRx) 334 printf(" IsochRx"); 335 if (intmask & OHCI_Int_IsochTx) 336 printf(" IsochTx"); 337 if (intmask & OHCI_Int_RQPkt) 338 printf(" RQPkt"); 339 if (intmask & OHCI_Int_RSPkt) 340 printf(" RSPkt"); 341 printf("\n"); 342 #endif /* FW_DEBUG */ 343 if (intmask & OHCI_Int_BusReset) { 344 if (sc->sc_uidtbl != NULL) { 345 free(sc->sc_uidtbl, M_DEVBUF); 346 sc->sc_uidtbl = NULL; 347 } 348 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 349 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 350 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 351 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 352 fwohci_buf_init(sc); 353 } 354 if (intmask & OHCI_Int_SelfIDComplete) { 355 fwohci_selfid_input(sc); 356 fwohci_uid_collect(sc); 357 } 358 359 if (intmask & OHCI_Int_ReqTxComplete) 360 fwohci_at_done(sc, sc->sc_ctx_atrq); 361 if (intmask & OHCI_Int_RespTxComplete) 362 fwohci_at_done(sc, sc->sc_ctx_atrs); 363 if (intmask & OHCI_Int_RQPkt) 364 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 365 if (intmask & OHCI_Int_RSPkt) 366 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 367 368 if (intmask & OHCI_Int_IsochTx) { 369 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 370 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 371 } 372 if (intmask & OHCI_Int_IsochRx) { 373 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 374 for (i = 0; i < sc->sc_isoctx; i++) { 375 if (iso & (1 << i)) 376 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 377 } 378 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 379 } 380 381 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, intmask); 382 progress = 1; 383 } 384 } 385 386 int 387 fwohci_print(void *aux, const char *pnp) 388 { 389 char *name = aux; 390 391 if (pnp) 392 printf("%s at %s", name, pnp); 393 394 return UNCONF; 395 } 396 397 /* 398 * COMMON FUNCTIONS 399 */ 400 401 /* 402 * Initiate Bus Reset 403 */ 404 static void 405 fwohci_phy_busreset(struct fwohci_softc *sc) 406 { 407 int i; 408 u_int8_t reg; 409 u_int32_t val; 410 411 reg = 1; 412 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 413 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 414 for (i = 0; i < OHCI_LOOP; i++) { 415 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 416 OHCI_PhyControl_RdDone) 417 break; 418 } 419 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 420 val = (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 421 val = (val & 0x80) | 0x40 | 0x3f; /* XXX: gap */ 422 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 423 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 424 (val << OHCI_PhyControl_WrData_BITPOS)); 425 for (i = 0; i < OHCI_LOOP; i++) { 426 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 427 OHCI_PhyControl_WrReg)) 428 break; 429 } 430 } 431 432 /* 433 * Descriptor for context DMA. 434 */ 435 static int 436 fwohci_desc_alloc(struct fwohci_softc *sc) 437 { 438 int error; 439 440 /* 441 * allocate descriptor buffer 442 */ 443 444 sc->sc_descsize = sizeof(struct fwohci_desc) * 445 (OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 446 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 447 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2); 448 449 if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_descsize, 450 OHCI_PAGE_SIZE, 0, &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 451 printf("%s: unable to allocate descriptor buffer, error = %d\n", 452 sc->sc_sc1394.sc1394_dev.dv_xname, error); 453 goto fail_0; 454 } 455 456 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 457 sc->sc_descsize, &sc->sc_desc, BUS_DMA_COHERENT)) != 0) { 458 printf("%s: unable to map descriptor buffer, error = %d\n", 459 sc->sc_sc1394.sc1394_dev.dv_xname, error); 460 goto fail_1; 461 } 462 463 if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_descsize, 464 sc->sc_dnseg, sc->sc_descsize, 0, 0, &sc->sc_ddmamap)) != 0) { 465 printf("%s: unable to create descriptor buffer DMA map, " 466 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 467 goto fail_2; 468 } 469 470 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 471 sc->sc_descsize, NULL, 0)) != 0) { 472 printf("%s: unable to load descriptor buffer DMA map, " 473 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 474 goto fail_3; 475 } 476 477 return 0; 478 479 fail_3: 480 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 481 fail_2: 482 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, sc->sc_descsize); 483 fail_1: 484 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 485 fail_0: 486 return error; 487 } 488 489 /* 490 * Asyncronous/Isochronous Transmit/Receive Context 491 */ 492 static int 493 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 494 int bufcnt, int ctx) 495 { 496 int i, error; 497 struct fwohci_ctx *fc; 498 struct fwohci_buf *fb; 499 struct fwohci_desc *fd; 500 501 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 502 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 503 LIST_INIT(&fc->fc_handler); 504 TAILQ_INIT(&fc->fc_buf); 505 TAILQ_INIT(&fc->fc_busy); 506 fc->fc_ctx = ctx; 507 fc->fc_bufcnt = bufcnt; 508 fb = (struct fwohci_buf *)&fc[1]; 509 for (i = 0; i < bufcnt; i++, fb++) { 510 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 511 goto fail; 512 fd = (struct fwohci_desc *)sc->sc_desc + sc->sc_descfree++; 513 fb->fb_desc = fd; 514 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 515 ((caddr_t)fd - sc->sc_desc); 516 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 517 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 518 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 519 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 520 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 521 } 522 *fcp = fc; 523 return 0; 524 525 fail: 526 while (i-- > 0) 527 fwohci_buf_free(sc, --fb); 528 free(fc, M_DEVBUF); 529 return error; 530 } 531 532 static void 533 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 534 { 535 struct fwohci_buf *fb, *nfb; 536 struct fwohci_desc *fd; 537 538 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 539 nfb = TAILQ_NEXT(fb, fb_list); 540 fb->fb_off = 0; 541 fd = fb->fb_desc; 542 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 543 fd->fd_rescount = fd->fd_reqcount; 544 } 545 } 546 547 /* 548 * DMA data buffer 549 */ 550 static int 551 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 552 { 553 int error; 554 555 if ((error = bus_dmamem_alloc(sc->sc_dmat, OHCI_PAGE_SIZE, 556 OHCI_PAGE_SIZE, 0, &fb->fb_seg, 1, &fb->fb_nseg, 0)) != 0) { 557 printf("%s: unable to allocate buffer, error = %d\n", 558 sc->sc_sc1394.sc1394_dev.dv_xname, error); 559 goto fail_0; 560 } 561 562 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 563 fb->fb_nseg, OHCI_PAGE_SIZE, &fb->fb_buf, 0)) != 0) { 564 printf("%s: unable to map buffer, error = %d\n", 565 sc->sc_sc1394.sc1394_dev.dv_xname, error); 566 goto fail_1; 567 } 568 569 if ((error = bus_dmamap_create(sc->sc_dmat, OHCI_PAGE_SIZE, 570 fb->fb_nseg, OHCI_PAGE_SIZE, 0, 0, &fb->fb_dmamap)) != 0) { 571 printf("%s: unable to create buffer DMA map, " 572 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 573 error); 574 goto fail_2; 575 } 576 577 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 578 fb->fb_buf, OHCI_PAGE_SIZE, NULL, 0)) != 0) { 579 printf("%s: unable to load buffer DMA map, " 580 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 581 error); 582 goto fail_3; 583 } 584 585 return 0; 586 587 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 588 fail_3: 589 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 590 fail_2: 591 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, OHCI_PAGE_SIZE); 592 fail_1: 593 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 594 fail_0: 595 return error; 596 } 597 598 static void 599 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 600 { 601 602 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 603 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 604 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, OHCI_PAGE_SIZE); 605 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 606 } 607 608 static void 609 fwohci_buf_init(struct fwohci_softc *sc) 610 { 611 int i; 612 struct fwohci_buf *fb; 613 614 /* 615 * Stop the transmitter and receiver. 616 */ 617 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 618 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 619 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 620 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 621 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 622 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 623 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 624 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 625 for (i = 0; i < sc->sc_isoctx; i++) { 626 OHCI_SYNC_RX_DMA_WRITE(sc, i, 627 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 628 } 629 630 /* 631 * Initialize for Asynchronous Transmit Request. 632 */ 633 while ((fb = TAILQ_FIRST(&sc->sc_ctx_atrq->fc_busy)) != NULL) { 634 TAILQ_REMOVE(&sc->sc_ctx_atrq->fc_busy, fb, fb_list); 635 if (fb->fb_m != NULL) { 636 if (fb->fb_callback != NULL) { 637 (*fb->fb_callback) 638 (sc->sc_sc1394.sc1394_if, fb->fb_m); 639 fb->fb_callback = NULL; 640 } else 641 m_freem(fb->fb_m); 642 fb->fb_m = NULL; 643 } 644 TAILQ_INSERT_TAIL(&sc->sc_ctx_atrq->fc_buf, fb, fb_list); 645 } 646 sc->sc_ctx_atrq->fc_branch = NULL; 647 648 /* 649 * Initialize for Asynchronous Transmit Response. 650 */ 651 while ((fb = TAILQ_FIRST(&sc->sc_ctx_atrs->fc_busy)) != NULL) { 652 TAILQ_REMOVE(&sc->sc_ctx_atrs->fc_busy, fb, fb_list); 653 if (fb->fb_m != NULL) { 654 if (fb->fb_callback != NULL) { 655 (*fb->fb_callback) 656 (sc->sc_sc1394.sc1394_if, fb->fb_m); 657 fb->fb_callback = NULL; 658 } else 659 m_freem(fb->fb_m); 660 fb->fb_m = NULL; 661 } 662 TAILQ_INSERT_TAIL(&sc->sc_ctx_atrs->fc_buf, fb, fb_list); 663 } 664 sc->sc_ctx_atrq->fc_branch = NULL; 665 666 /* 667 * Initialize for Asynchronous Receive Request. 668 */ 669 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 670 fb = TAILQ_FIRST(&sc->sc_ctx_arrq->fc_buf); 671 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 672 OHCI_SUBREG_CommandPtr, fb->fb_daddr | 1); 673 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 674 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 675 676 /* 677 * Initialize for Asynchronous Receive Response. 678 */ 679 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 680 fb = TAILQ_FIRST(&sc->sc_ctx_arrs->fc_buf); 681 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 682 OHCI_SUBREG_CommandPtr, fb->fb_daddr | 1); 683 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 684 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 685 686 /* 687 * Initialize for Isochronous Receive. 688 */ 689 for (i = 0; i < sc->sc_isoctx; i++) { 690 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 691 fb = TAILQ_FIRST(&sc->sc_ctx_ir[i]->fc_buf); 692 OHCI_SYNC_RX_DMA_WRITE(sc, 0, OHCI_SUBREG_CommandPtr, 693 fb->fb_daddr | 1); 694 OHCI_SYNC_RX_DMA_WRITE(sc, 0, OHCI_SUBREG_ContextControlClear, 695 OHCI_CTXCTL_RX_BUFFER_FILL | 696 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 697 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 698 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 699 OHCI_SYNC_RX_DMA_WRITE(sc, 0, OHCI_SUBREG_ContextControlSet, 700 OHCI_CTXCTL_RX_ISOCH_HEADER); 701 if (LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 702 OHCI_SYNC_RX_DMA_WRITE(sc, i, 703 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 704 } 705 } 706 } 707 708 static void 709 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 710 { 711 struct fwohci_buf *fb, *tfb; 712 713 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 714 if (fb->fb_off != fb->fb_desc->fd_reqcount || 715 fb->fb_desc->fd_rescount != 0) 716 break; 717 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 718 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 719 fb->fb_off = 0; 720 fb->fb_desc->fd_branch = 0; 721 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 722 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 723 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 724 } 725 } 726 727 static int 728 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 729 int len) 730 { 731 struct fwohci_buf *fb; 732 struct fwohci_desc *fd; 733 int bufend; 734 735 fb = TAILQ_FIRST(&fc->fc_buf); 736 again: 737 fd = fb->fb_desc; 738 #ifdef FW_DEBUG 739 printf("fwohci_buf_pktget: desc %d, off %d, req %d, res %d\n", fd - (struct fwohci_desc *)sc->sc_desc, fb->fb_off, fd->fd_reqcount, fd->fd_rescount); 740 #endif 741 bufend = fd->fd_reqcount - fd->fd_rescount; 742 if (fb->fb_off >= bufend) { 743 if (fc->fc_ppbmode && fb->fb_off > 0) { 744 fb->fb_off = fd->fd_reqcount; 745 fd->fd_rescount = 0; 746 } 747 if (fd->fd_rescount == 0) { 748 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 749 goto again; 750 } 751 return 0; 752 } 753 if (fb->fb_off + len > bufend) 754 len = bufend - fb->fb_off; 755 *pp = fb->fb_buf + fb->fb_off; 756 fb->fb_off += roundup(len, 4); 757 return len; 758 } 759 760 static int 761 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 762 struct fwohci_pkt *pkt) 763 { 764 caddr_t p; 765 int len, count, i; 766 767 /* get first quadlet */ 768 count = 4; 769 if (fc->fc_ppbmode) { 770 /* 771 * get trailer first, may be bogus data unless status update 772 * in descriptor is set. 773 */ 774 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 775 sizeof(pkt->fp_trail)); 776 if (len <= 0) 777 return 0; 778 } 779 len = fwohci_buf_pktget(sc, fc, &p, count); 780 if (len <= 0) { 781 #ifdef FW_DEBUG 782 printf("fwohci_buf_input: no input\n"); 783 #endif 784 return 0; 785 } 786 pkt->fp_hdr[0] = *(u_int32_t *)p; 787 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 788 switch (pkt->fp_tcode) { 789 case IEEE1394_TCODE_WRITE_REQ_QUAD: 790 case IEEE1394_TCODE_READ_RESP_QUAD: 791 pkt->fp_hlen = 12; 792 pkt->fp_dlen = 4; 793 break; 794 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 795 case IEEE1394_TCODE_READ_RESP_BLOCK: 796 case IEEE1394_TCODE_LOCK_REQ: 797 case IEEE1394_TCODE_LOCK_RESP: 798 pkt->fp_hlen = 16; 799 break; 800 case IEEE1394_TCODE_STREAM_DATA: 801 pkt->fp_hlen = 4; 802 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 803 break; 804 default: 805 pkt->fp_hlen = 12; 806 pkt->fp_dlen = 0; 807 break; 808 } 809 810 /* get header */ 811 while (count < pkt->fp_hlen) { 812 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 813 if (len == 0) { 814 printf("fwohci_buf_input: malformed input 1: %d\n", 815 pkt->fp_hlen - count); 816 return 0; 817 } 818 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 819 count += len; 820 } 821 if (pkt->fp_hlen == 16) 822 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 823 #ifdef FW_DEBUG 824 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 825 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 826 #endif 827 828 /* get data */ 829 count = 0; 830 i = 0; 831 while (count < pkt->fp_dlen) { 832 len = fwohci_buf_pktget(sc, fc, 833 (caddr_t *)&pkt->fp_iov[i].iov_base, 834 pkt->fp_dlen - count); 835 if (len == 0) { 836 printf("fwohci_buf_input: malformed input 2: %d\n", 837 pkt->fp_hlen - count); 838 return 0; 839 } 840 pkt->fp_iov[i++].iov_len = len; 841 count += len; 842 } 843 844 if (!fc->fc_ppbmode) { 845 /* get trailer */ 846 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 847 sizeof(pkt->fp_trail)); 848 if (len <= 0) { 849 printf("fwohci_buf_input: malformed input 3: %d\n", 850 pkt->fp_hlen - count); 851 return 0; 852 } 853 } 854 return 1; 855 } 856 857 static int 858 fwohci_handler_set(struct fwohci_softc *sc, 859 int tcode, u_int32_t key1, u_int32_t key2, 860 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 861 void *arg) 862 { 863 struct fwohci_ctx *fc; 864 struct fwohci_handler *fh; 865 int i; 866 867 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 868 for (i = 0; ; i++) { 869 if (i == sc->sc_isoctx) { 870 /* no more free ctx */ 871 return ENOMEM; 872 } 873 fc = sc->sc_ctx_ir[i]; 874 fh = LIST_FIRST(&fc->fc_handler); 875 if (fh == NULL) 876 break; 877 if (fh->fh_tcode == tcode && fh->fh_key1 == key1 && 878 fh->fh_key2 == key2) 879 break; 880 } 881 } else { 882 switch (tcode) { 883 case IEEE1394_TCODE_WRITE_REQ_QUAD: 884 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 885 case IEEE1394_TCODE_READ_REQ_QUAD: 886 case IEEE1394_TCODE_READ_REQ_BLOCK: 887 case IEEE1394_TCODE_LOCK_REQ: 888 fc = sc->sc_ctx_arrq; 889 break; 890 case IEEE1394_TCODE_WRITE_RESP: 891 case IEEE1394_TCODE_READ_RESP_QUAD: 892 case IEEE1394_TCODE_READ_RESP_BLOCK: 893 case IEEE1394_TCODE_LOCK_RESP: 894 fc = sc->sc_ctx_arrs; 895 break; 896 default: 897 return EIO; 898 } 899 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 900 fh = LIST_NEXT(fh, fh_list)) { 901 if (fh->fh_tcode == tcode && fh->fh_key1 == key1 && 902 fh->fh_key2 == key2) 903 break; 904 } 905 } 906 if (handler == NULL) { 907 if (fh != NULL) 908 LIST_REMOVE(fh, fh_list); 909 return 0; 910 } 911 if (fh == NULL) { 912 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 913 if (fh == NULL) 914 return ENOMEM; 915 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 916 } 917 fh->fh_tcode = tcode; 918 fh->fh_key1 = key1; 919 fh->fh_key2 = key2; 920 fh->fh_handler = handler; 921 fh->fh_handarg = arg; 922 923 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 924 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextMatch, 925 (OHCI_CTXMATCH_TAG0 << key2) | key1); 926 } 927 return 0; 928 } 929 930 /* 931 * Asyncronous Receive Requests input frontend. 932 */ 933 static void 934 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 935 { 936 int rcode; 937 u_int32_t key1, key2; 938 struct fwohci_handler *fh; 939 struct fwohci_pkt pkt, res; 940 941 while (fwohci_buf_input(sc, fc, &pkt)) { 942 key1 = pkt.fp_hdr[1] & 0xffff; 943 key2 = pkt.fp_hdr[2]; 944 memset(&res, 0, sizeof(res)); 945 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 946 fh = LIST_NEXT(fh, fh_list)) { 947 if (pkt.fp_tcode == fh->fh_tcode && 948 key1 == fh->fh_key1 && 949 key2 == fh->fh_key2) { 950 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 951 &pkt); 952 break; 953 } 954 } 955 if (fh == NULL) { 956 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 957 #ifdef FW_DEBUG 958 printf("fwohci_arrq_input: no listener: tcode 0x%x, " 959 "addr=0x%04x %08x\n", pkt.fp_tcode, 960 key1, key2); 961 #endif 962 } 963 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 964 OHCI_CTXCTL_EVENT_ACK_PENDING) 965 continue; 966 if (rcode != -1) 967 fwohci_atrs_output(sc, rcode, &pkt, &res); 968 } 969 fwohci_buf_next(sc, fc); 970 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 971 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 972 } 973 974 /* 975 * Asynchronous Receive Response input frontend. 976 */ 977 static void 978 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 979 { 980 struct fwohci_pkt pkt; 981 struct fwohci_handler *fh; 982 u_int16_t srcid; 983 int rcode, tlabel; 984 985 while (fwohci_buf_input(sc, fc, &pkt)) { 986 srcid = pkt.fp_hdr[1] >> 16; 987 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 988 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 989 #ifdef FW_DEBUG 990 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x, tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 991 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, pkt.fp_dlen); 992 #endif 993 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 994 fh = LIST_NEXT(fh, fh_list)) { 995 if (pkt.fp_tcode == fh->fh_tcode && 996 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 997 tlabel == fh->fh_key2) { 998 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 999 LIST_REMOVE(fh, fh_list); 1000 free(fh, M_DEVBUF); 1001 break; 1002 } 1003 } 1004 #ifdef FW_DEBUG 1005 if (fh == NULL) 1006 printf("fwohci_arrs_input: no lister\n"); 1007 #endif 1008 } 1009 fwohci_buf_next(sc, fc); 1010 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1011 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1012 } 1013 1014 /* 1015 * Isochronous Receive input frontend. 1016 */ 1017 static void 1018 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1019 { 1020 int rcode, chan, tag; 1021 struct iovec *iov; 1022 struct fwohci_handler *fh; 1023 struct fwohci_pkt pkt; 1024 1025 while (fwohci_buf_input(sc, fc, &pkt)) { 1026 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1027 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1028 #ifdef FW_DEBUG 1029 printf("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1030 #endif 1031 if (tag == IEEE1394_TAG_GASP) { 1032 /* 1033 * The pkt with tag=3 is GASP format. 1034 * Move GASP header to header part. 1035 */ 1036 if (pkt.fp_dlen < 8) 1037 continue; 1038 iov = pkt.fp_iov; 1039 /* assuming pkt per buffer mode */ 1040 memcpy(pkt.fp_hdr + 1, iov->iov_base, 8); 1041 iov->iov_base = (caddr_t)iov->iov_base + 8; 1042 iov->iov_len -= 8; 1043 pkt.fp_hlen += 8; 1044 pkt.fp_dlen -= 8; 1045 } 1046 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1047 fh = LIST_NEXT(fh, fh_list)) { 1048 if (pkt.fp_tcode == fh->fh_tcode && 1049 chan == fh->fh_key1 && tag == fh->fh_key2) { 1050 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1051 &pkt); 1052 break; 1053 } 1054 } 1055 #ifdef FW_DEBUG 1056 if (fh == NULL) 1057 printf("fwohci_ir_input: no handler\n"); 1058 else 1059 printf("fwohci_ir_input: rcode %d\n", rcode); 1060 #endif 1061 } 1062 fwohci_buf_next(sc, fc); 1063 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1064 OHCI_CTXCTL_WAKE); 1065 } 1066 1067 /* 1068 * Asynchronous Transmit common routine. 1069 */ 1070 static int 1071 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1072 struct fwohci_pkt *pkt) 1073 { 1074 struct fwohci_buf *fb, *nfb; 1075 struct fwohci_desc *fd; 1076 struct iovec *iov; 1077 int i, ndesc; 1078 u_int32_t val; 1079 1080 #ifdef FW_DEBUG 1081 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1082 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1083 for (i = 0; i < pkt->fp_hlen/4; i++) 1084 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1085 printf("$"); 1086 for (ndesc = 0, iov = pkt->fp_iov; ndesc < pkt->fp_iovcnt; ndesc++, iov++) { 1087 for (i = 0; i < iov->iov_len; i++) 1088 printf("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1089 ((u_int8_t *)iov->iov_base)[i]); 1090 printf("$"); 1091 } 1092 printf("\n"); 1093 #endif 1094 1095 ndesc = 2 + pkt->fp_iovcnt; 1096 if (ndesc > 8) 1097 return ENOBUFS; 1098 1099 fb = TAILQ_FIRST(&fc->fc_buf); 1100 if (fb == NULL) 1101 return ENOBUFS; 1102 for (i = 1, fb = TAILQ_FIRST(&fc->fc_buf); i < ndesc; i++, fb = nfb) { 1103 nfb = TAILQ_NEXT(fb, fb_list); 1104 if (nfb == NULL) 1105 return ENOBUFS; 1106 if (nfb->fb_desc != fb->fb_desc + 1) { 1107 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != nfb) { 1108 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1109 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1110 } 1111 break; 1112 } 1113 } 1114 1115 fb = TAILQ_FIRST(&fc->fc_buf); 1116 fd = fb->fb_desc; 1117 fd->fd_flags = OHCI_DESC_IMMED; 1118 fd->fd_reqcount = pkt->fp_hlen; 1119 fd->fd_data = 0; 1120 fd->fd_branch = 0; 1121 fd->fd_status = 0; 1122 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1123 i = 3; /* XXX: 3 sec */ 1124 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1125 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1126 ((((val >> 25) + i) & 0x7) << 13); 1127 } else 1128 fd->fd_timestamp = 0; 1129 fb = TAILQ_NEXT(fb, fb_list); 1130 memcpy(fb->fb_desc, pkt->fp_hdr, pkt->fp_hlen); 1131 for (i = 0, iov = pkt->fp_iov; i < pkt->fp_iovcnt; i++, iov++) { 1132 fb = TAILQ_NEXT(fb, fb_list); 1133 memcpy(fb->fb_buf, iov->iov_base, iov->iov_len); /*XXX*/ 1134 fd = fb->fb_desc; 1135 fd->fd_flags = 0; 1136 fd->fd_reqcount = iov->iov_len; 1137 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1138 fd->fd_branch = 0; 1139 fd->fd_status = 0; 1140 fd->fd_timestamp = 0; 1141 } 1142 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1143 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1144 /* hang mbuf on the last buffer */ 1145 fb->fb_m = pkt->fp_m; 1146 fb->fb_callback = pkt->fp_callback; 1147 1148 fb = TAILQ_FIRST(&fc->fc_buf); 1149 #ifdef FW_DEBUG 1150 printf("fwohci_at_output: desc %d", fb->fb_desc - (struct fwohci_desc *)sc->sc_desc); 1151 for (i = 0; i < ndesc * 4; i++) 1152 printf("%s%08x", i&7?" ":"\n\t", ((u_int32_t *)fb->fb_desc)[i]); 1153 printf("\n"); 1154 #endif 1155 1156 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1157 OHCI_SUBREG_ContextControlClear); 1158 1159 if (val & OHCI_CTXCTL_RUN) { 1160 if (fc->fc_branch == NULL) { 1161 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1162 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1163 goto run; 1164 } 1165 *fc->fc_branch = fb->fb_daddr | ndesc; 1166 if ((val & OHCI_CTXCTL_ACTIVE) == 0) 1167 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1168 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1169 } else { 1170 run: 1171 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1172 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1173 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1174 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1175 } 1176 fc->fc_branch = &fd->fd_branch; 1177 1178 for (i = 0; i < ndesc; i++) { 1179 fb = TAILQ_FIRST(&fc->fc_buf); 1180 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1181 TAILQ_INSERT_TAIL(&fc->fc_busy, fb, fb_list); 1182 } 1183 return 0; 1184 } 1185 1186 static void 1187 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1188 { 1189 struct fwohci_buf *fb, *lfb; 1190 1191 while ((fb = TAILQ_FIRST(&fc->fc_busy)) != NULL) { 1192 for (lfb = fb; lfb != NULL; lfb = TAILQ_NEXT(lfb, fb_list)) { 1193 #ifdef FW_DEBUG 1194 printf("fwohci_at_done: desc %d, %08x %08x %08x %08x\n", 1195 lfb->fb_desc - (struct fwohci_desc *)sc->sc_desc, 1196 ((u_int32_t *)lfb->fb_desc)[0], 1197 ((u_int32_t *)lfb->fb_desc)[1], 1198 ((u_int32_t *)lfb->fb_desc)[2], 1199 ((u_int32_t *)lfb->fb_desc)[3]); 1200 #endif 1201 if (lfb->fb_desc->fd_flags & OHCI_DESC_LAST) 1202 break; 1203 } 1204 if (lfb == NULL) { 1205 printf("fwohci_at_done: last not found\n"); 1206 break; 1207 } 1208 if (!(lfb->fb_desc->fd_status & OHCI_CTXCTL_ACTIVE)) 1209 break; 1210 if (lfb->fb_desc->fd_flags & OHCI_DESC_IMMED) 1211 lfb = TAILQ_NEXT(lfb, fb_list); 1212 do { 1213 fb = TAILQ_FIRST(&fc->fc_busy); 1214 TAILQ_REMOVE(&fc->fc_busy, fb, fb_list); 1215 if (fb->fb_m != NULL) { 1216 if (fb->fb_callback != NULL) { 1217 (*fb->fb_callback) 1218 (sc->sc_sc1394.sc1394_if, fb->fb_m); 1219 fb->fb_callback = NULL; 1220 } else { 1221 m_freem(fb->fb_m); 1222 } 1223 fb->fb_m = NULL; 1224 } 1225 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1226 } while (fb != lfb); 1227 } 1228 } 1229 1230 /* 1231 * Asynchronous Transmit Reponse -- in response of request packet. 1232 */ 1233 static void 1234 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1235 struct fwohci_pkt *res) 1236 { 1237 int i; 1238 1239 if (((*req->fp_trail & 0x001f0000) >> 16) != 1240 OHCI_CTXCTL_EVENT_ACK_PENDING) 1241 return; 1242 1243 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1244 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1245 switch (req->fp_tcode) { 1246 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1247 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1248 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1249 res->fp_hlen = 12; 1250 break; 1251 case IEEE1394_TCODE_READ_REQ_QUAD: 1252 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1253 res->fp_hlen = 16; 1254 res->fp_dlen = 0; 1255 if (res->fp_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1256 res->fp_hdr[3] = 1257 *(u_int32_t *)res->fp_iov[0].iov_base; 1258 res->fp_iovcnt = 0; 1259 break; 1260 case IEEE1394_TCODE_READ_REQ_BLOCK: 1261 case IEEE1394_TCODE_LOCK_REQ: 1262 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1263 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1264 else 1265 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1266 res->fp_hlen = 16; 1267 res->fp_dlen = 0; 1268 for (i = 0; i < res->fp_iovcnt; i++) 1269 res->fp_dlen += res->fp_iov[i].iov_len; 1270 res->fp_hdr[3] = res->fp_dlen << 16; 1271 break; 1272 } 1273 res->fp_hdr[0] |= (res->fp_tcode << 4); 1274 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1275 } 1276 1277 /* 1278 * APPLICATION LAYER SERVICES 1279 */ 1280 1281 /* 1282 * Initialization for Configuration ROM (no DMA context) 1283 */ 1284 1285 #define CFR_MAXUNIT 20 1286 1287 struct configromctx { 1288 u_int32_t *ptr; 1289 int curunit; 1290 struct { 1291 u_int32_t *start; 1292 int length; 1293 u_int32_t *refer; 1294 int refunit; 1295 } unit[CFR_MAXUNIT]; 1296 }; 1297 1298 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1299 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1300 1301 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1302 1303 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1304 1305 #define CFR_PUT_CRC(cfr, n) \ 1306 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1307 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1308 1309 #define CFR_START_UNIT(cfr, n) \ 1310 do { \ 1311 if ((cfr)->unit[n].refer != NULL) { \ 1312 *(cfr)->unit[n].refer |= \ 1313 (cfr)->ptr - (cfr)->unit[n].refer; \ 1314 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1315 } \ 1316 (cfr)->curunit = (n); \ 1317 (cfr)->unit[n].start = (cfr)->ptr++; \ 1318 } while (0 /* CONSTCOND */) 1319 1320 #define CFR_PUT_REFER(cfr, key, n) \ 1321 do { \ 1322 (cfr)->unit[n].refer = (cfr)->ptr; \ 1323 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1324 *(cfr)->ptr++ = (key) << 24; \ 1325 } while (0 /* CONSTCOND */) 1326 1327 #define CFR_END_UNIT(cfr) \ 1328 do { \ 1329 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1330 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1331 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1332 } while (0 /* CONSTCOND */) 1333 1334 static u_int16_t 1335 fwohci_crc16(u_int32_t *ptr, int len) 1336 { 1337 int shift; 1338 u_int32_t crc, sum, data; 1339 1340 crc = 0; 1341 while (len-- > 0) { 1342 data = *ptr++; 1343 for (shift = 28; shift >= 0; shift -= 4) { 1344 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1345 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1346 } 1347 crc &= 0xffff; 1348 } 1349 return crc; 1350 } 1351 1352 static void 1353 fwohci_configrom_init(struct fwohci_softc *sc) 1354 { 1355 int i; 1356 struct fwohci_buf *fb; 1357 u_int32_t *hdr; 1358 struct configromctx cfr; 1359 1360 fb = &sc->sc_buf_cnfrom; 1361 memset(&cfr, 0, sizeof(cfr)); 1362 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1363 1364 /* headers */ 1365 CFR_START_UNIT(&cfr, 0); 1366 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1367 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1368 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1369 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1370 CFR_END_UNIT(&cfr); 1371 /* copy info_length from crc_length */ 1372 *hdr |= (*hdr & 0x00ff0000) << 8; 1373 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1374 1375 /* root directory */ 1376 CFR_START_UNIT(&cfr, 1); 1377 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1378 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1379 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1380 /* spt,64,fix,lst,drq */ 1381 #ifdef INET 1382 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1383 #endif /* INET */ 1384 #ifdef INET6 1385 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1386 #endif /* INET6 */ 1387 CFR_END_UNIT(&cfr); 1388 1389 CFR_START_UNIT(&cfr, 2); 1390 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1391 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1392 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1393 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1394 CFR_END_UNIT(&cfr); 1395 1396 #ifdef INET 1397 /* IPv4 unit directory */ 1398 CFR_START_UNIT(&cfr, 3); 1399 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1400 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1401 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1402 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1403 CFR_END_UNIT(&cfr); 1404 1405 CFR_START_UNIT(&cfr, 6); 1406 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1407 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1408 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1409 CFR_END_UNIT(&cfr); 1410 1411 CFR_START_UNIT(&cfr, 7); 1412 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1413 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1414 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1415 CFR_END_UNIT(&cfr); 1416 #endif /* INET */ 1417 1418 #ifdef INET6 1419 /* IPv6 unit directory */ 1420 CFR_START_UNIT(&cfr, 4); 1421 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1422 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1423 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1424 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1425 CFR_END_UNIT(&cfr); 1426 1427 CFR_START_UNIT(&cfr, 8); 1428 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1429 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1430 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1431 CFR_END_UNIT(&cfr); 1432 1433 CFR_START_UNIT(&cfr, 9); 1434 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1435 CFR_PUT_DATA1(&cfr, 0); 1436 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1437 CFR_END_UNIT(&cfr); 1438 #endif /* INET6 */ 1439 1440 #ifdef FW_DEBUG 1441 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 1442 for (i = 0; i < cfr.ptr - hdr; i++) 1443 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 1444 printf("\n"); 1445 #endif /* FW_DEBUG */ 1446 1447 /* 1448 * Make network byte order for DMA 1449 */ 1450 for (i = 0; i < cfr.ptr - hdr; i++) 1451 NTOHL(hdr[i]); 1452 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 1453 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 1454 1455 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 1456 fb->fb_dmamap->dm_segs[0].ds_addr); 1457 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 1458 } 1459 1460 /* 1461 * SelfID buffer (no DMA context) 1462 */ 1463 static void 1464 fwohci_selfid_init(struct fwohci_softc *sc) 1465 { 1466 struct fwohci_buf *fb; 1467 1468 fb = &sc->sc_buf_selfid; 1469 memset(fb->fb_buf, 0, OHCI_PAGE_SIZE); 1470 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, OHCI_PAGE_SIZE, 1471 BUS_DMASYNC_PREREAD); 1472 1473 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 1474 fb->fb_dmamap->dm_segs[0].ds_addr); 1475 } 1476 1477 static void 1478 fwohci_selfid_input(struct fwohci_softc *sc) 1479 { 1480 int i; 1481 u_int32_t count, val; 1482 u_int32_t *buf; 1483 1484 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 1485 if (val & OHCI_SelfID_Error) { 1486 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 1487 return; 1488 } 1489 count = (val & OHCI_SelfID_Size_MASK) >> OHCI_SelfID_Size_BITPOS; 1490 1491 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 1492 0, count << 2, BUS_DMASYNC_POSTREAD); 1493 1494 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 1495 if ((val & OHCI_SelfID_Gen_MASK) != (*buf & OHCI_SelfID_Gen_MASK)) { 1496 printf("%s: SelfID Gen mismatch (%d, %d)\n", 1497 sc->sc_sc1394.sc1394_dev.dv_xname, 1498 (val & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS, 1499 (*buf & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS); 1500 return; 1501 } 1502 1503 #ifdef FW_DEBUG 1504 printf("\n%s: SelfID:", sc->sc_sc1394.sc1394_dev.dv_xname); 1505 for (i = 0; i < count; i++) 1506 printf("%s%08x", i&7?" ":"\n ", buf[i]); 1507 printf("\n"); 1508 #endif /* FW_DEBUG */ 1509 1510 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 1511 for (i = 1; i < count; i += 2) { 1512 if (buf[i] != ~buf[i + 1]) { 1513 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 1514 sc->sc_sc1394.sc1394_dev.dv_xname, i, 1515 buf[i], buf[i + 1]); 1516 return; 1517 } 1518 if (buf[i] & 0x00000001) 1519 continue; /* more pkt */ 1520 if (buf[i] & 0x00800000) 1521 continue; /* external id */ 1522 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 1523 if ((buf[i] & 0x00400800) == 0x00400800) 1524 sc->sc_irmid = sc->sc_rootid; 1525 } 1526 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 1527 if ((val & OHCI_NodeId_IDValid) == 0) { 1528 sc->sc_nodeid = IEEE1394_BCAST_PHY_ID; /* invalid */ 1529 return; 1530 } 1531 sc->sc_nodeid = val & 0xffff; 1532 #ifdef FW_DEBUG 1533 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 1534 sc->sc_sc1394.sc1394_dev.dv_xname, 1535 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 1536 sc->sc_rootid, sc->sc_irmid); 1537 #endif 1538 1539 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1540 return; 1541 1542 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 1543 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 1544 OHCI_LinkControl_CycleMaster); 1545 else 1546 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 1547 OHCI_LinkControl_CycleMaster); 1548 } 1549 1550 1551 /* 1552 * some CSRs are handled by driver. 1553 */ 1554 static void 1555 fwohci_csr_init(struct fwohci_softc *sc) 1556 { 1557 int i; 1558 static u_int32_t csr[] = { 1559 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 1560 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 1561 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 1562 CSR_SB_BROADCAST_CHANNEL 1563 }; 1564 1565 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 1566 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 1567 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 1568 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 1569 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 1570 } 1571 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 1572 } 1573 1574 static int 1575 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 1576 { 1577 struct fwohci_pkt res; 1578 u_int32_t reg; 1579 1580 /* 1581 * XXX need to do special functionality other than just r/w... 1582 */ 1583 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 1584 1585 if ((reg & 0x03) != 0) { 1586 /* alignment error */ 1587 return IEEE1394_RCODE_ADDRESS_ERROR; 1588 } 1589 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 1590 #ifdef FW_DEBUG 1591 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x -> 0x%08x\n", 1592 reg, *(u_int32_t *)(&sc->sc_csr[reg]), 1593 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 1594 #endif 1595 *(u_int32_t *)&sc->sc_csr[reg] = 1596 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 1597 } else { 1598 #ifdef FW_DEBUG 1599 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x\n", 1600 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 1601 #endif 1602 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 1603 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 1604 res.fp_iov[0].iov_len = 4; 1605 res.fp_iovcnt = 1; 1606 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 1607 return -1; 1608 } 1609 return IEEE1394_RCODE_COMPLETE; 1610 } 1611 1612 /* 1613 * Mapping between nodeid and unique ID (EUI-64). 1614 */ 1615 static void 1616 fwohci_uid_collect(struct fwohci_softc *sc) 1617 { 1618 int i; 1619 struct fwohci_uidtbl *fu; 1620 struct fwohci_pkt pkt; 1621 1622 if (sc->sc_uidtbl != NULL) 1623 free(sc->sc_uidtbl, M_DEVBUF); 1624 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 1625 M_DEVBUF, M_NOWAIT); 1626 if (sc->sc_uidtbl == NULL) 1627 return; 1628 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 1629 1630 memset(&pkt, 0, sizeof(pkt)); 1631 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 1632 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 1633 memcpy(fu->fu_hi.fu_uid, sc->sc_sc1394.sc1394_guid, 4); 1634 memcpy(fu->fu_lo.fu_uid, sc->sc_sc1394.sc1394_guid, 4); 1635 fu->fu_hi.fu_valid = fu->fu_lo.fu_valid = 1; 1636 continue; 1637 } 1638 fu->fu_hi.fu_valid = fu->fu_lo.fu_valid = 0; 1639 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 1640 pkt.fp_hlen = 12; 1641 pkt.fp_dlen = 0; 1642 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 1643 (pkt.fp_tcode << 4); 1644 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 1645 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 1646 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 1647 sc->sc_tlabel, fwohci_uid_input, &fu->fu_hi); 1648 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 1649 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 1650 1651 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 1652 (pkt.fp_tcode << 4); 1653 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 1654 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 1655 sc->sc_tlabel, fwohci_uid_input, &fu->fu_lo); 1656 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 1657 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 1658 } 1659 } 1660 1661 static int 1662 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 1663 { 1664 struct fwohci_uident *fu = arg; 1665 1666 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 1667 fu->fu_valid = 1; 1668 #ifdef FW_DEBUG 1669 printf("fwohci_uid_input: %02x%02x%02x%02x\n", 1670 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3]); 1671 #endif 1672 return 0; 1673 } 1674 1675 static int 1676 fwohci_uid_lookup(struct fwohci_softc *sc, u_int8_t *uid) 1677 { 1678 struct fwohci_uidtbl *fu; 1679 int n; 1680 static const u_int8_t bcast[] = 1681 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1682 1683 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 1684 return IEEE1394_BCAST_PHY_ID; 1685 fu = sc->sc_uidtbl; 1686 if (fu == NULL) { 1687 fwohci_uid_collect(sc); /* try to get */ 1688 return -1; 1689 } 1690 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 1691 if (fu->fu_hi.fu_valid && fu->fu_lo.fu_valid && 1692 memcmp(fu->fu_hi.fu_uid, uid, 4) == 0 && 1693 memcmp(fu->fu_lo.fu_uid, uid + 4, 4) == 0) 1694 break; 1695 } 1696 if (n > sc->sc_rootid) { 1697 fwohci_uid_collect(sc); /* try to get */ 1698 return -1; 1699 } 1700 return n; 1701 } 1702 1703 /* 1704 * functions to support network interface 1705 */ 1706 static int 1707 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 1708 void (*handler)(struct device *, struct mbuf *)) 1709 { 1710 struct fwohci_softc *sc = (struct fwohci_softc *)self; 1711 1712 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 1713 fwohci_if_input, handler); 1714 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 1715 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 1716 IEEE1394_TAG_GASP, fwohci_if_input, handler); 1717 return 0; 1718 } 1719 1720 static int 1721 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 1722 { 1723 #ifdef FW_DEBUG 1724 int i; 1725 #endif 1726 int n, len; 1727 struct mbuf *m; 1728 struct iovec *iov; 1729 void (*handler)(struct device *, struct mbuf *) = arg; 1730 1731 #ifdef FW_DEBUG 1732 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 1733 pkt->fp_tcode, pkt->fp_dlen); 1734 for (i = 0; i < pkt->fp_hlen/4; i++) 1735 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1736 printf("$"); 1737 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++) { 1738 iov = &pkt->fp_iov[n]; 1739 for (i = 0; i < iov->iov_len; i++) 1740 printf("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1741 ((u_int8_t *)iov->iov_base)[i]); 1742 printf("$"); 1743 } 1744 printf("\n"); 1745 #endif /* FW_DEBUG */ 1746 len = pkt->fp_dlen; 1747 MGETHDR(m, M_DONTWAIT, MT_DATA); 1748 if (m == NULL) 1749 return IEEE1394_RCODE_COMPLETE; 1750 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) 1751 m->m_flags |= M_BCAST; 1752 m->m_pkthdr.rcvif = NULL; /* set in child */ 1753 m->m_pkthdr.len = len; 1754 m->m_len = 0; 1755 if (len > MHLEN) { 1756 MCLGET(m, M_DONTWAIT); 1757 if ((m->m_flags & M_EXT) == 0) { 1758 m_freem(m); 1759 return IEEE1394_RCODE_COMPLETE; 1760 } 1761 } 1762 /* 1763 * We may use receive buffer by external mbuf instead of copy here. 1764 * But asynchronous receive buffer must be operate in buffer fill 1765 * mode, so that each receive buffer will shared by multiple mbufs. 1766 * If upper layer doesn't free mbuf soon, e.g. application program 1767 * is suspended, buffer must be reallocated. 1768 * Isochronous buffer must be operate in packet buffer mode, and 1769 * it is easy to map receive buffer to external mbuf. But it is 1770 * used for broadcast/multicast only, and is expected not so 1771 * performance sensitive for now. 1772 * XXX: The performance may be important for multicast case, 1773 * so we should revisit here later. 1774 * -- onoe 1775 */ 1776 n = 0; 1777 iov = pkt->fp_iov; 1778 while (len > 0) { 1779 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 1780 iov->iov_len); 1781 m->m_len += iov->iov_len; 1782 len -= iov->iov_len; 1783 iov++; 1784 } 1785 (*handler)(sc->sc_sc1394.sc1394_if, m); 1786 return IEEE1394_RCODE_COMPLETE; 1787 } 1788 1789 static int 1790 fwohci_if_output(struct device *self, struct mbuf *m0, 1791 void (*callback)(struct device *, struct mbuf *)) 1792 { 1793 struct fwohci_softc *sc = (struct fwohci_softc *)self; 1794 struct mbuf *m; 1795 struct fwohci_pkt pkt; 1796 struct iovec *iov; 1797 u_int8_t *p; 1798 int n; 1799 int error; 1800 1801 memset(&pkt, 0, sizeof(pkt)); 1802 if (m0->m_flags & (M_BCAST|M_MCAST)) { 1803 m_adj(m0, 8); 1804 /* construct GASP header */ 1805 p = mtod(m0, u_int8_t *); 1806 p[0] = sc->sc_nodeid >> 8; 1807 p[1] = sc->sc_nodeid & 0xff; 1808 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 1809 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 1810 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 1811 pkt.fp_hlen = 8; 1812 pkt.fp_hdr[0] = (IEEE1394_TAG_GASP << 14) | 1813 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 1814 OHCI_NodeId_NodeNumber) << 8); 1815 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 1816 } else { 1817 p = mtod(m0, u_int8_t *); 1818 m_adj(m0, 16); 1819 n = fwohci_uid_lookup(sc, p); 1820 if (n < 0) { 1821 printf("fwohci_if_output: nodeid unknown: %08x%08x\n", 1822 htonl(((u_int32_t *)p)[0]), 1823 htonl(((u_int32_t *)p)[1])); 1824 error = EHOSTUNREACH; 1825 goto end; 1826 } 1827 if (n == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 1828 /* should not come here */ 1829 error = EIO; 1830 goto end; 1831 } 1832 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 1833 pkt.fp_hlen = 16; 1834 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 1835 (p[9] << 16); 1836 pkt.fp_hdr[1] = 1837 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 1838 (p[10] << 8) | p[11]; 1839 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 1840 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 1841 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 1842 } 1843 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 1844 pkt.fp_dlen = m0->m_pkthdr.len; 1845 for (m = m0; m != NULL; m = m->m_next) { 1846 iov = &pkt.fp_iov[pkt.fp_iovcnt++]; 1847 iov->iov_base = mtod(m, caddr_t); 1848 iov->iov_len = m->m_len; 1849 } 1850 pkt.fp_m = m0; 1851 pkt.fp_callback = callback; 1852 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 1853 end: 1854 if (error) { 1855 if (callback) 1856 (*callback)(sc->sc_sc1394.sc1394_if, m0); 1857 else 1858 m_freem(m0); 1859 } 1860 return error; 1861 } 1862
Indexes created Tue Sep 23 20:09:58 GMT 2025