fwohci.c revision 1.45
1 /* $NetBSD: fwohci.c,v 1.45 2001/11/13 12:24:11 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 /* 47 * The first version to support isochronous acquisition part is wrtten 48 * by HAYAKAWA Koichi <haya (at) netbsd.org>. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.45 2001/11/13 12:24:11 lukem Exp $"); 53 54 #define DOUBLEBUF 1 55 #define NO_THREAD 1 56 57 #include "opt_inet.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kthread.h> 62 #include <sys/types.h> 63 #include <sys/socket.h> 64 #include <sys/callout.h> 65 #include <sys/device.h> 66 #include <sys/kernel.h> 67 #include <sys/malloc.h> 68 #include <sys/mbuf.h> 69 70 #if __NetBSD_Version__ >= 105010000 71 #include <uvm/uvm_extern.h> 72 #else 73 #include <vm/vm.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/ieee1394/ieee1394reg.h> 80 #include <dev/ieee1394/fwohcireg.h> 81 82 #include <dev/ieee1394/ieee1394var.h> 83 #include <dev/ieee1394/fwohcivar.h> 84 85 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 86 87 #if 0 88 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 89 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 90 #endif 91 static void fwohci_create_event_thread(void *); 92 static void fwohci_thread_init(void *); 93 94 static void fwohci_event_thread(struct fwohci_softc *); 95 static void fwohci_hw_init(struct fwohci_softc *); 96 static void fwohci_power(int, void *); 97 static void fwohci_shutdown(void *); 98 99 static int fwohci_desc_alloc(struct fwohci_softc *); 100 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 101 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 102 103 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 104 int, int, int); 105 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 106 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 107 108 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 109 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 110 static void fwohci_buf_init_rx(struct fwohci_softc *); 111 static void fwohci_buf_start_rx(struct fwohci_softc *); 112 static void fwohci_buf_stop_tx(struct fwohci_softc *); 113 static void fwohci_buf_stop_rx(struct fwohci_softc *); 114 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 115 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_buf **, 116 caddr_t *, int); 117 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 118 struct fwohci_pkt *); 119 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 120 struct fwohci_pkt *); 121 122 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 123 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 124 static void fwohci_phy_busreset(struct fwohci_softc *); 125 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 126 127 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 128 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 129 130 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 131 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 132 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 133 134 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 135 struct fwohci_pkt *); 136 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 137 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 138 struct fwohci_pkt *); 139 140 static int fwohci_guidrom_init(struct fwohci_softc *); 141 static void fwohci_configrom_init(struct fwohci_softc *); 142 static int fwohci_configrom_input(struct fwohci_softc *, void *, 143 struct fwohci_pkt *); 144 static void fwohci_selfid_init(struct fwohci_softc *); 145 static int fwohci_selfid_input(struct fwohci_softc *); 146 147 static void fwohci_csr_init(struct fwohci_softc *); 148 static int fwohci_csr_input(struct fwohci_softc *, void *, 149 struct fwohci_pkt *); 150 151 static void fwohci_uid_collect(struct fwohci_softc *); 152 static void fwohci_uid_req(struct fwohci_softc *, int); 153 static int fwohci_uid_input(struct fwohci_softc *, void *, 154 struct fwohci_pkt *); 155 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 156 static void fwohci_check_nodes(struct fwohci_softc *); 157 158 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 159 void (*)(struct device *, struct mbuf *)); 160 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 161 static int fwohci_if_input_iso(struct fwohci_softc *, void *, struct fwohci_pkt *); 162 static int fwohci_if_output(struct device *, struct mbuf *, 163 void (*)(struct device *, struct mbuf *)); 164 static int fwohci_if_setiso(struct device *, u_int32_t, u_int32_t, u_int32_t, 165 void (*)(struct device *, struct mbuf *)); 166 static int fwohci_read(struct ieee1394_abuf *); 167 static int fwohci_write(struct ieee1394_abuf *); 168 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 169 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 170 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 171 struct fwohci_pkt *); 172 static int fwohci_inreg(struct ieee1394_abuf *, int); 173 static int fwohci_parse_input(struct fwohci_softc *, void *, 174 struct fwohci_pkt *); 175 static int fwohci_submatch(struct device *, struct cfdata *, void *); 176 177 #ifdef FW_DEBUG 178 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 179 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 180 181 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 182 183 #define DPRINTF(x) if (fwdebug) printf x 184 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 185 int fwdebug = 0; 186 #else 187 #define DPRINTF(x) 188 #define DPRINTFN(n,x) 189 #endif 190 191 int 192 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 193 { 194 int i; 195 u_int32_t val; 196 #if 0 197 int error; 198 #endif 199 200 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 201 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 202 203 evcnt_attach_dynamic(&sc->sc_isocnt, EVCNT_TYPE_MISC, ev, 204 sc->sc_sc1394.sc1394_dev.dv_xname, "iso"); 205 evcnt_attach_dynamic(&sc->sc_isopktcnt, EVCNT_TYPE_MISC, ev, 206 sc->sc_sc1394.sc1394_dev.dv_xname, "isopackets"); 207 208 /* 209 * Wait for reset completion 210 */ 211 for (i = 0; i < OHCI_LOOP; i++) { 212 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 213 if ((val & OHCI_HCControl_SoftReset) == 0) 214 break; 215 DELAY(10); 216 } 217 218 /* What dialect of OHCI is this device? 219 */ 220 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 221 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 222 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 223 224 LIST_INIT(&sc->sc_nodelist); 225 226 if (fwohci_guidrom_init(sc) != 0) { 227 printf("\n%s: fatal: no global UID ROM\n", 228 sc->sc_sc1394.sc1394_dev.dv_xname); 229 return -1; 230 } 231 232 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 233 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 234 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 235 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 236 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 237 238 /* Get the maximum link speed and receive size 239 */ 240 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 241 sc->sc_sc1394.sc1394_link_speed = 242 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 243 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 244 printf(", %s", 245 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 246 } else { 247 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 248 } 249 250 /* MaxRec is encoded as log2(max_rec_octets)-1 251 */ 252 sc->sc_sc1394.sc1394_max_receive = 253 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 254 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 255 256 /* 257 * Count how many isochronous ctx we have. 258 */ 259 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 260 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 261 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 262 for (i = 0; val != 0; val >>= 1) { 263 if (val & 0x1) 264 i++; 265 } 266 sc->sc_isoctx = i; 267 printf(", %d iso_ctx", sc->sc_isoctx); 268 269 printf("\n"); 270 271 #if 0 272 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 273 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 274 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 275 return error; 276 #endif 277 278 sc->sc_dying = 0; 279 sc->sc_nodeid = 0xffff; /* invalid */ 280 281 kthread_create(fwohci_create_event_thread, sc); 282 return 0; 283 } 284 285 static int 286 fwohci_if_setiso(struct device *self, u_int32_t channel, u_int32_t tag, 287 u_int32_t direction, void (*handler)(struct device *, struct mbuf *)) 288 { 289 struct fwohci_softc *sc = (struct fwohci_softc *)self; 290 int retval; 291 int s; 292 293 if (direction == 1) { 294 return EIO; 295 } 296 297 s = splnet(); 298 retval = fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 299 channel, tag, fwohci_if_input_iso, handler); 300 splx(s); 301 302 if (!retval) { 303 printf("%s: dummy iso handler set\n", 304 sc->sc_sc1394.sc1394_dev.dv_xname); 305 } else { 306 printf("%s: dummy iso handler cannot set\n", 307 sc->sc_sc1394.sc1394_dev.dv_xname); 308 } 309 310 return retval; 311 } 312 313 int 314 fwohci_intr(void *arg) 315 { 316 struct fwohci_softc * const sc = arg; 317 int progress = 0; 318 u_int32_t intmask, iso; 319 320 for (;;) { 321 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 322 323 /* 324 * On a bus reset, everything except bus reset gets 325 * cleared. That can't get cleared until the selfid 326 * phase completes (which happens outside the 327 * interrupt routines). So if just a bus reset is left 328 * in the mask and it's already in the sc_intmask, 329 * just return. 330 */ 331 332 if ((intmask == 0) || 333 (progress && (intmask == OHCI_Int_BusReset) && 334 (sc->sc_intmask & OHCI_Int_BusReset))) { 335 if (progress) 336 wakeup(fwohci_event_thread); 337 return progress; 338 } 339 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 340 intmask & ~OHCI_Int_BusReset); 341 #ifdef FW_DEBUG 342 if (fwdebug > 1) 343 fwohci_show_intr(sc, intmask); 344 #endif 345 346 if (intmask & OHCI_Int_BusReset) { 347 /* 348 * According to OHCI spec 6.1.1 "busReset", 349 * All asynchronous transmit must be stopped before 350 * clearing BusReset. Moreover, the BusReset 351 * interrupt bit should not be cleared during the 352 * SelfID phase. Thus we turned off interrupt mask 353 * bit of BusReset instead until SelfID completion 354 * or SelfID timeout. 355 */ 356 intmask &= OHCI_Int_SelfIDComplete; 357 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 358 OHCI_Int_BusReset); 359 sc->sc_intmask = OHCI_Int_BusReset; 360 } 361 sc->sc_intmask |= intmask; 362 363 if (intmask & OHCI_Int_IsochTx) { 364 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 365 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 366 } 367 if (intmask & OHCI_Int_IsochRx) { 368 #if NO_THREAD 369 int i; 370 int asyncstream = 0; 371 #endif 372 373 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 374 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 375 #if NO_THREAD 376 for (i = 0; i < sc->sc_isoctx; i++) { 377 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) { 378 if (sc->sc_ctx_ir[i]->fc_type == FWOHCI_CTX_ISO_SINGLE) { 379 asyncstream |= (1 << i); 380 continue; 381 } 382 bus_dmamap_sync(sc->sc_dmat, 383 sc->sc_ddmamap, 384 0, sizeof(struct fwohci_desc) * sc->sc_descsize, 385 BUS_DMASYNC_PREREAD); 386 sc->sc_isocnt.ev_count++; 387 388 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 389 } 390 } 391 if (asyncstream != 0) { 392 sc->sc_iso |= asyncstream; 393 } else { 394 /* all iso intr is pure isochronous */ 395 sc->sc_intmask &= ~OHCI_Int_IsochRx; 396 } 397 #else 398 sc->sc_iso |= iso; 399 #endif /* NO_THREAD */ 400 } 401 402 if (!progress) { 403 sc->sc_intrcnt.ev_count++; 404 progress = 1; 405 } 406 } 407 } 408 409 static void 410 fwohci_create_event_thread(void *arg) 411 { 412 struct fwohci_softc *sc = arg; 413 414 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 415 sc->sc_sc1394.sc1394_dev.dv_xname)) { 416 printf("%s: unable to create event thread\n", 417 sc->sc_sc1394.sc1394_dev.dv_xname); 418 panic("fwohci_create_event_thread"); 419 } 420 } 421 422 static void 423 fwohci_thread_init(void *arg) 424 { 425 struct fwohci_softc *sc = arg; 426 int i; 427 428 /* 429 * Allocate descriptors 430 */ 431 if (fwohci_desc_alloc(sc)) { 432 printf("%s: not enabling interrupts\n", 433 sc->sc_sc1394.sc1394_dev.dv_xname); 434 kthread_exit(1); 435 } 436 437 /* 438 * Enable Link Power 439 */ 440 441 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 442 443 /* 444 * Allocate DMA Context 445 */ 446 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 447 OHCI_CTX_ASYNC_RX_REQUEST, FWOHCI_CTX_ASYNC); 448 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 449 OHCI_CTX_ASYNC_RX_RESPONSE, FWOHCI_CTX_ASYNC); 450 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST, 451 FWOHCI_CTX_ASYNC); 452 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE, 453 FWOHCI_CTX_ASYNC); 454 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 455 M_DEVBUF, M_WAITOK); 456 for (i = 0; i < sc->sc_isoctx; i++) 457 sc->sc_ctx_ir[i] = NULL; 458 459 /* 460 * Allocate buffer for configuration ROM and SelfID buffer 461 */ 462 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 463 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 464 465 callout_init(&sc->sc_selfid_callout); 466 467 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 468 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 469 sc->sc_sc1394.sc1394_ifsetiso = fwohci_if_setiso; 470 471 /* 472 * establish hooks for shutdown and suspend/resume 473 */ 474 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 475 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 476 477 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 478 fwohci_print); 479 480 /* Main loop. It's not coming back normally. */ 481 482 fwohci_event_thread(sc); 483 484 kthread_exit(0); 485 } 486 487 static void 488 fwohci_event_thread(struct fwohci_softc *sc) 489 { 490 int i, s; 491 u_int32_t intmask, iso; 492 493 s = splbio(); 494 495 /* 496 * Initialize hardware registers. 497 */ 498 499 fwohci_hw_init(sc); 500 501 /* Initial Bus Reset */ 502 fwohci_phy_busreset(sc); 503 splx(s); 504 505 while (!sc->sc_dying) { 506 s = splbio(); 507 intmask = sc->sc_intmask; 508 if (intmask == 0) { 509 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 510 splx(s); 511 continue; 512 } 513 sc->sc_intmask = 0; 514 splx(s); 515 516 if (intmask & OHCI_Int_BusReset) { 517 fwohci_buf_stop_tx(sc); 518 if (sc->sc_uidtbl != NULL) { 519 free(sc->sc_uidtbl, M_DEVBUF); 520 sc->sc_uidtbl = NULL; 521 } 522 523 callout_reset(&sc->sc_selfid_callout, 524 OHCI_SELFID_TIMEOUT, 525 (void (*)(void *))fwohci_phy_busreset, sc); 526 sc->sc_nodeid = 0xffff; /* indicate invalid */ 527 sc->sc_rootid = 0; 528 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 529 } 530 if (intmask & OHCI_Int_SelfIDComplete) { 531 s = splbio(); 532 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 533 OHCI_Int_BusReset); 534 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 535 OHCI_Int_BusReset); 536 splx(s); 537 callout_stop(&sc->sc_selfid_callout); 538 if (fwohci_selfid_input(sc) == 0) { 539 fwohci_buf_start_rx(sc); 540 fwohci_uid_collect(sc); 541 } 542 } 543 if (intmask & OHCI_Int_ReqTxComplete) 544 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 545 if (intmask & OHCI_Int_RespTxComplete) 546 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 547 if (intmask & OHCI_Int_RQPkt) 548 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 549 if (intmask & OHCI_Int_RSPkt) 550 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 551 if (intmask & OHCI_Int_IsochRx) { 552 s = splbio(); 553 iso = sc->sc_iso; 554 sc->sc_iso = 0; 555 splx(s); 556 for (i = 0; i < sc->sc_isoctx; i++) { 557 if ((iso & (1 << i)) && 558 sc->sc_ctx_ir[i] != NULL) { 559 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 560 sc->sc_isocnt.ev_count++; 561 } 562 } 563 } 564 } 565 } 566 567 #if 0 568 static int 569 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 570 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 571 { 572 bus_dma_segment_t segs[1]; 573 int error, nsegs, steps; 574 575 steps = 0; 576 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 577 segs, 1, &nsegs, flags); 578 if (error) 579 goto cleanup; 580 581 steps = 1; 582 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 583 kvap, flags); 584 if (error) 585 goto cleanup; 586 587 if (error == 0) 588 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 589 size, flags, mapp); 590 if (error) 591 goto cleanup; 592 if (error == 0) 593 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 594 flags); 595 if (error) 596 goto cleanup; 597 598 cleanup: 599 switch (steps) { 600 case 1: 601 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 602 } 603 604 return error; 605 } 606 #endif 607 608 int 609 fwohci_print(void *aux, const char *pnp) 610 { 611 char *name = aux; 612 613 if (pnp) 614 printf("%s at %s", name, pnp); 615 616 return QUIET; 617 } 618 619 static void 620 fwohci_hw_init(struct fwohci_softc *sc) 621 { 622 int i; 623 u_int32_t val; 624 625 /* 626 * Software Reset. 627 */ 628 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 629 for (i = 0; i < OHCI_LOOP; i++) { 630 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 631 if ((val & OHCI_HCControl_SoftReset) == 0) 632 break; 633 DELAY(10); 634 } 635 636 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 637 638 /* 639 * First, initilize CSRs with undefined value to default settings. 640 */ 641 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 642 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 643 #if 0 644 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 645 #else 646 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 647 #endif 648 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 649 for (i = 0; i < sc->sc_isoctx; i++) { 650 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 651 ~0); 652 } 653 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 654 655 fwohci_configrom_init(sc); 656 fwohci_selfid_init(sc); 657 fwohci_buf_init_rx(sc); 658 fwohci_csr_init(sc); 659 660 /* 661 * Final CSR settings. 662 */ 663 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 664 OHCI_LinkControl_CycleTimerEnable | 665 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 666 667 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 668 669 /* clear receive filter */ 670 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 671 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 672 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 673 674 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 675 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 676 #if BYTE_ORDER == BIG_ENDIAN 677 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 678 OHCI_HCControl_NoByteSwapData); 679 #endif 680 681 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 682 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 683 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 684 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 685 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 686 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 687 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 688 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 689 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 690 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 691 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 692 693 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 694 695 /* 696 * Start the receivers 697 */ 698 fwohci_buf_start_rx(sc); 699 } 700 701 static void 702 fwohci_power(int why, void *arg) 703 { 704 struct fwohci_softc *sc = arg; 705 int s; 706 707 s = splbio(); 708 switch (why) { 709 case PWR_SUSPEND: 710 case PWR_STANDBY: 711 fwohci_shutdown(sc); 712 break; 713 case PWR_RESUME: 714 fwohci_hw_init(sc); 715 fwohci_phy_busreset(sc); 716 break; 717 case PWR_SOFTSUSPEND: 718 case PWR_SOFTSTANDBY: 719 case PWR_SOFTRESUME: 720 break; 721 } 722 splx(s); 723 } 724 725 static void 726 fwohci_shutdown(void *arg) 727 { 728 struct fwohci_softc *sc = arg; 729 u_int32_t val; 730 731 callout_stop(&sc->sc_selfid_callout); 732 /* disable all interrupt */ 733 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 734 fwohci_buf_stop_tx(sc); 735 fwohci_buf_stop_rx(sc); 736 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 737 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 738 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 739 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 740 fwohci_phy_busreset(sc); 741 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 742 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 743 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 744 } 745 746 /* 747 * COMMON FUNCTIONS 748 */ 749 750 /* 751 * read the PHY Register. 752 */ 753 static u_int8_t 754 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 755 { 756 int i; 757 u_int32_t val; 758 759 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 760 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 761 for (i = 0; i < OHCI_LOOP; i++) { 762 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 763 OHCI_PhyControl_RdDone) 764 break; 765 DELAY(10); 766 } 767 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 768 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 769 } 770 771 /* 772 * write the PHY Register. 773 */ 774 static void 775 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 776 { 777 int i; 778 779 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 780 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 781 (val << OHCI_PhyControl_WrData_BITPOS)); 782 for (i = 0; i < OHCI_LOOP; i++) { 783 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 784 OHCI_PhyControl_WrReg)) 785 break; 786 DELAY(10); 787 } 788 } 789 790 /* 791 * Initiate Bus Reset 792 */ 793 static void 794 fwohci_phy_busreset(struct fwohci_softc *sc) 795 { 796 int s; 797 u_int8_t val; 798 799 s = splbio(); 800 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 801 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 802 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 803 callout_stop(&sc->sc_selfid_callout); 804 val = fwohci_phy_read(sc, 1); 805 val = (val & 0x80) | /* preserve RHB (force root) */ 806 0x40 | /* Initiate Bus Reset */ 807 0x3f; /* default GAP count */ 808 fwohci_phy_write(sc, 1, val); 809 splx(s); 810 } 811 812 /* 813 * PHY Packet 814 */ 815 static void 816 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 817 { 818 u_int32_t val; 819 820 val = pkt->fp_hdr[1]; 821 if (val != ~pkt->fp_hdr[2]) { 822 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 823 OHCI_CTXCTL_EVENT_BUS_RESET) { 824 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 825 pkt->fp_hdr[2])); 826 } else { 827 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 828 sc->sc_sc1394.sc1394_dev.dv_xname, val, 829 pkt->fp_hdr[2]); 830 } 831 return; 832 } 833 #ifdef FW_DEBUG 834 if (fwdebug > 1) 835 fwohci_show_phypkt(sc, val); 836 #endif 837 } 838 839 /* 840 * Descriptor for context DMA. 841 */ 842 static int 843 fwohci_desc_alloc(struct fwohci_softc *sc) 844 { 845 int error, mapsize, dsize; 846 847 /* 848 * allocate descriptor buffer 849 */ 850 851 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 852 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 853 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 854 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 855 mapsize = howmany(sc->sc_descsize, NBBY); 856 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK); 857 memset(sc->sc_descmap, 0, mapsize); 858 859 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 860 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 861 printf("%s: unable to allocate descriptor buffer, error = %d\n", 862 sc->sc_sc1394.sc1394_dev.dv_xname, error); 863 goto fail_0; 864 } 865 866 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 867 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 868 != 0) { 869 printf("%s: unable to map descriptor buffer, error = %d\n", 870 sc->sc_sc1394.sc1394_dev.dv_xname, error); 871 goto fail_1; 872 } 873 874 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 875 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 876 printf("%s: unable to create descriptor buffer DMA map, " 877 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 878 goto fail_2; 879 } 880 881 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 882 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 883 printf("%s: unable to load descriptor buffer DMA map, " 884 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 885 goto fail_3; 886 } 887 888 return 0; 889 890 fail_3: 891 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 892 fail_2: 893 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 894 fail_1: 895 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 896 fail_0: 897 return error; 898 } 899 900 static struct fwohci_desc * 901 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 902 { 903 int i, n; 904 905 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 906 for (i = 0; ; i++) { 907 if (i == ndesc) { 908 for (i = 0; i < ndesc; i++) 909 setbit(sc->sc_descmap, n + i); 910 return sc->sc_desc + n; 911 } 912 if (isset(sc->sc_descmap, n + i)) 913 break; 914 } 915 } 916 return NULL; 917 } 918 919 static void 920 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 921 { 922 int i, n; 923 924 n = fd - sc->sc_desc; 925 for (i = 0; i < ndesc; i++, n++) { 926 #ifdef DIAGNOSTIC 927 if (isclr(sc->sc_descmap, n)) 928 panic("fwohci_desc_put: duplicated free"); 929 #endif 930 clrbit(sc->sc_descmap, n); 931 } 932 } 933 934 /* 935 * Asyncronous/Isochronous Transmit/Receive Context 936 */ 937 static int 938 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 939 int bufcnt, int ctx, int ctxtype) 940 { 941 int i, error; 942 struct fwohci_ctx *fc; 943 struct fwohci_buf *fb; 944 struct fwohci_desc *fd; 945 #if DOUBLEBUF 946 int buf2cnt; 947 #endif 948 949 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 950 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 951 LIST_INIT(&fc->fc_handler); 952 TAILQ_INIT(&fc->fc_buf); 953 fc->fc_ctx = ctx; 954 fc->fc_bufcnt = bufcnt; 955 fb = (struct fwohci_buf *)&fc[1]; 956 #if DOUBLEBUF 957 TAILQ_INIT(&fc->fc_buf2); /* for isochronous */ 958 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 959 buf2cnt = bufcnt/2; 960 bufcnt -= buf2cnt; 961 if (buf2cnt == 0) { 962 panic("cannot allocate iso buffer"); 963 } 964 } 965 #endif 966 for (i = 0; i < bufcnt; i++, fb++) { 967 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 968 goto fail; 969 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 970 error = ENOBUFS; 971 goto fail; 972 } 973 fb->fb_desc = fd; 974 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 975 ((caddr_t)fd - (caddr_t)sc->sc_desc); 976 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 977 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 978 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 979 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 980 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 981 } 982 #if DOUBLEBUF 983 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 984 for (i = bufcnt; i < bufcnt + buf2cnt; i++, fb++) { 985 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 986 goto fail; 987 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 988 error = ENOBUFS; 989 goto fail; 990 } 991 fb->fb_desc = fd; 992 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 993 ((caddr_t)fd - (caddr_t)sc->sc_desc); 994 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 995 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 996 BUS_DMASYNC_PREWRITE); 997 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 998 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 999 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1000 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1001 TAILQ_INSERT_TAIL(&fc->fc_buf2, fb, fb_list); 1002 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1003 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1004 BUS_DMASYNC_POSTWRITE); 1005 } 1006 } 1007 #endif /* DOUBLEBUF */ 1008 fc->fc_type = ctxtype; 1009 *fcp = fc; 1010 return 0; 1011 1012 fail: 1013 while (i-- > 0) { 1014 fb--; 1015 if (fb->fb_desc) 1016 fwohci_desc_put(sc, fb->fb_desc, 1); 1017 fwohci_buf_free(sc, fb); 1018 } 1019 free(fc, M_DEVBUF); 1020 return error; 1021 } 1022 1023 static void 1024 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1025 { 1026 struct fwohci_buf *fb; 1027 struct fwohci_handler *fh; 1028 1029 #if DOUBLEBUF 1030 if ((fc->fc_type == FWOHCI_CTX_ISO_MULTI) && 1031 (TAILQ_FIRST(&fc->fc_buf) > TAILQ_FIRST(&fc->fc_buf2))) { 1032 struct fwohci_buf_s fctmp; 1033 1034 fctmp = fc->fc_buf; 1035 fc->fc_buf = fc->fc_buf2; 1036 fc->fc_buf2 = fctmp; 1037 } 1038 #endif 1039 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1040 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1041 NULL, NULL); 1042 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1043 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1044 if (fb->fb_desc) 1045 fwohci_desc_put(sc, fb->fb_desc, 1); 1046 fwohci_buf_free(sc, fb); 1047 } 1048 #if DOUBLEBUF 1049 while ((fb = TAILQ_FIRST(&fc->fc_buf2)) != NULL) { 1050 TAILQ_REMOVE(&fc->fc_buf2, fb, fb_list); 1051 if (fb->fb_desc) 1052 fwohci_desc_put(sc, fb->fb_desc, 1); 1053 fwohci_buf_free(sc, fb); 1054 } 1055 #endif /* DOUBLEBUF */ 1056 free(fc, M_DEVBUF); 1057 } 1058 1059 static void 1060 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1061 { 1062 struct fwohci_buf *fb, *nfb; 1063 struct fwohci_desc *fd; 1064 struct fwohci_handler *fh; 1065 int n; 1066 1067 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1068 nfb = TAILQ_NEXT(fb, fb_list); 1069 fb->fb_off = 0; 1070 fd = fb->fb_desc; 1071 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1072 fd->fd_rescount = fd->fd_reqcount; 1073 } 1074 1075 #if DOUBLEBUF 1076 for (fb = TAILQ_FIRST(&fc->fc_buf2); fb != NULL; fb = nfb) { 1077 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1078 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1079 BUS_DMASYNC_PREWRITE); 1080 nfb = TAILQ_NEXT(fb, fb_list); 1081 fb->fb_off = 0; 1082 fd = fb->fb_desc; 1083 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1084 fd->fd_rescount = fd->fd_reqcount; 1085 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1086 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1087 BUS_DMASYNC_POSTWRITE); 1088 } 1089 #endif /* DOUBLEBUF */ 1090 1091 n = fc->fc_ctx; 1092 fb = TAILQ_FIRST(&fc->fc_buf); 1093 if (fc->fc_type != FWOHCI_CTX_ASYNC) { 1094 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1095 fb->fb_daddr | 1); 1096 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1097 OHCI_CTXCTL_RX_BUFFER_FILL | 1098 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1099 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1100 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1101 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1102 OHCI_CTXCTL_RX_ISOCH_HEADER); 1103 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1104 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1105 OHCI_SUBREG_ContextControlSet, 1106 OHCI_CTXCTL_RX_BUFFER_FILL); 1107 } 1108 fh = LIST_FIRST(&fc->fc_handler); 1109 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1110 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1111 } else { 1112 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1113 fb->fb_daddr | 1); 1114 } 1115 } 1116 1117 /* 1118 * DMA data buffer 1119 */ 1120 static int 1121 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1122 { 1123 int error; 1124 1125 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1126 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1127 printf("%s: unable to allocate buffer, error = %d\n", 1128 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1129 goto fail_0; 1130 } 1131 1132 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1133 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1134 printf("%s: unable to map buffer, error = %d\n", 1135 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1136 goto fail_1; 1137 } 1138 1139 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1140 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1141 printf("%s: unable to create buffer DMA map, " 1142 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1143 error); 1144 goto fail_2; 1145 } 1146 1147 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1148 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1149 printf("%s: unable to load buffer DMA map, " 1150 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1151 error); 1152 goto fail_3; 1153 } 1154 1155 return 0; 1156 1157 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1158 fail_3: 1159 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1160 fail_2: 1161 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1162 fail_1: 1163 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1164 fail_0: 1165 return error; 1166 } 1167 1168 static void 1169 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1170 { 1171 1172 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1173 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1174 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1175 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1176 } 1177 1178 static void 1179 fwohci_buf_init_rx(struct fwohci_softc *sc) 1180 { 1181 int i; 1182 1183 /* 1184 * Initialize for Asynchronous Receive Queue. 1185 */ 1186 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1187 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1188 1189 /* 1190 * Initialize for Isochronous Receive Queue. 1191 */ 1192 for (i = 0; i < sc->sc_isoctx; i++) { 1193 if (sc->sc_ctx_ir[i] != NULL) 1194 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1195 } 1196 } 1197 1198 static void 1199 fwohci_buf_start_rx(struct fwohci_softc *sc) 1200 { 1201 int i; 1202 1203 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1204 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1205 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1206 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1207 for (i = 0; i < sc->sc_isoctx; i++) { 1208 if (sc->sc_ctx_ir[i] != NULL) 1209 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1210 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1211 } 1212 } 1213 1214 static void 1215 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1216 { 1217 int i; 1218 1219 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1220 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1221 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1222 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1223 1224 /* 1225 * Make sure the transmitter is stopped. 1226 */ 1227 for (i = 0; i < OHCI_LOOP; i++) { 1228 DELAY(10); 1229 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1230 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1231 continue; 1232 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1233 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1234 continue; 1235 break; 1236 } 1237 1238 /* 1239 * Initialize for Asynchronous Transmit Queue. 1240 */ 1241 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1242 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1243 } 1244 1245 static void 1246 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1247 { 1248 int i; 1249 1250 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1251 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1252 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1253 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1254 for (i = 0; i < sc->sc_isoctx; i++) { 1255 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1256 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1257 } 1258 } 1259 1260 static void 1261 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1262 { 1263 struct fwohci_buf *fb, *tfb; 1264 1265 #if DOUBLEBUF 1266 if (fc->fc_type != FWOHCI_CTX_ISO_MULTI) { 1267 #endif 1268 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1269 if (fc->fc_type) { 1270 if (fb->fb_off == 0) 1271 break; 1272 } else { 1273 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1274 fb->fb_desc->fd_rescount != 0) 1275 break; 1276 } 1277 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1278 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1279 fb->fb_off = 0; 1280 fb->fb_desc->fd_branch = 0; 1281 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1282 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1283 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1284 } 1285 #if DOUBLEBUF 1286 } else { 1287 struct fwohci_buf_s fctmp; 1288 1289 /* cleaning buffer */ 1290 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; 1291 fb = TAILQ_NEXT(fb, fb_list)) { 1292 fb->fb_off = 0; 1293 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1294 } 1295 1296 /* rotating buffer */ 1297 fctmp = fc->fc_buf; 1298 fc->fc_buf = fc->fc_buf2; 1299 fc->fc_buf2 = fctmp; 1300 } 1301 #endif 1302 } 1303 1304 static int 1305 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_buf **fbp, caddr_t *pp, 1306 int len) 1307 { 1308 struct fwohci_buf *fb; 1309 struct fwohci_desc *fd; 1310 int bufend; 1311 1312 fb = *fbp; 1313 again: 1314 fd = fb->fb_desc; 1315 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1316 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1317 fd->fd_reqcount, fd->fd_rescount, len, 1318 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1319 bufend = fd->fd_reqcount - fd->fd_rescount; 1320 if (fb->fb_off >= bufend) { 1321 DPRINTFN(5, ("buf %x finish req %d res %d off %d ", 1322 fb->fb_desc->fd_data, fd->fd_reqcount, fd->fd_rescount, 1323 fb->fb_off)); 1324 if (fd->fd_rescount == 0) { 1325 *fbp = fb = TAILQ_NEXT(fb, fb_list); 1326 if (fb != NULL) 1327 goto again; 1328 } 1329 return 0; 1330 } 1331 if (fb->fb_off + len > bufend) 1332 len = bufend - fb->fb_off; 1333 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1334 BUS_DMASYNC_POSTREAD); 1335 *pp = fb->fb_buf + fb->fb_off; 1336 fb->fb_off += roundup(len, 4); 1337 return len; 1338 } 1339 1340 static int 1341 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1342 struct fwohci_pkt *pkt) 1343 { 1344 caddr_t p; 1345 struct fwohci_buf *fb; 1346 int len, count, i; 1347 1348 memset(pkt, 0, sizeof(*pkt)); 1349 pkt->fp_uio.uio_iov = pkt->fp_iov; 1350 pkt->fp_uio.uio_rw = UIO_WRITE; 1351 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1352 1353 /* get first quadlet */ 1354 fb = TAILQ_FIRST(&fc->fc_buf); 1355 count = 4; 1356 len = fwohci_buf_pktget(sc, &fb, &p, count); 1357 if (len <= 0) { 1358 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1359 fc->fc_ctx)); 1360 return 0; 1361 } 1362 pkt->fp_hdr[0] = *(u_int32_t *)p; 1363 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1364 switch (pkt->fp_tcode) { 1365 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1366 case IEEE1394_TCODE_READ_RESP_QUAD: 1367 pkt->fp_hlen = 12; 1368 pkt->fp_dlen = 4; 1369 break; 1370 case IEEE1394_TCODE_READ_REQ_BLOCK: 1371 pkt->fp_hlen = 16; 1372 pkt->fp_dlen = 0; 1373 break; 1374 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1375 case IEEE1394_TCODE_READ_RESP_BLOCK: 1376 case IEEE1394_TCODE_LOCK_REQ: 1377 case IEEE1394_TCODE_LOCK_RESP: 1378 pkt->fp_hlen = 16; 1379 break; 1380 case IEEE1394_TCODE_STREAM_DATA: 1381 #ifdef DIAGNOSTIC 1382 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) 1383 #endif 1384 { 1385 pkt->fp_hlen = 4; 1386 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1387 DPRINTFN(5, ("[%d]", pkt->fp_dlen)); 1388 break; 1389 } 1390 #ifdef DIAGNOSTIC 1391 else { 1392 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1393 return 0; 1394 } 1395 #endif 1396 default: 1397 pkt->fp_hlen = 12; 1398 pkt->fp_dlen = 0; 1399 break; 1400 } 1401 1402 /* get header */ 1403 while (count < pkt->fp_hlen) { 1404 len = fwohci_buf_pktget(sc, &fb, &p, pkt->fp_hlen - count); 1405 if (len == 0) { 1406 printf("fwohci_buf_input: malformed input 1: %d\n", 1407 pkt->fp_hlen - count); 1408 return 0; 1409 } 1410 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1411 count += len; 1412 } 1413 if (pkt->fp_hlen == 16 && 1414 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1415 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1416 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1417 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1418 1419 /* get data */ 1420 count = 0; 1421 i = 0; 1422 while (count < pkt->fp_dlen) { 1423 len = fwohci_buf_pktget(sc, &fb, 1424 (caddr_t *)&pkt->fp_iov[i].iov_base, 1425 pkt->fp_dlen - count); 1426 if (len == 0) { 1427 printf("fwohci_buf_input: malformed input 2: %d\n", 1428 pkt->fp_dlen - count); 1429 return 0; 1430 } 1431 pkt->fp_iov[i++].iov_len = len; 1432 count += len; 1433 } 1434 pkt->fp_uio.uio_iovcnt = i; 1435 pkt->fp_uio.uio_resid = count; 1436 1437 /* get trailer */ 1438 len = fwohci_buf_pktget(sc, &fb, (caddr_t *)&pkt->fp_trail, 1439 sizeof(*pkt->fp_trail)); 1440 if (len <= 0) { 1441 printf("fwohci_buf_input: malformed input 3: %d\n", 1442 pkt->fp_hlen - count); 1443 return 0; 1444 } 1445 return 1; 1446 } 1447 1448 static int 1449 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1450 struct fwohci_pkt *pkt) 1451 { 1452 caddr_t p; 1453 int len; 1454 struct fwohci_buf *fb; 1455 struct fwohci_desc *fd; 1456 1457 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1458 return fwohci_buf_input(sc, fc, pkt); 1459 } 1460 1461 memset(pkt, 0, sizeof(*pkt)); 1462 pkt->fp_uio.uio_iov = pkt->fp_iov; 1463 pkt->fp_uio.uio_rw = UIO_WRITE; 1464 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1465 1466 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1467 if (fb == NULL) 1468 return 0; 1469 if (fb->fb_off == 0) 1470 break; 1471 } 1472 fd = fb->fb_desc; 1473 len = fd->fd_reqcount - fd->fd_rescount; 1474 if (len == 0) 1475 return 0; 1476 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1477 BUS_DMASYNC_POSTREAD); 1478 1479 p = fb->fb_buf; 1480 fb->fb_off += roundup(len, 4); 1481 if (len < 8) { 1482 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1483 return 0; 1484 } 1485 1486 /* 1487 * get trailer first, may be bogus data unless status update 1488 * in descriptor is set. 1489 */ 1490 pkt->fp_trail = (u_int32_t *)p; 1491 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1492 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1493 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1494 #ifdef DIAGNOSTIC 1495 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1496 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1497 pkt->fp_tcode); 1498 return 0; 1499 } 1500 #endif 1501 pkt->fp_hlen = 4; 1502 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1503 p += 8; 1504 len -= 8; 1505 if (pkt->fp_dlen != len) { 1506 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1507 pkt->fp_dlen, len); 1508 return 0; 1509 } 1510 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1511 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1512 pkt->fp_iov[0].iov_base = p; 1513 pkt->fp_iov[0].iov_len = len; 1514 pkt->fp_uio.uio_iovcnt = 0; 1515 pkt->fp_uio.uio_resid = len; 1516 return 1; 1517 } 1518 1519 static int 1520 fwohci_handler_set(struct fwohci_softc *sc, 1521 int tcode, u_int32_t key1, u_int32_t key2, 1522 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1523 void *arg) 1524 { 1525 struct fwohci_ctx *fc; 1526 struct fwohci_handler *fh; 1527 int i, j; 1528 1529 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1530 int isasync = key1 & OHCI_ASYNC_STREAM; 1531 1532 key1 &= IEEE1394_ISOCH_MASK; 1533 j = sc->sc_isoctx; 1534 fh = NULL; 1535 for (i = 0; i < sc->sc_isoctx; i++) { 1536 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1537 if (j == sc->sc_isoctx) 1538 j = i; 1539 continue; 1540 } 1541 fh = LIST_FIRST(&fc->fc_handler); 1542 if (fh->fh_tcode == tcode && 1543 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1544 break; 1545 fh = NULL; 1546 } 1547 if (fh == NULL) { 1548 if (handler == NULL) 1549 return 0; 1550 if (j == sc->sc_isoctx) { 1551 DPRINTF(("fwohci_handler_set: no more free " 1552 "context\n")); 1553 return ENOMEM; 1554 } 1555 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1556 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j, 1557 isasync ? FWOHCI_CTX_ISO_SINGLE : 1558 FWOHCI_CTX_ISO_MULTI); 1559 sc->sc_ctx_ir[j] = fc; 1560 } 1561 } 1562 } else { 1563 switch (tcode) { 1564 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1565 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1566 case IEEE1394_TCODE_READ_REQ_QUAD: 1567 case IEEE1394_TCODE_READ_REQ_BLOCK: 1568 case IEEE1394_TCODE_LOCK_REQ: 1569 fc = sc->sc_ctx_arrq; 1570 break; 1571 case IEEE1394_TCODE_WRITE_RESP: 1572 case IEEE1394_TCODE_READ_RESP_QUAD: 1573 case IEEE1394_TCODE_READ_RESP_BLOCK: 1574 case IEEE1394_TCODE_LOCK_RESP: 1575 fc = sc->sc_ctx_arrs; 1576 break; 1577 default: 1578 return EIO; 1579 } 1580 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1581 fh = LIST_NEXT(fh, fh_list)) { 1582 if (fh->fh_tcode == tcode && 1583 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1584 break; 1585 } 1586 } 1587 if (handler == NULL) { 1588 if (fh != NULL) { 1589 LIST_REMOVE(fh, fh_list); 1590 free(fh, M_DEVBUF); 1591 } 1592 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1593 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1594 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1595 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1596 fwohci_ctx_free(sc, fc); 1597 } 1598 return 0; 1599 } 1600 if (fh == NULL) { 1601 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1602 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1603 } 1604 fh->fh_tcode = tcode; 1605 fh->fh_key1 = key1; 1606 fh->fh_key2 = key2; 1607 fh->fh_handler = handler; 1608 fh->fh_handarg = arg; 1609 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1610 fc->fc_ctx, tcode, key1, key2)); 1611 1612 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1613 fwohci_ctx_init(sc, fc); 1614 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1615 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1616 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1617 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1618 } 1619 return 0; 1620 } 1621 1622 /* 1623 * Asyncronous Receive Requests input frontend. 1624 */ 1625 static void 1626 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1627 { 1628 int rcode; 1629 u_int32_t key1, key2; 1630 struct fwohci_handler *fh; 1631 struct fwohci_pkt pkt, res; 1632 1633 /* 1634 * Do not return if next packet is in the buffer, or the next 1635 * packet cannot be received until the next receive interrupt. 1636 */ 1637 while (fwohci_buf_input(sc, fc, &pkt)) { 1638 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1639 fwohci_phy_input(sc, &pkt); 1640 continue; 1641 } 1642 key1 = pkt.fp_hdr[1] & 0xffff; 1643 key2 = pkt.fp_hdr[2]; 1644 memset(&res, 0, sizeof(res)); 1645 res.fp_uio.uio_rw = UIO_WRITE; 1646 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1647 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1648 fh = LIST_NEXT(fh, fh_list)) { 1649 if (pkt.fp_tcode == fh->fh_tcode && 1650 key1 == fh->fh_key1 && 1651 key2 == fh->fh_key2) { 1652 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1653 &pkt); 1654 break; 1655 } 1656 } 1657 if (fh == NULL) { 1658 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1659 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1660 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1661 key2)); 1662 } 1663 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1664 OHCI_CTXCTL_EVENT_ACK_PENDING) 1665 continue; 1666 if (rcode != -1) 1667 fwohci_atrs_output(sc, rcode, &pkt, &res); 1668 } 1669 fwohci_buf_next(sc, fc); 1670 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1671 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1672 } 1673 1674 1675 /* 1676 * Asynchronous Receive Response input frontend. 1677 */ 1678 static void 1679 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1680 { 1681 struct fwohci_pkt pkt; 1682 struct fwohci_handler *fh; 1683 u_int16_t srcid; 1684 int rcode, tlabel; 1685 1686 while (fwohci_buf_input(sc, fc, &pkt)) { 1687 srcid = pkt.fp_hdr[1] >> 16; 1688 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1689 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1690 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1691 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1692 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1693 pkt.fp_dlen)); 1694 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1695 fh = LIST_NEXT(fh, fh_list)) { 1696 if (pkt.fp_tcode == fh->fh_tcode && 1697 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1698 tlabel == fh->fh_key2) { 1699 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1700 LIST_REMOVE(fh, fh_list); 1701 free(fh, M_DEVBUF); 1702 break; 1703 } 1704 } 1705 if (fh == NULL) 1706 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1707 } 1708 fwohci_buf_next(sc, fc); 1709 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1710 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1711 } 1712 1713 /* 1714 * Isochronous Receive input frontend. 1715 */ 1716 static void 1717 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1718 { 1719 int rcode, chan, tag; 1720 struct iovec *iov; 1721 struct fwohci_handler *fh; 1722 struct fwohci_pkt pkt; 1723 1724 #if DOUBLEBUF 1725 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1726 struct fwohci_buf *fb; 1727 int i; 1728 u_int32_t reg; 1729 1730 /* stop dma engine before read buffer */ 1731 reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, 1732 OHCI_SUBREG_ContextControlClear); 1733 DPRINTFN(5, ("ir_input %08x =>", reg)); 1734 if (reg & OHCI_CTXCTL_RUN) { 1735 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1736 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1737 } 1738 DPRINTFN(5, (" %08x\n", OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlClear))); 1739 1740 i = 0; 1741 while ((reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet)) & OHCI_CTXCTL_ACTIVE) { 1742 delay(10); 1743 if (++i > 10000) { 1744 printf("cannot stop dma engine 0x%08x\n", reg); 1745 return; 1746 } 1747 } 1748 1749 /* rotate dma buffer */ 1750 fb = TAILQ_FIRST(&fc->fc_buf2); 1751 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_CommandPtr, 1752 fb->fb_daddr | 1); 1753 /* start dma engine */ 1754 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1755 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1756 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 1757 (1 << fc->fc_ctx)); 1758 } 1759 #endif 1760 1761 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 1762 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1763 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1764 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, " 1765 "dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1766 pkt.fp_dlen)); 1767 if (tag == IEEE1394_TAG_GASP) { 1768 /* 1769 * The pkt with tag=3 is GASP format. 1770 * Move GASP header to header part. 1771 */ 1772 if (pkt.fp_dlen < 8) 1773 continue; 1774 iov = pkt.fp_iov; 1775 /* assuming pkt per buffer mode */ 1776 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1777 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1778 iov->iov_base = (caddr_t)iov->iov_base + 8; 1779 iov->iov_len -= 8; 1780 pkt.fp_hlen += 8; 1781 pkt.fp_dlen -= 8; 1782 } 1783 sc->sc_isopktcnt.ev_count++; 1784 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1785 fh = LIST_NEXT(fh, fh_list)) { 1786 if (pkt.fp_tcode == fh->fh_tcode && 1787 chan == fh->fh_key1 && tag == fh->fh_key2) { 1788 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1789 &pkt); 1790 break; 1791 } 1792 } 1793 #ifdef FW_DEBUG 1794 if (fh == NULL) { 1795 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1796 } else { 1797 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1798 } 1799 #endif 1800 } 1801 fwohci_buf_next(sc, fc); 1802 1803 if (fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 1804 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1805 OHCI_SUBREG_ContextControlSet, 1806 OHCI_CTXCTL_WAKE); 1807 } 1808 } 1809 1810 /* 1811 * Asynchronous Transmit common routine. 1812 */ 1813 static int 1814 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1815 struct fwohci_pkt *pkt) 1816 { 1817 struct fwohci_buf *fb; 1818 struct fwohci_desc *fd; 1819 struct mbuf *m, *m0; 1820 int i, ndesc, error, off, len; 1821 u_int32_t val; 1822 #ifdef FW_DEBUG 1823 struct iovec *iov; 1824 #endif 1825 1826 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 1827 /* We can't send anything during selfid duration */ 1828 return EAGAIN; 1829 1830 #ifdef FW_DEBUG 1831 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1832 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1833 for (i = 0; i < pkt->fp_hlen/4; i++) 1834 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 1835 DPRINTFN(2, ("$")); 1836 for (ndesc = 0, iov = pkt->fp_iov; 1837 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1838 for (i = 0; i < iov->iov_len; i++) 1839 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 1840 ((u_int8_t *)iov->iov_base)[i])); 1841 DPRINTFN(2, ("$")); 1842 } 1843 DPRINTFN(1, ("\n")); 1844 #endif 1845 1846 if ((m = pkt->fp_m) != NULL) { 1847 for (ndesc = 2; m != NULL; m = m->m_next) 1848 ndesc++; 1849 if (ndesc > OHCI_DESC_MAX) { 1850 m0 = NULL; 1851 ndesc = 2; 1852 for (off = 0; off < pkt->fp_dlen; off += len) { 1853 if (m0 == NULL) { 1854 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1855 if (m0 != NULL) 1856 M_COPY_PKTHDR(m0, pkt->fp_m); 1857 m = m0; 1858 } else { 1859 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1860 m = m->m_next; 1861 } 1862 if (m != NULL) 1863 MCLGET(m, M_DONTWAIT); 1864 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1865 m_freem(m0); 1866 return ENOMEM; 1867 } 1868 len = pkt->fp_dlen - off; 1869 if (len > m->m_ext.ext_size) 1870 len = m->m_ext.ext_size; 1871 m_copydata(pkt->fp_m, off, len, 1872 mtod(m, caddr_t)); 1873 m->m_len = len; 1874 ndesc++; 1875 } 1876 m_freem(pkt->fp_m); 1877 pkt->fp_m = m0; 1878 } 1879 } else 1880 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1881 1882 if (ndesc > OHCI_DESC_MAX) 1883 return ENOBUFS; 1884 1885 if (fc->fc_bufcnt > 50) /*XXX*/ 1886 return ENOBUFS; 1887 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1888 fb->fb_nseg = ndesc; 1889 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1890 if (fb->fb_desc == NULL) { 1891 free(fb, M_DEVBUF); 1892 return ENOBUFS; 1893 } 1894 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1895 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1896 fb->fb_m = pkt->fp_m; 1897 fb->fb_callback = pkt->fp_callback; 1898 fb->fb_statuscb = pkt->fp_statuscb; 1899 fb->fb_statusarg = pkt->fp_statusarg; 1900 1901 if (ndesc > 2) { 1902 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1903 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1904 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1905 free(fb, M_DEVBUF); 1906 return error; 1907 } 1908 1909 if (pkt->fp_m != NULL) 1910 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1911 pkt->fp_m, BUS_DMA_WAITOK); 1912 else 1913 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1914 &pkt->fp_uio, BUS_DMA_WAITOK); 1915 if (error != 0) { 1916 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1917 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1918 free(fb, M_DEVBUF); 1919 return error; 1920 } 1921 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1922 BUS_DMASYNC_PREWRITE); 1923 } 1924 1925 fd = fb->fb_desc; 1926 fd->fd_flags = OHCI_DESC_IMMED; 1927 fd->fd_reqcount = pkt->fp_hlen; 1928 fd->fd_data = 0; 1929 fd->fd_branch = 0; 1930 fd->fd_status = 0; 1931 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1932 i = 3; /* XXX: 3 sec */ 1933 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1934 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1935 ((((val >> 25) + i) & 0x7) << 13); 1936 } else 1937 fd->fd_timestamp = 0; 1938 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1939 for (i = 0; i < ndesc - 2; i++) { 1940 fd = fb->fb_desc + 2 + i; 1941 fd->fd_flags = 0; 1942 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1943 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1944 fd->fd_branch = 0; 1945 fd->fd_status = 0; 1946 fd->fd_timestamp = 0; 1947 } 1948 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1949 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1950 1951 #ifdef FW_DEBUG 1952 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1953 (long)(fb->fb_desc - sc->sc_desc))); 1954 for (i = 0; i < ndesc * 4; i++) 1955 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1956 ((u_int32_t *)fb->fb_desc)[i])); 1957 DPRINTFN(1, ("\n")); 1958 #endif 1959 1960 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1961 OHCI_SUBREG_ContextControlClear); 1962 1963 if (val & OHCI_CTXCTL_RUN) { 1964 if (fc->fc_branch == NULL) { 1965 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1966 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1967 goto run; 1968 } 1969 *fc->fc_branch = fb->fb_daddr | ndesc; 1970 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1971 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1972 } else { 1973 run: 1974 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1975 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1976 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1977 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1978 } 1979 fc->fc_branch = &fd->fd_branch; 1980 1981 fc->fc_bufcnt++; 1982 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1983 pkt->fp_m = NULL; 1984 return 0; 1985 } 1986 1987 static void 1988 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1989 { 1990 struct fwohci_buf *fb; 1991 struct fwohci_desc *fd; 1992 struct fwohci_pkt pkt; 1993 int i; 1994 1995 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1996 fd = fb->fb_desc; 1997 #ifdef FW_DEBUG 1998 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 1999 force ? "force " : "", (long)(fd - sc->sc_desc), 2000 fb->fb_nseg)); 2001 for (i = 0; i < fb->fb_nseg * 4; i++) 2002 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2003 ((u_int32_t *)fd)[i])); 2004 DPRINTFN(1, ("\n")); 2005 #endif 2006 if (fb->fb_nseg > 2) 2007 fd += fb->fb_nseg - 1; 2008 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 2009 break; 2010 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 2011 if (fc->fc_branch == &fd->fd_branch) { 2012 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2013 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2014 fc->fc_branch = NULL; 2015 for (i = 0; i < OHCI_LOOP; i++) { 2016 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2017 OHCI_SUBREG_ContextControlClear) & 2018 OHCI_CTXCTL_ACTIVE)) 2019 break; 2020 DELAY(10); 2021 } 2022 } 2023 2024 if (fb->fb_statuscb) { 2025 memset(&pkt, 0, sizeof(pkt)); 2026 pkt.fp_status = fd->fd_status; 2027 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 2028 2029 /* Indicate this is just returning the status bits. */ 2030 pkt.fp_tcode = -1; 2031 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 2032 fb->fb_statuscb = NULL; 2033 fb->fb_statusarg = NULL; 2034 } 2035 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 2036 if (fb->fb_nseg > 2) 2037 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2038 fc->fc_bufcnt--; 2039 if (fb->fb_callback) { 2040 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 2041 fb->fb_callback = NULL; 2042 } else if (fb->fb_m != NULL) 2043 m_freem(fb->fb_m); 2044 free(fb, M_DEVBUF); 2045 } 2046 } 2047 2048 /* 2049 * Asynchronous Transmit Reponse -- in response of request packet. 2050 */ 2051 static void 2052 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 2053 struct fwohci_pkt *res) 2054 { 2055 2056 if (((*req->fp_trail & 0x001f0000) >> 16) != 2057 OHCI_CTXCTL_EVENT_ACK_PENDING) 2058 return; 2059 2060 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 2061 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 2062 switch (req->fp_tcode) { 2063 case IEEE1394_TCODE_WRITE_REQ_QUAD: 2064 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 2065 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 2066 res->fp_hlen = 12; 2067 break; 2068 case IEEE1394_TCODE_READ_REQ_QUAD: 2069 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2070 res->fp_hlen = 16; 2071 res->fp_dlen = 0; 2072 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 2073 res->fp_hdr[3] = 2074 *(u_int32_t *)res->fp_iov[0].iov_base; 2075 res->fp_uio.uio_iovcnt = 0; 2076 break; 2077 case IEEE1394_TCODE_READ_REQ_BLOCK: 2078 case IEEE1394_TCODE_LOCK_REQ: 2079 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 2080 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 2081 else 2082 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2083 res->fp_hlen = 16; 2084 res->fp_dlen = res->fp_uio.uio_resid; 2085 res->fp_hdr[3] = res->fp_dlen << 16; 2086 break; 2087 } 2088 res->fp_hdr[0] |= (res->fp_tcode << 4); 2089 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 2090 } 2091 2092 /* 2093 * APPLICATION LAYER SERVICES 2094 */ 2095 2096 /* 2097 * Retrieve Global UID from GUID ROM 2098 */ 2099 static int 2100 fwohci_guidrom_init(struct fwohci_softc *sc) 2101 { 2102 int i, n, off; 2103 u_int32_t val1, val2; 2104 2105 /* Extract the Global UID 2106 */ 2107 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 2108 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 2109 2110 if (val1 != 0 || val2 != 0) { 2111 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 2112 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 2113 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 2114 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 2115 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 2116 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 2117 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 2118 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 2119 } else { 2120 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 2121 if ((val1 & OHCI_Version_GUID_ROM) == 0) 2122 return -1; 2123 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 2124 for (i = 0; i < OHCI_LOOP; i++) { 2125 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2126 if (!(val1 & OHCI_Guid_AddrReset)) 2127 break; 2128 DELAY(10); 2129 } 2130 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 2131 val2 = 0; 2132 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 2133 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 2134 OHCI_Guid_RdStart); 2135 for (i = 0; i < OHCI_LOOP; i++) { 2136 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2137 if (!(val1 & OHCI_Guid_RdStart)) 2138 break; 2139 DELAY(10); 2140 } 2141 if (n < off) 2142 continue; 2143 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 2144 sc->sc_sc1394.sc1394_guid[n - off] = val1; 2145 val2 |= val1; 2146 } 2147 if (val2 == 0) 2148 return -1; 2149 } 2150 return 0; 2151 } 2152 2153 /* 2154 * Initialization for Configuration ROM (no DMA context) 2155 */ 2156 2157 #define CFR_MAXUNIT 20 2158 2159 struct configromctx { 2160 u_int32_t *ptr; 2161 int curunit; 2162 struct { 2163 u_int32_t *start; 2164 int length; 2165 u_int32_t *refer; 2166 int refunit; 2167 } unit[CFR_MAXUNIT]; 2168 }; 2169 2170 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2171 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2172 2173 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2174 2175 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2176 2177 #define CFR_PUT_CRC(cfr, n) \ 2178 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2179 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2180 2181 #define CFR_START_UNIT(cfr, n) \ 2182 do { \ 2183 if ((cfr)->unit[n].refer != NULL) { \ 2184 *(cfr)->unit[n].refer |= \ 2185 (cfr)->ptr - (cfr)->unit[n].refer; \ 2186 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2187 } \ 2188 (cfr)->curunit = (n); \ 2189 (cfr)->unit[n].start = (cfr)->ptr++; \ 2190 } while (0 /* CONSTCOND */) 2191 2192 #define CFR_PUT_REFER(cfr, key, n) \ 2193 do { \ 2194 (cfr)->unit[n].refer = (cfr)->ptr; \ 2195 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2196 *(cfr)->ptr++ = (key) << 24; \ 2197 } while (0 /* CONSTCOND */) 2198 2199 #define CFR_END_UNIT(cfr) \ 2200 do { \ 2201 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2202 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2203 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2204 } while (0 /* CONSTCOND */) 2205 2206 static u_int16_t 2207 fwohci_crc16(u_int32_t *ptr, int len) 2208 { 2209 int shift; 2210 u_int32_t crc, sum, data; 2211 2212 crc = 0; 2213 while (len-- > 0) { 2214 data = *ptr++; 2215 for (shift = 28; shift >= 0; shift -= 4) { 2216 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2217 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2218 } 2219 crc &= 0xffff; 2220 } 2221 return crc; 2222 } 2223 2224 static void 2225 fwohci_configrom_init(struct fwohci_softc *sc) 2226 { 2227 int i, val; 2228 struct fwohci_buf *fb; 2229 u_int32_t *hdr; 2230 struct configromctx cfr; 2231 2232 fb = &sc->sc_buf_cnfrom; 2233 memset(&cfr, 0, sizeof(cfr)); 2234 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2235 2236 /* headers */ 2237 CFR_START_UNIT(&cfr, 0); 2238 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2239 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2240 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2241 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2242 CFR_END_UNIT(&cfr); 2243 /* copy info_length from crc_length */ 2244 *hdr |= (*hdr & 0x00ff0000) << 8; 2245 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2246 2247 /* root directory */ 2248 CFR_START_UNIT(&cfr, 1); 2249 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2250 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2251 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2252 /* spt,64,fix,lst,drq */ 2253 #ifdef INET 2254 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2255 #endif /* INET */ 2256 #ifdef INET6 2257 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2258 #endif /* INET6 */ 2259 CFR_END_UNIT(&cfr); 2260 2261 CFR_START_UNIT(&cfr, 2); 2262 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2263 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2264 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2265 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2266 CFR_END_UNIT(&cfr); 2267 2268 #ifdef INET 2269 /* IPv4 unit directory */ 2270 CFR_START_UNIT(&cfr, 3); 2271 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2272 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2273 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2274 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2275 CFR_END_UNIT(&cfr); 2276 2277 CFR_START_UNIT(&cfr, 6); 2278 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2279 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2280 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2281 CFR_END_UNIT(&cfr); 2282 2283 CFR_START_UNIT(&cfr, 7); 2284 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2285 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2286 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2287 CFR_END_UNIT(&cfr); 2288 #endif /* INET */ 2289 2290 #ifdef INET6 2291 /* IPv6 unit directory */ 2292 CFR_START_UNIT(&cfr, 4); 2293 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2294 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 2295 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2296 /* XXX: TBA by IANA */ 2297 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2298 CFR_END_UNIT(&cfr); 2299 2300 CFR_START_UNIT(&cfr, 8); 2301 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2302 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2303 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2304 CFR_END_UNIT(&cfr); 2305 2306 CFR_START_UNIT(&cfr, 9); 2307 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2308 CFR_PUT_DATA1(&cfr, 0); 2309 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2310 CFR_END_UNIT(&cfr); 2311 #endif /* INET6 */ 2312 2313 fb->fb_off = cfr.ptr - hdr; 2314 #ifdef FW_DEBUG 2315 DPRINTFN(2, ("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2316 for (i = 0; i < fb->fb_off; i++) 2317 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", hdr[i])); 2318 DPRINTFN(2, ("\n")); 2319 #endif /* FW_DEBUG */ 2320 2321 /* 2322 * Make network byte order for DMA 2323 */ 2324 for (i = 0; i < fb->fb_off; i++) 2325 HTONL(hdr[i]); 2326 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2327 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2328 2329 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2330 fb->fb_dmamap->dm_segs[0].ds_addr); 2331 2332 /* This register is only valid on OHCI 1.1. */ 2333 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2334 if ((OHCI_Version_GET_Version(val) == 1) && 2335 (OHCI_Version_GET_Revision(val) == 1)) 2336 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2337 OHCI_HCControl_BIBImageValid); 2338 2339 /* Just allow quad reads of the rom. */ 2340 for (i = 0; i < fb->fb_off; i++) 2341 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2342 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2343 fwohci_configrom_input, NULL); 2344 } 2345 2346 static int 2347 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2348 struct fwohci_pkt *pkt) 2349 { 2350 struct fwohci_pkt res; 2351 u_int32_t loc, *rom; 2352 2353 /* This will be used as an array index so size accordingly. */ 2354 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2355 if ((loc & 0x03) != 0) { 2356 /* alignment error */ 2357 return IEEE1394_RCODE_ADDRESS_ERROR; 2358 } 2359 else 2360 loc /= 4; 2361 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2362 2363 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2364 ntohl(rom[loc]))); 2365 2366 memset(&res, 0, sizeof(res)); 2367 res.fp_hdr[3] = rom[loc]; 2368 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2369 return -1; 2370 } 2371 2372 /* 2373 * SelfID buffer (no DMA context) 2374 */ 2375 static void 2376 fwohci_selfid_init(struct fwohci_softc *sc) 2377 { 2378 struct fwohci_buf *fb; 2379 2380 fb = &sc->sc_buf_selfid; 2381 #ifdef DIAGNOSTIC 2382 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2383 panic("fwohci_selfid_init: not aligned: %p (%ld) %p", 2384 (caddr_t)fb->fb_dmamap->dm_segs[0].ds_addr, 2385 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2386 #endif 2387 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2388 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2389 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2390 2391 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2392 fb->fb_dmamap->dm_segs[0].ds_addr); 2393 } 2394 2395 static int 2396 fwohci_selfid_input(struct fwohci_softc *sc) 2397 { 2398 int i; 2399 u_int32_t count, val, gen; 2400 u_int32_t *buf; 2401 2402 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2403 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2404 again: 2405 if (val & OHCI_SelfID_Error) { 2406 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2407 return -1; 2408 } 2409 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2410 2411 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2412 0, count << 2, BUS_DMASYNC_POSTREAD); 2413 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2414 2415 #ifdef FW_DEBUG 2416 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2417 val)); 2418 for (i = 0; i < count; i++) 2419 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2420 DPRINTFN(1, ("\n")); 2421 #endif /* FW_DEBUG */ 2422 2423 for (i = 1; i < count; i += 2) { 2424 if (buf[i] != ~buf[i + 1]) 2425 break; 2426 if (buf[i] & 0x00000001) 2427 continue; /* more pkt */ 2428 if (buf[i] & 0x00800000) 2429 continue; /* external id */ 2430 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2431 if ((buf[i] & 0x00400800) == 0x00400800) 2432 sc->sc_irmid = sc->sc_rootid; 2433 } 2434 2435 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2436 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2437 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2438 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2439 goto again; 2440 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2441 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2442 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2443 return -1; 2444 } 2445 if (i != count) { 2446 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2447 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2448 #if 1 2449 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2450 /* 2451 * XXX: CXD3222 sometimes fails to DMA 2452 * selfid packet?? 2453 */ 2454 sc->sc_rootid = (count - 1) / 2 - 1; 2455 sc->sc_irmid = sc->sc_rootid; 2456 } else 2457 #endif 2458 return -1; 2459 } 2460 2461 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2462 if ((val & OHCI_NodeId_IDValid) == 0) { 2463 sc->sc_nodeid = 0xffff; /* invalid */ 2464 printf("%s: nodeid is invalid\n", 2465 sc->sc_sc1394.sc1394_dev.dv_xname); 2466 return -1; 2467 } 2468 sc->sc_nodeid = val & 0xffff; 2469 2470 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2471 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2472 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2473 sc->sc_irmid)); 2474 2475 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2476 return -1; 2477 2478 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2479 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2480 OHCI_LinkControl_CycleMaster); 2481 else 2482 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2483 OHCI_LinkControl_CycleMaster); 2484 return 0; 2485 } 2486 2487 /* 2488 * some CSRs are handled by driver. 2489 */ 2490 static void 2491 fwohci_csr_init(struct fwohci_softc *sc) 2492 { 2493 int i; 2494 static u_int32_t csr[] = { 2495 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2496 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2497 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2498 CSR_SB_BROADCAST_CHANNEL 2499 }; 2500 2501 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2502 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2503 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2504 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2505 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2506 } 2507 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2508 } 2509 2510 static int 2511 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2512 { 2513 struct fwohci_pkt res; 2514 u_int32_t reg; 2515 2516 /* 2517 * XXX need to do special functionality other than just r/w... 2518 */ 2519 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2520 2521 if ((reg & 0x03) != 0) { 2522 /* alignment error */ 2523 return IEEE1394_RCODE_ADDRESS_ERROR; 2524 } 2525 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2526 *(u_int32_t *)(&sc->sc_csr[reg]))); 2527 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2528 DPRINTFN(1, (" -> 0x%08x\n", 2529 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2530 *(u_int32_t *)&sc->sc_csr[reg] = 2531 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2532 } else { 2533 DPRINTFN(1, ("\n")); 2534 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2535 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2536 res.fp_iov[0].iov_len = 4; 2537 res.fp_uio.uio_resid = 4; 2538 res.fp_uio.uio_iovcnt = 1; 2539 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2540 return -1; 2541 } 2542 return IEEE1394_RCODE_COMPLETE; 2543 } 2544 2545 /* 2546 * Mapping between nodeid and unique ID (EUI-64). 2547 * 2548 * Track old mappings and simply update their devices with the new id's when 2549 * they match an existing EUI. This allows proper renumeration of the bus. 2550 */ 2551 static void 2552 fwohci_uid_collect(struct fwohci_softc *sc) 2553 { 2554 int i; 2555 struct fwohci_uidtbl *fu; 2556 struct ieee1394_softc *iea; 2557 2558 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2559 iea->sc1394_node_id = 0xffff; 2560 2561 if (sc->sc_uidtbl != NULL) 2562 free(sc->sc_uidtbl, M_DEVBUF); 2563 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2564 M_NOWAIT); /* XXX M_WAITOK requires locks */ 2565 if (sc->sc_uidtbl == NULL) 2566 return; 2567 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 2568 2569 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2570 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2571 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2572 fu->fu_valid = 3; 2573 2574 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2575 if (iea) { 2576 iea->sc1394_node_id = i; 2577 DPRINTF(("%s: Updating nodeid to %d\n", 2578 iea->sc1394_dev.dv_xname, 2579 iea->sc1394_node_id)); 2580 } 2581 } else { 2582 fu->fu_valid = 0; 2583 fwohci_uid_req(sc, i); 2584 } 2585 } 2586 if (sc->sc_rootid == 0) 2587 fwohci_check_nodes(sc); 2588 } 2589 2590 static void 2591 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 2592 { 2593 struct fwohci_pkt pkt; 2594 2595 memset(&pkt, 0, sizeof(pkt)); 2596 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2597 pkt.fp_hlen = 12; 2598 pkt.fp_dlen = 0; 2599 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2600 (pkt.fp_tcode << 4); 2601 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 2602 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2603 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2604 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2605 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2606 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2607 2608 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2609 (pkt.fp_tcode << 4); 2610 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2611 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2612 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2613 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2614 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2615 } 2616 2617 static int 2618 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2619 { 2620 struct fwohci_uidtbl *fu; 2621 struct ieee1394_softc *iea; 2622 struct ieee1394_attach_args fwa; 2623 int i, n, done, rcode, found; 2624 2625 found = 0; 2626 2627 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2628 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2629 if (rcode != IEEE1394_RCODE_COMPLETE || 2630 sc->sc_uidtbl == NULL || 2631 n > sc->sc_rootid) 2632 return 0; 2633 fu = &sc->sc_uidtbl[n]; 2634 if (arg == 0) { 2635 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2636 fu->fu_valid |= 0x1; 2637 } else { 2638 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2639 fu->fu_valid |= 0x2; 2640 } 2641 #ifdef FW_DEBUG 2642 if (fu->fu_valid == 0x3) 2643 DPRINTFN(1, ("fwohci_uid_input: " 2644 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2645 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2646 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2647 #endif 2648 if (fu->fu_valid == 0x3) { 2649 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2650 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2651 found = 1; 2652 iea->sc1394_node_id = n; 2653 DPRINTF(("%s: Updating nodeid to %d\n", 2654 iea->sc1394_dev.dv_xname, 2655 iea->sc1394_node_id)); 2656 break; 2657 } 2658 if (!found) { 2659 strcpy(fwa.name, "fwnode"); 2660 memcpy(fwa.uid, fu->fu_uid, 8); 2661 fwa.nodeid = n; 2662 fwa.read = fwohci_read; 2663 fwa.write = fwohci_write; 2664 fwa.inreg = fwohci_inreg; 2665 iea = (struct ieee1394_softc *) 2666 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2667 fwohci_print, fwohci_submatch); 2668 if (iea != NULL) 2669 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2670 sc1394_node); 2671 } 2672 } 2673 done = 1; 2674 2675 for (i = 0; i < sc->sc_rootid + 1; i++) { 2676 fu = &sc->sc_uidtbl[i]; 2677 if (fu->fu_valid != 0x3) { 2678 done = 0; 2679 break; 2680 } 2681 } 2682 if (done) 2683 fwohci_check_nodes(sc); 2684 2685 return 0; 2686 } 2687 2688 static void 2689 fwohci_check_nodes(struct fwohci_softc *sc) 2690 { 2691 struct device *detach = NULL; 2692 struct ieee1394_softc *iea; 2693 2694 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2695 2696 /* 2697 * Have to defer detachment until the next 2698 * loop iteration since config_detach 2699 * free's the softc and the loop iterator 2700 * needs data from the softc to move 2701 * forward. 2702 */ 2703 2704 if (detach) { 2705 config_detach(detach, 0); 2706 detach = NULL; 2707 } 2708 if (iea->sc1394_node_id == 0xffff) { 2709 detach = (struct device *)iea; 2710 LIST_REMOVE(iea, sc1394_node); 2711 } 2712 } 2713 if (detach) 2714 config_detach(detach, 0); 2715 } 2716 2717 static int 2718 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2719 { 2720 struct fwohci_uidtbl *fu; 2721 int n; 2722 static const u_int8_t bcast[] = 2723 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2724 2725 fu = sc->sc_uidtbl; 2726 if (fu == NULL) { 2727 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2728 return IEEE1394_BCAST_PHY_ID; 2729 fwohci_uid_collect(sc); /* try to get */ 2730 return -1; 2731 } 2732 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 2733 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2734 return n; 2735 } 2736 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2737 return IEEE1394_BCAST_PHY_ID; 2738 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 2739 if (fu->fu_valid != 0x3) { 2740 /* 2741 * XXX: need timer before retransmission 2742 */ 2743 fwohci_uid_req(sc, n); 2744 } 2745 } 2746 return -1; 2747 } 2748 2749 /* 2750 * functions to support network interface 2751 */ 2752 static int 2753 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2754 void (*handler)(struct device *, struct mbuf *)) 2755 { 2756 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2757 2758 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2759 handler ? fwohci_if_input : NULL, handler); 2760 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2761 (sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & IEEE1394_ISOCH_MASK) | OHCI_ASYNC_STREAM, 2762 IEEE1394_TAG_GASP, handler ? fwohci_if_input : NULL, handler); 2763 return 0; 2764 } 2765 2766 static int 2767 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2768 { 2769 int n, len; 2770 struct mbuf *m; 2771 struct iovec *iov; 2772 void (*handler)(struct device *, struct mbuf *) = arg; 2773 2774 #ifdef FW_DEBUG 2775 int i; 2776 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2777 pkt->fp_dlen)); 2778 for (i = 0; i < pkt->fp_hlen/4; i++) 2779 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2780 DPRINTFN(2, ("$")); 2781 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2782 iov = &pkt->fp_iov[n]; 2783 for (i = 0; i < iov->iov_len; i++) 2784 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2785 ((u_int8_t *)iov->iov_base)[i])); 2786 DPRINTFN(2, ("$")); 2787 } 2788 DPRINTFN(1, ("\n")); 2789 #endif /* FW_DEBUG */ 2790 len = pkt->fp_dlen; 2791 MGETHDR(m, M_DONTWAIT, MT_DATA); 2792 if (m == NULL) 2793 return IEEE1394_RCODE_COMPLETE; 2794 m->m_len = 16; 2795 if (len + m->m_len > MHLEN) { 2796 MCLGET(m, M_DONTWAIT); 2797 if ((m->m_flags & M_EXT) == 0) { 2798 m_freem(m); 2799 return IEEE1394_RCODE_COMPLETE; 2800 } 2801 } 2802 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2803 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2804 sc->sc_uidtbl[n].fu_valid != 0x3) { 2805 printf("%s: packet from unknown node: phy id %d\n", 2806 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2807 m_freem(m); 2808 fwohci_uid_req(sc, n); 2809 return IEEE1394_RCODE_COMPLETE; 2810 } 2811 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2812 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2813 m->m_flags |= M_BCAST; 2814 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2815 } else { 2816 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2817 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2818 } 2819 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2820 mtod(m, u_int8_t *)[9] = 2821 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2822 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2823 2824 m->m_pkthdr.rcvif = NULL; /* set in child */ 2825 m->m_pkthdr.len = len + m->m_len; 2826 /* 2827 * We may use receive buffer by external mbuf instead of copy here. 2828 * But asynchronous receive buffer must be operate in buffer fill 2829 * mode, so that each receive buffer will shared by multiple mbufs. 2830 * If upper layer doesn't free mbuf soon, e.g. application program 2831 * is suspended, buffer must be reallocated. 2832 * Isochronous buffer must be operate in packet buffer mode, and 2833 * it is easy to map receive buffer to external mbuf. But it is 2834 * used for broadcast/multicast only, and is expected not so 2835 * performance sensitive for now. 2836 * XXX: The performance may be important for multicast case, 2837 * so we should revisit here later. 2838 * -- onoe 2839 */ 2840 n = 0; 2841 iov = pkt->fp_uio.uio_iov; 2842 while (len > 0) { 2843 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2844 iov->iov_len); 2845 m->m_len += iov->iov_len; 2846 len -= iov->iov_len; 2847 iov++; 2848 } 2849 (*handler)(sc->sc_sc1394.sc1394_if, m); 2850 return IEEE1394_RCODE_COMPLETE; 2851 } 2852 2853 static int 2854 fwohci_if_input_iso(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2855 { 2856 int n, len; 2857 int chan, tag; 2858 struct mbuf *m; 2859 struct iovec *iov; 2860 void (*handler)(struct device *, struct mbuf *) = arg; 2861 #ifdef FW_DEBUG 2862 int i; 2863 #endif 2864 2865 chan = (pkt->fp_hdr[0] & 0x00003f00) >> 8; 2866 tag = (pkt->fp_hdr[0] & 0x0000c000) >> 14; 2867 #ifdef FW_DEBUG 2868 DPRINTFN(1, ("fwohci_if_input_iso: " 2869 "tcode=0x%x, chan=%d, tag=%x, dlen=%d", 2870 pkt->fp_tcode, chan, tag, pkt->fp_dlen)); 2871 for (i = 0; i < pkt->fp_hlen/4; i++) 2872 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2873 DPRINTFN(2, ("$")); 2874 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2875 iov = &pkt->fp_iov[n]; 2876 for (i = 0; i < iov->iov_len; i++) 2877 DPRINTFN(2, ("%s%02x", 2878 (i%32)?((i%4)?"":" "):"\n\t", 2879 ((u_int8_t *)iov->iov_base)[i])); 2880 DPRINTFN(2, ("$")); 2881 } 2882 DPRINTFN(2, ("\n")); 2883 #endif /* FW_DEBUG */ 2884 len = pkt->fp_dlen; 2885 MGETHDR(m, M_DONTWAIT, MT_DATA); 2886 if (m == NULL) 2887 return IEEE1394_RCODE_COMPLETE; 2888 m->m_len = 16; 2889 if (m->m_len + len > MHLEN) { 2890 MCLGET(m, M_DONTWAIT); 2891 if ((m->m_flags & M_EXT) == 0) { 2892 m_freem(m); 2893 return IEEE1394_RCODE_COMPLETE; 2894 } 2895 } 2896 2897 m->m_flags |= M_BCAST; 2898 2899 if (tag == IEEE1394_TAG_GASP) { 2900 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2901 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2902 sc->sc_uidtbl[n].fu_valid != 0x3) { 2903 printf("%s: packet from unknown node: phy id %d\n", 2904 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2905 m_freem(m); 2906 return IEEE1394_RCODE_COMPLETE; 2907 } 2908 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2909 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2910 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2911 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2912 mtod(m, u_int8_t *)[9] = 2913 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2914 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2915 } else { 2916 m->m_flags |= M_LINK0; 2917 } 2918 mtod(m, u_int8_t *)[14] = chan; 2919 mtod(m, u_int8_t *)[15] = tag; 2920 2921 2922 m->m_pkthdr.rcvif = NULL; /* set in child */ 2923 m->m_pkthdr.len = len + m->m_len; 2924 /* 2925 * We may use receive buffer by external mbuf instead of copy here. 2926 * But asynchronous receive buffer must be operate in buffer fill 2927 * mode, so that each receive buffer will shared by multiple mbufs. 2928 * If upper layer doesn't free mbuf soon, e.g. application program 2929 * is suspended, buffer must be reallocated. 2930 * Isochronous buffer must be operate in packet buffer mode, and 2931 * it is easy to map receive buffer to external mbuf. But it is 2932 * used for broadcast/multicast only, and is expected not so 2933 * performance sensitive for now. 2934 * XXX: The performance may be important for multicast case, 2935 * so we should revisit here later. 2936 * -- onoe 2937 */ 2938 n = 0; 2939 iov = pkt->fp_uio.uio_iov; 2940 while (len > 0) { 2941 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2942 iov->iov_len); 2943 m->m_len += iov->iov_len; 2944 len -= iov->iov_len; 2945 iov++; 2946 } 2947 (*handler)(sc->sc_sc1394.sc1394_if, m); 2948 return IEEE1394_RCODE_COMPLETE; 2949 } 2950 2951 2952 2953 static int 2954 fwohci_if_output(struct device *self, struct mbuf *m0, 2955 void (*callback)(struct device *, struct mbuf *)) 2956 { 2957 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2958 struct fwohci_pkt pkt; 2959 u_int8_t *p; 2960 int n, error, spd, hdrlen, maxrec; 2961 #ifdef FW_DEBUG 2962 struct mbuf *m; 2963 #endif 2964 2965 p = mtod(m0, u_int8_t *); 2966 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2967 spd = IEEE1394_SPD_S100; /*XXX*/ 2968 maxrec = 512; /*XXX*/ 2969 hdrlen = 8; 2970 } else { 2971 n = fwohci_uid_lookup(sc, p); 2972 if (n < 0) { 2973 printf("%s: nodeid unknown:" 2974 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2975 sc->sc_sc1394.sc1394_dev.dv_xname, 2976 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2977 error = EHOSTUNREACH; 2978 goto end; 2979 } 2980 if (n == IEEE1394_BCAST_PHY_ID) { 2981 printf("%s: broadcast with !M_MCAST\n", 2982 sc->sc_sc1394.sc1394_dev.dv_xname); 2983 #ifdef FW_DEBUG 2984 DPRINTFN(2, ("packet:")); 2985 for (m = m0; m != NULL; m = m->m_next) { 2986 for (n = 0; n < m->m_len; n++) 2987 DPRINTFN(2, ("%s%02x", (n%32)? 2988 ((n%4)?"":" "):"\n ", 2989 mtod(m, u_int8_t *)[n])); 2990 DPRINTFN(2, ("$")); 2991 } 2992 DPRINTFN(2, ("\n")); 2993 #endif 2994 error = EHOSTUNREACH; 2995 goto end; 2996 } 2997 maxrec = 2 << p[8]; 2998 spd = p[9]; 2999 hdrlen = 0; 3000 } 3001 if (spd > sc->sc_sc1394.sc1394_link_speed) { 3002 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 3003 spd, sc->sc_sc1394.sc1394_link_speed)); 3004 spd = sc->sc_sc1394.sc1394_link_speed; 3005 } 3006 if (maxrec > (512 << spd)) { 3007 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 3008 "\n", maxrec, spd)); 3009 maxrec = 512 << spd; 3010 } 3011 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 3012 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 3013 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 3014 maxrec >>= 1; 3015 } 3016 if (maxrec < 512) { 3017 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 3018 "minimum\n", maxrec)); 3019 maxrec = 512; 3020 } 3021 3022 m_adj(m0, 16 - hdrlen); 3023 if (m0->m_pkthdr.len > maxrec) { 3024 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 3025 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 3026 error = E2BIG; /*XXX*/ 3027 goto end; 3028 } 3029 3030 memset(&pkt, 0, sizeof(pkt)); 3031 pkt.fp_uio.uio_iov = pkt.fp_iov; 3032 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3033 pkt.fp_uio.uio_rw = UIO_WRITE; 3034 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3035 /* construct GASP header */ 3036 p = mtod(m0, u_int8_t *); 3037 p[0] = sc->sc_nodeid >> 8; 3038 p[1] = sc->sc_nodeid & 0xff; 3039 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 3040 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 3041 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 3042 pkt.fp_hlen = 8; 3043 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 3044 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 3045 OHCI_NodeId_NodeNumber) << 8); 3046 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 3047 } else { 3048 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 3049 pkt.fp_hlen = 16; 3050 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 3051 (spd << 16); 3052 pkt.fp_hdr[1] = 3053 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 3054 (p[10] << 8) | p[11]; 3055 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 3056 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 3057 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3058 } 3059 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 3060 pkt.fp_dlen = m0->m_pkthdr.len; 3061 pkt.fp_m = m0; 3062 pkt.fp_callback = callback; 3063 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3064 m0 = pkt.fp_m; 3065 end: 3066 if (m0 != NULL) { 3067 if (callback) 3068 (*callback)(sc->sc_sc1394.sc1394_if, m0); 3069 else 3070 m_freem(m0); 3071 } 3072 return error; 3073 } 3074 3075 /* 3076 * High level routines to provide abstraction to attaching layers to 3077 * send/receive data. 3078 */ 3079 3080 /* 3081 * These break down into 4 routines as follows: 3082 * 3083 * int fwohci_read(struct ieee1394_abuf *) 3084 * 3085 * This routine will attempt to read a region from the requested node. 3086 * A callback must be provided which will be called when either the completed 3087 * read is done or an unrecoverable error occurs. This is mainly a convenience 3088 * routine since it will encapsulate retrying a region as quadlet vs. block reads 3089 * and recombining all the returned data. This could also be done with a series 3090 * of write/inreg's for each packet sent. 3091 * 3092 * int fwohci_write(struct ieee1394_abuf *) 3093 * 3094 * The work horse main entry point for putting packets on the bus. This is the 3095 * generalized interface for fwnode/etc code to put packets out onto the bus. 3096 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and optionally 3097 * will callback via a func pointer to the calling code with the resulting ACK 3098 * code from the packet. If the ACK code is to be ignored (i.e. no cb) then the 3099 * write routine will take care of free'ing the abuf since the fwnode/etc code 3100 * won't have any knowledge of when to do this. This allows for simple one-off 3101 * packets to be sent from the upper-level code without worrying about a callback 3102 * for cleanup. 3103 * 3104 * int fwohci_inreg(struct ieee1394_abuf *, int) 3105 * 3106 * This is very simple. It evals the abuf passed in and registers an internal 3107 * handler as the callback for packets received for that operation. 3108 * The integer argument specifies whether on a block read/write operation to 3109 * allow sub-regions to be read/written (in block form) as well. 3110 * 3111 * XXX: This whole structure needs to be redone as a list of regions and 3112 * operations allowed on those regions. 3113 * 3114 * int fwohci_unreg(struct ieee1394_abuf *, int) 3115 * 3116 * XXX: TBD. For now passing in a NULL ab_cb to inreg will unregister. This 3117 * routine will simply verify ab_cb is NULL and call inreg. 3118 * 3119 * This simply unregisters the respective callback done via inreg for items 3120 * which only need to register an area for a one-time operation (like a status 3121 * buffer a remote node will write to when the current operation is done). The 3122 * int argument specifies the same behavior as inreg, except in reverse (i.e. 3123 * it unregisters). 3124 */ 3125 3126 static int 3127 fwohci_read(struct ieee1394_abuf *ab) 3128 { 3129 struct fwohci_pkt pkt; 3130 struct ieee1394_softc *sc = ab->ab_req; 3131 struct fwohci_softc *psc = 3132 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3133 struct fwohci_cb *fcb; 3134 u_int32_t high, lo; 3135 int rv, tcode; 3136 3137 /* Have to have a callback when reading. */ 3138 if (ab->ab_cb == NULL) 3139 return -1; 3140 3141 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 3142 fcb->ab = ab; 3143 fcb->count = 0; 3144 fcb->abuf_valid = 1; 3145 3146 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3147 lo = (ab->ab_csr & 0x00000000ffffffff); 3148 3149 memset(&pkt, 0, sizeof(pkt)); 3150 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3151 pkt.fp_hdr[2] = lo; 3152 pkt.fp_dlen = 0; 3153 3154 if (ab->ab_length == 4) { 3155 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3156 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 3157 pkt.fp_hlen = 12; 3158 } else { 3159 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 3160 pkt.fp_hlen = 16; 3161 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 3162 pkt.fp_hdr[3] = (ab->ab_length << 16); 3163 } 3164 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3165 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3166 3167 pkt.fp_statusarg = fcb; 3168 pkt.fp_statuscb = fwohci_read_resp; 3169 3170 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3171 psc->sc_tlabel, fwohci_read_resp, fcb); 3172 if (rv) 3173 return rv; 3174 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3175 if (rv) 3176 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3177 psc->sc_tlabel, NULL, NULL); 3178 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3179 fcb->count = 1; 3180 return rv; 3181 } 3182 3183 static int 3184 fwohci_write(struct ieee1394_abuf *ab) 3185 { 3186 struct fwohci_pkt pkt; 3187 struct ieee1394_softc *sc = ab->ab_req; 3188 struct fwohci_softc *psc = 3189 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3190 u_int32_t high, lo; 3191 int rv; 3192 3193 if (ab->ab_length > sc->sc1394_max_receive) { 3194 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3195 return E2BIG; 3196 } 3197 3198 memset(&pkt, 0, sizeof(pkt)); 3199 3200 pkt.fp_tcode = ab->ab_tcode; 3201 pkt.fp_uio.uio_iov = pkt.fp_iov; 3202 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3203 pkt.fp_uio.uio_rw = UIO_WRITE; 3204 3205 pkt.fp_statusarg = ab; 3206 pkt.fp_statuscb = fwohci_write_ack; 3207 3208 switch (ab->ab_tcode) { 3209 case IEEE1394_TCODE_WRITE_RESP: 3210 pkt.fp_hlen = 12; 3211 case IEEE1394_TCODE_READ_RESP_QUAD: 3212 case IEEE1394_TCODE_READ_RESP_BLOCK: 3213 if (!pkt.fp_hlen) 3214 pkt.fp_hlen = 16; 3215 high = ab->ab_retlen; 3216 ab->ab_retlen = 0; 3217 lo = 0; 3218 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3219 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 3220 break; 3221 default: 3222 pkt.fp_hlen = 16; 3223 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3224 lo = (ab->ab_csr & 0x00000000ffffffff); 3225 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3226 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3227 break; 3228 } 3229 3230 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3231 pkt.fp_hdr[2] = lo; 3232 if (pkt.fp_hlen == 16) { 3233 if (ab->ab_length == 4) { 3234 pkt.fp_hdr[3] = ab->ab_data[0]; 3235 pkt.fp_dlen = 0; 3236 } else { 3237 pkt.fp_hdr[3] = (ab->ab_length << 16); 3238 pkt.fp_dlen = ab->ab_length; 3239 pkt.fp_uio.uio_iovcnt = 1; 3240 pkt.fp_uio.uio_resid = ab->ab_length; 3241 pkt.fp_iov[0].iov_base = ab->ab_data; 3242 pkt.fp_iov[0].iov_len = ab->ab_length; 3243 } 3244 } 3245 switch (ab->ab_tcode) { 3246 case IEEE1394_TCODE_WRITE_RESP: 3247 case IEEE1394_TCODE_READ_RESP_QUAD: 3248 case IEEE1394_TCODE_READ_RESP_BLOCK: 3249 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 3250 break; 3251 default: 3252 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3253 break; 3254 } 3255 return rv; 3256 } 3257 3258 static int 3259 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3260 { 3261 struct fwohci_cb *fcb = arg; 3262 struct ieee1394_abuf *ab = fcb->ab; 3263 struct fwohci_pkt newpkt; 3264 u_int32_t *cur, high, lo; 3265 int i, tcode, rcode, status, rv; 3266 3267 /* 3268 * Both the ACK handling and normal response callbacks are handled here. 3269 * The main reason for this is the various error conditions that can 3270 * occur trying to block read some areas and the ways that gets reported 3271 * back to calling station. This is a variety of ACK codes, responses, 3272 * etc which makes it much more difficult to process if both aren't 3273 * handled here. 3274 */ 3275 3276 /* Check for status packet. */ 3277 3278 if (pkt->fp_tcode == -1) { 3279 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3280 rcode = -1; 3281 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3282 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3283 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3284 DPRINTF(("Got status packet: 0x%02x\n", 3285 (unsigned int)status)); 3286 fcb->count--; 3287 3288 /* 3289 * Got all the ack's back and the buffer is invalid (i.e. the 3290 * callback has been called. Clean up. 3291 */ 3292 3293 if (fcb->abuf_valid == 0) { 3294 if (fcb->count == 0) 3295 free(fcb, M_DEVBUF); 3296 return IEEE1394_RCODE_COMPLETE; 3297 } 3298 } else { 3299 status = -1; 3300 tcode = pkt->fp_tcode; 3301 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3302 } 3303 3304 /* 3305 * Some area's (like the config rom want to be read as quadlets only. 3306 * 3307 * The current ideas to try are: 3308 * 3309 * Got an ACK_TYPE_ERROR on a block read. 3310 * 3311 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 3312 * response. 3313 * 3314 * In all cases construct a new packet for a quadlet read and let 3315 * mutli_resp handle the iteration over the space. 3316 */ 3317 3318 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 3319 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 3320 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 3321 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 3322 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 3323 3324 /* Read the area in quadlet chunks (internally track this). */ 3325 3326 memset(&newpkt, 0, sizeof(newpkt)); 3327 3328 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3329 lo = (ab->ab_csr & 0x00000000ffffffff); 3330 3331 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3332 newpkt.fp_hlen = 12; 3333 newpkt.fp_dlen = 0; 3334 newpkt.fp_hdr[1] = 3335 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3336 newpkt.fp_hdr[2] = lo; 3337 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3338 (newpkt.fp_tcode << 4); 3339 3340 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3341 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3342 fwohci_read_multi_resp, fcb); 3343 if (rv) { 3344 (*ab->ab_cb)(ab, -1); 3345 goto cleanup; 3346 } 3347 newpkt.fp_statusarg = fcb; 3348 newpkt.fp_statuscb = fwohci_read_resp; 3349 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3350 if (rv) { 3351 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3352 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3353 NULL); 3354 (*ab->ab_cb)(ab, -1); 3355 goto cleanup; 3356 } 3357 fcb->count++; 3358 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3359 return IEEE1394_RCODE_COMPLETE; 3360 } else if ((rcode != -1) || ((status != -1) && 3361 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3362 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3363 3364 /* 3365 * Recombine all the iov data into 1 chunk for higher 3366 * level code. 3367 */ 3368 3369 if (rcode != -1) { 3370 cur = ab->ab_data; 3371 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3372 /* 3373 * Make sure and don't exceed the buffer 3374 * allocated for return. 3375 */ 3376 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3377 ab->ab_length) { 3378 memcpy(cur, pkt->fp_iov[i].iov_base, 3379 (ab->ab_length - ab->ab_retlen)); 3380 ab->ab_retlen = ab->ab_length; 3381 break; 3382 } 3383 memcpy(cur, pkt->fp_iov[i].iov_base, 3384 pkt->fp_iov[i].iov_len); 3385 cur += pkt->fp_iov[i].iov_len; 3386 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3387 } 3388 } 3389 if (status != -1) 3390 /* XXX: Need a complete tlabel interface. */ 3391 for (i = 0; i < 64; i++) 3392 fwohci_handler_set(sc, 3393 IEEE1394_TCODE_READ_RESP_QUAD, 3394 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3395 (*ab->ab_cb)(ab, rcode); 3396 goto cleanup; 3397 } else 3398 /* Good ack packet. */ 3399 return IEEE1394_RCODE_COMPLETE; 3400 3401 /* Can't get here unless ab->ab_cb has been called. */ 3402 3403 cleanup: 3404 fcb->abuf_valid = 0; 3405 if (fcb->count == 0) 3406 free(fcb, M_DEVBUF); 3407 return IEEE1394_RCODE_COMPLETE; 3408 } 3409 3410 static int 3411 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3412 struct fwohci_pkt *pkt) 3413 { 3414 struct fwohci_cb *fcb = arg; 3415 struct ieee1394_abuf *ab = fcb->ab; 3416 struct fwohci_pkt newpkt; 3417 u_int32_t high, lo; 3418 int rcode, rv; 3419 3420 /* 3421 * Bad return codes from the wire, just return what's already in the 3422 * buf. 3423 */ 3424 3425 /* Make sure a response packet didn't arrive after a bad ACK. */ 3426 if (fcb->abuf_valid == 0) 3427 return IEEE1394_RCODE_COMPLETE; 3428 3429 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3430 3431 if (rcode) { 3432 (*ab->ab_cb)(ab, rcode); 3433 goto cleanup; 3434 } 3435 3436 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3437 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3438 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3439 ab->ab_retlen = ab->ab_length; 3440 } else { 3441 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3442 pkt->fp_iov[0].iov_base, 4); 3443 ab->ab_retlen += 4; 3444 } 3445 /* Still more, loop and read 4 more bytes. */ 3446 if (ab->ab_retlen < ab->ab_length) { 3447 memset(&newpkt, 0, sizeof(newpkt)); 3448 3449 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3450 lo = (ab->ab_csr & 0x00000000ffffffff) + ab->ab_retlen; 3451 3452 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3453 newpkt.fp_hlen = 12; 3454 newpkt.fp_dlen = 0; 3455 newpkt.fp_hdr[1] = 3456 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3457 newpkt.fp_hdr[2] = lo; 3458 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3459 (newpkt.fp_tcode << 4); 3460 3461 newpkt.fp_statusarg = fcb; 3462 newpkt.fp_statuscb = fwohci_read_resp; 3463 3464 /* 3465 * Bad return code. Just give up and return what's 3466 * come in now. 3467 */ 3468 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3469 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3470 fwohci_read_multi_resp, fcb); 3471 if (rv) 3472 (*ab->ab_cb)(ab, -1); 3473 else { 3474 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3475 if (rv) { 3476 fwohci_handler_set(sc, 3477 IEEE1394_TCODE_READ_RESP_QUAD, 3478 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3479 NULL, NULL); 3480 (*ab->ab_cb)(ab, -1); 3481 } else { 3482 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3483 fcb->count++; 3484 return IEEE1394_RCODE_COMPLETE; 3485 } 3486 } 3487 } else 3488 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3489 3490 cleanup: 3491 /* Can't get here unless ab_cb has been called. */ 3492 fcb->abuf_valid = 0; 3493 if (fcb->count == 0) 3494 free(fcb, M_DEVBUF); 3495 return IEEE1394_RCODE_COMPLETE; 3496 } 3497 3498 static int 3499 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3500 { 3501 struct ieee1394_abuf *ab = arg; 3502 u_int16_t status; 3503 3504 3505 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3506 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3507 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3508 DPRINTF(("Got status packet: 0x%02x\n", 3509 (unsigned int)status)); 3510 3511 /* No callback means this level should free the buffers. */ 3512 if (ab->ab_cb) 3513 (*ab->ab_cb)(ab, status); 3514 else { 3515 if (ab->ab_data) 3516 free(ab->ab_data, M_1394DATA); 3517 free(ab, M_1394DATA); 3518 } 3519 return IEEE1394_RCODE_COMPLETE; 3520 } 3521 3522 static int 3523 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3524 { 3525 struct ieee1394_softc *sc = ab->ab_req; 3526 struct fwohci_softc *psc = 3527 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3528 u_int32_t high, lo; 3529 int i, j, rv; 3530 3531 high = ((ab->ab_csr & 0x0000ffff00000000) >> 32); 3532 lo = (ab->ab_csr & 0x00000000ffffffff); 3533 3534 rv = 0; 3535 switch (ab->ab_tcode) { 3536 case IEEE1394_TCODE_READ_REQ_QUAD: 3537 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3538 if (ab->ab_cb) 3539 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3540 fwohci_parse_input, ab); 3541 else 3542 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3543 NULL); 3544 break; 3545 case IEEE1394_TCODE_READ_REQ_BLOCK: 3546 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3547 if (allow) { 3548 for (i = 0; i < (ab->ab_length / 4); i++) { 3549 if (ab->ab_cb) { 3550 rv = fwohci_handler_set(psc, 3551 ab->ab_tcode, high, lo + (i * 4), 3552 fwohci_parse_input, ab); 3553 if (rv) 3554 break; 3555 } else 3556 fwohci_handler_set(psc, ab->ab_tcode, 3557 high, lo + (i * 4), NULL, NULL); 3558 } 3559 if (i != (ab->ab_length / 4)) { 3560 j = i + 1; 3561 for (i = 0; i < j; i++) 3562 fwohci_handler_set(psc, ab->ab_tcode, 3563 high, lo + (i * 4), NULL, NULL); 3564 } else 3565 ab->ab_data = (void *)1; 3566 } else { 3567 if (ab->ab_cb) 3568 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3569 lo, fwohci_parse_input, ab); 3570 else 3571 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3572 NULL, NULL); 3573 } 3574 break; 3575 default: 3576 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3577 return -1; 3578 break; 3579 } 3580 return rv; 3581 } 3582 3583 static int 3584 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3585 { 3586 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3587 u_int64_t csr; 3588 u_int32_t *cur; 3589 int i, count; 3590 3591 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3592 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3593 csr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3594 3595 switch (ab->ab_tcode) { 3596 case IEEE1394_TCODE_READ_REQ_QUAD: 3597 ab->ab_retlen = 4; 3598 break; 3599 case IEEE1394_TCODE_READ_REQ_BLOCK: 3600 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3601 if (ab->ab_data) { 3602 if ((csr + ab->ab_retlen) > 3603 (ab->ab_csr + ab->ab_length)) 3604 return IEEE1394_RCODE_ADDRESS_ERROR; 3605 ab->ab_data = NULL; 3606 } else 3607 if (ab->ab_retlen != ab->ab_length) 3608 return IEEE1394_RCODE_ADDRESS_ERROR; 3609 break; 3610 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3611 ab->ab_retlen = 4; 3612 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3613 if (!ab->ab_retlen) 3614 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3615 if (ab->ab_data) { 3616 if ((csr + ab->ab_retlen) > 3617 (ab->ab_csr + ab->ab_length)) 3618 return IEEE1394_RCODE_ADDRESS_ERROR; 3619 ab->ab_data = NULL; 3620 } else 3621 if (ab->ab_retlen != ab->ab_length) 3622 return IEEE1394_RCODE_ADDRESS_ERROR; 3623 3624 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3625 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3626 ab->ab_data[0] = pkt->fp_hdr[3]; 3627 else { 3628 count = 0; 3629 cur = ab->ab_data; 3630 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3631 memcpy(cur, pkt->fp_iov[i].iov_base, 3632 pkt->fp_iov[i].iov_len); 3633 cur += pkt->fp_iov[i].iov_len; 3634 count += pkt->fp_iov[i].iov_len; 3635 } 3636 if (ab->ab_retlen != count) 3637 panic("Packet claims %d length " 3638 "but only %d bytes returned\n", 3639 ab->ab_retlen, count); 3640 } 3641 break; 3642 default: 3643 panic("Got a callback for a tcode that wasn't requested: %d\n", 3644 ab->ab_tcode); 3645 break; 3646 } 3647 ab->ab_csr = csr; 3648 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3649 return -1; 3650 } 3651 3652 static int 3653 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3654 { 3655 struct ieee1394_attach_args *fwa = aux; 3656 3657 /* Both halves must be filled in for a match. */ 3658 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3659 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3660 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3661 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3662 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 3663 return 0; 3664 } 3665 3666 #ifdef FW_DEBUG 3667 static void 3668 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3669 { 3670 3671 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3672 intmask); 3673 if (intmask & OHCI_Int_CycleTooLong) 3674 printf(" CycleTooLong"); 3675 if (intmask & OHCI_Int_UnrecoverableError) 3676 printf(" UnrecoverableError"); 3677 if (intmask & OHCI_Int_CycleInconsistent) 3678 printf(" CycleInconsistent"); 3679 if (intmask & OHCI_Int_BusReset) 3680 printf(" BusReset"); 3681 if (intmask & OHCI_Int_SelfIDComplete) 3682 printf(" SelfIDComplete"); 3683 if (intmask & OHCI_Int_LockRespErr) 3684 printf(" LockRespErr"); 3685 if (intmask & OHCI_Int_PostedWriteErr) 3686 printf(" PostedWriteErr"); 3687 if (intmask & OHCI_Int_ReqTxComplete) 3688 printf(" ReqTxComplete(0x%04x)", 3689 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3690 OHCI_SUBREG_ContextControlClear)); 3691 if (intmask & OHCI_Int_RespTxComplete) 3692 printf(" RespTxComplete(0x%04x)", 3693 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3694 OHCI_SUBREG_ContextControlClear)); 3695 if (intmask & OHCI_Int_ARRS) 3696 printf(" ARRS(0x%04x)", 3697 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3698 OHCI_SUBREG_ContextControlClear)); 3699 if (intmask & OHCI_Int_ARRQ) 3700 printf(" ARRQ(0x%04x)", 3701 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3702 OHCI_SUBREG_ContextControlClear)); 3703 if (intmask & OHCI_Int_IsochRx) 3704 printf(" IsochRx(0x%08x)", 3705 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3706 if (intmask & OHCI_Int_IsochTx) 3707 printf(" IsochTx(0x%08x)", 3708 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3709 if (intmask & OHCI_Int_RQPkt) 3710 printf(" RQPkt(0x%04x)", 3711 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3712 OHCI_SUBREG_ContextControlClear)); 3713 if (intmask & OHCI_Int_RSPkt) 3714 printf(" RSPkt(0x%04x)", 3715 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3716 OHCI_SUBREG_ContextControlClear)); 3717 printf("\n"); 3718 } 3719 3720 static void 3721 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3722 { 3723 u_int8_t key, phyid; 3724 3725 key = (val & 0xc0000000) >> 30; 3726 phyid = (val & 0x3f000000) >> 24; 3727 printf("%s: PHY packet from %d: ", 3728 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3729 switch (key) { 3730 case 0: 3731 printf("PHY Config:"); 3732 if (val & 0x00800000) 3733 printf(" ForceRoot"); 3734 if (val & 0x00400000) 3735 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3736 printf("\n"); 3737 break; 3738 case 1: 3739 printf("Link-on\n"); 3740 break; 3741 case 2: 3742 printf("SelfID:"); 3743 if (val & 0x00800000) { 3744 printf(" #%d", (val & 0x00700000) >> 20); 3745 } else { 3746 if (val & 0x00400000) 3747 printf(" LinkActive"); 3748 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3749 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3750 if (val & 0x00000800) 3751 printf(" Cont"); 3752 if (val & 0x00000002) 3753 printf(" InitiateBusReset"); 3754 } 3755 if (val & 0x00000001) 3756 printf(" +"); 3757 printf("\n"); 3758 break; 3759 default: 3760 printf("unknown: 0x%08x\n", val); 3761 break; 3762 } 3763 } 3764 #endif /* FW_DEBUG */ 3765
Indexes created Sat Sep 27 14:09:57 GMT 2025